RT9238 Preliminary VRM8.5 PWM and Triple Linear Power System Controller General Description Features The RT9238 is a 4-in-one power controller optimized z 4-in-one Regulated Voltages for Microprocessor Core, AGTL+ Bus, AGP Bus Power, and for high-performance microprocessor and computer North/South Bridge Core applications. The IC integrates a PWM controller, triple linear controller as well as monitoring and z Compatible with ISL6524 protection functions into a 28-pin SOP package. The z Power-good Output Voltage Monitor PWM controller regulates the microprocessor core Switching section voltage with a synchronous buck converter. The first linear controller supplies the computer system’s AGTL+ 1.2V bus power. The second linear controller provides power for the 1.5V AGP bus and the 3rd linear controller provides 1.8V power for the chipset core voltage and/or cache memory circuits. z VRM8.5 TTL-Compatible 5-bit DAC Programmable from 1.090V to 1.865V z ±1% DAC Accuracy Fast Transient Response z VRM 8.5 Voltage Droop Tuning Uses MOSFET z R DS(ON) The RT9238 features an Intel VRM8.5 compatible, z Fixed 200KHz Switching Frequency TTL 5-bit programmable DAC that adjusts the core z Adaptive Non-overlapping Gate Driver voltage from 1.090V to 1.865V in 25mV steps. The 5- z Over-current Monitor Uses MOSFET RDS(ON) bit DAC has a typical ±1% tolerance. The linear z Over-voltage Protection Uses Lower MOSFET regulators provide fixed output voltages of 1.2V Linear Section (VOUT2), 1.5V (VOUT3) and 1.8V (VOUT4) or useradjustable with an internal 1.265V reference. All the three linear regulators drive external N-MOSFET or z Fixed or User-adjustable Linear Regulator Output Voltage z MOSFET and NPN Driving Capability z Ultra Fast Response Speed The RT9238 monitors all the output voltages. A z Under-voltage Protection power-good signal is issued when the core voltage is z Internal Thermal Shutdown within ±10% of the DAC setting and the other levels Pin Configurations NPNs bipolar for the pass transistor. are above their under-voltage levels. Additional buildin over-voltage protection for the core output uses the lower MOSFET to prevent output voltage above 115% of the DAC setting. The PWM over-current function monitors the output current using the voltage drop across the MOSFET’s RDS(ON), which eliminates the need for a current sensing resistor. Applications z Motherboard Power Regulation for Computers DS9238-01 July 2001 Part Number RT9238CS (Plastic SOP-28) Pin Configurations DRIVE2 FIX 1 28 2 27 VCC UGATE1 VID3 VID2 3 26 PHASE1 4 25 VID1 VID0 5 24 LGATE1 PGND 6 23 VID25 7 PGOOD 8 22 OCSET1 FB1 21 VDAC VTTPG 9 20 ICOMP FAULT/VID4 VSEN2 SS24 SS13 VSEN4 10 19 11 18 VSEN3 DRIVE3 12 17 13 16 GND VAUX 14 15 DRIVE4 www.richtek-ic.com.tw 1 RT9238 Preliminary Ordering Information RT9238 Package type S : SOP-28 Operating temperature range C: Commercial standard Typical Application Circuit L1 5V 1µH + R1 12V 10 C14 1µF Z1 15V C2 28 VCC FIX 2 C1 2000µF OCSET1 FIX PGOOD VAUX 23 8 1000pF R2 1K PGOOD Q1 PHB83N03LT UGATE1 27 VTT VOUT2 1.2V 1 Q3 PHD3055E + C5 1000µF R6 1K 11 PGND 16 FB1 VTTPG VAUX VDAC + C15 10µF AGP VOUT3 1.5V MCH VOUT4 1.8V Q4 PHD3055E + 18 19 C9 560µF C8 1µF Q5 2SD1802 + C11 560µF C10 1µF 15 14 26 L2; 1.8µH VSEN2 LGATE1 25 RT9238 C6 1µF 9 VTTPG DRIVE2 PHASE1 ICOMP VID25 VID0 VID1 VSEN3 VID2 VID3 FAULT/VID4 DRIVE4 SS24 VSEN4 SS13 DRIVE3 GND 17 Q2 PHB95N03LT 24 R3 10K + VCORE VOUT1 VRM8.5 C4 1µF C3 8000µF 22 21 20 R6 7 6 5 4 3 10 1K VID25 VID0 VID1 VID2 VID3 FAULT C16 10nF C17 1µF * C17 near the FB1 pin as close as possible 12 13 C12 0.1µF C13 0.1µF Fig.1 VRM 8.5 Power Solution www.richtek-ic.com.tw 2 DS9238-01 July 2001 RT9238 Preliminary L1 5V 1µH + R1 12V 10 C14 1µF Z1 15V C2 28 VCC FIX 2 C1 2000µF OCSET1 FIX PGOOD VAUX 23 8 1000pF R2 1K PGOOD Q1 PHB83N03LT UGATE1 27 VTT VOUT2 1.2V 1 Q3 PHD3055E + C5 1000µF R6 1K 11 PGND 9 16 + AGP VOUT3 1.5V MCH VOUT4 1.8V Q4 PHD3055E + 19 C9 560µF C8 1µF Q5 2SD1802 + C11 560µF C10 1µF 15 14 FB1 VTTPG VDAC VAUX C15 10µF 18 26 L2; 1.8µH VSEN2 LGATE1 25 RT9238 C6 1µF VTTPG DRIVE2 PHASE1 ICOMP VID25 DRIVE3 VID0 VID1 VSEN3 VID2 VID3 FAULT/VID4 DRIVE4 SS24 VSEN4 SS13 GND 17 Q2 PHB95N03LT 24 R3 10K + VCORE C4 1µF C3 8000µF VOUT1 VRM8.5 22 C17 1µF 21 C16 10nF 20 R6 7 6 5 4 3 10 1K VID25 VID0 Q7 VID1 MMBT3906 VID2 D1 VID3 1N4148 R13; 47K R15 10K FAULT VAUX TUAL5 * TUAL5: Hi Tualatin TUAL5: Lo Coppermine 12 13 C12 0.1µF C13 0.1µF Fig.2 VRM 8.4 & 8.5 Power Solution DS9238-01 July 2001 www.richtek-ic.com.tw 3 VSEN2 DRIVE2 FIX VSEN4 DRIVE4 ×0.90 EA4 _ ×0.75 ×0.75 UV2 1.26V + SOFTSTART & FAULT LOGIC VTTPG FAULT/VID4 28µA OV SS24 4.5V VCC SS13 FAULT OSCILLATOR EA2 INHIBIT UV4 UV3 CLK Q D CLR + Q SET + 1.2V + + + DRIVE3 _ EA3 _ _ VAUX EA1 OC FB1 VDAC ICOMP 4.5V 28µA ×1.15 ×0.90 ×1.10 + OCSET _ _ 40mV RS RS 3K SYNCH DRIVE GATE CONTROL VID3 VID1 VID25 VID2 VID0 VCC DRIVE1 VCC POWER-ON RESET (POR) VCC TTL D/A CONVERTER (DAC) PWM PWM COMP _ 200µA + _ VSEN3 + _ + + _ + _ 4 + _ _ www.richtek-ic.com.tw _ + + + GND PGND LGATE1 PHASE1 UGATE1 PGOOD VAUX RT9238 Preliminary Function Block Diagram DS9238-01 July 2001 RT9238 Preliminary Absolute Maximum Ratings z Supply Voltage +15V z FAULT/VID4 and GATE Voltage GND−0.3V ~ VCC+0.3V z Input, Output or I/O Voltage GND−0.3V ~ 7V z Ambient Temperature Range 0°C ~ +70°C z Operating Junction Temperature Range 0°C ~ +125°C z Storage Temperature Range −65°C ~ +150°C z Lead Temperature (Soldering, 10 sec.) 300°C z Package Thermal Resistance SOP-28, θJA 60°C/W Recommended Operating Conditions z Supply Voltage +12V±10% z Ambient Temperature Range 0°C to 70°C z Junction Temperature Range 0°C to 125°C CAUTION: Stresses beyond the ratings specified in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Characteristics (VCC = 12V, PGND = 0V, TA = 25°C, Unless otherwise specified.) Parameter Symbol Test Conditions Min Typ Max Units -- 10 -- mA VCC Supply Current Nominal Supply Current ICC UGATE1, LGATE1, DRIVE2, DRIVE3, and DRIVE4 Open Power-On Reset VCC Rising Threshold VOCSET1 = 4.5V 6.5 -- 9.5 V VCC Falling Threshold VOCSET1 = 4.5V 6 -- 9 V Rising VAUX Threshold VOCSET1 = 4.5V -- 1.5 -- V VAUX Threshold Hysteresis VOCSET1 = 4.5V -- 0.2 -- V -- 1.25 -- V DAC (VID25-VID3) Input Low Voltage -- -- 0.8 V DAC(VID25-VID3) Input High Voltage 2.0 -- -- V -10 -- +20 mV 180 200 225 KHz -- 1.9 -- VP-P Rising VOCSET1 Threshold DAC AND Band Gap Reference DACOUT Voltage Accuracy VDAC + 40mV Oscillator Free Running Frequency Ramp Amplitude ∆ VOSC To be continued DS9238-01 July 2001 www.richtek-ic.com.tw 5 RT9238 Parameter Preliminary Symbol Test Conditions Min Typ Max Units Linear Regulators (VOUT2, VOUT3, and VOUT4) VSEN3,4 Voltage Regulation VREG2,3,4 FIX = 0V 1.240 1.265 1.290 V VSEN2 Regulation Voltage VREG2 1.180 1.200 1.240 V VSEN3 Regulation Voltage VREG3 FIX = open 1.455 1.500 1.545 V VSEN3 Bias Current IBVSEN3 FIX = open VSEN4 Regulation Voltage VREG4 FIX = open VSEN4 Bias Current IBVSEN4 FIX = open -- 350 -- µA Under-Voltage Level (All Linears) (VSEN/VREG) VSEN3,4 Rising -- 75 -- % Under-Voltage Hysteresis (All Linears) (VSEN/VREG) VSEN3,4 Falling -- 100 -- mV Output Drive Current (All Linears) VAUX – VDRIVER2,3,4 > 0.6V 20 40 -- mA -- 65 -- dB -- 260 -- 1.746 1.800 1.854 µA V Synchronous PWM Controller Error Amplifier DC Gain PWM Controller Gate Driver UGATE Source RUGATE1 VCC = 12V VCC-VUGATE1 = 1V -- 4 7 Ω UGATE Sink RUGATE1 VUGATE1 = 1V -- 3 7 Ω LGATE Source ILGATE1 VCC = 12V, VLGATE1 = 2V -- 1 -- A LGATE Sink RLGATE1 VLGATE1 = 1V -- 2 6 Ω 112 118 125 % 5 10 -- mA Protection VOUT1 Over-Voltage Trip FB1 Rising FAULT Souring Current VFAULT = 8V OCSET1 Current Source IOCSET VOCSET1 = 4.5V 170 200 230 µA Soft-Start Current ISS13,24 VSS13,SS24 = 2V -- 28 -- µA Power Good VOUT1 Upper Threshold FB1 Rising 108 -- 112 % VOUT1 Under Voltage FB1 Rising 87 -- 92 % VOUT1 Hysteresis (FB1/DACOUT) Upper/Lower Threshold -- 2 -- % VTTPG Upper Threshold VSEN2 Rising -- 1.08 -- V VTTPG Delay Threshold SS13 Rising -- 1.25 -- V VTTPG Voltage Low VVTTPG IVTTPG = -4mA -- -- 0.5 V PGOOD Voltage Low VPGOOD IPGOOD = -4mA -- -- 0.5 V www.richtek-ic.com.tw 6 DS9238-01 July 2001 RT9238 Preliminary Typical Operating Charateristics Frequency vs. VCC IOCSET1 vs. VCC 205 205 TA = 25°C TA = 25°C 203 IOCSET1 (uA) Frequency (KHz) 203 201 199 197 201 199 197 195 10 11 12 13 195 14 10 VCC (Volt) 11 12 13 VOUT1 Line Regulation VOUT2,3,4 Line Regulation 1.00 1 TA = 25°C TA = 25°C 0.6 Percentage (%) Percentage (%) 0.60 0.20 -0.20 -0.60 0.2 -0.2 -0.6 -1.00 -1 10 11 12 13 14 10 11 12 VCC (Volt) 13 14 VCC (Volt) Frequency vs. Temperature 205 IOCSET1 vs. Temperature 300 VCC = 12V VCC = 12V 275 IOCSENT1 (uA) 203 Frequency (KHz) 14 VCC (Volt) 201 199 197 250 225 200 175 195 -40 -20 0 20 40 60 Temperature (°C) DS9238-01 July 2001 80 100 120 150 -40 -20 0 20 40 60 80 100 120 Temperature (°C) www.richtek-ic.com.tw 7 RT9238 Preliminary VOUT2,3,4 vs. Temperature VOUT1 vs. Temperature 1 1 VCC = 12V VCC = 12V 0.6 Percentage (%) Percentage (%) 0.6 0.2 -0.2 -0.6 0.2 -0.2 -0.6 -1 -40 -20 0 20 40 60 80 100 Temperature (°C) 120 -1 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Dead Time Dead Time UGATE1 UGATE1 LGATE1 LGATE1 TT TT T 12 > 1) Ch 1: 2) Ch 2: 12 > 2 Volt 50 n s 2 Volt 50 n s 1 ) Ch 1: 2 ) Ch 2: 2 Volt 5T0 ns 2 Volt 5 0 ns Time Time VOUT2,3,4 Short VOUT1 Short TT FAULT UGATE1 T 1> 3> LGATE1 1> TT TT SS13,24 2> 1) Ch 1 : 2) Ch 2 : 5 Volt 2 5 ms 2 Volt 2 5 ms Time www.richtek-ic.com.tw 8 T SS13,24 2 > 1) Ch 1: 5 Volt 2 5 ms 2) Ch 2: 2 Volt 2 5 ms 3) Ref A: 5 Volt 25 ms Time DS9238-01 July 2001 RT9238 Preliminary Functional Pin Description DRIVE2 (Pin 1) Connect this pin to the gate of an external MOSEFT. when SS13 pin is below 1.25V. This pin provides the drive for the VTT (VOUT2) FAULT/VID4 (Pin 10) regulator’s pass transistor. This pin provides two combined functions. One is fault condition indicator, the other is VID4 for FIX (Pin 2) VRM8.4 DAC (see the Table I). Pull up this pin up to Grounding this pin bypasses the internal resistor over 2V, it act like the VID4 of VRM8.4. When this dividers that set the voltage of the 1.5V and 1.8V pin linear regulators. This way, the output voltage of the 1.890V~2.090V output voltages. two regulators can be adjusted from 1.26V up to the Nominally, the voltage at this pin is pulled low by a input voltage (+3.3V or +5V) by way of an external internal 47kΩ, in the event of an over-voltage or resistor divider corrected at the corresponding VSEN over-current condition, this pin is internally pulled to pin. The new output voltage set by the external about 8V (VCC = 12V). resistor divider can be determined using the following formula: VOUT = 1.265V x (1+ ROUT RGND is pulled high, the DACOUT provide VSEN2 (Pin 11) Connect this pin to the output of the VTT (VOUT2) ) Where ROUT is the resistor connected from VSEN to the output of the regulator, and RGND is the resistor connected from VSEN to ground. Left open, this pin is pulled high enabling fixed output voltage operation. VID25, VID0, VID1, VID2, VID3 (Pin 7, 6, 5, 4, and 3) VID3-25 are TTL-compatible the input pins to the 5bit DAC. The state logic of these five pins program the internal voltage reference, DACOUT. The level of DACOUT sets the microprocessor core converter output voltage, as well as the corresponding PGOOD and OVP thresholds. Table 1 specifies the DACOUT voltage of 32 combinations of VID levels. PGOOD (Pin 8) PGOOD is an open collector output used to indicate the status of the PWM converter output voltage. This pin is pulled low when the synchronous regulator output is not within ±10% of the DACOUT reference voltage, or when any of the other outputs are below their under-voltage thresholds. linear regulator. This pin is also monitored for undervoltage events. SS24 (Pin 12) Connect a capacitor from this pin to ground. This capacitor, along with an internal 28µA (VSS24>1V) current source, sets the soft-start interval of the VOUT2 regulator. Pulling this pin below 0.8V induces a chip reset and shutdown. SS13 (Pin 13) Connect a capacitor from this pin to ground. This capacitor, along with an internal 28µA (VSS13>1V) current source, sets the soft-start interval of the synchronous PWM converter (VOUT1) and the AGP regulator (VOUT3). A VTTPG high signal is also delayed by the time interval required by the charging of this capacitor from 0V to 1.25V. VSEN4 (Pin 14) Connect this pin to the output of the 1.8V regulator. This pin is monitored for under-voltage events. DRIVE4 (Pin 15) VTTPG (Pin 9) Connect this pin to the gate of an external MOSEFT. VTTPG is an open collector output used to indicate This pin provides the drive for the 1.8V regulator’s the status of the VTT (VOUT2) regulator output pass transistor. voltage. This pin is pulled low when the output voltage is below 1.08V under-voltage threshold or DS9238-01 July 2001 www.richtek-ic.com.tw 9 RT9238 Preliminary VAUX (Pin 16) This pin provides boost current for the three linear An over-current trip cycles the soft-start function. The regulator output drives in the event bipolar NPN voltage at this pin is monitored for power-on reset transistors (instead of N-channel MOSFETs) are (POR) purpose and pulling this pin low with an open employed as pass elements. The voltage at this pin drain device will shut down the IC. is monitored for power-on reset (POR) purpose. PGND (Pin 24) GND (Pin 17) This is the power ground of UGATE1&LGATE1. Tie Signal ground for the IC. All voltage levels are the synchronous PWM converter’s lower MOSFET measured with respect to this pin. source to this pin. DRIVE3 (Pin 18) LGATE1 (Pin 25) Connect this pin to the gate of an external MOSEFT. Connect LGATE1 to the PWM converter’s lower This pin provides the drive for the 1.5V regulator’s MOSFET gate. This pin provides the gate drive for pass transistor. the lower MOSFET. VSEN3 (Pin 19) Connect this pin to the output of the 1.5V linear regulator. This pin is monitored for under-voltage events. PHASE1 (Pin 26) This pin is used to monitor the voltage drop across the upper MOSFET for over-current protection. This pin is also used to sense lower MOSFET voltage drop for VOUT1 voltage droop tuning. ICOMP (Pin 20) UGATE1 (Pin 27) This pin is non-inverting input of the PWM error Connect UGATE1 pin to the PWM converter’s upper amplifier. It determine the VOUT1 voltage. Connect a MOSFET gate. This pin provides the gate drive for resistor (RF) to VDAC pin. A sense current of lower the upper MOSFET. MOSFET is fed to this pin to pull low the DACOUT voltage. (see VDAC) VDAC (Pin 21) This pin is internal DAC buffer output. Connect a resistor(RF) from this pin to ICOMP pin. The resistor provide a voltage drop rated from lower MOSFET VCC (Pin 28) Provide a 12V supply voltage for the IC to this pin. This pin also provides the gate bias charge for all the MOSFETs controlled by the IC. The voltage at this pin monitored for power-on reset (POR) purpose. turn on voltage drop. A sample hold circuit sense the voltage drop of lower MOSFET(IL x RDSON ) when LGATE1 turn on. The ratio is : (IL x RDSON ) x RF/3k FB1 (Pin 22) This pin is connected to the PWM converter’s output voltage. This pin also connects to internal PWM error amplifier inverting input and power good monitor. OCSET1 (Pin 23) Connect a resistor from this pin to the drain of the respective upper MOSFET. This resistor, an internal 200µA current source, and the upper MOSFET onresistance set the converter over-current trip point. www.richtek-ic.com.tw 10 DS9238-01 July 2001 RT9238 Preliminary Functional Description Operation The RT9238 monitors and precisely controls 4 output input supplies ramp up. Immediately following, OUT4 voltage levels (Refer to Figures 1, 2, and function is also ramped up, lagging the ATX 3.3V by about block). It is designed for microprocessor computer 1.8V. At time T1, the POR function initiates the SS24 applications with 3.3V, 5V, and 12V bias input from soft-start sequence. Initially, the voltage on the SS24 an ATX power supply. The IC has one PWM and pin rapidly increases to approximately 1V (this three linear controllers. The PWM controller is minimizes the soft-start interval). Then, an internal designed to regulate the microprocessor core voltage 28µA current source charges an external capacitor (VOUT1). The PWM controller drives 2 MOSFETs (Q1 (CSS24) on the SS24 pin to about 4.5V. As the SS24 and Q2) in a synchronous-rectified buck converter voltage increases, the EA2 error amplifier drives Q3 configuration and regulates the core voltage to a level to provide a smooth transition to the final set voltage. programmed by the 5-bit digital-to-analog converter The OUT4 reference (clamped to SS24) increasing (DAC). The first linear controller (EA2) is designed to past the intermediary level, established based on the provide the AGTL+ bus voltage (VOUT2) by driving a ATX 3.3V presence at the VAUX pin, brings the MOSFET (Q3) pass element to regulate the output output in regulation soon after T2. voltage to a level of 1.2V. The remaining two linear controllers (EA3 and EA4) supply the 1.5V advanced As OUT2 increases past the 90% power-good level, graphics port (AGP) bus power (VOUT3) and the 1.8V the second soft-start (SS13) is released. Between T2 chipset core power (VOUT4). Initialization The RT9238 automatically initializes in ATX-based systems upon receipt of input power. The Power-On Reset (POR) function continually monitors the input supply voltages. The POR monitors the bias voltage (+12VIN) at the VCC pin, the 5V input voltage (+5VIN) at the OCSET pin, and the 3.3V input voltage (+3.3VIN) at the VAUX pin. The normal level on OCSET is equal to +5VIN less a fixed voltage drop (see over-current protection). The POR function initiates soft-start operation after all supply voltages exceed their POR thresholds. and T3, the SS13 pin voltage ramps from 0V to the valley of the oscillator’s triangle wave (at 1.25V). Contingent upon OUT2 remaining above 1.08V, the first PWM pulse on PHASE1 triggers the VTTPG pin to go high. The oscillator’s triangular wave form is compared to the clamped error amplifier output voltage. As the SS13 pin voltage increases, the pulse-width on the PHASE1 pin increases, bringing the OUT1 output within regulation limits. Similarly, the SS13 voltage clamps the reference voltage for OUT3, enabling a controlled output voltage ramp-up. At time T4, all output voltages are within power-good limits, situation reported by the PGOOD pin going high. Soft-Start The T2 to T3 time interval is dependent upon the The 1.8V supply designed to power the chipset value of CSS13. The same capacitor is also (OUT4), cannot lag the ATX 3.3V by more than 2V, at responsible for the ramp-up time of the OUT1 and any time. To meet this special requirement, the linear OUT3 voltages. If selecting a different capacitor then block controlling this output operates independently recommended in the circuit application literature, of the chip’s power-on reset. Thus, DRIVE4 is driven consider the effects the different value will have on to raise the OUT4 voltage before the input supplies the ramp-up time and inrush currents of the OUT1 reach their POR levels. As seen in Fig.3, at time T0 and OUT3 outputs. the power is turned on and the DS9238-01 July 2001 www.richtek-ic.com.tw 11 RT9238 Preliminary VSEN4) is ignored until the respective UP signal ATX12V goes high. This allows VOUT3 and VOUT4 to increase 10V VTTPG SS13 without fault at start-up. Following an over-current event (OC1, UV2, or UV3 event), bringing the SS24 ATX5V pin below 0.8V resets the over-current latch and SS24 generates a soft-started ramp-up of the outputs 1, 2, PGOOD 0V and 3. 3.0V ATX3.3V VOUT4 (1.8V) VOUT1 (1.65V) SS13UP UV3 OC LATCH S OC1 VOUT3 (1.5V) 4V T3 T4T5 TIME 0.8V SS24 + Fig.3 Soft-start Interval FAULT LATCH 4V SS24UP POR _ T2 _ T1 R + T0 SSDOWN COUNTER + SS13 0V INHIBIT 1,2,3 Q R _ VOUT2 (1.2V) S Q R Q OV Fault Protection UV4 OC LATCH All four outputs are monitored and protected against extreme overload. The chip’s response to an output overload is selective, depending on the faulting FAULT R COUNTER R S UV2 Q output. Fig.4 Fault Logic-simplified Schematic An over-voltage on VOUT1 output (FB1) disables outputs 1, 2, and 3, and latches the IC off. An undervoltage on VOUT4 output latches the IC off. A single over-current event on output 1, or an under-voltage event on output 2 or 3, increments the respective fault counters and triggers a shutdown of outputs 1, 2, and 3, followed by a soft-start re-start. After three consecutive fault events on either counter, the chip is latched off. Removal of bias power resets both the fault latch and the counters. Both counters are also reset by a successful start-up of all the outputs. Fig.3 shows a simplified schematic of the fault logic. The over-current latches are set dependent upon the states of the over-current (OC1), output 2 and 3 under-voltage (UV2, UV3) and the soft-start signals (SS13, SS24). Window comparators monitor the SS pins and indicate when the respective CSS pins are OUT1 Over-Voltage Protection During operation, a short across the synchronous PWM upper MOSFET (Q1) causes VOUT1 to increase. When the output exceeds the over-voltage threshold of 115% of DACOUT, the over-voltage comparator trips to set the fault latch and turns the lower MOSFET (Q2) on. This blows the input fuse and reduces VOUT1. A separate over-voltage circuit provides protection during the initial application of power. For voltages on the VCC pin below the power-on reset (and above ~4V), the output level is monitored for voltages above 1.3V. Should FB1 exceed this level, the lower MOSFET, Q2, is driven on. Over-Current Protection fully charged to above 4.0V (UP signals). An under- All outputs are protected against excessive over- voltage on either linear output (VSEN2, VSEN3, or currents. The PWM controller uses the upper www.richtek-ic.com.tw 12 DS9238-01 July 2001 RT9238 Preliminary MOSFET’s on-resistance, RDS(ON) to monitor the The three linear controllers monitor their respective current for protection against a shorted output. All VSEN pins for under-voltage. Should excessive linear regulators monitor their respective VSEN pins currents cause VSEN3 or VSEN4 to fall below the for under-voltage to protect against excessive linear under-voltage threshold, the respective UV currents. signals set the OC latch or the FAULT latch, Fig.5 illustrates the over-current protection with an overload on OUT1. The overload is applied at T0 and the current increases through the inductor (LOUT1). At time T1, the OC1 comparator trips when the voltage across Q1 (iD•RDS(ON)) exceeds the level programmed by ROCSET . This inhibits outputs 1, 2, and 3, discharges the soft-start capacitor CSS24 with 28µA current sink, and increments the counter. Softstart capacitor CSS13 is quickly discharged. CSS13 starts ramping up at T2 and initiates a new soft-start cycle. With OUT2 still overloaded, the inductor current increases to trip the over-current comparator. Again, this inhibits the outputs, but the CSS24 softstart voltage continues increasing to above 4.0V before discharging. Soft-start capacitor CSS13 is, again, quickly discharged. The counter increments to 2. The soft-start cycle repeats at T3 and trips the over-current comparator. The SS24 pin voltage increases to above 4.0V at T4 and the counter increments to 3. This sets the fault latch to disable providing FAULT/RT are fully resets the counter and the fault latch. An external resistor (ROCSET) programs the overcurrent trip level for the PWM converter. As shown in Fig.6, the internal 200µA current sink (IOCSET) develops a voltage across ROCSET (VSET) that is referenced to VIN. The DRIVE signal enables the over-current comparator (OC). When the voltage across the upper MOSFET (VDS(ON)) exceeds VSET, the over-current comparator trips to set the overcurrent latch. Both VSET and VDS are referenced to VIN and a small capacitor across ROCSET helps VOCSET track the variations of VIN due to MOSFET switching. The over-current function will trip at a peak inductor current (IPEAK) determined by: IOCSET × ROCSET RDS(ON) The OC trip point varies with MOSFET’s RDS(ON) temperature variations. To avoid over-current tripping FAULT REPORTED 0V in the normal operating load range, determine the COUNT = 1 COUNT = 2 SS 24 SS 13 capacitors operation. Cycling the bias input power off then on IPEAK = 10V CSS above the under-voltage threshold during normal the converter. INDUCTOR CURRENT respective charged. Blanking the UV signals during the CSS charge interval allows the linear outputs to build COUNT = 3 4V ROCSET resistor value from the equation above with: 2V 1. The maximum RDS(ON) at the highest junction 0V temperature OVERLOAD APPLIED 2. The minimum IOCSET from the specification table 3. Determine IPEAK for IPEAK > IOUT(MAX) + (∆I)/ 2, where ∆I is the output inductor ripple current. 0A T0T1 T3T4 T2 TIME Fig.5 Over-current Operation DS9238-01 July 2001 For an equation for the ripple current see the section under component guidelines titled ‘Output Inductor Selection’. www.richtek-ic.com.tw 13 RT9238 Preliminary 1.865V which are shifted high 40mV from 1.050V to OVER-CURRENT TRIP: 1.825V for voltage droop gap tuning. This output VDS > VSET iD ×R DS(ON) > IOCSET × ROCSET (OUT1) is designed to supply the core voltage of VIN = +5V Intel’s ROCSET OCSET VSET+ IOCSET 200µA voltage digital-to-analog converter (DAC). The level of UGATE VDS+ DACOUT also sets the PGOOD and OVP thresholds. Table 1 specifies the DACOUT voltage for the _ PWM The reference (DACOUT) with a TTL-compatible 5-bit + OC microprocessors. identification (VID) pins program an internal voltage iD VCC DRIVE advanced different combinations of connections on the VID PHASE GATE pins. The VID pins can be left open for a logic 1 input, VPHASE = VIN - VDS CONTROL since they are internally pulled to the VAUX pin VOCSET = VIN - VSET through 5KΩ resistors. Changing the VID inputs Fig.6 Current Limiting Setting during operation is not recommended and could OUT1 Voltage Program toggle the PGOOD signal and exercise the over- The output voltage of the PWM converter is voltage protection. The output voltage program is programmed to discrete levels between 1.090V and Intel VRM8.5 compatible. Table 1. VOUT1 Voltage Program Pin Name VID4 VID3 VID2 VID1 VID0 VID25 DACOUT 0 0 1 0 0 0 1.050+40mV=1.090 0 0 1 0 0 1 1.075+40mV=1.115 0 0 0 1 1 0 1.100+40mV=1.140 0 0 0 1 1 1 1.125+40mV=1.165 0 0 0 1 0 0 1.150+40mV=1.190 0 0 0 1 0 1 1.175+40mV=1.215 0 0 0 0 1 0 1.200+40mV=1.240 0 0 0 0 1 1 1.225+40mV=1.265 0 0 0 0 0 0 1.250+40mV=1.290 0 0 0 0 0 1 1.275+40mV=1.315 0 1 1 1 1 0 1.300+40mV=1.340 0 1 1 1 1 1 1.325+40mV=1.365 0 1 1 1 0 0 1.350+40mV=1.390 0 1 1 1 0 1 1.375+40mV=1.415 0 1 1 0 1 0 1.400+40mV=1.440 0 1 1 0 1 1 1.425+40mV=1.465 0 1 1 0 0 0 1.450+40mV=1.490 0 1 1 0 0 1 1.475+40mV=1.515 0 1 0 1 1 0 1.500+40mV=1.540 To be continued www.richtek-ic.com.tw 14 Normal OUT1 Voltage DS9238-01 July 2001 RT9238 Preliminary Pin Name Normal OUT1 Voltage VID4 VID3 VID2 VID1 VID0 VID25 DACOUT 0 1 0 1 1 1 1.525+40mV=1.565 0 1 0 1 0 0 1.550+40mV=1.590 0 1 0 1 0 1 1.575+40mV=1.615 0 1 0 0 1 0 1.600+40mV=1.640 0 1 0 0 1 1 1.625+40mV=1.665 0 1 0 0 0 0 1.650+40mV=1.690 0 1 0 0 0 1 1.675+40mV=1.715 0 0 1 1 1 0 1.700+40mV=1.740 0 0 1 1 1 1 1.725+40mV=1.765 0 0 1 1 0 0 1.750+40mV=1.790 0 0 1 1 0 1 1.775+40mV=1.815 0 0 1 0 1 0 1.800+40mV=1.840 0 0 1 0 1 1 1.825+40mV=1.865 1 0 1 0 0 0 1.850+40mV=1.890 1 0 0 1 1 0 1.900+40mV=1.940 1 0 0 1 0 0 1.950+40mV=1.990 1 0 0 0 1 0 2.000+40mV=2.040 1 0 0 0 0 0 2.050+40mV=2.090 Notes: 0=connect to GND, 1=open or connect to 3.3V through pull up resistor Application Guidelines Soft-Start Interval Shutdown Initially, the soft-start function clamps the error The PWM output does not switch until the soft-start amplifier’s output of the PWM converter. This voltage (VSS13) exceeds the oscillator’s generates PHASE pulses of increasing width that voltage. Additionally, the reference on each linear’s charge the output capacitor(s). The resulting output amplifier is clamped to the soft-start voltage. Holding voltages start-up as shown in Fig.3. the SS24 pin low (with an open drain or open valley collector signal) turns off regulators 1, 2 and 3. The soft-start function controls the output voltage rate Regulator 4 (MCH) will simply drop its output to the of rise to limit the current surge at start-up. The soft- intermediate soft-start level. This output is not start interval and the surge current are programmed allowed to violate the 2V maximum potential gap to by the soft-start capacitor, CSS. Programming a the ATX 3.3V output. faster soft-start interval increases the peak surge current. Using the recommended 0.1µF soft start capacitors ensure all output voltages ramp up to their set values in a quick and controlled fashion, while meeting the system timing requirements. DS9238-01 July 2001 Layout Considerations MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit www.richtek-ic.com.tw 15 RT9238 Preliminary elements. The voltage spikes can degrade efficiency, component ground connections with vias to this layer. radiate noise into the circuit, and lead to device over- Dedicate another solid layer as a power plane and voltage stress. Careful component layout and printed break this plane into smaller islands of common circuit design minimizes the voltage spikes in the voltage levels. The power plane should support the converter. Consider, as an example, the turn-off input power and output power nodes. Use copper transition of the upper MOSFET. Prior to turn-off, the filled polygons on the top and bottom circuit layers for upper MOSFET was carrying the full load current. the PHASE node, but do not unnecessarily oversize During the turn-off, current stops flowing in the upper this particular island. Since the PHASE node is MOSFET and is picked up by the lower MOSFET or subject to very high dV/dt voltages, the stray Schottky diode. Any inductance in the switched capacitor formed between these island and the current path generates a large voltage spike during surrounding circuitry will tend to couple switching the switching interval. Careful component selection, noise. Use the remaining printed circuit layers for tight layout of the critical components, and short, small signal wiring. The wiring traces from the control wide circuit traces minimize the magnitude of voltage IC to the MOSFET gate and source should be sized spikes. to carry 2A peak currents. There are two sets of critical components in a DC-DC CIN switch large amounts of energy, and as such, they tend to generate equally large amounts of noise. The +12V CVCC +3.3VIN VCC critical small signal components are those connected VOUT2 to sensitive nodes or those supplying critical bypass COUT2 The power components and the controller IC should the high-frequency ceramic de-coupling capacitors, close to the power switches. Locate the output inductor and output capacitors between the MOSFETs and the load. Locate the PWM controller Q1 SS13 CSS24,13 LOUT PHASE SS24 COUT1 Q2 LGATE CR1 VOUT1 RT9238 VOUT3 LOAD be placed first. Locate the input capacitors, especially ROCSET DRIVE2 UGATE LOAD current. Q3 COCSET GND OCSET LOAD power components are the most critical because they LIN +5VIN VOUT4 COUT3 Q4 DRIVE3 DRIVE4 PGND LOAD converter using an RT9238 controller. The switching Q5 COUT4 close to the MOSFETs. The critical small signal components include the bypass capacitor for VCC and the soft-start capacitor, CSS. Locate these components close to their connecting pins on the control IC. Minimize any ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT PLANE LAYER VIA/THROUGH-HOLE CONNECTION TO GROUND PLANE leakage current paths from any SS node, since the Fig.7 Layout Planning internal current source is only 28µA. PWM1 Controller Feedback Compensation A multi-layer printed circuit board is recommended. The PWM controller uses voltage-mode control for Fig.7 output shows the connections of the critical regulation. An internal pole-zero components in the converter. Note that the capacitors compensation scheme is used with an active CIN and COUT each could represent numerous capacitor and a passive resistor shown in Fig.8. The physical capacitors. Dedicate one solid layer for a zero FZ1 is fixed at about 1kHz to compensate the ground plane and make all critical output ‘s LC pole FLC. The compensation is to www.richtek-ic.com.tw 16 DS9238-01 July 2001 RT9238 Preliminary Volt provide closed loop transfer function with 0 dB crossing frequency and adequate phase margin. For Fig.9 VCORE 4µH/6000µF, 3uH/8000uF or 2µH/12000µF. VCORE Maximum 1.70 some suggestion LC combinations are L/C = shows an asymptotic plot of the DC-DC converter’s gain vs. frequency. VCORE Typical VCORE Minimum 1.60 + EA _ 10 20 30 A Fig.11 VCORE Load Line Active Cap Two things have to be completed at load transient Fig.8 Error Amplifier Compensation response, first is to sense the instantaneous load current, second is real time to drop the VCORE voltage based on the loadlines. A RT9238 internal transconductance (Gm) amplifier sample the on-state drop 100 across the lower MOSFET per clock cycle, the 80 voltage drop is simply RDS-ON X inductor current IL. In 60 step-down DC-DC converter, the IL is relative to load COMPENSATION 40 FZ1 20 0 20log -20 1/3k, this mean the current output of Gm amplifier is FP1 ISENSE = RDS(ON) x IL/3k. CLOSED LOOP GAIN FLC FESR Fig.12 shown the voltage droop tuning circuit, a DACOUT buffer amplifier connect a RF resistor to the non-inverting input of the PWM error amplifier, when MODULATOR GAIN -40 -60 VIN VP-P current. The transferred rate of the Gm amplifier is load transient happened, the feedback ISENSE current fitted to the non-inverting input of the PWM error 10 100 1K 10K 100K 1M amplifier to drop the VCORE voltage. The drop voltage is equal to Fig.9 PWM Bode Plot VDROOP = ISENSE x RF Transient Response V5V IM1 Modern micro-processsor’s power supply request a loadlines at static state load changing as shown in Sample Hold + Fig.10, and Fig.11. Gm_ LG RS RS VCORE IM2 + Rds-on Low Side Current Sense Error Amp _ COMP RF VNI Isense DAC Buffer + REF _ VCORE Ripple Fig.10 Transient Response IL PHASE + ∆ IO UG Control Logic voltage droop at load transient response and a REFOUT Reference Output Fig.12 Voltage Droop Tuning DS9238-01 July 2001 www.richtek-ic.com.tw 17 RT9238 Preliminary Fig.13, 14 shown the ISENSE and VCORE wave forms. PWM Output Capacitors Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient current and slow the load rate-ofchange seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the 0µA ESR (effective series resistance) and voltage rating requirements ISENSE -20µA rather than actual capacitance requirements. -40µA High frequency decoupling capacitors should be -60µA placed as close to the power pins of the load as physically possible. Be careful not to add inductance -80µA 1.6ms 1.8ms 2.0ms in the circuit board wiring that could cancel the Time Time usefulness of these low inductance components. Fig.13 ISENSE Current Consult with the manufacturer of the load on specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching-regulator 1.4V applications for the bulk capacitors. The bulk capacitor’s ESR determines the VCORE output ripple voltage and the initial voltage drop following a high slew-rate transient’s edge. An 1.3V aluminum electrolytic capacitor’s ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with 1.2V 1.6ms 1.8ms 2.0ms 2.2ms Time Time Fig.14 VCORE Wave Form at Load Transient case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a Component Selection Guidelines Output Capacitor Selection The output capacitors for each output have unique suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. requirements. In general the output capacitors should Linear Output Capacitors be regulation The output capacitors for the linear regulators provide converter dynamic load current. Thus capacitors COUT2, COUT3, requires an output capacitor to filter the current ripple. and COUT4 should be selected for transient load The load transient for the microprocessor core regulation. requires high quality capacitors to supply the high PWM Output Inductor Selection slew rate (di/dt) current demands. The PWM converter requires an output inductor. The selected requirements. to meet the Additionally, dynamic the PWM output inductor is selected to meet the output voltage ripple requirements and sets the converter’s www.richtek-ic.com.tw 18 DS9238-01 July 2001 RT9238 Preliminary determines the converter’s ripple current and the Input Capacitor Selection The important parameters for the bulk input capacitor ripple voltage is a function of the ripple current. The are the voltage rating and the RMS current rating. For ripple voltage and current are approximated by the reliable operation, select bulk input capacitors with following equations: voltage and current ratings above the maximum input response time to a load transient. The inductor value voltage and largest RMS current required by the VIN − VOUT VOUT ∆I = × FS × L VIN ∆VOUT = ∆I × ESR Increasing the value of inductance reduces the ripple current and voltage. However, large inductance values increase the converter’s response time to a load transient. circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage. The maximum RMS current rating requirement for the input capacitors of a buck regulator is approximately 1/2 of the DC output load current. Worst-case RMS current draw in a circuit employing the RT9238 amounts to the largest RMS current draw of the One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the RT9238 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time interval required to slew the inductor current from an initial current value to the post-transient current level. During this interval the difference between the switching regulator. Use a mix of input bypass capacitors to control the voltage ceramic overshoot across capacitance for the MOSFETs. the high Use frequency decoupling and bulk capacitors to supply the RMS current. Small ceramic capacitors can be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedances. inductor current and the transient current level must For a through-hole design, several electrolytic be supplied by the output capacitor(s). Minimizing the capacitors (Panasonic HFQ series or Nichicon PL response time can minimize the output capacitance series or Sanyo MV-GX or equivalent) may be required. needed. For surface mount designs, solid tantalum The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: tRISE = capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge current at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested. LO × ITRAN VIN − VOUT tFALL = LO × ITRAN VOUT MOSFET Selection/Considerations The RT9238 requires 5 external transistors. Two Nchannel MOSFETs are employed by the PWM where: ITRAN is the transient load current step, tRISE converter. The GTL, AGP, and memory linear is the response time to the application of load, and controllers can each drive a MOSFET or a NPN tFALL is the response time to the removal of load. Be bipolar as a pass transistor. All these transistors sure to check both of these equations at the minimum and maximum output levels for the worst case should be selected based upon RDS(ON) , current gain, saturation voltages, gate supply requirements, response time. and thermal management considerations. DS9238-01 July 2001 www.richtek-ic.com.tw 19 RT9238 Preliminary gate-to-source voltage rating exceeds the maximum PWM MOSFET Selection and Considerations In high-current PWM applications, the MOSFET voltage applied to VCC. power dissipation, package selection and heatsink are the dominant design factors. The +12V power +5V OR LESS VCC dissipation includes two main loss components: conduction losses and switching losses. These UGATE losses are distributed between the upper and lower PHASE according to the duty factor. NOTE: VGS ≈ VCC - 5V The conduction losses are the main component of power + dissipation for the lower MOSFETs. Only the upper LGATE _ MOSFET Q1 PGND MOSFET has significant switching losses, since the current transitions and do not model power losses CR1 NOTE: VGS ≈ 8V GND lower device turns on and off into near zero voltage. The equations presented assume linear voltage- Q2 Fig.15 Upper Gate Drive-direct VCC Drive due to the lower MOSFET’s body diode or the output Rectifier CR1 is a clamp that catches the negative capacitances associated with either MOSFET. The inductor swing during the dead time between the turn gate charge losses are dissipated by the controller IC off of the lower MOSFET and the turn on of the upper (RT9238) and do not contribute to the MOSFETs’ MOSFET. For best results, the diode must be a heat rise. Ensure that both MOSFETs are within their surface-mount Schottky type to prevent the parasitic maximum junction temperature at high ambient MOSFET temperature by calculating the acceptable to omit the diode and let the body diode of according to specifications. package A temperature rise thermal separate heatsink resistance may body diode from conducting. It is the lower MOSFET clamp the negative inductor be swing, but one must ensure the PHASE node necessary depending upon MOSFET power, package negative voltage swing does not exceed -3V to -5V type, ambient temperature and air flow. peak. The diode’s rated reverse breakdown voltage must be equal or greater to 1.5 times the maximum 2 PUPPER = IO × RDS(ON) × VOUT PLOWER = VIN + IO × VIN × tSW × FS 2 IO 2 × RDS(ON) × ( VIN − VOUT ) VIN The RDS(ON) is different for the two equations above even if the same device is used for both. This is because the gate drive applied to the upper MOSFET is different than the lower MOSFET. Fig.15 shows the input voltage. Linear Controllers Transistor Selection The RT9238 linear controllers are compatible with both NPN bipolar as well as N-channel MOSFET transistors. The main criteria for selection of pass transistors for the linear regulators is package selection for efficient removal of heat. The power dissipated in a linear regulator is PLINEAR = IO × ( VIN − VOUT ) gate drive where the upper MOSFET’s gate-tosource voltage is approximately VCC less the input Select a package and heatsink that maintains the supply. For +5V main power and +12VDC for the junction temperature below the maximum desired bias, the approximate gate-to-source voltage of Q1 is temperature with the maximum expected ambient 7V. The lower gate drive voltage is about 8V. A logic- temperature. level MOSFET is a good choice for Q1 and a logiclevel MOSFET can be used for Q2 if its absolute www.richtek-ic.com.tw 20 When selecting bipolar NPN transistors for use with the linear controllers, insure the current gain at the DS9238-01 July 2001 Preliminary RT9238 given operating VCE is sufficiently large to provide the desired output load current when the base is fed with the minimum driver output current. In order to ensure the strict timing/level requirement of OUT4, a NPN transistor is recommended for use as a pass element on this output (Q5). An low gate threshold NMOS could be used, but meeting the requirements would then depend on the VCC bias being sufficiently high to allow control of the MOSFET. DS9238-01 July 2001 www.richtek-ic.com.tw 21 RT9238 Preliminary Package Information H M B B J A C F Symbol www.richtek-ic.com.tw 22 D I Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 17.704 18.110 0.697 0.713 B 7.391 7.595 0.291 0.299 C 2.362 2.642 0.093 0.104 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.229 0.330 0.009 0.013 I 0.102 0.305 0.004 0.012 J 10.008 10.643 0.394 0.419 M 0.381 1.270 0.015 0.050 DS9238-01 July 2001 RT9238 DS9238-01 July 2001 Preliminary www.richtek-ic.com.tw 23 RT9238 Preliminary RICHTEK TECHNOLOGY CORP. RICHTEK TECHNOLOGY CORP. Headquarter Taipei Office (Marketing) 6F, No. 35, Hsintai Road, Chupei City 8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5510047 Fax: (8863)5537749 Tel: (8862)89191466 Fax: (8862)89191465 Email: [email protected] www.richtek-ic.com.tw 24 DS9238-01 July 2001