IRF9Z34S, SiHF9Z34S www.vishay.com Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • • • • • • • -60 RDS(on) () VGS = -10 V 0.14 Qg max. (nC) 34 Qgs (nC) 9.9 Qgd (nC) 16 Configuration Single Advanced process technology Surface mount (IRF9Z34S, SiHF9Z34S) 175 °C operating temperature Available Fast switching P-channel Available Fully avalanche rated Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 Note * This datasheet provides information about parts that are RoHS-compliant and / or parts that are non-RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details. S D2PAK (TO-263) DESCRIPTION G Third generation power MOSFETs from Vishay utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D2PAK is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D2PAK is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0 W in a typical surface mount application. G D D S P-Channel MOSFET ORDERING INFORMATION Package Lead (Pb)-free and Halogen-free Lead (Pb)-free D2PAK (TO-263) D2PAK (TO-263) D2PAK (TO-263) SiHF9Z34S-GE3 SiHF9Z34STRL-GE3 a SiHF9Z34STRR-GE3 a IRF9Z34SPbF IRF9Z34STRLPbF a IRF9Z34STRRPbF a Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS -60 Gate-Source Voltage VGS ± 20 Continuous Drain Current Pulsed Drain VGS at -10 V TC = 25 °C TC = 100 °C Current a, e ID IDM Linear Derating Factor UNIT V -18 -13 A -72 0.59 W/°C mJ Single Pulse Avalanche Energy b, e EAS 370 Avalanche Current a IAR -18 A Repetitive Avalanche Energy a EAR 8.8 mJ Maximum Power Dissipation TC = 25 °C TA = 25 °C Peak Diode Recovery dV/dt c, e Operating Junction and Storage Temperature Range Soldering Recommendations (Peak temperature) d for 10 s PD 88 3.7 dV/dt -4.5 TJ, Tstg -55 to +175 300 W V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = - 25 V, starting TJ = 25 °C, L = 1.3 mH, Rg = 25 , IAS = - 18 A (see fig. 12). c. ISD - 18 A, dI/dt 170 A/μs, VDD VDS, TJ 175 °C. d. 1.6 mm from case. e. Uses IRF9Z34, SiHF9Z34 data and test conditions. S16-0754-Rev. E, 02-May-16 Document Number: 91093 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF9Z34S, SiHF9Z34S www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient (PCB mounted, steady-state) a RthJA - 40 Maximum Junction-to-Case (Drain) RthJC - 1.7 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS VDS VGS = 0 V, ID = -250 μA MIN. TYP. MAX. UNIT -60 - - V V/°C Static Drain-Source Breakdown Voltage VDS Temperature Coefficient VDS/TJ - -0.06 - VGS(th) VDS = VGS, ID = -250 μA -2.0 - -4.0 V Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = -60 V, VGS = 0 V - - -100 VDS = -48 V, VGS = 0 V, TJ = 150 °C - - -500 Gate-Source Threshold Voltage Drain-Source On-State Resistance Forward Transconductance Reference to 25 °C, ID = -1 mA c μA - - 0.14 gfs VDS = -25 V, ID = -11 A c 5.9 - - S VGS = 0 V, VDS = -25 V, f = 1.0 MHz, see fig. 5 c - 1100 - - 620 - - 100 - - - 34 - - 9.9 - 16 RDS(on) ID = -11 A b VGS = -10 V Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss pF Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd - Turn-On Delay Time td(on) - 18 - tr VDD = -30 V, ID = -18 A, Rg = 12 , RD = 1.5 , see fig. 10 b, c - 120 - - 20 - - 58 - f = 1 MHz, open drain 0.7 - 3.9 - - -18 S - - -72 TJ = 25 °C, IS = -18 A, VGS = 0 V b - - -6.3 V - 100 200 ns - 280 520 nC Rise Time Turn-Off Delay Time td(off) Fall Time tf Gate Input Resistance Rg VGS = -10 V ID = -18 A, VDS = -48 V, see fig. 6 and 13 b, c nC ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Current a ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p -n junction diode D A G TJ = 25 °C, IF = -18 A, dI/dt = 100 A/μs b, c Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes b. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). c. Pulse width 300 μs; duty cycle 2 %. d. Uses IRF9Z34, SiHF9Z34 data and test conditions. S16-0754-Rev. E, 02-May-16 Document Number: 91093 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF9Z34S, SiHF9Z34S www.vishay.com Vishay Siliconix VGS - 15 V - 10 V - 8.0 V - 7.0 V - 6.0 V - 5.5 V - 5.0 V Bottom - 4.5 V - ID, Drain Current (A) Top 101 - 4.5 V 100 20 µs Pulse Width TC = 25 °C 10-1 100 101 - VDS, Drain-to-Source Voltage (V) 91093_01 - ID, Drain Current (A) 2.0 1.5 1.0 0.5 0.0 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 180 TJ, Junction Temperature (°C) 2000 VGS Top - 15 V - 10 V - 8.0 V - 7.0 V - 6.0 V - 5.5 V - 5.0 V Bottom - 4.5 V 101 ID = - 18 A VGS = - 10 V Fig. 4 - Normalized On-Resistance vs. Temperature Fig. 1 - Typical Output Characteristics 102 2.5 91093_04 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd 1600 - 4.5 V Capacitance (pF) 102 RDS(on), Drain-to-Source On Resistance (Normalized) TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 1200 Ciss 800 Coss 400 100 Crss 20 µs Pulse Width TC = 175 °C 100 10-1 100 - VDS, Drain-to-Source Voltage (V) 91093_02 0 101 - VDS, Drain-to-Source Voltage (V) 91093_05 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 2 - Typical Output Characteristics 25 °C 175 °C 101 20 µs Pulse Width VDS = - 25 V - VGS, Gate-to-Source Voltage (V) - ID, Drain Current (A) 20 100 101 ID = - 18 A VDS = - 48 V 16 VDS = - 30 V 12 8 4 For test circuit see figure 13 0 4 91093_03 5 6 7 8 9 - VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S16-0754-Rev. E, 02-May-16 10 0 91093_06 5 10 15 20 25 30 35 QG, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91093 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF9Z34S, SiHF9Z34S www.vishay.com Vishay Siliconix 101 - ID, Drain Current (A) - ISD, Reverse Drain Current (A) 20 175 °C 25 °C 100 VGS = 0 V 0.0 1.0 2.0 4.0 3.0 4 50 75 100 125 150 175 TC, Case Temperature (°C) 91093_09 Fig. 9 - Maximum Drain Current vs. Case Temperature RD 103 VDS Operation in this area limited by RDS(on) 5 - ID, Drain Current (A) 8 25 Fig. 7 - Typical Source-Drain Diode Forward Voltage VGS 2 D.U.T. Rg 102 +VDD 10 µs 5 100 µs - 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 2 1 ms 10 Fig. 10a - Switching Time Test Circuit 5 10 ms TC = 25 °C TJ = 175 °C Single Pulse 2 1 0.1 12 0 5.0 - VSD, Source-to-Drain Voltage (V) 91093_07 16 2 5 1 2 5 10 2 td(on) 5 102 2 5 td(off) tf tr VGS 103 10 % - VDS, Drain-to-Source Voltage (V) 91093_08 Fig. 8 - Maximum Safe Operating Area 90 % VDS Fig. 10b - Switching Time Waveforms Thermal Response (ZthJC) 10 1 D = 0.5 0.2 PDM 0.1 0.1 0.05 t1 Single Pulse (Thermal Response) 0.02 0.01 t2 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC 10-2 10-5 91093_11 10-4 10-3 10-2 0.1 1 10 t1, Rectangular Pulse Duration (s) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case S16-0754-Rev. E, 02-May-16 Document Number: 91093 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF9Z34S, SiHF9Z34S www.vishay.com Vishay Siliconix L Vary tp to obtain required IAS IAS VDS VDS D.U.T. Rg + V DD VDD IAS tp - 10 V 0.01 Ω tp VDS Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms EAS, Single Pulse Energy (mJ) 1200 ID - 7.3 A - 13 A Bottom - 18 A Top 1000 800 600 400 200 0 VDD = - 25 V 25 91093_12c 50 75 100 125 150 175 Starting TJ, Junction Temperature (°C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG - 10 V 12 V 0.2 µF 0.3 µF QGS - QGD D.U.T. VG + VDS VGS - 3 mA Charge IG ID Current sampling resistors Fig. 13 - Maximum Avalanche Energy vs. Drain Current S16-0754-Rev. E, 02-May-16 Fig. 13b - Gate Charge Test Circuit Document Number: 91093 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF9Z34S, SiHF9Z34S www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit D.U.T. + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg + • dV/dt controlled by Rg • ISD controlled by duty factor “D” • D.U.T. - device under test + - VDD Note • Compliment N-Channel of D.U.T. for driver Driver gate drive P.W. Period D= P.W. Period VGS = - 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = - 5 V for logic level and - 3 V drive devices Fig. 14 - For P-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data see www.vishay.com/ppg?91093. S16-0754-Rev. E, 02-May-16 Document Number: 91093 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0° to 8° 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail “A” Rotated 90° CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B ± 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 AN826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead 0.420 0.355 0.635 (16.129) (9.017) (10.668) 0.145 (3.683) 0.135 (3.429) 0.200 0.050 (5.080) (1.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: 73397 11-Apr-05 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000