an1274

ISL6268EVAL1Z User Guide
®
Application Note
October 9, 2007
AN1274.0
Introduction
Interface Connections
The ISL6268EVAL1Z evaluation board demonstrates the
performance of the ISL6268HZ single-phase
synchronous-buck PWM controller featuring Intersil's Robust
Ripple Regulator (R3) technology. The evaluation DC/DC
converter design criteria is located in Table 1. An on-board
dynamic-load generator is included for evaluating the
transient-load response. The dynamic-load applies a 2.5ms
pulse of 250mΩ across VOUT and GND every 30ms.
Contents of this document include:
• VIN: Input voltage to the power stage of the converter
- J1: VIN positive power input
- TP1: VIN positive voltage sense
- J2: VIN return power input
- TP2: VIN return voltage sense
• Recommended Test Equipment
• Interface Connections
• VOUT: Regulated output voltage from the converter
- J3: VOUT positive power output
- TP3: VOUT positive voltage sense
- J4: VOUT return power output
- TP4: VOUT return voltage sense
• VCC: +5V input voltage for VCC, PVCC, PGOOD-LED
and pull-up voltage rail
- J5: 5V positive input
- J6: 5V return input
• Switch Descriptions
• Jumper Descriptions
• Test Point Descriptions
• +12V: Input voltage for the dynamic-load generator
- J7: 12V positive input
- J8: 12V return input
• Typical Waveforms
- Start-up
- Shut-down
- Diode-emulation
- Load-transient response
- Line-transient response
- Overvoltage protection
- Undervoltage protection
- Overcurrent protection
• Evaluation Board Documentation
- Schematic
- Bill of materials
- Silk-screen plots
- Board layer plots
Switch Descriptions
• S1: ENABLE
- OFF: Shorts the EN pin to GND (disable PWM)
- ON: Allows the EN pin to pull-up to +5V (enable PWM)
• S2: DYNAMIC LOAD
- OFF: Load disabled
- ON: Load enabled
Jumper Descriptions
• JP1: Connects +5V supply to the PGOOD LED circuit. The
shunt jumper is normally installed. Remove the shunt
jumper when making low power efficiency measurements
TABLE 1. DC/DC DESIGN CRITERIA
PARAMETER
VALUE
UNITS
VIN
7 to 25
VDC
VOUT
1.20
VDC
FULL-LOAD
5.0
ADC
PWM FREQUENCY
300
kHz
Test-point Descriptions
• P1: Scope-probe socket for measuring the PHASE node
• P2: Scope-probe socket for measuring VOUT
• P3: Scope-probe socket for measuring voltage across the
dynamic-load resistors (hence load current)
Recommended Equipment
• TP5: Monitor the PGOOD pin
• (QTY 1) Adjustable 25V, 3A Power Supply
• TP6: Monitor or drive the EN pin
• (QTY 1) Fixed 12V, 100mA Power Supply
• TP7: Monitor the COMP pin (SENSITIVE!)
• (QTY 1) Fixed 5V, 100mA Power Supply
• TP8: Monitor the FB pin (SENSITIVE!)
• (QTY 1) Adjustable 10A Constant Current Electronic Load
• (QTY 1) DVM
• JP2: Isolates the EN pin from switch S1 so that it can be
externally driven
• TP9: Monitor the FSET pin
• TP10: Monitor the PVCC pin
• (QTY 1) Four Channel Oscilloscope
1
• TP11 to TP16: Signal Ground
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Application Note 1274
Typical Waveforms
VOUT
PGOOD
VOUT
VOUT
VCC
PGOOD
VCC
VCC
EN
EN
EN
PGOOD
500μs/DIV
FIGURE 1. SOFT-START: NO LOAD
FIGURE 2. SOFT-START: NO LOAD, 50% VOUT-PREBIAS
VOUT
VOUT
PGOOD
PGOOD
EN
EN
I-CHOKE
I-CHOKE
FIGURE 3. IN-RUSH CURRENT: NO LOAD
FIGURE 4. IN-RUSH CURRENT: NO LOAD, 50% VOUT-PREBIAS
VOUT
VOUT
EN
EN
I-CHOKE
I-CHOKE
PHASE
PHASE
FIGURE 5. SHUTDOWN: EN FALLING, 250mΩ LOAD
FIGURE 6. SHUTDOWN: EN FALLING, NO LOAD
2
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October 9, 2007
Application Note 1274
Typical Waveforms (Continued)
VOUT
VOUT
I-CHOKE
I-CHOKE
EN
LG
PHASE
PHASE
FIGURE 7. SHUTDOWN: EN-FALLING TO PGOOD-FALLING,
NO LOAD
FIGURE 8. ENTERING DEM: 750mΩ LOAD DUMP, 100mA DC
STATIC LOAD
V-250mΩ LOAD
VOUT
VOUT
I-CHOKE
VCOMP
LG
PHASE
PHASE
FIGURE 9. EXITING DEM: 750mΩ LOAD STEP, 1.75A DC
STATIC LOAD
FIGURE 10. LOAD TRANSIENT: 250mΩ LOAD STEP, 10mA DC
STATIC LOAD
V-250mΩ LOAD
VOUT
VIN
VOUT
VCOMP
PHASE
FIGURE 11. LOAD TRANSIENT: 250mΩ LOAD STEP, 5A DC
STATIC LOAD
3
VCOMP
PHASE
FIGURE 12. LINE TRANSIENT: 7V TO 20V STEP, 5A LOAD
AN1274.0
October 9, 2007
Application Note 1274
Typical Waveforms (Continued)
PGOOD
VOVR
FB
I-CHOKE
VOUT
VIN
VOVF
VCOMP
PHASE
PHASE
FIGURE 13. LINE TRANSIENT: 20V TO 7V STEP, 100mA LOAD
FIGURE 14. OVERVOLTAGE PROTECTION: SHORT ACROSS
HIGH-SIDE MOSFET DRAIN-SOURCE, 2A DC
STATIC LOAD
PGOOD
VUV
IOC
I-CHOKE
FB
PGOOD
PHASE
VOUT
FIGURE 15. UNDERVOLTAGE PROTECTION: SHORT
ACROSS HIGH-SIDE MOSFET GATE-SOURCE,
2A DC STATIC LOAD
I-CHOKE
PHASE
FIGURE 16. OVERCURRENT PROTECTION: 11.8APEAK
CHOKE CURRENT, 5.0mΩ r DS(ON), 2.1kΩ RSEN
The value of the OCP overcurrent programming resistor
RSEN is calculated using Equation 1:
The value of the frequency programming resistor RFSET is
calculated using Equation 2:
I PP
⎛ I + --------⎞ • OC SP • r DS ( ON )
⎝ FL
2 ⎠
R SEN = ---------------------------------------------------------------------------I OC
1
R FSET = -----------------K • f SW
(EQ. 1)
where:
- rDS(ON) is the on-state resistance of the low-side MOSFET
- IOC is the ISEN threshold current that trips the OCP circuit
- IFL is the maximum continuous design load current
- IPP is the inductor peak-to-peak ripple current
- OCSP is the desired OCP setpoint multiplier relative to IFL
The ISL6268EVAL1Z delivers 5A IFL with approximately 30%
inductor ripple current (1.5AP-P) The low-side MOSFET has
5mΩ rDS(ON). The OCP setpoint should be chosen to avoid
nuisance tripping due to component tolerances and
temperature effects. The ISL6268EVAL1Z is programmed to
190% (OCSP = 1.9). Using Equation 1 finds RSEN = 2.1kΩ.
4
(EQ. 2)
where:
- fSW is the PWM switching frequency
- K = 66 x 10-12
The ISL6268EVAL1Z is programmed for 300kHz. Using
Equation 2 finds RFSET = 49.9kΩ.
The regulation voltage setpoint programming resistors RTOP
and RBOTTOM are calculated using Equation 3:
R BOTTOM
V REF = V OUT • -------------------------------------------------R
+R
TOP
(EQ. 3)
BOTTOM
where:
- VREF = 600mV
The ISL6268EVAL1Z is programmed for 1.20V, therefore,
RTOP = RBOTTOM. The loop compensation is usually
responsible for selecting RTOP, which in this case is 2.49kΩ.
AN1274.0
October 9, 2007
VOUT_+SNS
VOUT_+SNS
C10
22UF
R20
2.49K
R21
2.49K
D2
DNI
C12
330UF
DNI
DNI
1
2
C11
330UF
7
8
8
7
5
6
3
4
1
2
Q4
IRF7832
8
7
6
3
P2
J3
VOUT
TP3
TP4
J4
GND_POWER
C14
0.1UF
R2
249
3
1
P1
5A
C9
22UF
6
1
C5
10UF
5
2
Q3
3
7
1
4
6
8
2
Q1
IRF7821
5
3
DNI
5
DNI
Q2
4
2
1
L1
2.2UH
GND_POWER
R1
249
5
J2
4
5
6
Q9
3
4
8
7
C4
10UF
VIN_-SNS
Q9
VIN_+SNS
C3
10UF
TP2
1.2V
PHASE
C2
56UF
TP1
VIN
C1
DNI
J1
1 2
JP1
R4
10K
3
4
2
1
R9
2.1K
VIN
R23
VCC
VCC
EN
10
GND
2
1
TP6
16
4
15
U1
QSOP16 14
ISL6268
13
5
12
6
11
7
10
8
9
3
OFF
GND
J6
JP2
ON
3
FB
C15
1UF
S1
1 2
C6
10UF
R5
10K
COMP
1
2
BOOT
TP10
PVCC
LG
PGND
ISEN
VO
FSET
SHORT
TP7
GND_POWER
R10
49.9K
R6
75K
C19
47PF
TP9
C18
1000PF
C20
470PF
R22
0
TP8
12V
2
J7
UG
C21
1UF
PGOOD
C16
4.7UF
TP5
R13
1
Q6
BSS138
2
3
2
1
PHASE
J5
Application Note 1274
R3
10K
D1
GRN
RED
Q5
BSS138
C13
0.22UF
AN1274.0
October 9, 2007
J8
R12
249
3
GND_POWER
FIGURE 17. ISL6268EVAL1Z REV B CIRCUIT SCHEMATIC
TP16
TP15
TP14
TP13
4
TP12
3
HS
U2
HIP2100
TP11
HO
HI
R19
1.5
LI
5
R18
1.5
2
R17
1.5
1
HB
R16
1.5
VDD
VSS
R14
1.5
LO
7
6
BAT54S
8
R15
1.5
OFF
P3
3
1
2
C17
1000PF
ON
1
C8
10UF
S2
3
R7
499
2
C7
10UF
N/C
SUD50N03_07
D3
1
Q7
Q8
1
R11
249
2
3
R8
49.9K
BSS138
REV:
TITLE:
B
ISL6268EVAL1Z
GND
ENGINEER:
NATHAN MITCHELL
DATE:
09/06/06
ISL6268
SHEET:
1
1.2V,
5A APPLICATION
OF
Application Note 1274
μ
FIGURE 18. PCB TOP SILK SCREEN
6
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October 9, 2007
Application Note 1274
μ
FIGURE 19. PCB BOTTOM SILK SCREEN (MIRRORED)
7
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October 9, 2007
Application Note 1274
μ
FIGURE 20. PCB TOP LAYER ETCH
8
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Application Note 1274
FIGURE 21. PCB LAYER 2 ETCH
9
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October 9, 2007
Application Note 1274
μ
FIGURE 22. PCB LAYER 3 ETCH
10
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October 9, 2007
Application Note 1274
FIGURE 23. PCB BOTTOM LAYER ETCH
11
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October 9, 2007
Application Note 1274
Bill of Materials
QTY
REFERENCE
1
C2
2
C11, C12
1
DESCRIPTION/COMMENT
CAP, RADIAL, 56µF, 25V, OSCON
MFG NAME
SANYO
MFG NUMBER
25SP56M
CAP, SMD, [7.3mmx4.3mm], 330µF, 2V, 7mΩ, 20%, SP-CAP PANASONIC
EEF-SD0D331R
C13
CAPACITOR, 0805, 0.22µF, 16V, 20%, X7R
GENERIC
NA
1
C14
CAPACITOR, 0805, 0.1µF, 50V, 20%, X7R
GENERIC
NA
2
C15, C21
CAPACITOR, 0805, 1µF, 6.3V, 20%, X5R
GENERIC
NA
1
C16
CAPACITOR, 0805, 4.7µF, 6.3V, 20%, X5R
GENERIC
NA
2
C17, C18
CAPACITOR, 0805, 1000pF, 50V, 10%, X7R
GENERIC
NA
1
C19
CAPACITOR, 0805, 47pF, 50V, 5%, X7R
GENERIC
NA
1
C20
CAPACITOR, 0805, 470pF, 50V, 5%, X7R
GENERIC
NA
2
C9, C10
CAPACITOR, 1206, 22µF, 6.3V, 20%, X5R
GENERIC
NA
6
C3 to C8
CAPACITOR, 1206, 10µF, 25V, 20%, X5R
GENERIC
NA
1
D1
LED, SMD, 3mmx2.5mm, 4P, RED/GREEN,12/20MCD, 2V
LUMEX
SSL-LXA3025IGC-TR
1
D3
DIODE, SCHOTTKY, DUAL, SOT23, 30V, 200mA
ON-SEMI
BAT54S
3
TP7, TP8, TP9
TEST-POINT, SMD, 0.070x0.135 PAD
KEYSTONE
MTP5015SM
2
J1, J3
PLUG, BANANA, THRU-HOLE, RED, 4.23mm
MOUSER
164-6219
2
J2, J4
PLUG, BANANA, THRU-HOLE, BLK, 4.23mm
MOUSER
164-6218
4
J5, J7, TP1, TP3
TEST-POINT, VERTICAL, RED
KEYSTONE
CTP5005
10
J6, J8, TP2, TP4, TP11 to TP16
TEST-POINT, VERTICAL, BLACK
KEYSTONE
CTP5006
3
TP5, TP6, TP10
TEST-POINT, VERTICAL, WHITE
KEYSTONE
CTP5007
2
JP1, JP2
HEADER, 1x2, RETENTIVE, 2.54mm
FCI
68000-236
1
L1
INDUCTOR, SMD, 13mm, 2.2µH, 20%, 29A, SHIELDED
VISHAY
IHLP-5050CE-01-2R2M
1
Q1
MOSFET, N-CH, SMD, 8P, SO8, 30V, 9.5mΩ
IR
IRF7821
1
Q2
MOSFET, N-CH, SMD, 8P, SO8, 30V, 4mΩ
IR
IRF7832
3
Q5-Q7
MOSFET, N-CH, SMD, 3P, SOT23, 50V, 200mA
FAIRCHILD
BSS138LT1
1
Q8
MOSFET, N-CH, SMD, TO-252AA, 30V, 7mΩ
SILICONIX
SUD50N03-07
4
R1, R2, R11, R12
RESISTOR, 0805, 249Ω, 1%
GENERIC
NA
2
R8, R10
RESISTOR, 0805, 49.9kΩ, 1%
GENERIC
NA
1
R13
RESISTOR, 0805, 1Ω, 5%
GENERIC
NA
6
R14 to R19
RESISTOR, 1206, 1.5Ω, 1%
GENERIC
NA
1
R22
RESISTOR, 0805, 1kΩ, 1%
GENERIC
NA
3
R3 to R5
RESISTOR, 0805, 10kΩ, 1%
GENERIC
NA
1
R6
RESISTOR, 0805, 75kΩ, 1%
GENERIC
NA
1
R7
RESISTOR, 0805, 499Ω, 1%
GENERIC
NA
1
R9
RESISTOR, 0805, 2.1kΩ, 1%
GENERIC
NA
2
R20, R21
RESISTOR, 0805, 1.5kΩ, 1%
GENERIC
NA
2
S1, S2
TOGGLE-SWITCH, SPDT, On-None-On, SMT
C&K
GT13MSCKE
1
U1
IC, PWM-CONTROLLER, 1CH, 16P, SSOP
INTERSIL
ISL6268
U2
IC, DRIVER, BRIDGE, 8P, SOIC, 100V
INTERSIL
HIP2100B
1
C1, D2, P1, P2, P3, Q3, Q4, Q9
NOT POPULATED
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
AN1274.0
October 9, 2007
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