IRFR9022, IRFU9022, SiHFR9022, SiHFU9022 Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) - 50 RDS(on) (Ω) VGS = - 10 V 0.33 Qg (Max.) (nC) 14 Qgs (nC) 6.5 Qgd (nC) 6.5 Configuration Single IPAK (TO-251) G D D G S G Surface Mountable (Order as IRFR9022, SiHFR9022) Straight Lead Option (Order as IRFU9022, SiHFU9022) Available Repetitive Avalanche Ratings RoHS* COMPLIANT Dynamic dV/dt Rating Simple Drive Requirements Ease of Paralleling DESCRIPTION S DPAK (TO-252) • • • • • • D S D P-Channel MOSFET The Power MOSFET technology is the key to Vishay’s advanced line of Power MOSFET transistors. The efficient geometry and unique processing of this latest “State of the Art” design achieves: very low on-state resistance combined with high transconductance; superior reverse energy and diode recovery dV/dt. The Power MOSFET transistors also feature all of the well established advantages of MOSFET’S such as voltage control, very fast switching, ease of paralleling and temperature stability of the electrical parameters. Surface mount packages enhance circuit performance by reducing stray inductances and capacitance. The TO-252 surface mount package brings the advantages of Power MOSFET’s to high volume applications where PC Board surface mounting is desirable. The surface mount option IRFR9022, SiHFR9022 is provided on 16 mm tape. The straight lead option IRFU9022, SiHFU9022 of the device is called the IPAK (TO-251). They are well suited for applications where limited heat dissipation is required such as, computers and peripherals, telecommunication equipment, DC/DC converters, and a wide range of consumer products. ORDERING INFORMATION Package Lead (Pb)-free SnPb DPAK (TO-252) IRFR9022PbF SiHFR9022-E3 IRFR9022 SiHFR9022 DPAK (TO-252) IRFR9022TRPbFa SiHFR9022T-E3a IRFR9022TRa SiHFR9022Ta DPAK (TO-252) IRFR9022TRLPbFa SiHFR9022TL-E3a IRFR9022TRLa SiHFR9022TLa IPAK (TO-251) IRFU9022PbF SiHFU9022-E3 IRFU9022 SiHFU9022 Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current SYMBOL VDS VGS VGS at - 10 V TC = 25 °C TC = 100 °C Currenta ID IDM Pulsed Drain Linear Derating Factor EAS Single Pulse Avalanche Energyb IAR Repetitive Avalanche Currenta EAR Repetitive Avalanche Energya PD Maximum Power Dissipation TC = 25 °C dV/dt Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range TJ, Tstg Soldering Recommendations (Peak Temperature) for 10 s Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 14). b. VDD = - 25 V, Starting TJ = 25 °C, L = 5.1 mH, RG = 25 Ω, Peak IL = - 9.9 A c. ISD ≤ - 9.9 A, dI/dt ≤ -120 A/µs, VDD ≤ 40 V, TJ ≤ 150 °C. d. 0.063" (1.6 mm) from case. e. When mounted on 1" square PCB (FR-4 or G-10 material). LIMIT - 50 ± 20 - 9.0 - 5.7 - 36 0.33 440 - 9.9 4.2 42 5.8 - 55 to + 150 300d UNIT V A W/°C mJ A mJ W V/ns °C * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91349 S09-0073-Rev. A, 02-Feb-09 www.vishay.com 1 IRFR9022, IRFU9022, SiHFR9022, SiHFU9022 Vishay Siliconix THERMAL RESISTANCE RATINGS SYMBOL MIN. TYP. MAX. Maximum Junction-to-Ambient PARAMETER RthJA - - 110 Case-to-Sink RthCS - 1.7 - Maximum Junction-to-Case (Drain) RthJC - - 3.0 UNIT °C/W SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance VDS VGS = 0 V, ID = - 250 µA - 50 - - V VGS(th) VDS = VGS, ID = - 250 µA - 2.0 - - 4.0 V nA IGSS IDSS RDS(on) gfs VGS = ± 20 V - - ± 500 VDS = max. rating, VGS = 0 V - - 250 VDS = 0.8 x max. rating, VGS = 0 V, TJ = 125 °C - - 1000 - 0.28 0.33 Ω VDS ≤ - 50 V, IDS = - 5.7 A 2.3 3.5 - S VGS = 0 V, VDS = - 25 V, f = 1.0 MHz, see fig. 9 - 490 - - 320 - - 70 - ID = 5.7 Ab VGS = - 10 V µA Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time Fall Time tr td(off) VGS = - 10 V ID = - 9.7 A, VDS = 0.8 x max. rating, see fig. 16 (Independent operating temperature) VDD = - 25 V, ID = - 9.7 A, RG = 18 Ω, RD = 2.4 Ω, see fig. 15 (Independent operating temperature) tf Internal Drain Inductance LD Internal Source Inductance LS Between lead, 6 mm (0.25") from package and center of die contact. - 9.4 14 - 4.3 6.5 - 4.3 6.5 - 8.2 12 - 57 66 - 12 18 - 25 38 - 4.5 - - 7.5 - - - - 9.9 - - - 40 pF nC ns D nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = - 9.9 A, VGS = 0 Vb TJ = 25 °C, IF = - 9,7 A, dI/dt = 100 A/µsb - - - 6.3 V 56 110 280 ns 0.17 0.34 0.85 nC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 14). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. www.vishay.com 2 Document Number: 91349 S09-0073-Rev. A, 02-Feb-09 IRFR9022, IRFU9022, SiHFR9022, SiHFU9022 Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig. 1 - Typical Output Characteristics Fig. 4 - Maximum Safe Operating Area Fig. 2 - Typical Transfer Characteristics Fig. 5 - Typical Transconductance vs. Drain Current Fig. 3 - Typical Saturation Characteristics Fig. 6 - Typical Source-Drain Diode Forward Voltage Document Number: 91349 S09-0073-Rev. A, 02-Feb-09 www.vishay.com 3 IRFR9022, IRFU9022, SiHFR9022, SiHFU9022 Vishay Siliconix Fig. 7 - Breakdown Voltage vs. Temperature Fig. 8 - Normalized On-Resistance vs. Temperature www.vishay.com 4 Fig. 9 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 10 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91349 S09-0073-Rev. A, 02-Feb-09 IRFR9022, IRFU9022, SiHFR9022, SiHFU9022 Vishay Siliconix Fig. 11 - Typical On-Resistance vs. Drain Current Fig. 13 - Maximum Avalanche vs. Starting Junction Temperature Fig. 13b - Unclamped Inductive Test Circuit IAS VDS IL VDD Fig. 12 - Maximum Drain Current vs. Case Temperature tp VDS Fig. 13c - Unclamped Inductive Waveforms Document Number: 91349 S09-0073-Rev. A, 02-Feb-09 www.vishay.com 5 IRFR9022, IRFU9022, SiHFR9022, SiHFU9022 Vishay Siliconix Fig. 14 - Maximum Effective Transient Thermal Impedance, Junction-to-Case vs. Pulse Duration td(on) tr td(off) tf VGS QG - 10 V 10 % QGS QGD VG 90 % VDS Charge Fig. 15a - Switching Time Waveforms Fig. 16a - Basic Gate Charge Waveform Fig. 15b - Switching Time Test Circuit Fig. 16b - Gate Charge Test Circuit www.vishay.com 6 Document Number: 91349 S09-0073-Rev. A, 02-Feb-09 IRFR9022, IRFU9022, SiHFR9022, SiHFU9022 Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit D.U.T. + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - RG + • dV/dt controlled by RG • ISD controlled by duty factor "D" • D.U.T. - device under test + - VDD Compliment N-Channel of D.U.T. for driver Driver gate drive P.W. Period D= P.W. Period VGS = - 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage VDD Body diode forward drop Inductor current Ripple ≤ 5 % * ISD VGS = - 5 V for logic level and - 3 V drive devices Fig. 17 - For P-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91349. Document Number: 91349 S09-0073-Rev. A, 02-Feb-09 www.vishay.com 7 Package Information Vishay Siliconix TO-252AA (HIGH VOLTAGE) E b3 E1 L3 D1 D H L4 b2 b A c2 e A1 L1 L c θ L2 MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. E 6.40 6.73 0.252 0.265 L 1.40 1.77 0.055 L1 2.743 REF L2 0.070 0.108 REF 0.508 BSC 0.020 BSC L3 0.89 1.27 0.035 0.050 L4 0.64 1.01 0.025 0.040 D 6.00 6.22 0.236 0.245 H 9.40 10.40 0.370 0.409 b 0.64 0.88 0.025 0.035 b2 0.77 1.14 0.030 0.045 b3 5.21 5.46 0.205 e 2.286 BSC 0.215 0.090 BSC A 2.20 2.38 0.087 A1 0.00 0.13 0.000 0.094 0.005 c 0.45 0.60 0.018 0.024 c2 0.45 0.58 0.018 0.023 D1 5.30 - 0.209 - E1 4.40 - 0.173 - θ 0' 10' 0' 10' ECN: S-81965-Rev. A, 15-Sep-08 DWG: 5973 Notes 1. Package body sizes exclude mold flash, protrusion or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side. 2. Package body sizes determined at the outermost extremes of the plastic body exclusive of mold flash, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 3. The package top may be smaller than the package bottom. 4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimension at maximum material condition. The dambar cannot be located on the lower radius of the foot. Document Number: 91344 Revision: 15-Sep-08 www.vishay.com 1 Package Information Vishay Siliconix TO-251AA (HIGH VOLTAGE) 4 3 E1 E Thermal PAD 4 b4 θ2 4 A 0.010 0.25 M C A B L2 4 c2 A θ1 B D D1 A C 3 Seating plane 5 C L1 L3 (Datum A) C L B B A A1 3 x b2 View A - A 2xe c 3xb 0.010 0.25 M C A B Plating 5 b1, b3 Base metal Lead tip c1 (c) 5 (b, b2) Section B - B and C - C MILLIMETERS DIM. MIN. MAX. INCHES MIN. MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 2.18 2.39 0.086 0.094 D1 5.21 - 0.205 - A1 0.89 1.14 0.035 0.045 E 6.35 6.73 0.250 0.265 4.32 - 0.170 - b 0.64 0.89 0.025 0.035 E1 b1 0.65 0.79 0.026 0.031 e b2 0.76 1.14 0.030 0.045 L 8.89 9.65 0.350 0.380 b3 0.76 1.04 0.030 0.041 L1 1.91 2.29 0.075 0.090 b4 4.95 5.46 0.195 0.215 L2 0.89 1.27 0.035 0.050 2.29 BSC 2.29 BSC c 0.46 0.61 0.018 0.024 L3 1.14 1.52 0.045 0.060 c1 0.41 0.56 0.016 0.022 θ1 0' 15' 0' 15' c2 0.46 0.86 0.018 0.034 θ2 25' 35' 25' 35' D 5.97 6.22 0.235 0.245 ECN: S-82111-Rev. A, 15-Sep-08 DWG: 5968 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension are shown in inches and millimeters. 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body. 4. Thermal pad contour optional with dimensions b4, L2, E1 and D1. 5. Lead dimension uncontrolled in L3. 6. Dimension b1, b3 and c1 apply to base metal only. 7. Outline conforms to JEDEC outline TO-251AA. Document Number: 91362 Revision: 15-Sep-08 www.vishay.com 1 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR DPAK (TO-252) 0.224 0.243 0.087 (2.202) 0.090 (2.286) (10.668) 0.420 (6.180) (5.690) 0.180 0.055 (4.572) (1.397) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 72594 Revision: 21-Jan-08 www.vishay.com 3 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000