DATASHEET

ISL6551I
Data Sheet
November 17, 2011
FN6762.2
ZVS Full Bridge PWM Controller
Features
The ISL6551IREC is a zero voltage switching (ZVS) full
bridge PWM controller designed for isolated power systems.
This part implements a unique control algorithm for fixed
frequency ZVS current mode control, yielding high efficiency
with low EMI. The two lower drivers are PWM-controlled on
the trailing edge and employ resonant delay while the two
upper drivers are driven at a fixed 50% duty cycle.
• Full Traceability Through Assembly and Test by
Date/Trace Code Assignment
This IC integrates many features in a 28 lead 6mmx6mm2
QFN package to yield a complete and sophisticated power
supply solution. Control features include programmable softstart for controlled start-up, programmable resonant delay
for zero voltage switching, programmable leading edge
blanking to prevent false triggering of the PWM comparator
due to the leading edge spike of the current ramp, adjustable
ramp for slope compensation, drive signals for implementing
synchronous rectification in high output current, ultra high
efficiency applications, and current share support for
paralleling up to 10 units, which helps achieve higher
reliability and availability as well as better thermal
management. Protective features include adjustable cycleby-cycle peak current limiting for overcurrent protection, fast
short-circuit protection (in hiccup mode), a latching shutdown
input to turn off the IC completely on output overvoltage
conditions or other extreme and undesirable faults, a nonlatching enable input to accept an enable command when
monitoring the input voltage and thermal condition of a
converter, and VDD undervoltage lockout with hysteresis.
Additionally, the ISL6551IREC includes high current highside and low-side totem-pole drivers to avoid additional
external drivers for moderate gate capacitance (up to 1.6nF
at 1MHz) applications, an uncommitted high bandwidth
(10MHz) error amplifier for feedback loop compensation, a
precision bandgap reference with ±1.5% or ±1% tolerance
over recommended operating conditions, and a ±5% “in
regulation” monitor.
• Current Mode Control Compatible
In addition to the ISL6551IREC, other external elements
such as transformers, pulse transformers, capacitors,
inductors and Schottky or synchronous rectifiers are
required for a complete power supply solution. A detailed
200W telecom power supply reference design using the
ISL6551IREC with companion Intersil ICs, Supervisor and
Monitor ISL6550 and Half-bridge Driver HIP2100, is
presented in Application Note AN1002.
• Enhanced Process Change Notification per MIL-PRF-38535
• Enhanced Obsolescence Management
• High Speed PWM (up to 1MHz) for ZVS Full Bridge
Control
• High Current High-Side and Low-Side Totem-Pole Drivers
• Adjustable Resonant Delay for ZVS
• 10MHz Error Amplifier Bandwidth
• Programmable Soft-Start
• Precision Bandgap Reference
• Latching Shutdown Input
• Non-latching Enable Input
• Adjustable Leading Edge Blanking
• Adjustable Dead Time Control
• Adjustable Ramp for Slope Compensation
• Fast Short-Circuit Protection (Hiccup Mode)
• Adjustable Cycle-by-Cycle Peak Current Limiting
• Drive Signals to Implement Synchronous Rectification
• VDD Undervoltage Lockout
• Current Share Support
• ±5% “In Regulation” Indication
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package Footprint, which Improves
PCB Efficiency and has a Thinner Profile
Applications
• Full-Bridge and Push-Pull Converters
• Power Supplies for Off-line and Telecom/Datacom
• Power Supplies for High End Microprocessors and
Servers
In addition, the ISL6551IREC can also be designed in pushpull converters using all of the features except the two upper
drivers and adjustable resonant delay features.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2008, 2011. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL6551I
Ordering Information
PART
NUMBER
PART
MARKING
TEMP RANGE
(°C)
PKG.
DWG. #
PACKAGE
ISL6551IREC
ISL 6551IR
0 to +85
28 Ld 6x6 QFN (Pb-free)
L28.6x6
ISL6551IR-TEC*
ISL 6551IR
0 to +85
28 Ld 6x6 QFN (Pb-free)
L28.6x6
*Please refer to TB347 for details on reel specifications.
Pinout
2
RD
CT
VSS
VDD
VDDP1
VDDP2
PGND
ISL6551IREC
(28 LD QFN)
TOP VIEW
28
27
26
25
24
23
22
3
19 LOWER1
PKILIM
4
18 LOWER2
BGREF
5
17 SYNC1
R_LEB
6
16 SYNC2
CS_COMP
7
15 ON/OFF
8
9
10
11
12
13
14
DCOK
ISENSE
LATSD
20 UPPER2
SHARE
2
EAO
R_RA
EAI
21 UPPER1
EANI
1
CSS
R_RESDLY
FN6762.2
November 17, 2011
ISL6551I
Functional Pin Description
PIN #
PIN SYMBOL
FUNCTION
26
VSS
27
CT
Set the oscillator frequency, up to 1MHz.
28
RD
Adjust the clock dead time from 50ns to 1000ns.
1
R_RESDLY
Program the resonant delay from 50ns to 500ns.
2
R_RA
3
ISENSE
The pin receives the current information via a current sense transformer or a power resistor.
4
PKILIM
Set the overcurrent limit with the bandgap reference as the trip threshold.
5
BGREF
Precision bandgap reference, 1.263V ±2% overall recommended operating conditions.
6
R_LEB
Program the leading edge blanking from 50ns to 300ns.
7
CS_COMP
8
CSS
Program the rise time and the clamping voltage with a capacitor and a resistor, respectively.
9
EANI
Non-inverting input of Error Amp. It is clamped by the voltage at the CSS pin (Vclamp).
10
EAI
Inverting input of Error Amp. It receives the feedback voltage.
11
EAO
Output of Error Amp. It is clamped by the voltage at the CSS pin (Vclamp).
12
SHARE
This pin is the SHARE BUS connecting with other unit(s) for current share operation.
13
LATSD
The IC is latched off with a voltage greater than 3V at this pin and is reset by recycling VDD.
14
DCOK
Power-Good indication with a ±5% window.
15
ON/OFF
16, 17
SYNC2, SYNC1
18, 19
LOWER2, LOWER1
Both lower drivers are PWM-controlled on the trailing edge.
20, 21
UPPER2, UPPER1
Both upper drivers are driven at a fixed 50% duty cycle.
22
PGND
23, 24
VDDP2, VDDP1
25
VDD
Reference ground. All control circuits are referenced to this pin.
Adjust the ramp for slope compensation (from 50mV to 250mV).
Set a low current sharing loop bandwidth with a capacitor.
This is an Enable pin that controls the states of all drive signals and the soft-start.
These are the gate control signals for the output synchronous rectifiers.
Power Ground. High current return paths for both the upper and the lower drivers.
Power is delivered to both the upper and the lower drivers through these pins.
Power is delivered to all control circuits including SYNC1 and SYNC2 via this pin.
3
FN6762.2
November 17, 2011
ISL6551I
BANDGAP
REFERENCE
BGREF
11 CSS
16 LATSD
28 VDD
18 ON/OFF
Functional Block Diagram
SHUTDOWN
SHUTDOWN
LATCH
LATCH
UVLO
SOFT
SOFTSTART
START
8
PKILIM 7
SHUTDOWN
SHUTDOWN
27 VDDP1
UPPER1
DRIVER
24 UPPER1
R_LEB 9
R_RESDLY 4
RESODLY
RESODLY
UPPER2
DRIVER
LEB
ISENSE 6
R_RA 5
CT 2
RD 3
EAO 14
EAI 13
EANI 12
23 UPPER2
RAMP
RAMP
ADJUST
ADJUST
26 VDDP2
CLOCK
GENERATOR
PWM
LOGIC
ERROR AMP
(SEE FIG. 4)
22 LOWER1
LOWER2
DRIVER
21 LOWER2
CURRENT
SHARE
DC OK
25 PGND
20 SYNC1
19 SYNC2
15 SHARE
VSS
10 CS_COMP
1
17 DCOK
CIRCUITS REFERENCED TO VSS
LOWER1
DRIVER
CIRCUITS REFERENCED TO PGND
EXTERNAL SINGLE POINT CONNECTION REQUIRED
4
FN6762.2
November 17, 2011
ISL6551I
Absolute Maximum Ratings
Thermal Information
Supply Voltage VDD, VDDP1, VDDP2 . . . . . . . . . . . . . . -0.3 to 16V
Enable Inputs (ON/OFF, LATSD) . . . . . . . . . . . . . . . . . . . . . . . . VDD
Power Good Sink Current (IDCOK) . . . . . . . . . . . . . . . . . . . . . . 5mA
Thermal Resistance
Recommended Operating Conditions
θJA (°C/W)
θJC (°C/W)
QFN Package (Notes 1, 2). . . . . . . . . .
30
2.5
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . 0°C to +85°C
Supply Voltage Range, VDD . . . . . . . . . . . . . . . . . . . 10.8V to 13.2V
Supply Voltage Range, VDDP1 and VDDP2 . . . . . . . . . . . . . <13.2V
Maximum Operating Junction Temperature . . . . . . . . . . . . . . +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379 for details.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
These specifications apply for VDD = VDDP = 12V and TA = 0°C to +85°C, Unless Otherwise Stated.
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature
limits established by characterization and are not production tested.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
10.8
12.0
13.2
V
5
13
18
mA
SUPPLY (VDD, VDDP1, VDDP2)
Supply Voltage
VDD
Bias Current from VDD
IDD
VDD = 12V (not including drivers current at VDDP)
Total Current from VDD and VDDP
ICC
VDD = VDDP = 12V, F = 1MHz, 1.6nF Load
60
mA
UNDERVOLTAGE LOCKOUT (UVLO)
Start Threshold
VDDON
9.2
9.6
9.9
V
Stop Threshold
VDDOFF
8.03
8.6
8.87
V
Hysteresis
VDDHYS
0.3
1
1.9
V
CLOCK GENERATOR (CT, RD)
Frequency Range
Dead Time Pulse Width (Note 3)
F
VDD = 12V (Figure 1)
100
1000
kHz
DT
VDD = 12V (Figure 3)
50
1000
ns
BANDGAP REFERENCE (BGREF)
Bandgap Reference Voltage
VREF
VDD = 12V, 399kΩ pull-up, 0.1µF, after trimming
Bandgap Reference Output Current
IREF
VDD = 12V, see “Block/Pin Functional
Descriptions” on page 9 for details
1.250 1.263 1.280
100
V
µA
PWM DELAYS (Note 3)
LOW1, 2 delay “Rising”
LOWR
With respect to RESDLY rising
5
ns
LOW1, 2 delay “Falling”
LOWF
Compare Delay @ Verror = Vramp
44
ns
SYNC1, 2 delay “Falling”
SYNCF
With respect to RESDLY falling and with 20pF load
18
ns
SYNC1, 2 delay “Rising”
SYNCR
With respect to CLK rising and with 20pF load
20
ns
UGBW
10
MHz
DCG
79
dB
ERROR AMPLIFIER (EANI, EAI, EAO) (Note 3)
Unity Gain Bandwidth
DC Gain
Maximum Offset Error Voltage
Vos
Input Common Mode Range
Vcm
Common Mode Rejection Ratio
CMMR
Power Supply Rejection Ratio
PSSR
Maximum Output Source Current
ISRC
5
VDD = 12V
0.4
1mA load
2
3.1
mV
9
V
82
dB
95
dB
mA
FN6762.2
November 17, 2011
ISL6551I
Electrical Specifications
These specifications apply for VDD = VDDP = 12V and TA = 0°C to +85°C, Unless Otherwise Stated.
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature
limits established by characterization and are not production tested. (Continued)
PARAMETER
SYMBOL
Maximum Lower Saturation Voltage
Vsatlow
TEST CONDITIONS
MIN
TYP
Sinking 0.27mA
MAX UNITS
125
mV
1000
kHz
RAMP ADJUST (R_RA) (Note 3)
Ramp Frequency
F
Linear Voltage Ramp, Minimum
100
50
mV
Linear Voltage Ramp, Maximum
LVR
250
mV
Overall Variation
25
%
PEAK CURRENT LIMIT (PKILIM)
Peak Current Shutdown Threshold
IpkThr
Peak Current Shutdown Delay (Note 3)
IpkDel
BGREF = 0.1µF, 399kΩ pull-up
1.25
1.263
1.31
75
V
ns
SOFT-START (CSS)
8
12
μA
Idis
1.6
5.2
mA
Vclamp
2
8
V
Charge Current
Iss
Discharge Current
Cycle-by-Cycle Current Limit
Vcss = 0.6V
DRIVERS (UPPER1, UPPER2, LOWER1, LOWER2)
Maximum Capacitive Load (each)
CL
VDD = VDDP = 12V, F = 1MHz,
Thermal Dependence
1600
pF
Turn-On Rise Time
tr
1.0nF Capacitive load
8.9
16
ns
Turn-Off Fall Time
tf
1.0nF Capacitive load
6.4
10
ns
Shutdown Delay (Note 3)
tSD
1.0nF Capacitive load
14.5
ns
Rising Edge Delay (Note 3)
tRD
1.0nF Capacitive load
16.4
ns
Falling Edge Delay (Note 3)
tFD
1.0nF Capacitive load
13.7
ns
Vsat_sourcing
Vsat_high
Sourcing 20mA
1.00
V
Sourcing 200mA
1.35
V
Vsat_sinking
Vsat_low
Sinking 20mA
0.035
V
Sinking 200mA
0.31
V
SYNCHRONOUS SIGNALS (SYNC1, SYNC2)
Maximum Capacitive Load
VDD = 12, F = 1MHz
20
(Figure 7)
50
pF
PROGRAMMABLE DELAYS (RESDLY, LEB) (Note 3)
Resonant Delay Adjust Range
Resonant Delay
tRESDLY
R_RESDLY = 10k
55
R_RESDLY = 120k
Leading Edge Blanking Adjust Range
Leading Edge Blanking
(Figure 8)
tLEB
500
ns
488
50
ns
ns
300
ns
R_LEB = 20k
64
ns
R_LEB = 140k
302
ns
R_LEB = 12V
0
ns
LATCHING SHUTDOWN (LATSD)
Fault Threshold
VIN
Fault_NOT Threshold
VINN
Time to Set latch (Note 3)
tSET
3
V
1.9
415
V
ns
ON/OFF (ONOFF)
Turn-off Threshold
OFF
Turn-on Threshold
ON
6
0.8
2
V
V
FN6762.2
November 17, 2011
ISL6551I
Electrical Specifications
These specifications apply for VDD = VDDP = 12V and TA = 0°C to +85°C, Unless Otherwise Stated.
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature
limits established by characterization and are not production tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
CURRENT SHARE (SHARE, CS_COMP) (Note 3)
Voltage Offset Between Error Amp Voltage of
Master and Slave
Vcs_offset SHARE = 30k
30
mV
Maximum Source Current to External Reference Ics_source SHARE = 30k
190
μA
Maximum Correctable Deviation In Reference
Voltage Between Master and Slave
SHARE = 30K, Rsource = 1k,
OUTPUT REFERENCE = 1 to 5V,
(See Figure 10)
190
mV
CS_COMP = 0.1µF
500
Hz
Share/Adjust Loop Bandwidth
CS BW
DC OK (DCOK)
Sink Current
IDCOK
VSATDCOK IDCOK = 5mA
Saturation Voltage
Input Reference
Vref_in
1
5
mA
0.4
V
5
V
Threshold (Relative to Vref_in)
OV
(Figure 11)
5
%
Recovery (Relative to Vref_in)
OV
(Figure 11)
3
%
Threshold (Relative to Vref_in)
UV
(Figure 11)
-5
%
Recovery (Relative to Vref_in)
UV
(Figure 11)
-3
%
250
μs
Transient Rejection (Note 3)
TRej
100mV transient on Vout (system implicit rejection
and feedback network dependence (Figure 12)
NOTE:
3. Limits established by characterization and are not production tested.
7
FN6762.2
November 17, 2011
ISL6551I
Drive Signals Timing Diagrams
CLOCK
UPPER1
UPPER2
SYNC1
SYNC2
LOWER1
EAO
ILOWER1
LOWER2
EAO
ILOWER2
EAO
RAMP ADJUST
OUTPUT TO
PWM
LOGIC
t1
t2
t3
t4
t5
NOTES:
t1 = Leading edge blanking
t2 = t4 = Resonant delay
t3 = t5 = dead time
In the above figure, the values for t1 through t5 are exaggerated for demonstration purposes.
Timing Diagram Descriptions
The two upper drivers (UPPER1 and UPPER2) are driven at
a fixed 50% duty cycle and the two lower drivers (LOWER1
and LOWER2) are PWM-controlled on the trailing edge,
while the leading edge employs resonant delay (t2 and t4).
In current mode control, the sensed switch (FET) current
(ILOWER1 and ILOWER2) is processed in the Ramp Adjust
and Leading Edge Blanking (LEB) circuits and then compared
to a control signal (EAO). Spikes, due to parasitic elements in
the bridge circuit, would falsely trigger the comparator
generating the PWM signal. To prevent false triggering, the
leading edge of the sensed current signal is blanked out by t1,
which can be programmed at the R_LEB pin with a resistor.
Internal switches gate the analog input to the PWM
comparator, implementing the blanking function that
eliminates response degrading delays, which would be
8
caused if filtering of the current feedback was incorporated.
The dead time (t3 and t5) is the delay to turn on the upper
FET (UPPER1/UPPER2) after its corresponding lower FET
(LOWER1/LOWER2) is turned off when the bridge is
operating at maximum duty cycle in normal conditions, or is
responding to load transients or input line dipping conditions.
Therefore, the upper and lower FETs that are located at the
same side of the bridge can never be turned on together, which
eliminates shoot-through currents. SYNC1 and SYNC2 are the
gate control signals for the output synchronous rectifiers. They
are biased by VDD and are capable of driving capacitive loads
up to 20pF at 1MHz clock frequency (500kHz switching
frequency). External drivers with high current capabilities are
required to drive the synchronous rectifiers, cascading with
both synchronous signals (SYNC1 and SYNC2).
FN6762.2
November 17, 2011
ISL6551I
Shutdown Timing Diagrams
LATCH CANNOT BE RESET BY ON/OFF
C
LATSD
D
ON/OFF
A
E
VDDON
VDD
LATCH RESET BY
REMOVING VDD
PKILIM > BGREF
B
F
VDDOFF
PKILIM < BGREF
ILIM_OUT
SOFT-START
DRIVER
ENABLE
SOFT-START
SHUTDOWN
FAULT
FAULT
OFF
OVERCURRENT LATCHED
OFF/ON
LATCH
RESET
UNDERVOLTAGE
LOCKOUT
Shutdown Timing Descriptions
A (ON/OFF)
E (LATCH RESET)
When the ON/OFF is pulled low, the soft-start capacitor is
discharged and all the drivers are disabled. When the
ON/OFF is released without a fault condition, a soft-start is
initiated.
The latch is reset by removing the VDD. The soft-start
capacitor starts to be charged after VDD increases above
the turn-on threshold VDDON.
B (OVERCURRENT)
If the output of the converter is over loaded, i.e., the PKILIM
is above the bandgap reference voltage (BGREF), the softstart capacitor is discharged very quickly and all the drivers
are turned off. Thereafter, the soft-start capacitor is charged
slowly, and discharged quickly if the output is overloaded
again. The soft-start will remain in hiccup mode as long as
the overload conditions persist. Once the overload is
removed, the soft-start capacitor is charged up and the
converter is then back to normal operation.
C (LATCHING SHUTDOWN)
The IC is latched off completely as the LATSD pin is pulled
high, and the soft-start capacitor is reset.
D (ON/OFF)
F (VDD UVLO)
The IC is turned off when the VDD is below the turn-off
threshold VDDOFF. Hysteresis VDDHYS is incorporated in
the undervoltage lockout (UVLO) circuit.
Block/Pin Functional Descriptions
Detailed descriptions of each individual block in the
functional block diagram on page 3 are included in this
section. Application information and design considerations
for each pin and/or each block are also included.
IC Bias Power (VDD, VDDP1, VDDP2)
• The IC is powered from a 12V ±10% supply.
• VDD supplies power to both the digital and analog circuits
and should be bypassed directly to the VSS pin with an
0.1µF low ESR ceramic capacitor.
The latch cannot be reset by the ON/OFF.
9
FN6762.2
November 17, 2011
ISL6551I
• VDDP1 and VDDP2 are the bias supplies for the upper
drivers and the lower drivers, respectively. They should be
decoupled with ceramic capacitors to the PGND pin.
• This pin must also be decoupled with an 0.1µF low ESR
ceramic capacitor.
• Heavy copper should be attached to these pins for a better
heat spreading.
• This free-running oscillator is set by two external
components, as shown in Figure 2. A capacitor at CT is
charged and discharged with two equal constant current
sources and fed into a window comparator to set the clock
frequency. A resistor at RD sets the clock dead time. RD and
CT should be tied to the VSS pin on their other ends as close
as possible. The corresponding CT for a particular frequency
can be selected from Figure 1.
IC GNDs (VSS, PGND)
• VSS is the reference ground, the return of VDD, of all control
circuits and must be kept away from nodes with switching
noises. It should be connected to the PGND in only one
location as close to the IC as practical. For a secondary side
control system, it should be connected to the net after the
output capacitors, i.e., the output return pinout(s). For a
primary side control system, it should be connected to the net
before the input capacitors, i.e., the input return pinout(s).
Clock Generator (CT, RD)
• The switching frequency (Fsw) of the power train is half of the
clock frequency (Fclock), as shown in Equation 1.
Fclock
Fsw = ------------------2
• PGND is the power return, the high-current return path of both
VDDP1 and VDDP2. It should be connected to the SOURCE
pins of two lower power switches or the RETURNs of external
drivers as close as possible with heavy copper traces.
3,000
F (kHz)
2,000
• UVLO establishes an orderly start-up and verifies that VDD is
above the turn-on threshold voltage (VDDON). All the drivers
are held low during the lockout. UVLO incorporates
hysteresis VDDHYS to prevent multiple startup/shutdowns
while powering up.
+0°C
2,500 +60°C
• Copper planes should be attached to both pins.
Undervoltage Lockout (UVLO)
(EQ. 1)
+120°C
1,500
1,000
500
• UVLO limits are not applicable to VDDP1 and VDDP2.
0
10
100
Bandgap Reference (BGREF)
• The reference voltage VREF is generated by a precision
bandgap circuit.
CT (pF)
1,000
10,000
RECOMMENDED RANGE
FIGURE 1. CT vs FREQUENCY
• This pin must be pulled up to VDD with a resistance of
approximately 399kΩ for proper operation. For additional
reference loads (no more than 1mA), this pull-up resistor
should be scaled accordingly.
RD
SET CLOCK
DEAD TIME (DT)
RD
VDDI_CT
VMAX
+
OUT
CT
CT
CLK
S
VMIN
I_CT
- OUT
+
R
Q
Q
Q
Q
CLK
DT
DT
FIGURE 2. SIMPLIFIED CLOCK GENERATOR CIRCUIT
10
FN6762.2
November 17, 2011
ISL6551I
• Note that the capacitance of a scope probe (~12pF for
single-ended) would induce a smaller frequency at the CT
pin. It can be easily seen at a higher frequency. An
accurate operating frequency can be measured at the
outputs of the bridge/synchronous drivers.
The dead time is the delay to turn on the upper FET
(UPPER1/UPPER2) after its corresponding lower FET
(LOWER1/LOWER2) is turned off when the bridge is
operating at maximum duty cycle in normal conditions, or is
responding to load transients or input line dipping conditions.
This helps to prevent shoot through between the upper FET
and the lower FET that are located at the same side of the
bridge. The dead time can be estimated using Equation 2:
M × RD
DT = -------------------kΩ
(ns)
(EQ. 2)
Vclamp = Rcss • Iss
(EQ. 3)
(V)
• Per Equation 3, the clamping voltage is a function of the
charge current Iss. For a more predictable clamping
voltage, the CSS pin can be connected to a reference
based clamp circuit, as shown in Figure 4. To make the
Vclamp less dependent on the soft-start current (Iss), the
currents flowing through R1 and R2 should be scaled
much greater than Iss. The relationship of this circuit can
be found in Equation 4.
VREF
where M = 11.4 (VDD = 12V), 11.1(VDD = 14V), and 12
(VDD = 10V), and RD is in kΩ. This relationship is shown in
Figure 3.
2.0
DEAD TIME (µs)
• The clamping voltage determines the cycle-by-cycle peak
current limiting of the power supply. It should be set above
the EANI and EAO voltages and can be programmed by
an external resistor, as shown in Figure 5 using
Equation 3.
R1
CSS
R2
1.6
1.2
FIGURE 4. REFERENCE-BASED CLAMP CIRCUIT
0.8
0.4
R1 × R2
R2
Vclamp ≈ Iss • ---------------------- + Vref • ---------------------R1 + R2
R1 + R2
0
0
20
40
60
80
100
120
140
160
RD (kΩ)
FIGURE 3. RD vs DEAD TIME (VDD = 12V)
Error Amplifier (EAI, EANI, EAO)
(EQ. 4)
• The soft-start rise time (tss) can be calculated with
Equation 5. The rise time (trise) of the output voltage is
approximated with Equation 6.
EANI × Css
t rise = -------------------------------Iss
(s)
(EQ. 6)
Vclamp × Css
t ss = --------------------------------------Iss
(s)
(EQ. 5)
• This amplifier compares the feedback signal received at
the EAI pin to a reference signal set at the EANI pin and
provides an error signal (EAO) to the PWM Logic. The
feedback loop compensation can be programmed via
these pins.
Drivers (Upper1, Upper2, Lower1, Lower2)
• Both EANI and EAO are clamped by the voltage (Vclamp)
set at the CSS pin, as shown in Figure 5. Note that the
diodes in the functional block diagram represent the clamp
function of the CSS in a simplified way.
• The two upper drivers are driven at a fixed 50% duty cycle
and the two lower drivers are PWM-controlled on the
trailing edge while the leading edge employs resonant delay.
They are biased by VDDP1 and VDDP2, respectively.
Soft-Start (CSS)
• Each driver is capable of driving capacitive loads up to CL at
1MHz clock frequency and higher loads at lower frequencies
on a layout with high effective thermal conductivity.
• The voltage on an external capacitor charged by an internal
current source ISS is fed into a control pin on the error
amplifier. This causes the Error Amplifier to: 1) limit the
EAO to the soft-start voltage level; and 2) over-ride the
reference signal at the EANI with the soft-start voltage,
when the EANI voltage is higher than the soft-start voltage.
Thus, both the output voltage and current of the power
supply can be controlled by the soft-start.
11
• The UVLO holds all the drivers low until the VDD has
reached the turn-on threshold VDDON.
• The upper drivers require assistance of external level-shifting
circuits, such as Intersil’s HIP2100 or pulse transformers to
drive the upper power switches of a bridge converter.
FN6762.2
November 17, 2011
ISL6551I
400mV
+
-
VDD
CSS
(SEE FIG. 9)
SSL
(TO
BLANKING
CIRCUIT)
EAI
(–)
Iss
EANI
(+)
RCSS
SHUTDOWN
ERROR AMP
EAO
FIGURE 5. SIMPLIFIED CLAMP/SOFT-START
Peak Current Limit (PKILIM)
• When the voltage at PKILIM exceeds the BGREF voltage,
the gate pulses are terminated and held low until the next
clock cycle. The peak current limit circuit has a high-speed
loop with propagation delay IpkDel. Peak current shutdown
initiates a soft-start sequence.
• The peak current shutdown threshold is usually set slightly
higher than the normal cycle-by-cycle PWM peak current
limit (Vclamp) and therefore will normally only be activated in
a short-circuit condition. The limit can be set with a resistor
divider from the ISENSE pin. The resistor divider relationship
is defined in Equation 7.
• In general, the trip point is a little smaller than the BGREF
due to the noise and/or ripple at the BGREF.
• This pin is a non-latching input and can accept an enable
command when monitoring the input voltage and the thermal
condition of a converter.
Resonant Delay (R_RESDLY)
• A resistor tied between R_RESDLY and VSS determines the
delay that is required to turn on a lower FET after its
corresponding upper FET is turned off. This is the resonant
delay, which can be estimated with Equation 8.
(EQ. 8)
tRESDLY = 4.01 x R_RESDLY/kΩ + 13 (ns)
• Figure 7 illustrates the relationship of the value of the resistor
(R_RESDLY) and the resonant delay (tRESDLY). The
percentages in the figure are the tolerances at the two end
points of the curve.
500
ISENSE
+18%
450
RUP
-24%
400
PKILIM
tRESDLY (ns)
RDOWN
FIGURE 6. PEAK CURRENT LIMIT SET CIRCUIT
350
300
250
200
150
Rdown
BGREF
-------------------------------------- = ----------------------------------------Rdown + Rup
ISENSE ( max )
(EQ. 7)
Latching Shutdown (LATSD)
• A high TTL level on LATSD latches the IC off. The IC goes
into a low power mode and is reset only after the power at the
VDD pin is removed completely. The ON/OFF cannot reset
the latch.
• This pin can be used to latch the power supply off on output
overvoltage or other undesired conditions.
ON/OFF (ON/OFF)
• A high standard TTL input (safe also for VDD level) signals
the controller to turn on. A low TTL input turns off the
controller and terminates all drive signals including the SYNC
outputs. The soft-start is reset.
12
+37%
100
+4%
50
0
20
40
60
80
100
120
R_RESDLY (kΩ)
FIGURE 7. R_RESDLY vs RESDLY
Leading Edge Blanking (R_LEB)
• In current mode control, the sensed switch (FET) current is
processed in the Ramp Adjust and LEB circuits and then
compared to a control signal (EAO voltage). Spikes, due to
parasitic elements in the bridge circuit, would falsely trigger
the comparator generating the PWM signal. To prevent false
triggering, the leading edge of the sensed current signal is
blanked out by a period that can be programmed with the
R_LEB resistor. Internal switches gate the analog input to the
PWM comparator, implementing the blanking function that
FN6762.2
November 17, 2011
ISL6551I
Ramp Adjust (R_RA, ISENSE)
eliminates response degrading delays which would be
caused if filtering of the current feedback was incorporated.
The current ramp is blanked out during the resonant delay
period because no switching occurs in the lower FETs. The
leading edge blanking function will not be activated until the
soft-start (CSS) reaches over 400mV, as illustrated in Figures
5 and 9. The leading edge blanking (LEB) function can be
disabled by tying the R_LEB pin to VDD, i.e., LEB = 1. Never
leave the pin floating.
• The ramp adjust block adds an offset component (200mV)
and a slope adjust component to the ISENSE signal
before processing it at the PWM Logic block, as shown in
Figure 9. This ensures that the ramp voltage is always
higher than the OAGS (ground sensing op amp) minimum
voltage to achieve a “zero” state.
• It is critical that the input signal to ISENSE decays to zero
prior to or during the clock dead time. The level-shifting
and capacitive summing circuits in the RAMP ADJUST
block are reset during the dead time. Any input signal
transitions that occur after the rising edge of CLK and prior
to the rising edge of RESDLY can cause severe errors in
the signal reaching the PWM comparator.
• The blanking time can be estimated with Equation 9, whose
relationship can be seen in Figure 8. The percentages in the
figure are the tolerances at the two endpoints of the curve.
tLEB = 2 x R_LEB / kΩ + 15 (ns)
(EQ. 9)
300
• Typical ramp values are hundreds of mV over the period
on a 3V full scale current. Too much ramp makes the
controller look like a voltage mode PWM, and too little
ramp leads to noise issues (jitter). The amount of ramp
(Vramp), as shown in Figure 9, is programmed with the
R_RA resistor and can be calculated with Equation 10.
+20%
-18%
250
tLEB (ns)
200
150
Vramp = BGREF x dt /(R_RA x 500E-12) (V)
(EQ. 10)
+51%
100
where dt = Duty Cycle/Fsw - tLEB (s). Duty cycle is
discussed in detail in application note AN1002.
-11%
50
0
20
40
60
80
100
120
• The voltage representation of the current flowing through
the power train at ISENSE pin is normally scaled such that
the desired peak current is less than or equal to
Vclamp-200mV-Vramp, where the clamping voltage is set
at the CSS pin.
140
R_LEB (kΩ)
FIGURE 8. R_LEB vs tLEB
0.1µ
VDD
ADJ_RAMP
ADJ_RAMP
399k
200mV
RAMP_OUT
(TO PWM
COMPARATOR)
BGREF
R_RA
ISENSE
0
RAMP_OUT
200mV
R_RA
BLANK
ADD RAMP
+
ISENSE
200mV
R_LEB
SET
BLANKING
TIME
R_LEB
-
RESDLY
LEB
SSL
RAMP_OUT
0
X
X
BLANK
RESDLY
LEB
X
0
0
BLANK
1
1
X
NO BLANK
SSL
(SEE FIG. 4)
1
X
1
NO BLANK
FIGURE 9. SIMPLIFIED RAMP ADJUST AND LEADING EDGE BLANKING CIRCUITS
13
FN6762.2
November 17, 2011
ISL6551I
CS_COMP
0.1µF
30mV
+
-
EAO
1k
ADJ
+
+
-
EANI
(+)
OTA
OUTPUT
REFERENCE
SHARE
30k
FIGURE 10. SIMPLIFIED CURRENT SHARE CIRCUIT
SYNC Outputs (SYNC1, SYNC2)
• SYNC1 and SYNC2 are the gate control signals for the
output synchronous rectifiers. They are biased by VDD
and are capable of driving capacitive loads up to 20pF at
1MHz clock frequency (500kHz switching frequency).
These outputs are turned off sooner than the turn-off at
UPPER1 and UPPER2 by the clock dead time, DT.
• Inverting both SYNC signals or both LOWER signals is
another possible way to control the drivers of the
synchronous rectifiers. When using these drive schemes,
the user should understand the issues that might occur in
his/her applications, especially the impacts on current
share operation and light load operation. Refer to
application note AN1002 for more details.
between CS_COMP and VSS pins to achieve a low
current sharing loop bandwidth (100Hz to 500Hz).
Power-Good (DCOK)
• DCOK pin is an open drain output capable of sinking 5mA.
It is low when the output voltage is within the UVOV
window. The static regulation limit is ±3%, while the ±5% is
the dynamic regulation limit. It indicates power-good when
the EAI is within -3% to +5% on the rising edge and within
+3% to -5% on the falling edge, as shown in Figure 11.
EAI
+5%
+3%
EANI
• External high current drivers controlled by the
synchronous signals are required to drive the
synchronous rectifiers. A pulse transformer is required to
pass the drive signals to the secondary side if the IC is
used in a primary control system.
-3%
-5%
Share Support (SHARE, CS_COMP)
• The unit with the highest reference is the master. Other
units, as slaves, adjust their references via a source resistor
to match the master reference sharing the load current. The
source resistor is typically 1kΩ connecting the EANI pin and
the OUTPUT REFERENCE (external reference or
BGREF), as shown in Figure 10. The share bus represents
a 30kΩ resistive load per unit, up to 10 units.
• The output (ADJ) of “Operational Transconductance
Amplifier (OTA)” can only pull high and it is floating while in
master mode. This ensures that no current is sourced to the
OUTPUT REFERENCE when the IC is working by itself.
• The slave units attempt to drive their error amplifier
voltage to be within a pre-determined offset (30mV typical)
of the master error voltage (the share bus). The currentshare error is nominally (30mV/EAO)*100% assuming no
other source of error. With a 2.5V full load error amp
voltage, the current-share error at full load would be -1.2%
(slaves relative to master).
• The bandwidth of the current sharing loop should be much
lower than that of the voltage loop to eliminate noise pickup and interactions between the voltage regulation loop
and the current loop. A 0.1µF capacitor is recommended
14
DCOK
FAULT
FIGURE 11. UNDERVOLTAGE-OVERVOLTAGE WINDOW
• The DCOK comparator might not be triggered even though
the output voltage exceeds ± 5% limits at load transients.
This is because the feedback network of the error amplifier
filters out part of the transients and the EAI only sees the
remaining portion that is still within the limits, as illustrated in
Figure 12. The lower the “zero (1/RC)” of the error amplifier,
the larger the portion of the transient that is filtered out.
Thermal Pad (in QFN only)
• In the QFN package, the pad underneath the center of
the IC is a “floating” thermal substrate. The PCB “thermal
land” design for this exposed die pad should include
thermal vias that drop down and connect to one or more
buried copper plane(s). This combination of vias for
vertical heat escape and buried planes for heat
spreading allows the QFN to achieve its full thermal
potential. This pad should be connected to a low noise
copper plane such as Vss.
• Refer to TB389 for design guidelines.
FN6762.2
November 17, 2011
ISL6551I
18k
EAI
R
VOUT
1k
Table 11 highlights parameter setting for the ISL6551IREC.
Designers can use this table as a design checklist. For
detailed operation of the ISL6551IREC, see “Block/Pin
Functional Descriptions” on page 9.
C
+
EANI
Additional Applications Information
15N
EAO
Figure 13 shows the block diagram of a power supply system
employing the ISL6551IREC full bridge controller. The
ISL6551IREC not only is a full bridge PWM controller but also
can be used as a push-pull PWM controller. Users can design
a power supply by selecting appropriate blocks in the System
Blocks Chart based on the power system requirements.
Figures 13A, 14A, 15A, 16A, 17A, 18A, 19, 20A, 21, 22A, and
24A have been used in the 200W telecom power supply
reference design, which can be found in the Application Note
AN1002. To meet the specifications of the power supply,
minor modifications of each block are required. To take full
advantage of the integrated features of the ISL6551IREC,
“secondary side control” is recommended.
1.10V
VOUT
1.00V
0.90V
1.05V
EAI
1.00V
0.95V
FIGURE 12. OUTPUT TRANSIENT REJECTION
TABLE 1. PARAMETER SETTING HIGHLIGHTS/CHECKLIST
PARAMETER
PIN NAME
FORMULA OR SETTING HIGHLIGHT
UNIT
FIGURE #
kHz
1, 2
Frequency
CT
Set 50% Duty Cycle Pulses with a fixed frequency
Dead Time
RD
DT = MxRD/kΩ, where M = 11.4
ns
3
R_RESDLY
tRESDLY = 4.01xR_RESDLY/kΩ + 13
ns
7
R_RA
Vramp = BGREF/(R_RAx500E-12)xdt
V
-
Resonant Delay
Ramp Adjust
Current Sense
ISENSE
<Vclamp - 200mV - Vramp
V
-
Peak Current
PKILIM
<BGREF and slightly higher than Vclamp
V
6
Bandgap Reference
BGREF
1.263V ±2%, 399kΩ pull-up, No more than 100µA load
V
-
Leading Edge Blanking
R_LEB
tLEB = 2 x R_LEB/kΩ + 15, never leave it floating
ns
8, 9
0.1µ for a low current loop bandwidth (100 - 500Hz)
Hz
10
Current Share Compensation
CS_COMP
Soft-Start & Output Rise Time
CSS
tss = VclampxCss/Iss, trise = EANI x CSS/Iss, Iss = 10µA ±20%
S
4
Clamp Voltage (Vclamp)
CSS
Vclamp = IssxRcss, or Reference-based clamp
V
4, 5
EANI, EAO < Vclamp
V
-
Error Amplifier
EANI, EAI, EAO
Share Support
SHARE
30K load and a resistor (1k, typ.) between EANI and OUTPUT REF.
-
-
Latching Shutdown
LATSD
Latch IC off at > 3V
V
-
Power-Good
DCOK
±5% with hysteresis, Sink up to 5mA, transient rejection
V
11, 12
Turn on/off at TTL level
V
-
Connect to PGND in only one single point
-
-
Single point to VSS plane
-
-
IC Enable
ON/OFF
Reference Ground
VSS
Power Ground
PGND
Upper Drivers
UPPER1, UPPER2 Capacitive load up to 1.6nF at Fsw = 500kHz
-
-
Lower Drivers
LOWER1, LOWER2 Capacitive load up to 1.6nF at Fsw = 500kHz
-
-
Capacitive load up to 20pF at Fsw = 500kHz
-
-
12V ±10%, 0.1µF decoupling capacitor
V
-
Need decoupling capacitors
V
-
Synchronous Drive Signals
SYNC1, SYNC2
Bias for Control Circuits
VDD
Biases for Bridge Drivers
VDDP1, VDDP2
NOTE: VDD = 12V at room temperature, unless otherwise stated.
15
FN6762.2
November 17, 2011
ISL6551I
PRIMARY BIAS
BIASES
SECONDARY BIAS
VIN
INPUT
FILTER
PRIMARY
FETs
CURRENT
SENSE
MAIN
TRANSFORMER
PRIMARY FET
DRIVERS
RECTIFIERS
ISL6551IREC
CONTROLLER
VOUT
OUTPUT
FILTER
SECONDARY
DRIVERS
SUPERVISOR
CIRCUITS
FEEDBACK
FIGURE 13. BLOCK DIAGRAM OF A POWER SUPPLY SYSTEM USING ISL6551IREC CONTROLLER
Current Sense
System Blocks Chart
ISENSE
T_CURRENT
Input Filters
Q3_S
VIN
VINF
CIN
Q4_S
FIGURE 13A. GENERAL
FIGURE 14A. TWO-LEG SENSE
VIN
LIN
ISENSE
VINF
VINF
CIN
CURRENT_SEN_P
FIGURE 14B. TOP SENSE
FIGURE 13B. EMI
GENERAL
Input capacitors are required to absorb the power switch
(FET) pulsating currents.
Q3_S AND Q4_S
ISENSE
RSENSE
EMI
For good EMI performance, the ripple current that is
reflected back to the input line can be reduced by an input
L-C filter, which filters the differential-mode noises and
operates at two times the switching frequency, i.e., the
clock frequency (Fclock). In some cases, an additional
common-mode choke might be required to filter the
common-mode noises.
FIGURE 14C. RESISTOR SENSE (PRIMARY CONTROL)
TWO-LEG SENSE
Senses the current that flows through both lower primary FETs.
Operates at the switching frequency.
TOP SENSE
Senses the sum of the current that flows through both upper
primary FETs. Operates at the clock frequency.
16
FN6762.2
November 17, 2011
ISL6551I
Feedback
RESISTOR SENSE
This simple scheme is used in a primary side control system.
The sum of the current that flows through both lower primary
FETs is sensed with a low impedance power resistor. The
sources of Q3 and Q4 and ISENSE should be tied at the same
point as close as possible.
EAO
EAI
VOPOUT
Biases
Linear Regulator - In a primary side control system, a
linear regulator derived from the input line can be used for
the start-up purpose, and an extra winding coupled with the
main transformer can provide the controller power after the
start-up.
FIGURE 16A. SECONDARY CONTROL
DCM Flyback - Use a PWM controller to develop both
primary and secondary biases with discontinuous current
mode flyback topology.
VREF = 5V
Primary FETs
VOPOUT
IL207
VINF OR
CURRENT_SEN_P
Q1
Q1_G
P–
EAO
Q2
Q2_G
EAI
TL431
P+
Q3
Q3_G
Q4
Q4_G
Q3_S
Q4_S
FIGURE 16B. PRIMARY CONTROL
FIGURE 15A. FULL BRIDGE
SECONDARY CONTROL
P1–
In secondary side control systems, only a few resistors and
capacitors are required to complete the feedback loop.
P2–
PRIMARY CONTROL
Q3
Q3_G
Q4
Q4_G
Q4_S
Q3_S
This feedback loop configuration for primary side control
systems requires an optocoupler for isolation. The
bandwidth is limited by the optocoupler.
Rectifiers
FIGURE 15B. PUSH-PULL
SYNCHRONOUS FETs
S+
S+
FULL BRIDGE
Four MOSFETs are required for full bridge converters. The
drain to source voltage rating of the MOSFETs is Vin.
PUSH-PULL
SCHOTTKY
SYNP
SYNN
Only the two lower MOSFETs are required for push-pull
converters. The two upper drivers are not used. The VDS of
the MOSFETs is 2xVin.
S–
S–
FIGURE 17A. CURRENT DOUBLER RECTIFIERS
17
FN6762.2
November 17, 2011
ISL6551I
SYNCHRONOUS FETs
SCHOTTKY
S+
S+
P1–
VINF OR
CURRENT_SEN_P
P2–
SYNP
SYNN
S+
S–
FIGURE 18C. PUSH-PULL AND CURRENT DOUBLER
S–
S–
P1–
FIGURE 17B. CONVENTIONAL RECTIFIERS
VINF OR
CURRENT_SEN_P
P2–
S+
S+
VOUTF
S–
FIGURE 18D. CONVENTIONAL PUSH-PULL
FULL BRIDGE AND CURRENT DOUBLER
No center tap is required. The secondary winding carries half
of the load, i.e., only half of the load is reflected to the
primary.
S–
CONVENTIONAL FULL BRIDGE
FIGURE 17C. SELF-DRIVEN RECTIFIERS
CURRENT DOUBLER RECTIFIERS
1. Synchronous FETs are used for low output voltage, high
output current and/or high efficiency applications.
2. Schottky diodes are used for lower current applications.
Pins S+ and S- are connected to the output filter and the
main transformer with current doubler configurations.
CONVENTIONAL RECTIFIERS
1. Synchronous FETs are used for low output voltage, high
output current and/or high efficiency applications.
2. Schottky diodes are used for lower current applications.
Pins S+ and S- are connected to the main transformer
with conventional configurations.
Center tap is required on the secondary side, and no center
tap is required on the primary side. The secondary winding
carries all the load. i.e., all the load is reflected to the primary.
PUSH-PULL AND CURRENT DOUBLER
Center tap is required on the primary side, and no center tap
is required on the secondary side. The secondary winding
carries half of the load, i.e., only half of the load is reflected
to the primary.
CONVENTIONAL PUSH-PULL
Both primary and secondary sides require center taps. The
secondary winding carries all the load, i.e., all the load is
reflected to the primary.
Supervisor Circuits
SELF-DRIVEN RECTIFIERS
INTEGRATED SOLUTION
For low output voltage applications, both FETs can be driven
by the voltage across the secondary winding. This can work
with all kinds of main transformer configurations, as shown in
Figures 18A, 18B, 18C and 18D.
• Intersil ISL6550 Supervisor and Monitor (SAM).
• Over-temperature protection (discrete)
• Input UV lockout (discrete)
Main Transformers
S+
P+
VOPOUT
P–
S–
VREF5
FIGURE 18A. FULL BRIDGE AND CURRENT DOUBLER
BDAC
P+
S+
VOUTF
P–
VCC
1
20 UVDLY
VOPP
2
VOPM
3
19 OVUVSEN
18 PGOOD
PGOOD
VOPOUT
4
17 START
START
VREF5
5
16 PEN
PEN
GND
6
15 VID0
BDAC
7
14 VID1
OVUVTH
8
13 VID2
DACHI
9
12 VID3
DACLO 10
11 VID4
FIGURE 19. ISL6550
S–
FIGURE 18B. CONVENTIONAL FULL BRIDGE
18
FN6762.2
November 17, 2011
ISL6551I
DISCRETE SOLUTION
28 VDD
VSS 1
• Differential Amplifier
• VCC undervoltage lockout
• Programmable output OV and UV
CT 2
27 VDDP1
RD 3
26 VDDP2
25 PGND
R_RESDLY 4
• Programmable output
• Status indicators (PGOOD and START)
R_RA 5
24 UPPER1
ISENSE 6
23 UPPER2
PKILIM 7
ISL6551
INPUT
22 LOWER1 UV AND OV
• Precision Reference
BGREF 8
21 LOWER2
• Over- temperature protection
R_LEB 9
20 SYNC1
CS_COMP 10
19 SYNC2
• Input UV lockout
The Integrated Solution is much simpler than a discrete
solution. Over-temperature protection and input
undervoltage lockout can be added for better system
protection and performance.
OUTPUT
REFERENCE
(BDAC)
EAI
EAO
18 ON / OFF
EANI 12
17 DCOK
EAI 13
16 LSTSD
EAO 14
15 SHARE
LED
LSTSD
SHARE
BUS
The Discrete Solution requires a significant number of
components to implement the features that the ISL6550 can
provide.
FIGURE 21. ISL6551IREC CONTROLLER
Secondary Drivers
Output Filter
LOUT
S+
CSS 11
MIC4421BM
VOUT
COUT
SYNC2
IN OUT
/LOWER1
MIC4421BM
SYNP
SYNC1
/LOWER2
IN OUT
GND
GND
S–
SYNN
FIGURE 20A. CURRENT DOUBLER FILTER
FIGURE 22A. INVERTING DRIVERS
LOUT
VOUT
VOUTF
FCLOCK
MIC4422BM
MIC4422BM
COUT
FIGURE 20B. CONVENTIONAL FILTER
SYNC1
IN OUT
SYNP
SYNC2
IN OUT
GND
GND
Current Doubler Filter - Two inductors are needed, but they
can be integrated and coupled into one core. Each inductor
carries half of the load operating at the switching frequency.
FIGURE 22B. NON-INVERTING DRIVERS
Conventional Filter - One inductor is needed. The inductor
carries all the load operating at two times the switching
frequency.
IN OUT
T_SYN
Controller
ISL6551IREC CONTROLLER
It can be used as a full bridge or push-pull PWM controller. The
QFN package requires less space.
SYNN
SYNP
GND
SYN1
SYN2
IN OUT
FSW
SYNN
GND
FIGURE 22C. PRIMARY CONTROL
19
FN6762.2
November 17, 2011
ISL6551I
INVERTING
Primary FET Drivers
NON INVERTING
PUSH-PULL DRIVERS
SYN1
SYNC2/LOWER1
SYNC1
SYN2
SYNC1/LOWER2
SYNC2
IC
MIC4421BM
MIC4422BM
Push-Pull Medium Current Drivers
Upper drivers are not used. No external drivers are required.
Secondary control. Operate at the switching frequency.
INVERTING DRIVERS
Inverting the SYNC signals or the LOWER signals with
external high current drivers to drive the synchronous FETs.
Push-Pull High Current Drivers
Upper drivers are not used. External high current drivers are
required and less power is dissipated in the ISL6551IREC
controller. Secondary control. Operate at the switching
frequency.
NON-INVERTING DRIVERS
Cascading SYNC signals with non-inverting high current
drivers to drive the synchronous FETs. There is a dead time
between SYNC1 and SYNC2. For a higher efficiency,
Schottky diodes are normally in parallel with the
synchronous FETs to reduce the conduction losses during
the dead time in high output current applications.
Push-Pull Primary Control
Upper drivers are not used. Both lower drivers can directly
drive the power switches. External drivers are required in
high gate capacitance applications.
PRIMARY CONTROL
This requires a pulse transformer, operating at the switching
frequency, for isolation. There are three options to drive the
synchronous FETs, as described in previous lines.
HIP2100IB
Q3_G
HO
Q3_G
HS
LI
VSS LO
Q3_S
HI
LOWER1
Q3_S
LOWER1
Q4_S
Q4_G
Q4_S
LOWER2
LOWER2
Q4_G
FIGURE 23B. PUSH-PULL HIGH CURRENT DRIVERS
FIGURE 23A. PUSH-PULL MEDIUM CURRENT DRIVERS
HIP2100IB
LOWER1
LOWER2
PGND
HO
Q3_G
HS
Q3_S
VSS LO
Q4_G
HI
LI
Q4_S
FIGURE 23C. PUSH-PULL PRIMARY CONTROL
20
FN6762.2
November 17, 2011
ISL6551I
FULL BRIDGE DRIVERS
FULL BRIDGE PRIMARY CONTROL
FULL BRIDGE HIGH CURRENT DRIVERS
Lower drivers can directly drive the power switches, while
upper drivers require the assistance of level-shifting circuits
such as a pulse transformer or Intersil’s HIP2100 half-bridge
driver. External high current drivers are not required in
medium power applications, but level-shifting circuits are still
required for upper drivers. Operate at the switching frequency.
External high current drivers are required and less power is
dissipated in the ISL6551IREC controller. Secondary control.
Operate at the switching frequency.
FULL BRIDGE MEDIUM CURRENT DRIVERS
No external drivers are required. Secondary control. Operate
at the switching frequency.
HIP2100IB
HI
HO
HS
LI
VSS LO
UPPER1
Q1_G
Q1_G
P–
Q3_G
UPPER1
P–
Q3_S
UPPER2
P+
UPPER2
HIP2100IB
HO
HI
HS
LI
VSS LO
Q2_G
Q2_G
P+
Q3_G
Q4_G
LOWER1
Q4_S
LOWER1
LOWER2
Q3_S
Q4_S
LOWER2
Q4_G
FIGURE 24B. FULL BRIDGE MEDIUM CURRENT DRIVERS
FIGURE 24A. FULL BRIDGE HIGH CURRENT DRIVERS
HIP2100IB
UPPER1
LOWER1
HI
HO
HS
LI
VSS LO
PGND
Q1G
P–
Q3_G
Q3_S
HIP2100IB
UPPER2
HI
LOWER2
LI
VSS LO
PGND
HO
HS
Q2_G
P+
Q4_G
Q4_S
FIGURE 24C. FULL BRIDGE PRIMARY CONTROL
21
FN6762.2
November 17, 2011
Simplified Typical Application Schematics
SB+48V
SB+12V
SA+12V
VDD
HB
HO
HS
UPPER1
LOWER1
VS VS
OUT IN
OUT NC
GND GND
LO
VSS
LI
HI
SYNC2
3.3Vout
MIC4421
HIP2100
UPPER2
22
SA+12V
LOWER2
VS VS
OUT IN
OUT NC
GND GND
LOWER1
SB+12V
VDD
HB
HO
HS
LOWER2
SYNC1
MIC4421
LO
VSS
LI
HI
+
HIP2100
SA+12V
-
V+
+
V-
SA+12V
-
OUT
20
19
18
17
16
15
14
13
12
11
UVDLY
VCC
OVU VSEN VOPP
PGOOD
VOPM
START VOPOUT
PEN
VREF5
VID0
G ND
BDAC
VID1
OVUVTH
VID2
DACHI
VID3
DACLO
VID4
ISL6550
1.263V
PGND
UPPER1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
UPPER2
LOWER1
LOWER2
SYNC1
SYNC2
LED
VDD
VSS
VDDP1
CT
RD
VDDP2
PGND R_RESDLY
UPPER1
R_RA
UPPER2
ISENSE
LOWER1
PKILIM
LOWER2
BGREF
SYNC1
R_LEB
SYNC2 CS_COMP
ON/OFF
CSS
DCOK
EANI
LATSD
EAI
SHARE
EAO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ISL6551
FN6762.2
November 17, 2011
SHARE BUS
200W TELECOMMUNICATION POWER SUPPLY (SEE AN1002 FOR DETAILS)
1
2
3
4
5
6
7
8
9
10
ISL6551I
PGOOD
ISL6551I
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L28.6x6
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VJJC ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
A3
b
0.23
D
0.28
9
0.35
5, 8
6.00 BSC
D1
D2
9
0.20 REF
-
5.75 BSC
3.95
4.10
9
4.25
7, 8
E
6.00 BSC
-
E1
5.75 BSC
9
E2
3.95
e
4.10
4.25
7, 8
0.65 BSC
-
k
0.25
-
-
-
L
0.35
0.60
0.75
8
L1
-
-
0.15
10
N
28
2
Nd
7
3
Ne
7
3
P
-
-
0.60
9
θ
-
-
12
9
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
23
FN6762.2
November 17, 2011
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