DATASHEET

ISL6752
®
Data Sheet
October 31, 2008
ZVS Full-Bridge Current-Mode PWM with
Adjustable Synchronous Rectifier Control
The ISL6752 is a high-performance, low-pin-count alternative
zero-voltage switching (ZVS) full-bridge PWM controller. Like
Intersil’s ISL6551, it achieves ZVS operation by driving the
upper bridge FETs at a fixed 50% duty cycle while the lower
bridge FETs are trailing-edge modulated with adjustable
resonant switching delays. Compared to the more familiar
phase-shifted control method, this algorithm offers equivalent
efficiency and improved overcurrent and light-load performance
with less complexity in a lower pin count package.
FN9181.3
Features
• Adjustable Resonant Delay for ZVS Operation
• Synchronous Rectifier Control Outputs with Adjustable
Delay/Advance
• Current-Mode Control
• 3% Current Limit Threshold
• Adjustable Deadtime Control
• 175µA Start-up Current
• Supply UVLO
The ISL6752 features complemented PWM outputs for
synchronous rectifier (SR) control. The complemented
outputs may be dynamically advanced or delayed relative to
the PWM outputs using an external control voltage.
• Adjustable Oscillator Frequency Up to 2MHz
This advanced BiCMOS design features precision deadtime
and resonant delay control, and an oscillator adjustable to
2MHz operating frequency. Additionally, Multi-Pulse
Suppression ensures alternating output pulses at low duty
cycles where pulse skipping may occur.
• Fast Current Sense to Output Delay
Ordering Information
• Pb-Free (RoHS Compliant)
PART
NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6752AAZA* ISL 6752AAZ -40 to +105 16 Ld QSOP M16.15A
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
• Internal Over-Temperature Protection
• Buffered Oscillator Sawtooth Output
• Adjustable Cycle-by-Cycle Peak Current Limit
• 70ns Leading Edge Blanking
• Multi-Pulse Suppression
Applications
• ZVS Full-Bridge Converters
• Telecom and Datacom Power
• Wireless Base Station Power
• File Server Power
• Industrial Power Systems
Pinout
ISL6752
(16 LD QSOP)
TOP VIEW
VADJ 1
16 VDD
VREF 2
15 OUTLL
VERR 3
14 OUTLR
CTBUF 4
13 OUTUL
RTD 5
12 OUTUR
RESDEL 6
11 OUTLLN
CT 7
10 OUTLRN
CS 8
1
9 GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Functional Block Diagram
VDD
VDD
VREF
UVLO
OUTUL
50%
OUTUR
PWM
STEERING
LOGIC
OVERTEMPERATURE
PROTECTION
DELAY/
ADVANCE
TIMING
CONTROL
PWM
OUTLL
OUTLR
2
OUTLLN
GND
OUTLRN
VREF
RESDEL
OSCILLATOR
+
RTD
-
CS
1.00V
70ns
LEADING
EDGE
BLANKING
OVERCURRENT
COMPARATOR
CTBUF
80mV
+
PWM
COMPARATOR
0.33
VREF
1mA
VERR
ISL6752
CT
VADJ
FN9181.3
October 31, 2008
Typical Application - High Voltage Input Primary Side Control ZVS Full-Bridge Converter
VIN+
CR2
3
Q1
Q8A
Q8B
CR3
T3
R11
R10
Q5A
Q2
Q5B
C9
C8
+
T1
C1
R12
400 VDC
Q10A
Q10B
R1
C7 +
C15
C12
Q13
+
VOUT
L1
Q12
Q9A
Q9B
C10
R13
RETURN
Q7A
Q6B
Q7B
C13
Q3
ISL6752
Q4
Q6A
R18
VINR17
R19
T2
CR1
VDD
VREF
OUTLL
VERR
OUTLR
OUTUL
CTBUF
RTD
R2
R20
ISL6752
R8
VADJ
R16
EL7212
CT
CS
R4
R7
T4
EL7212
C14
OUTUR
CR4
RESDEL OUTLLN
R3
R23
C5
U5
OUTLRN
GND
U4
C11
U1
R24
R15
Q11
R23
R24
Q14
U3
VDD
U2
C3
C2
VR1
R5 R6
C17
C4
R21
R22
C16
C6
R14
FN9181.3
October 31, 2008
Typical Application - High Voltage Input Secondary Side Control ZVS Full-Bridge Converter
VIN+
T3
1:1:1
Q1
Q2
Q6
Q5
4
R13
CR2
CR3
T1
Np:Ns:Ns = 9:2:2
R12
R15
Ns
Np
C10
Q10A
Q10B
+ VOUT
L1
Q16
Ns
Q9A
Q9B
C13
C12
C14 +
+
400 VDC
C1
R14
T4
1:1:1
Q4
Q7A
Q7B
Q15
CR5
CR4
R10
Q3
Q8A
Q8B
RETURN
C9
C7
Q11A
Q12A
Q11B
Q12B
Q13A
Q13B
VINVREF
R7
T2
VDD
VREF
OUTLL
VERR
CTBUF
RTD
OUTLR
OUTUL
ISL6752
R8
VADJ
R17
Q14A
Q14B
OUTUR
RESDEL OUTLLN
CT
OUTLRN
CS
GND
R9
R1
R6
C17
C16
Q17
U1
C15
R18
R16
R20
SECONDARY
BIAS
SUPPLY
VREF
R22
C2
R4
FN9181.3
October 31, 2008
R2 R3
C3
C4
C5
R5
U3
+
C6
R19
R21
C18
ISL6752
R11
C8
CR1
C11
ISL6752
Absolute Maximum Ratings (Note 2)
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V
OUTxxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD
Signal Pins . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VREF + 0.3V
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1A
Thermal Resistance Junction to Ambient (Typical)
θJA (°C/W)
16 Ld QSOP (Note 1). . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . 9VDC to 16VDC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. All voltages are with respect to GND.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 2
and “Typical Application - High Voltage Input Primary Side Control ZVS Full-Bridge Converter” on page 3 and
“Typical Application - High Voltage Input Secondary Side Control ZVS Full-Bridge Converter” on page 4.
9V < VDD < 20V, RTD = 10.0kΩ, CT = 470pF, TA = -40°C to +105°C, Typical values are at TA = +25°C;
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature
limits established by characterization and are not production tested.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
-
20
V
SUPPLY VOLTAGE
Supply Voltage
Start-Up Current, IDD
VDD = 5.0V
-
175
400
µA
Operating Current, IDD
RLOAD, COUT = 0
-
11.0
15.5
mA
UVLO START Threshold
8.00
8.75
9.00
V
UVLO STOP Threshold
6.50
7.00
7.50
V
-
1.75
-
V
4.850
5.000
5.150
V
-
3
-
mV
-10
-
-
mA
5
-
-
mA
VREF = 4.85V
-15
-
-100
mA
Current Limit Threshold
VERR = VREF
0.97
1.00
1.03
V
CS to OUT Delay
Excl. LEB (Note 3)
-
35
50
ns
Leading Edge Blanking (LEB) Duration
(Note 3)
50
70
100
ns
CS to OUT Delay + LEB
TA = +25°C
-
-
130
ns
CS Sink Current Device Impedance
VCS = 1.1V
-
-
20
Ω
Input Bias Current
VCS = 0.3V
-6.00
-
-2.00
µA
CS to PWM Comparator Input Offset
TA = +25°C
65
80
95
mV
Hysteresis
REFERENCE VOLTAGE
Overall Accuracy
IVREF = 0mA to 10mA
Long Term Stability
TA = +125°C, 1000 hours (Note 3)
Operational Current (Source)
Operational Current (Sink)
Current Limit
CURRENT SENSE
PULSE WIDTH MODULATOR
VERR Pull-Up Current Source
VERR = 2.50V
0.80
1.00
1.30
mA
VERR VOH
ILOAD = 0mA
4.20
-
-
V
Minimum Duty Cycle
VERR < 0.6V
-
-
0
%
5
FN9181.3
October 31, 2008
ISL6752
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 2
and “Typical Application - High Voltage Input Primary Side Control ZVS Full-Bridge Converter” on page 3 and
“Typical Application - High Voltage Input Secondary Side Control ZVS Full-Bridge Converter” on page 4.
9V < VDD < 20V, RTD = 10.0kΩ, CT = 470pF, TA = -40°C to +105°C, Typical values are at TA = +25°C;
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature
limits established by characterization and are not production tested. (Continued)
PARAMETER
Maximum Duty Cycle (Per Half-cycle)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VERR = 4.20V, VCS = 0V (Note 4)
-
94
-
%
RTD = 2.00kΩ, CT = 220pF
-
97
-
%
RTD = 2.00kΩ, CT = 470pF
-
99
-
%
0.85
-
1.20
V
0.7
0.8
0.9
V
0.31
0.33
0.35
V/V
(Note 3)
0
-
4.45
V
(Note 3)
165
183
201
kHz
-10
-
10
%
Zero Duty Cycle VERR Voltage
VERR to PWM Comparator Input Offset
TA = +25°C
VERR to PWM Comparator Input Gain
Common Mode (CM) Input Range
OSCILLATOR
Frequency Accuracy, Overall
Frequency Variation with VDD
TA = +25°C, (F20V- - F10V)/F10V
-
0.3
1.7
%
Temperature Stability
VDD = 10V, |F-40°C - F0°C|/F0°C
-
4.5
-
%
|F0°C - F105°C|/F25°C (Note 3)
-
1.5
-
%
-193
-200
-207
µA
19
20
23
µA/µA
Charge Current
TA = +25°C
Discharge Current Gain
CT Valley Voltage
Static Threshold
0.75
0.80
0.88
V
CT Peak Voltage
Static Threshold
2.75
2.80
2.88
V
CT Pk-Pk Voltage
Static Value
1.92
2.00
2.05
V
1.97
2.00
2.03
V
0
-
2.00
V
RTD Voltage
RESDEL Voltage Range
CTBUF Gain (VCTBUFp-p/VCTp-p)
VCT = 0.8V, 2.6V
1.95
2.0
2.05
V/V
CTBUF Offset from GND
VCT = 0.8V
0.34
0.40
0.44
V
CTBUF VOH
ΔV(ILOAD = 0mA, ILOAD = -2mA),
VCT = 2.6V
-
-
0.10
V
CTBUF VOL
ΔV(ILOAD = 2mA, ILOAD = 0mA),
VCT = 0.8V
-
-
0.10
V
High Level Output Voltage (VOH)
IOUT = -10mA, VDD - VOH
-
0.5
1.0
V
Low Level Output Voltage (VOL)
IOUT = 10mA, VOL - GND
-
0.5
1.0
V
Rise Time
COUT = 220pF, VDD = 15V (Note 3)
-
110
200
ns
Fall Time
COUT = 220pF, VDD = 15V (Note 3)
-
90
150
ns
UVLO Output Voltage Clamp
VDD = 7V, ILOAD = 1mA (Note 5)
-
-
1.25
V
Output Delay/Advance Range
OUTLLN/OUTLRN relative to OUTLL/OUTLR
VADJ = 2.50V (Note 3)
-
-
3
ns
VADJ < 2.425V
-40
-
-300
ns
VADJ > 2.575V
40
-
300
ns
2.575
-
5.000
V
0
-
2.425
V
OUTPUT
Delay/Advance Control Voltage Range
OUTLLN/OUTLRN relative to OUTLL/OUTLR
6
OUTLxN Delayed
OUTLxN Advanced
FN9181.3
October 31, 2008
ISL6752
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 2
and “Typical Application - High Voltage Input Primary Side Control ZVS Full-Bridge Converter” on page 3 and
“Typical Application - High Voltage Input Secondary Side Control ZVS Full-Bridge Converter” on page 4.
9V < VDD < 20V, RTD = 10.0kΩ, CT = 470pF, TA = -40°C to +105°C, Typical values are at TA = +25°C;
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature
limits established by characterization and are not production tested. (Continued)
PARAMETER
TEST CONDITIONS
VADJ Delay Time
MIN
TYP
MAX
UNITS
VADJ = 0
280
300
320
ns
VADJ = 0.5V
92
105
118
ns
VADJ = 1.0V
61
70
80
ns
VADJ = 1.5V
48
55
65
ns
VADJ = 2.0V
41
50
58
ns
VADJ = VREF
280
300
320
ns
VADJ = VREF - 0.5V
86
100
114
ns
VADJ = VREF - 1.0V
59
68
77
ns
VADJ = VREF - 1.5V
47
55
62
ns
VADJ = VREF - 2.0V
41
48
55
ns
TA = +25°C (OUTLx Delayed) (Note 6)
TA = +25°C (OUTLxN Delayed)
THERMAL PROTECTION
Thermal Shutdown
(Note 3)
130
140
150
°C
Thermal Shutdown Clear
(Note 3)
115
125
135
°C
Hysteresis, Internal Protection
(Note 3)
-
15
-
°C
NOTES:
3. Limits established by characterization and are not production tested..
4. This is the maximum duty cycle achievable using the specified values of RTD and CT. Larger or smaller maximum duty cycles may be obtained
using other values for these components. See Equations 1 through 3.
5. Adjust VDD below the UVLO stop threshold prior to setting at 7V.
6. When OUTx is delayed relative to OUTLxN (VADJ < 2.425V), the delay duration as set by VADJ should not exceed 90% of the CT discharge
time (deadtime) as determined by CT and RTD.
Typical Performance Curves
CT DISCHARGE CURRENT GAIN
NORMALIZED VREF
1.02
1.01
1.00
0.99
0.98
-40
-25
-10
5
20
35
50
65
80
95
110
TEMPERATURE (°C)
FIGURE 1. REFERENCE VOLTAGE vs TEMPERATURE
7
25
24
23
22
21
20
19
18
0
200
400
600
800
1000
RTD CURRENT (µA)
FIGURE 2. CT DISCHARGE CURRENT GAIN vs RTD CURRENT
FN9181.3
October 31, 2008
ISL6752
Typical Performance Curves
1-103
CT = 1000pF
FREQUENCY (kHz)
DEADTIME TD (ns)
1-104
(Continued)
CT = 680pF
1-103
CT = 330pF
100
CT = 220pF
CT = 100pF
CT = 470pF
RTD = 10kΩ
100
RTD = 50kΩ
RTD = 100kΩ
10
0
10
20
30
40 50 60
RTD (kΩ)
70
80
90
100
FIGURE 3. DEADTIME (DT) vs CAPACITANCE
Pin Descriptions
VDD - VDD is the power connection for the IC. To optimize
noise immunity, bypass VDD to GND with a ceramic
capacitor as close to the VDD and GND pins as possible.
VDD is monitored for supply voltage undervoltage lock-out
(UVLO). The start and stop thresholds track each other
resulting in relatively constant hysteresis.
GND - Signal and power ground connections for this device.
Due to high peak currents and high frequency operation, a
low impedance layout is necessary. Ground planes and
short traces are highly recommended.
VREF - The 5.00V reference voltage output having 3%
tolerance over line, load and operating temperature. Bypass
to GND with a 0.1µF to 2.2µF low ESR capacitor.
CT - The oscillator timing capacitor is connected between
this pin and GND. It is charged through an internal 200µA
current source and discharged with a user adjustable current
source controlled by RTD.
RTD - This is the oscillator timing capacitor discharge
current control pin. The current flowing in a resistor
connected between this pin and GND determines the
magnitude of the current that discharges CT. The CT
discharge current is nominally 20x the resistor current. The
PWM deadtime is determined by the timing capacitor
discharge duration. The voltage at RTD is nominally 2V.
CS - This is the input to the overcurrent comparator. The
overcurrent comparator threshold is set at 1V nominal. The
CS pin is shorted to GND at the termination of either PWM
output.
Depending on the current sensing source impedance, a
series input resistor may be required due to the delay
between the internal clock and the external power switch.
This delay may result in CS being discharged prior to the
power switching device being turned off.
8
10
0.1
1
CT (nF)
10
FIGURE 4. CAPACITANCE vs FREQUENCY
OUTUL and OUTUR - These outputs control the upper
bridge FETs and operate at a fixed 50% duty cycle in
alternate sequence. OUTUL controls the upper left FET and
OUTUR controls the upper right FET. The left and right
designation may be switched as long as they are switched in
conjunction with the lower FET outputs, OUTLL and OUTLR.
RESDEL - Sets the resonant delay period between the
toggle of the upper FETs and the turn on of either of the
lower FETs. The voltage applied to RESDEL determines
when the upper FETs switch relative to a lower FET turning
on. Varying the control voltage from 0V to 2V increases the
resonant delay duration from 0 to 100% of the deadtime. The
control voltage divided by 2 represents the percent of the
deadtime equal to the resonant delay. In practice the
maximum resonant delay must be set lower than 2V to
ensure that the lower FETs, at maximum duty cycle, are OFF
prior to the switching of the upper FETs.
OUTLL and OUTLR - These outputs control the lower bridge
FETs, are pulse width modulated, and operate in alternate
sequence. OUTLL controls the lower left FET and OUTLR
controls the lower right FET. The left and right designation
may be switched as long as they are switched in conjunction
with the upper FET outputs, OUTUL and OUTUR.
OUTLLN and OUTLRN - These outputs are the
complements of the PWM (lower) bridge FETs. OUTLLN is
the complement of OUTLL and OUTLRN is the complement
of OUTLR. These outputs are suitable for control of
synchronous rectifiers. The phase relationship between
each output and its complement is controlled by the voltage
applied to VADJ.
VADJ - A 0V to 5V control voltage applied to this input sets
the relative delay or advance between OUTLL/OUTLR and
OUTLLN/OUTLRN. The phase relationship between
OUTUL/OUTUR and OUTLL/OUTLR is maintained
regardless of the phase adjustment between OUTLL/OUTLR
and OUTLLN/OUTLRN.
FN9181.3
October 31, 2008
ISL6752
Voltages below 2.425V result in OUTLLN/OUTLRN being
advanced relative to OUTLL/OUTLR. Voltages above
2.575V result in OUTLLN/OUTLRN being delayed relative to
OUTLL/OUTLR. A voltage of 2.50V ±75mV results in zero
phase difference. A weak internal 50% divider from VREF
results in no phase delay if this input is left floating.
The range of phase delay/advance is either zero or 40ns to
300ns with the phase differential increasing as the voltage
deviation from 2.5V increases. The relationship between the
control voltage and phase differential is non-linear. The gain
(Δt/ΔV) is low for control voltages near 2.5V and rapidly
increases as the voltage approaches the extremes of the
control range. This behavior provides the user increased
accuracy when selecting a shorter delay/advance duration.
When the PWM outputs are delayed relative to the SR
outputs (VADJ < 2.425V), the delay time should not exceed
90% of the deadtime as determined by RTD and CT.
VERR - The control voltage input to the inverting input of the
PWM comparator. The output of an external error amplifier
(EA) is applied to this input, either directly or through an
opto-coupler, for closed loop regulation. VERR has a
nominal 1mA pull-up current source.
CTBUF - CTBUF is the buffered output of the sawtooth
oscillator waveform present on CT and is capable of
sourcing 2mA. It is offset from ground by 0.40V and has a
nominal valley-to-peak gain of 2. It may be used for slope
compensation.
Functional Description
Features
The ISL6752 PWM is an excellent choice for low cost ZVS
full-bridge applications requiring adjustable synchronous
rectifier drive. With its many protection and control features,
a highly flexible design with minimal external components is
possible. Among its many features are a very accurate
overcurrent limit threshold, thermal protection, a buffered
sawtooth oscillator output suitable for slope compensation,
synchronous rectifier outputs with variable delay/advance
timing, and adjustable frequency.
The switching period is the sum of the timing capacitor
charge and discharge durations. The charge duration is
determined by CT and a fixed 200µA internal current source.
The discharge duration is determined by RTD and CT.
3
t C ≈ 11.5 ⋅ 10 ⋅ CT
S
(EQ. 1)
t D ≈ ( 0.06 ⋅ RTD ⋅ CT ) + 50 ⋅ 10
1
t SW = t C + t D = -----------F SW
–9
S
(EQ. 3)
where tC and tD are the charge and discharge times,
respectively, CT is the timing capacitor in Farads, RTD is the
discharge programming resistance in ohms, tSW is the
oscillator period, and FSW is the oscillator frequency. One
output switching cycle requires two oscillator cycles. The
actual times will be slightly longer than calculated due to
internal propagation delays of approximately 10ns/transition.
This delay adds directly to the switching duration, but also
causes overshoot of the timing capacitor peak and valley
voltage thresholds, effectively increasing the peak-to-peak
voltage on the timing capacitor. Additionally, if very small
discharge currents are used, there will be increased error
due to the input impedance at the CT pin. The maximum
recommended current through RTD is 1mA, which produces
a CT discharge current of 20mA.
The maximum duty cycle, D, and percent deadtime, DT, can
be calculated from Equations 4 and 5:
tC
D = ---------t SW
(EQ. 4)
DT = 1 – D
(EQ. 5)
Implementing Soft-Start
The ISL6752 does not have a soft-start feature. Soft-start
can be implemented externally using the components shown
in the following. The RC network governs the rate of rise of
the transistor’s base, which clamps the voltage at VERR.
1
2 VREF
If synchronous rectification is not required, please consider
the ISL6753 controller.
3 VERR
R
Oscillator
4
5
The ISL6752 has an oscillator with a programmable
frequency range to 2MHz, which can be programmed with a
resistor and capacitor.
(EQ. 2)
S
6
C
7
8
ISL6752
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
FIGURE 5. IMPLEMENTING SOFT-START
9
FN9181.3
October 31, 2008
ISL6752
The values of R and C should be selected to control the rate
of rise of VERR to the desired soft-start duration. The
soft-start duration may be calculated from Equation 6.
⎛
V SS – V be ⎞
t = – RC ⋅ ln ⎜ 1 – -------------------------------------------⎟
⎜
0.001R⎟
VREF + -------------------⎠
⎝
β
S
(EQ. 6)
1
1
Fm = ------------------------------------ = -------------------------m c S n t SW
( S n + S e )t SW
(EQ. 8)
where Se is slope of the external ramp and:
where VSS is the soft-start clamp voltage, Vbe is the base
emitter voltage drop of the transistor, and β is the DC gain of
the transistor. If β is sufficiently large, that term may be
ignored. The Schottky diode discharges the soft-start
capacitor so that the circuit may be reset quickly.
Gate Drive
The ISL6752 outputs are capable of sourcing and sinking
10mA (at rated VOH, VOL) and are intended to be used in
conjunction with integrated FET drivers or discrete bipolar
totem pole drivers. The typical ON-resistance of the outputs
is 50Ω.
Overcurrent Operation
The cycle-by-cycle peak current control results in
pulse-by-pulse duty cycle reduction when the current
feedback signal exceeds 1.0V. When the peak current
exceeds the threshold, the active output pulse is
immediately terminated. This results in a well controlled
decrease in output voltage as the load current increases
beyond the current limit threshold. The ISL6752 will operate
continuously in an overcurrent condition.
The propagation delay from CS exceeding the current limit
threshold to the termination of the output pulse is increased
by the leading edge blanking (LEB) interval. The effective
delay is the sum of the two delays and is nominally 105ns.
Slope Compensation
Peak current-mode control requires slope compensation to
improve noise immunity, particularly at lighter loads, and to
prevent current loop instability, particularly for duty cycles
greater than 50%. Slope compensation may be
accomplished by summing an external ramp with the current
feedback signal or by subtracting the external ramp from the
voltage feedback error signal. Adding the external ramp to
the current feedback signal is the more popular method.
From the small signal current-mode model [1] it can be
shown that the naturally-sampled modulator gain, Fm,
without slope compensation, is expressed in Equation 7:
1
Fm = -----------------S n t SW
where Sn is the slope of the sawtooth signal and tSW is the
duration of the half-cycle. When an external ramp is added,
the modulator gain becomes Equation 8:
(EQ. 7)
Se
m c = 1 + ------Sn
(EQ. 9)
The criteria for determining the correct amount of external
ramp can be determined by appropriately setting the
damping factor of the double-pole located at half the
oscillator frequency. The double-pole will be critically
damped if the Q-factor is set to 1, and over-damped for
Q > 1, and under-damped for Q < 1. An under-damped
condition can result in current loop instability.
1
Q = ------------------------------------------------π ( m c ( 1 – D ) – 0.5 )
(EQ. 10)
where D is the percent of on-time during a half cycle. Setting
Q = 1 and solving for Se yields Equation 11:
1
1
S e = S n ⎛ ⎛ --- + 0.5⎞ ------------- – 1⎞
⎠1 –D
⎝⎝π
⎠
(EQ. 11)
Since Sn and Se are the on-time slopes of the current ramp
and the external ramp, respectively, they can be multiplied
by tON to obtain the voltage change that occurs during tON.
1
1
V e = V n ⎛ ⎛ --- + 0.5⎞ ------------- – 1⎞
⎠1 –D
⎝⎝π
⎠
(EQ. 12)
where Vn is the change in the current feedback signal during
the on-time and Ve is the voltage that must be added by the
external ramp.
Vn can be solved for in terms of input voltage, current
transducer components, and output inductance yielding
Equation 13:
t SW ⋅ V ⋅ R CS N
O
S 1
V e = ---------------------------------------- ⋅ -------- ⎛ --- + D – 0.5⎞
⎠
N CT ⋅ L O
NP ⎝ π
V
(EQ. 13)
where RCS is the current sense burden resistor, NCT is the
current transformer turns ratio, LO is the output inductance,
VO is the output voltage, and NS and NP are the secondary
and primary turns, respectively.
The inductor current, when reflected through the isolation
transformer and the current sense transformer to obtain the
current feedback signal at the sense resistor yields
Equation 14:
N S ⋅ R CS ⎛
D ⋅ t SW ⎛
NS
⎞⎞
V CS = ------------------------ ⎜ I O + ------------------- ⎜ V IN ⋅ -------- – V O⎟ ⎟
2L O ⎝
NP
N P ⋅ N CT ⎝
⎠⎠
V
(EQ. 14)
where VCS is the voltage across the current sense resistor
and IO is the output current at current limit.
10
FN9181.3
October 31, 2008
ISL6752
Since the peak current limit threshold is 1.00V, the total
current feedback signal plus the external ramp voltage must
sum to this value.
1
V e + V CS = 1
3
14
4 CTBUF
13
5
12
6
11
7
10
8 CS
9
2
(EQ. 15)
Substituting Equations 13 and 14 into Equation 15 and
solving for RCS yields Equation 16:
N P ⋅ N CT
1
R CS = ------------------------ ⋅ ---------------------------------------------------VO
NS
1 D
I O + -------- t SW ⎛ --- + ----⎞
⎝ π 2⎠
L
Ω
R9
(EQ. 16)
O
(EQ. 17)
A
where VIN is the input voltage that corresponds to the duty
cycle D and Lm is the primary magnetizing inductance. The
effect of the magnetizing current at the current sense
resistor, RCS, is expressed in Equation 18:
ΔI P ⋅ R CS
ΔV CS = -------------------------N CT
ISL6752
15
R6
For simplicity, idealized components have been used for this
discussion, but the effect of magnetizing inductance must be
considered when determining the amount of external ramp
to add. Magnetizing inductance provides a degree of slope
compensation to the current feedback signal and reduces
the amount of external ramp required. The magnetizing
inductance adds primary current in excess of what is
reflected from the inductor current in the secondary.
V IN ⋅ Dt SW
ΔI P = ----------------------------Lm
16
(EQ. 18)
V
If ΔVCS is greater than or equal to Ve, then no additional slope
compensation is needed and RCS becomes Equation 19:
N CT
R CS = ---------------------------------------------------------------------------------------------------------------------------------NS ⎛
Dt SW ⎛
NS
⎞ ⎞ V IN ⋅ Dt SW
-------- ⋅ ⎜ I O + -------------- ⋅ ⎜ V ⋅ ------- – V O⎟ ⎟ + ----------------------------Lm
NP ⎝
2L O ⎝ IN N P
⎠⎠
R CS
C4
FIGURE 6. ADDING SLOPE COMPENSATION
Assuming the designer has selected values for the RC filter
placed on the CS pin, the value of R9 required to add the
appropriate external ramp can be found by superposition.
( D ( V CTBUF – 0.4 ) + 0.4 ) ⋅ R6
V e – ΔV CS = ------------------------------------------------------------------------------R6 + R9
(EQ. 20)
V
Rearranging to solve for R9 yields Equation 21:
( D ( V CTBUF – 0.4 ) – V e + ΔV CS + 0.4 ) ⋅ R6
R9 = ------------------------------------------------------------------------------------------------------------------V e – ΔV CS
Ω
(EQ. 21)
The value of RCS determined in Equation 16 must be
rescaled so that the current sense signal presented at the
CS pin is that predicted by Equation 14. The divider created
by R6 and R9 makes this necessary.
R6 + R9
R′ CS = ---------------------- ⋅ R CS
R9
(EQ. 22)
(EQ. 19)
Example:
If ΔVCS is less than Ve, then Equation 16 is still valid for the
value of RCS, but the amount of slope compensation added
by the external ramp must be reduced by ΔVCS.
Adding slope compensation may be accomplished in the
ISL6752 using the CTBUF signal. CTBUF is an amplified
representation of the sawtooth signal that appears on the CT
pin. It is offset from ground by 0.4V and is 2x the peak-to-peak
amplitude of CT (0.4V to 4.4V). A typical application sums this
signal with the current sense feedback and applies the result
to the CS pin, as shown in Figure 6.
VIN = 280V
VO = 12V
LO = 2.0µH
Np/Ns = 20
Lm = 2mH
IO = 55A
Oscillator Frequency, FSW = 400kHz
Duty Cycle, D = 85.7%
NCT = 50
R6 = 499Ω
Solve for the current sense resistor, RCS, using Equation 16.
RCS = 15.1Ω.
11
FN9181.3
October 31, 2008
ISL6752
Determine the amount of voltage, Ve, that must be added to
the current feedback signal using Equation 13.
Ve = 153mV
Next, determine the effect of the magnetizing current from
Equation 18.
ΔVCS = 91mV
Using Equation 21, solve for the summing resistor, R9, from
CTBUF to CS.
and Equation 21 becomes:
( 2D – V e + ΔV CS ) ⋅ R6
R9 = ------------------------------------------------------------V e – ΔV CS
Ω
(EQ. 24)
The buffer transistor used to create the external ramp from
CT should have a sufficiently high gain (>200) so as to
minimize the required base current. Whatever base current
is required reduces the charging current into CT and will
reduce the oscillator frequency.
ZVS Full-Bridge Operation
R9 = 30.1kΩ
Determine the new value of RCS, R’CS, using Equation 22.
R’CS = 15.4Ω
This discussion determines the minimum external ramp that
is required. Additional slope compensation may be
considered for design margin.
If the application requires deadtime of less than about
500ns, the CTBUF signal may not perform adequately for
slope compensation. CTBUF lags the CT sawtooth
waveform by 300ns to 400ns. This behavior results in a
non-zero value of CTBUF when the next half-cycle begins
when the deadtime is short.
The ISL6752 is a full-bridge zero-voltage switching (ZVS)
PWM controller that behaves much like a traditional hard
switched topology controller. Rather than drive the diagonal
bridge switches simultaneously, the upper switches (OUTUL,
OUTUR) are driven at a fixed 50% duty cycle and the lower
switches (OUTLL, OUTLR) are pulse width modulated on
the trailing edge.
CT
DEADTIME
OUTLL
Under these situations, slope compensation may be added
by externally buffering the CT signal as shown in Figure 7.
PWM
PWM
PWM
OUTLR
PWM
OUTUR
1
RESONANT
DELAY
2 VREF
3
ISL6752
OUTUL
RESDEL
WINDOW
4
FIGURE 8. BRIDGE DRIVE SIGNAL TIMING
5
6
R9
To understand how the ZVS method operates, one must
include the parasitic elements of the circuit and examine a
full switching cycle.
7 CT
8 CS
VIN+
R6
UL
UR
D1
VOUT+
LL
RCS
CT
C4
RTN
LL
LR
D2
VIN-
FIGURE 7. ADDING SLOPE COMPENSATION USING CT
Using CT to provide slope compensation instead of CTBUF
requires the same calculations, except that Equations 20
and 21 require modification. Equation 20 becomes:
2D ⋅ R6
V e – ΔV CS = ---------------------R6 + R9
V
(EQ. 23)
12
FIGURE 9. IDEALIZED FULL-BRIDGE
In Figure 9, the power semiconductor switches have been
replaced by ideal switch elements with parallel diodes and
capacitance, the output rectifiers are ideal, and the
transformer leakage inductance has been included as a
discrete element. The parasitic capacitance has been
lumped together as switch capacitance, but represents all
parasitic capacitance in the circuit including winding
FN9181.3
October 31, 2008
ISL6752
capacitance. Each switch is designated by its position; upper
left (UL), upper right (UR), lower left (LL), and lower right
(LR). The beginning of the cycle, shown in Figure 10, is
arbitrarily set as having switches UL and LR on and UR and
LL off. The direction of the primary and secondary currents
are indicated by IP and IS, respectively.
VIN+
UL
UR
D1
IS
VOUT+
LL
IP
RTN
LL
LR
D2
During the period when CT discharges (also referred to as
the deadtime), the upper switches toggle. Switch UL turns off
and switch UR turns on. The actual timing of the upper
switch toggle is dependent on RESDEL, which sets the
resonant delay. The voltage applied to RESDEL determines
how far in advance the toggle occurs prior to a lower switch
turning on. The ZVS transition occurs after the upper
switches toggle and before the diagonal lower switch turns
on. The required resonant delay is 1/4 of the period of the LC
resonant frequency of the circuit formed by the leakage
inductance and the parasitic capacitance. The resonant
transition may be estimated from Equation 25.
π
1
τ = --- ----------------------------------2
2
R
1
--------------- – ---------2
LL CP
4L L
VIN-
(EQ. 25)
FIGURE 10. UL - LR POWER TRANSFER CYCLE
The UL - LR power transfer period terminates when switch
LR turns off as determined by the PWM. The current flowing
in the primary cannot be interrupted instantaneously, so it
must find an alternate path. The current flows into the
parasitic switch capacitance of LR and UR, which charges
the node to VIN and then forward biases the body diode of
upper switch UR.
VIN+
UL
UR
D1
IS
VOUT+
LL
IP
RTN
LL
LR
D2
VIN-
FIGURE 11. UL - UR FREE-WHEELING PERIOD
The primary leakage inductance, LL, maintains the current,
which now circulates around the path of switch UL, the
transformer primary, and switch UR. When switch LR opens,
the output inductor current free-wheels through both output
diodes, D1 and D2. During the switch transition, the output
inductor current assists the leakage inductance in charging
the upper and lower bridge FET capacitance.
where τ is the resonant transition time, LL is the leakage
inductance, CP is the parasitic capacitance, and R is the
equivalent resistance in series with LL and CP.
The resonant delay is always less than or equal to the
deadtime and may be calculated using Equation 26.
V resdel
τ resdel = -------------------- ⋅ DT
2
(EQ. 26)
where τresdel is the desired resonant delay, Vresdel is a
voltage between 0V and 2V applied to the RESDEL pin, and
DT is the deadtime (see Equations 1 through 5).
When the upper switches toggle, the primary current that was
flowing through UL must find an alternate path. It
charges/discharges the parasitic capacitance of switches UL
and LL until the body diode of LL is forward-biased. If
RESDEL is set properly, switch LL will be turned on at this
time. The output inductor does not assist this transition. It is
purely a resonant transition driven by the leakage inductance.
VIN+
UL
UR
D1
IS
VOUT+
LL
IP
RTN
LL
The current flow from the previous power transfer cycle
tends to be maintained during the free-wheeling period
because the transformer primary winding is essentially
shorted. Diode D1 may conduct very little or none of the
free-wheeling current, depending on circuit parasitics. This
behavior is quite different than occurs in a conventional
hard-switched full-bridge topology where the free-wheeling
current splits nearly evenly between the output diodes, and
flows not at all in the primary.
S
LR
D2
VIN-
FIGURE 12. UPPER SWITCH TOGGLE AND RESONANT
TRANSITION
This condition persists through the remainder of the half
cycle.
13
FN9181.3
October 31, 2008
ISL6752
The second power transfer period commences when switch
LL closes. With switches UR and LL on, the primary and
secondary currents flow, as indicated in Figure 13.
VIN+
UL
UR
D1
VOUT+
LL
RTN
LL
LR
The first power transfer period commences when switch LR
closes and the cycle repeats. The ZVS transition requires
that the leakage inductance has sufficient energy stored to
fully charge the parasitic capacitances. Since the energy
stored is proportional to the square of the current (1/2 LLIP2),
the ZVS resonant transition is load dependent. If the leakage
inductance is not able to store sufficient energy for ZVS, a
discrete inductor may be added in series with the
transformer primary.
Synchronous Rectifier Outputs and Control
D2
VIN-
FIGURE 13. UR - LL POWER TRANSFER CYCLE
The UR - LL power transfer period terminates when switch
LL turns off, as determined by the PWM. The current flowing
in the primary must find an alternate path. The current flows
into the parasitic switch capacitance, which charges the
node to VIN and then forward biases the body diode of
upper switch UL. As before, the output inductor current
assists in this transition. The primary leakage inductance,
LL, maintains the current, which now circulates around the
path of switch UR, the transformer primary, and switch UL.
When switch LL opens, the output inductor current free
wheels predominantly through diode D1. Diode D2 may
actually conduct very little or none of the free-wheeling
current, depending on circuit parasitics. This condition
persists through the remainder of the half-cycle.
The ISL6752 provides double-ended PWM outputs, OUTLL
and OUTLR, and synchronous rectifier (SR) outputs,
OUTLLN and OUTLRN. The SR outputs are the
complements of the PWM outputs. It should be noted that
the complemented outputs are used in conjunction with the
opposite PWM output, i.e. OUTLL and OUTLRN are paired
together and OUTLR and OUTLLN are paired together.
CT
OUTLL
OUTLR
OUTLLN
(SR1)
VIN+
UL
UR
D1
IS
VOUT+
LL
OUTLRN
(SR2)
IP
RTN
LL
LR
D2
VIN-
FIGURE 14. UR - UL FREE-WHEELING PERIOD
When the upper switches toggle, the primary current that was
flowing through UR must find an alternate path. It
charges/discharges the parasitic capacitance of switches UR
and LR until the body diode of LR is forward-biased. If RESDEL
is set properly, switch LR will be turned on at this time.
VIN+
UL
UR
D1
IS
VOUT+
LL
IP
FIGURE 16. BASIC WAVEFORM TIMING
Referring to Figure 16, the SRs alternate between being both
on during the free-wheeling portion of the cycle (OUTLL/LR
off), and one or the other being off when OUTLL or OUTLR is
on. If OUTLL is on, its corresponding SR must also be on,
indicating that OUTLRN is the correct SR control signal.
Likewise, if OUTLR is on, its corresponding SR must also be
on, indicating that OUTLLN is the correct SR control signal.
A useful feature of the ISL6752 is the ability to vary the
phase relationship between the PWM outputs (OUTLL, OUT
LR) and their complements (OUTLLN, OUTLRN) by ±300ns.
This feature allows the designer to compensate for
differences in the propagation times between the PWM FETs
and the SR FETs. A voltage applied to VADJ controls the
phase relationship.
RTN
LL
LR
D2
VIN-
FIGURE 15. UPPER SWITCH TOGGLE AND RESONANT
TRANSITION
14
FN9181.3
October 31, 2008
ISL6752
When the PWM outputs are delayed, the 50% upper outputs
are equally delayed, so the resonant delay setting is
unaffected.
CT
On/Off Control
OUTLL
The ISL6753 does not have a separate enable/disable
control pin. The PWM outputs, OUTLL/OUTLR, may be
disabled by pulling VERR to ground. Doing so reduces the
duty cycle to zero, but the upper 50% duty cycle outputs,
OUTUL/OUTUR, will continue operation. Likewise, the SR
outputs OUTLLN/OUTLRN will be active high.
OUTLR
OUTLLN
(SR1)
If the application requires that all outputs be off, then the
supply voltage, VDD, must be removed from the IC. This
may be accomplished as shown in Figure 19.
OUTLRN
(SR2)
+VDD
FIGURE 17. WAVEFORM TIMING WITH PWM OUTPUTS
DELAYED, 0V < VADJ < 2.425V
ISL6752
CT
OUTLL
VADJ
VDD
VREF
OUTLL
VERR
OUTLR
CTBUF
OUTUL
RTD
OUTUR
RESDEL
OUTLLN
CT
OUTLRN
CS
GND
ON/OFF
(OPEN = OFF
GND = ON)
OUTLR
OUTLLN
(SR1)
FIGURE 19. ON/OFF CONTROL USING VDD
Fault Conditions
OUTLRN
(SR2)
FIGURE 18. WAVEFORM TIMING WITH SR OUTPUTS
DELAYED, 2.575V < VADJ < 5.00V
A fault condition occurs if VREF or VDD fall below their
undervoltage lockout (UVLO) thresholds or if the thermal
protection is triggered. When a fault is detected the outputs
are disabled low. When the fault condition clears the outputs
are re-enabled.
Setting VADJ to VREF/2 results in no delay on any output.
The no delay voltage has a ±75mV tolerance window.
Control voltages below the VREF/2 zero delay threshold
cause the PWM outputs, OUTLL/LR, to be delayed. Control
voltages greater than the VREF/2 zero delay threshold
cause the SR outputs, OUTLLN/LRN, to be delayed. It
should be noted that when the PWM outputs, OUTLL/LR,
are delayed, the CS to output propagation delay is increased
by the amount of the added delay.
An overcurrent condition is not considered a fault and does
not result in a shutdown.
The delay feature is provided to compensate for mismatched
propagation delays between the PWM and SR outputs as
may be experienced when one set of signals crosses the
primary-secondary isolation boundary. If required, individual
output pulses may be stretched or compressed as required
using external resistors, capacitors, and diodes.
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. VDD and
VREF should be bypassed directly to GND with good high
frequency capacitance.
Thermal Protection
Internal die over-temperature protection is provided. An
integrated temperature sensor protects the device should
the junction temperature exceed +140°C. There is
approximately +15°C of hysteresis.
Ground Plane Requirements
References
[1] Ridley, R., “A New Continuous-Time Model for Current
Mode Control”, IEEE Transactions on Power
Electronics, Vol. 6, No. 2, April 1991.
15
FN9181.3
October 31, 2008
ISL6752
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
M16.15A
N
INDEX
AREA
H
0.25(0.010) M
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
B M
E
-B1
2
INCHES
GAUGE
PLANE
3
0.25
0.010
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
α
A2
A1
B
0.17(0.007) M
L
C
0.10(0.004)
C A M
B S
NOTES:
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.061
0.068
1.55
1.73
-
A1
0.004
0.0098
0.102
0.249
-
A2
0.055
0.061
1.40
1.55
-
B
0.008
0.012
0.20
0.31
9
C
0.0075
0.0098
0.191
0.249
-
D
0.189
0.196
4.80
4.98
3
E
0.150
0.157
3.81
3.99
4
e
0.025 BSC
0.635 BSC
-
H
0.230
0.244
5.84
6.20
-
h
0.010
0.016
0.25
0.41
5
L
0.016
0.035
0.41
0.89
6
8°
0°
N
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
MILLIMETERS
α
16
0°
16
7
8°
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Rev. 2 6/04
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.10mm (0.004 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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16
FN9181.3
October 31, 2008
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