ISL6752/54EVAL1Z User Guide

Application Note 1603
Author: Richard Garcia
ISL6752/54EVAL1Z ZVS DC/DC Power Supply with
Synchronous Rectifiers User Guide
The ISL6752/54EVAL1Z is a new design based on the
ISL6752EVAL1Z but with several design modifications to
improve the efficiency from 90% to 95%. The control circuit
has been moved off the main board onto a daughter card. Two
different daughter cards are provided: one using the ISL6752
and the other using the ISL6754. Both control cards utilize the
Intersil zero voltage switching (ZVS) topology. The ISL6752
daughter card features pulse by pulse current limiting, and the
ISL6754 daughter card features a patented method for
average current limiting that results in a brick-wall current
limit profile.
The PCB layout of the ISL6752/54EVAL1Z has also been
greatly improved over the ISL6752EVAL1Z. Even though the
overall size of the board has been reduced, the copper losses
have been reduced.
In addition to the ZVS function, this board also incorporates
N-Channel FETs as secondary side rectifiers, also known as
synchronous rectifiers (SR). Power dissipation of the secondary
side rectifiers is reduced because the conduction losses of SRs
are significantly less than the conduction losses of PN or
Schottky diodes.
Scope
This application note covers implementation of synchronous
rectifiers (SRs) and their associated drive circuits as used on
the ISL6752/54EVAL1Z board. Implementation of the primary
side ZVS controller, based on the ISL6752 daughter card, is
described extensively in Intersil Application Note AN1262,
“Designing with the ISL6752, ISL6753 ZVS Full-Bridge
Controllers.”
Also reviewed is the performance of this evaluation board.
Oscillographs illustrate the performance of the power supply
with load transients on the output. The ZVS switching of the
bridge FETs is shown, and efficiency and load regulation are
measured.
At the end of this application note, the schematics, bill of
materials, and printed circuit board layouts are included for
reference.
TABLE 1. SPECIFICATIONS
Absolute Maximum Input Voltage
450VDC
Operating Input Voltage
350V to 450VDC
Maximum Input Current
2.5ADC
Rated Output Current
50ADC
Current Limit
60A ± 5%
Output Voltage
12V ± 5%
Efficiency at 100% (50A) Load
95%
Efficiency at 20% (10A) Load
92%
FIGURE 1. NEW ISL6752/54EVAL1Z
June 8, 2011
AN1603.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Application Note 1603
ZVS FULL BRIDGE
CURRENT DOUBLER RECTIFIER
400V
SYNCHRONOUS
RECTIFIERS
BRIDGE FETs
BIAS
12.6V
OUTPUT
FILTER
12VDC
POWER
TRANSFORMER
VOLTAGE
CLAMP
BRIDGE
DRIVERS
SR DRIVERS
WITH DELAYS
BRIDGE
CURRENT
SENSE
PULSE
TRANSFORMER
BRIDGE
DRIVES
ISL6752
OR
ISL6754
CONTROLLER
SR
DRIVES
BIAS
PRIMARY
OPTOISOLATOR
VOLTAGE
ERROR AMP
SECONDARY
DAUGHTER CARD
FIGURE 2. ISL6752/54EVAL1Z BLOCK DIAGRAM
Block Diagram
The evaluation board is composed of several distinct circuit
elements. The three main sections are the ZVS full bridge on the
input, the current doubler rectifier on the output, and the
controller daughter card. See “Schematics- Main Board,
ISL6752/54EVAL1Z” on page 23 and “Schematics - Daughter
Card” on page 25 for complete circuit details.
The only functional difference between the ISL6752 and
ISL6754 daughter cards is how current limit is implemented. The
ISL6752 uses pulse-by-pulse current limit, and the ISL6754 uses
average current limit.
Daughter Cards
The ISL6752 or ISL6754 control ICs are located on their
respective daughter cards, as shown in Figures 3 and 4. Both
daughter cards have the control ICs on the primary side and the
voltage error amplifier on the secondary side. Creepage spacing
between the primary and secondary is maintained on the cards.
The ISL6752 and the ISL6754 control ICs are located on the
primary side, eliminating the need for two AC line isolating gate
drive transformers to drive the primary side bridge FETs. Instead,
the low side FETs are driven directly by MOSFET drivers (on the
main board), and the high side FETs are driven by a gate drive
transformer that only requires operational insulation. Primary
side control also simplifies design of the current sensing
transformers because they also do not have to be AC line
isolating.
FIGURE 3. ISL6752 DAUGHTER CARD
A line isolation rated opto-coupler (D5 on ISL6752DB or D2 on
ISL6754DB) passes the analog error signal generated by the
error amplifier, U1, from the secondary to the primary. Opto D3
passes a digital signal from primary to secondary to turn off the
SRS for diode emulation.
Special test points located on the daughter cards aid in probing
nodes on the daughter cards for evaluation. Test points PGND
and TP_PRI are located on the primary side, and SGND and
TP_SEC are located on the secondary. With these test points, the
user can employ the spring-like probe accessories included with
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Application Note 1603
many scope probes. The scope signal pin is inserted in TP_PRI (or
TP_SEC), and the short spring ground lead is inserted in PGND (or
SGND).
FIGURE 4. ISL6754 DAUGHTER CARD
To probe any node on the daughter card, solder a 30ga insulated
wire between the desired node and the via that is associated with
the TP_PRI or TP_SEC test point. This method not only simplifies
probing of any node, but also implements the preferred
technique of measuring small signals in the presence of high
amplitude switching magnetic fields.
The ISL6752DBEVAL1Z and the ISL6754DBEVAL1Z daughter
cards are also available as standalone evaluation kits.
ZVS Full Bridge
The low side FETs, Q3 and Q4, are driven directly by the ISL89160
MOSFET driver, U1 (Figure 5). The two high-side FETs, Q1 and Q2,
are indirectly driven by the ISL89160 driver, U2. A level
translating gate drive transformer, T3, with complementary
output windings, directly drives the high-side bridge FETs with a
symmetrical square wave. The design of T3 is simplified because
it only needs 400V operational insulation, and it is always driven
with a square wave, thus eliminating the problems associated
with non-symmetrical drive waveforms.
FIGURE 5. FULL BRIDGE
High Voltage Protection
Because a failure of the bridge can cause catastrophic damage
to the primary side control elements, a voltage crowbar, F1 and
D3, and a voltage blocking diode, D4, are incorporated (Figure 6).
D3 clamps the bias voltage to a safe level. If 400V is applied to
the VDD node, F1 opens shortly after D3 conducts current. D4
provides additional protection by blocking high voltage from
being applied to the 13V lab supply. Note that a fully debugged
power supply does not need these additional components. These
parts are included on the evaluation board to minimize damage,
should the user accidently introduce a fault while evaluating the
circuits. The designer may want to keep F1 in the final design, to
prevent a loud bang if the bridge does fail.
Observe that the ISL89160 MOSFET drivers are located as close
as possible to their respective bridge FETs to minimize the
detrimental effects of parasitic inductance on the outputs of the
drivers. Although the input signal lead lengths between the
drivers and the daughter card are relatively long (about 5cm),
they are shielded on top and bottom by ground planes, to
significantly reduce the noise injected on these lines. The
hysteresis of the ISL89160 inputs also lessens the possibility of
noise corrupting the gate signals.
FIGURE 6. PROTECTION CIRCUITS
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Application Note 1603
Primary Side Current Sensing
The primary side bridge has two current sensing transformers, T2
and T4, one on each leg on the drains of the low-side bridge FETs
(Figure 7). Using two transformers allows each CT to reset during
alternate half cycles. Alternate current sensing methods are
reviewed in “Current Sensing” on page 8.
FIGURE 8. SRs AND DRIVERS
FIGURE 7. PRIMARY SIDE CURRENT SENSING
Synchronous Rectifier Drive Circuit
Two banks of SRs are driven by the ISL89163 MOSFET driver, U4
(Figure 8). An RCD network on the inputs to this driver delay the
turn-on of the SRs relative to the turn-off of the primary side
bridge FETs.
The ISL89367, U108, can optionally be used to drive the SRs
instead of the ISL89163. Review “Schematics - Daughter Card”
on page 25 to understand how to disconnect the ISL89163 and
connect the ISL89367.
The pulse transformer, T6, crosses the isolation boundary to
couple the control signals from the ISL6752, ISL6754 to the
MOSFET drivers (Figure 9). Note that this transformer also
provides the secondary side bias voltage for the MOSFET drivers.
4
FIGURE 9. PULSE TRANSFORMER AND DRIVER
Current Doubler Output
The current doubler output is composed of two banks of SRs,
Q107... Q109 and Q111... Q113; inductors L102 and L103; and
output filter capacitors, C133... C136 (Figure 10). The advantage
of this topology is that the output current is shared by the two
inductors, thus reducing conduction losses. Another advantage is
that the secondary winding of the power transformer does not
require a center tap.
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Application Note 1603
Disadvantages are:
• Additional complexity and cost
• Higher reverse recovery losses as compared to fast recovery
diodes.
• When paralleling units for redundancy, provisions must be
made to prevent current circulation among the paralleled
units.
SR Drive Timing Requirements
To emulate a diode, an SR must be driven ON when a diode
would normally be conducting. But unlike a diode, if the SR is ON,
the current through the SR can reverse if the voltage on the SR
“cathode” becomes positive. The consequence is that if the SR is
driven ON when the primary side is sourcing voltage to the
secondary, the secondary side will be shorted by the SR.
FIGURE 10. CURRENT DOUBLER OUTPUT
Basic SR Principles
Replacing diodes with MOSFETs has two major advantages:
• Dramatically reduces conduction losses
• The applied duty cycle remains virtually constant from no load
to full load.
Figure 11 illustrates the timing required to drive the SRs. Note
that the rising edges of the two lower bridge FETs are delayed by
the ISL6752/54 relative to the PWM signal. Likewise, the rising
edges of the SRs gate signals are delayed by the ISL89163
relative to the falling edge of the PWM signal. These delays are
necessary to prevent the overlap of drive signals that would
result with high amplitude short circuit currents.
When an SR is turned off while current is flowing from source to
drain, the current diverts from the FET channel to the internal
body diode. Because the voltage drop across the body diode is
higher than the channel, it is desirable to minimize dissipation by
minimizing the duration of the current flow through the body
diode.
+400V
VPWM
OUTLL
OUTLLN
DELAY
(ISL89163)
OUTLRN
DELAY
(ISL89163)
OUTLLN
RL
OUTLR
OUTLLR
VPWM
DELAY
(ISL6752/54)
OUTLL
SRS
400V RTN
VPWM
DELAY
(ISL6752/54)
OUTLR
FIGURE 11. TIMING FOR SRs AND BRIDGE FETs
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PWM
L
R
L
VBIAS
/OUTLLN
R27
D9
ENABLE
V2
/OUTLRN
OUTLLN
LRN
V1
Q100
V1
V2
R-SR
V4
EL7212
LLN
U4
R28
C123
ISL89163
OUTLRN
LSR
Q101
U4
V3
T6
V3
C9
C10
LLN
V4
Red dashed lines point out the turn-on
delay of the SRs when PWM goes low
LRN
FIGURE 12. SIMPLIFIED SR DRIVE SCHEMATIC
SR Drive and Bias
OUTLLN and OUTLRN in Figure 12 are control signals from the
ISL6752/54 that are used to drive the SRs. Because the
ISL6752/54 is located on the primary side, a pulse transformer,
T6, is used to cross the isolation boundary. The simplified
schematic of Figure 12 illustrates the use of T6 to not only couple
OUTLLN and OUTLRN to the secondary, but also to generate the
bias for drivers on the secondary.
When /OUTLLN or /OUTLRN (outputs of EL7212) transitions to a
logic high, it is necessary to turn off the associated SR quickly. For
example, when /OUTLRN (blue) transitions high, V1 is high, and
C10 is quickly discharged by Q100. U4 then drives R-SR off. In a
similar manner, when /OUTLLN is high, U4 drives L-SR off.
When /OUTLLN or /OUTLRN transitions to a logic low, it is
necessary to turn on the SRs after a time delay, to prevent the
SRs from shorting the primary side bridge when it is sourcing
current. For example, when /OUTLRN transitions to low, V1 is low
and Q100 turns off, allowing C10 to be charged by R27. When
the positive threshold of UR is exceeded, the output of U4 drives
on R_SR. In a similar manner, the high to low transition of
/OUTLLN results in the output of U4 driving on L_SR after a time
delay.
Note that the cathodes of D9 are connected together to peak
charge C123. Because C123 is large in value, after the initial
charging, the voltage does not change significantly from cycle to
cycle. An important aspect of generating the bias for U4 in this
manner is that the thresholds for the logic transitions on the
inputs of U4 are proportional to VBIAS, and the voltage to charge
C9 and C10 is also VBIAS. Consequently, the delays generated by
the RC networks are independent of the absolute value of VBIAS.
Current Doubler
Figure 13 illustrates the current flow in the two inductors of the
current doubler topology. Current flow in the circuit is correlated
with the waveforms by color coding. The green waveform
represents the sum of red and blue currents through RLOAD. For
circuit clarity, paralleled SRs and output capacitors of the
ISL6752/54EVAL1Z board are not shown.
6
When using diodes (instead of SRs), if the average load current is
less than half of the ramp current in the output inductors, the
current in the inductors becomes discontinuous, and the duty cycle
of the PWM is shortened to maintain the desired output voltage.
When using SRs, the inductor currents in L1 and L2 can become
negative because current in SRs can flow bidirectionally;
consequently, the duty cycle remains virtually unchanged. The
benefit is that the load transient performance is the same for any
load from zero up to current limit. Another advantage is that, for
very light loads, the duty cycle is not reduced to very small duty
cycles, pulse skipping does not occur, and the associated voltage
jitter does not happen.
An important design consideration for the current doubler topology
is that the DC resistance of both halves must be equal. PCB layout
must be as symmetrical as possible, and the DCRs of the inductors
should be reasonably equal. If not, the current between the two
sides does not split equally. Because perfect physical PCB
symmetry is not always possible, current sharing between
inductors must be confirmed.
In Figure 14, inductor current waveforms are taken from the
ISL6752/54EVAL1Z board. Current balance between the two
inductors was achieved after one board revision. The inductor
currents maintain the same waveform shape even at no load.
Another design consideration when using SRs is how to connect
the outputs of multiple power supplies in parallel for redundancy
or increased power capacity. A consequence of negative current
flow in an SR (when a diode would otherwise be reverse biased
and off) is that power can be transferred from the secondary to
the primary if one of the paralleled outputs has a higher voltage.
The voltage loop of the units with lower set point voltages
attempts to pull down the voltage by sinking current from the
higher set point units. The primary side bridge capacitor is
charged by the secondary side, eventually resulting in excessive
voltage damage. This damage can be avoided by using OR-ing
diodes (or FETs) on the paralleled outputs. Another solution is to
turn off the SRs (diode emulation mode) when the current
reverses in the SRs, but this eliminates some of the advantages
of using SRs. Paralleling features are not implemented on the
ISL6752/54EVAL1Z board.
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Application Note 1603
L1
RLOAD
Q1
Q2
L2
UNCHANGED
DUTY CYCLE
LIGHT LOAD
WITH SRS
LOAD WITH EITHER
DIODES OR SRS
UNCHANGED DUTY
CYCLE
REDUCED DUTY
CYCLE
LIGHT LOAD
WITH DIODES
NO LOAD WHEN
USING SRS
DISCONTINUOUS CURRENTS
FIGURE 13. CURRENT FLOW IN TWO INDUCTORS OF CURRENT DOUBLER TOPOLOGY
NO LOAD
30A LOAD
50A LOAD
FIGURE 14. INDUCTOR CURRENT WAVEFORMS
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Application Note 1603
Current Sensing
Current flowing from the secondary to the primary can result in
an unanticipated malfunction of the current sensing transformer
circuit if reverse SR currents are not considered. Figure 15 shows
a commonly used primary side current sensing circuit utilizing
one current sensing transformer (CT).
Figure 17 illustrates what happens at no load to the sense
voltage across RS.
PRIMARY
TRANSFORMER
VOLTAGE
+400V
PRIMARY
TRANSFORMER
CURRENT
NOT
RECOMMENDED
VOLTAGE
ACROSS RS
RS
FIGURE 17. NO LOAD SENSE VOLTAGE ACROSS R S
400V RTN
FIGURE 15. PRIMARY SIDE CURRENT SENSING CIRCUIT UTILIZING
ONE CT
This circuit works well for peak current mode control if power is
always flowing from primary to secondary, as is the case when
diodes are used instead of SRs. Figure 16 illustrates the
performance of the current sensing output when power always
flows from primary to secondary.
PRIMARY
TRANSFORMER
VOLTAGE
PRIMARY
TRANSFORMER
CURRENT
Notice that the negative components of the primary transformer
current are rectified, resulting in two peaks of current across RS
for each half cycle. Under steady state conditions, the rectified
negative component may cause erratic performance because
the cycle can terminate on the first peak (the inverted peak, as
indicated by the vertical red line) instead of the required second
peak. This condition can easily be corrected by having a small
load across the output to ensure that the negative peak is always
less than the positive.
A minimum load, however, does not correct a more serious
problem that occurs when there is a large load step from a heavy
load to no load. When the load current is interrupted, the output
capacitor charges higher than the regulated voltage. As the
regulation loop is starting to respond by slewing to a minimum
duty cycle, the excessive voltage on the output capacitor starts to
discharge back to the primary. This results in a large negative
current at the beginning of the duty cycle, which causes the duty
cycle to be terminated very early. The imbalance of the applied
volt-seconds to the power transformer may saturate the power
transformer and damage the power bridge.
Another scenario is that the current sensing transformer itself
may saturate, which also damages the bridge. The control loop
cannot maintain balanced alternate half cycles applied to the
power transformer without valid current sense information.
There are three solutions to this problem. Figure 18 illustrates
the placements of two current sensing transformers, one on each
drain leg of the bottom FETs.
VOLTAGE
ACROSS RS
FIGURE 16. PERFORMANCE OF CURRENT SENSING OUTPUT
The voltage across RS is as expected. The vertical dashed lines
show when the power cycle is terminated at the required peak of
the current.
8
In this configuration, only positive current flowing into the drains
of the bottom FETs are sensed across RS, solving the problem of
rectified negative currents being impressed across RS. An
advantage of using two CTs is that there is a full half cycle
available to reset the cores of the CTs. This is the solution used in
the ISL6752/54EVAL1Z board.
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Application Note 1603
In Equation 1, VSMAX is 1V (the current limit voltage of the
ISL6752); this is the ideal reset voltage. In practice, however, the
parasitic capacitance of the output windings suppresses the
peak voltage, and consequently, the reset time increases. If a
custom current sensing transformer is designed, the effects of
the parasitic capacitance can be minimized by increasing the
space between turns. If a standard, off-the-shelf transformer is
used, however, the output capacitance may be too large to allow
long duty cycles. In this case, the two-transformer solution may
be necessary.
+400V
RS
RR
Notice in Figure 19 that the 400V RTN is slightly more negative
than signal ground. This configuration is recommended for
applications that directly drive the bottom FETs with MOSFET
drivers. If the 400V RTN and the MOSFET drivers are grounded,
regenerative feedback will be present on the output of the
MOSFET drivers because of the CT windings in the gate drive loop.
RR
A variation on the current sense circuit in Figure 19 is to place
the current sensing transformer in the common drain lead of the
two high-side FETs, as shown in Figure 20.
400V RTN
FIGURE 18. PLACEMENT OF TWO CURRENT SENSING
TRANSFORMERS
Figure 19 shows a different current sensing implementation that
also solves the problem shown in Figure 15. In this example, both
drain currents of the bottom FETs are sensed by only one CT.
There are some limitations that must be considered, however.
The minimum time available to reset the core is the duration of
the selected dead time between the two FETs on the same side
of the bridge. To accommodate the resetting of the CT, this dead
time can be made longer, but the consequences of reducing the
maximum duty cycle available for output voltage regulation must
be considered.
+400V
RS
RR
+400V
400V RTN
FIGURE 20. CURRENT SENSING TRANSFORMER IN THE COMMON
DRAIN LEAD
The circuits shown in Figures 19 and 20 give exactly the same
performance, but the problem associated with the gate drives (as
explained in Figure 19) is avoided. The disadvantage of placing
the CT at this location is that the CT must be designed with
400VDC operational insulation.
RS
RR
Conclusion
400V RTN
FIGURE 19. CURRENT SENSING TRANSFORMER IN THE COMMON
SOURCE LEAD
If the dead time is kept short, then the peak voltage required for
resetting the core is relatively large. For example, assume that the
selected dead time is 2% of the duty cycle. The resulting
worst-case reset voltage is shown approximately in Equation 1:
( 0.98 ⁄ 0.02 ) • V SMAX = 49V
This application note reviews the use of MOSFETs as synchronous
rectifiers to replace conventional diodes. The advantages of
improved power efficiency and load transient are reviewed along
with implementation problems that must be solved.
The use of daughter cards for the ISL6752 and ISL6754 control
ICs also allows comparison of cycle-by-cycle peak current limiting
and average current limiting.
(EQ. 1)
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References
Turn-On Procedure
[1] Fred Greenfeld, Intersil Application Note AN1246,
“Techniques to Improve ZVS Full-bridge Performance”
1. Solder a wire between DISABLE and PGND-1 lugs located on
the lower left side of the main board. Optionally connect a
switch between these two lugs.
[2] Fred Greenfeld, Intersil Application Note AN1262, “Designing
with the ISL6752, ISL6753 ZVS Full-bridge Controllers”
2. Install either of the daughter control cards onto the main
board.
[3] Richard Garcia, Intersil Application Note AN1619, “Designing
with ISL6752DBEVAL1Z and ISL6754DBEVAL1Z Control
Cards”
3. Connect the DC load to the outputs of the evaluation board.
Adjust the load to zero current.
Evaluation Board Set-up
The following sections cover the set-up of the
ISL6752/54EVAL1Z evaluation board. Also included are
waveforms, performance parameters, PCB layout, and
schematics.
4. With both supplies turned off, connect the DC bias supply to
the +13V terminal and PGND.
5. Connect the 400V supply to +400V and 400V RTN.
6. Turn on the DC bias supply and adjust the current limit to
200mA. Adjust the voltage to +12.6 VDC. The lab supply
current should be approximately 150mA.
Caution
Setting Up
Danger
• This evaluation unit should be used and operated only by
persons experienced and knowledgeable in the design and
operation of high voltage power conversion equipment.
• Use of this evaluation unit constitutes acceptance of all risk
inherent in the operation of equipment having accessible
hazardous voltage. Careless operation may result in serious
injury or death.
• Use safety glasses or other suitable eye protection.
• A line isolated 400VDC supply is required.
Lab Equipment Required
• DC bias power supply, 12.6VDC @ 200mA minimum
• Adjustable 0VDC-400VDC regulated lab power supply, 2.5ADC
minimum with current limit
• Fan to cool heatsinks
• Oscilloscope, digital preferred, with 4 channels, 20MHz
minimum bandwidth
A voltage clamp, D3, is used to protect the primary side control
circuit from catastrophic damage should the high voltage bridge
fail. In order to prevent this clamp from conducting, do not
adjust the bias supply above 13.5VDC.
7. Turn on the 400V supply and adjust the current limit to 2.5A.
Adjust the voltage to 400VDC. Do not exceed 450VDC. The
current should be approximately 45mA.
8. Turn on the fan and direct the air flow through the heatsinks
mounted on the bottom of the board.
9. Using the test points that are adjacent to the output power
lugs, measure the output voltage of 12V ±0.5VDC.
The output load and input voltage can now be safely adjusted.
Because there is no thermal shut-down circuit, it is important to
maintain adequate airflow over the heatsinks, especially when
applying large loads. It is recommended to measure the
temperature of the power FETs (primary bridge and secondary
SRs) to ensure that their temperatures do not exceed +85°C. It is
usually necessary to have only a moderate airflow over the
heatsinks, even under worst-case loads.
• Adjustable DC load (electronic or resistor), 70A @ 12V,
100A @ 0V min, >850W
• DC Multimeter
• Infra-red temperature probe (optional but highly
recommended)
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Waveforms
ZVS
In Figure 21, the drain-source voltage of the low-side FETs
relative to the gate voltage is displayed to highlight the ZVS
performance of the bridge. The load is at the rated 50A. Notice
that full ZVS is not achieved because the minimum resonance
voltage is about 25VDC. Also, the gate drive is turning on late
(about 25ns), allowing the resonant voltage to start rising. Even
though the optimum zero voltage switching is not achieved, 98%
of the switching losses are still recovered [(4002-502)/
4002 = 98%]. This improvement over the ISL6752EVALZ was
achieved by increasing the leakage inductance of the
transformer and by using bridge FETs with less body capacitance.
In Figure 22, resonant switching with 50% load still saves 84% of
the switching losses. Other techniques can be used to improve
ZVS performance. For more information, see Application Note
AN1246, “Techniques to Improve ZVS Ful-bridge Performance”.
ZVS Waveforms
FIGURE 21. RESONANT SWITCHING WITH 100% (50A) LOAD
FIGURE 22. RESONANT SWITCHING WITH 50% (25A) LOAD
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Load Transients Waveforms
FIGURE 23. STEP LOAD: 0A TO 12.5A (12.5A DELTA)
FIGURE 24. STEP LOAD: 25A TO 37.5A (12.5A DELTA)
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Load Transients Waveforms
(Continued)
FIGURE 25. STEP LOAD: 37.5A TO 50A
FIGURE 26. STEP LOAD: 0A TO 25A
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Load Transients Waveforms
(Continued)
FIGURE 27. STEP LOAD: 0A TO 50A
NOTE:
VOUT recovers after a short circuit is removed when using the ISL6754DBEVAL controller.
After the short is removed, VOUT increases linearly because the output capacitance is being charged with a constant current (~55A).
FIGURE 28. SHORT CIRCUIT RELEASE WITH ISL6754
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Output Ripple and Noise Waveforms
FIGURE 29. OUTPUT RIPPLE, 50A LOAD, 40MHz BANDWIDTH
FIGURE 30. OUTPUT RIPPLE, 50A LOAD, 145MHz BANDWIDTH
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Transformer Current, Primary Winding Waveforms
FIGURE 31. PRIMARY TRANSFORMER CURRENT vs OUTPUT LOAD TRANSIENT (25A TO 50A)
FIGURE 32. PRIMARY TRANSFORMER CURRENT vs OUTPUT LOAD TRANSIENT (50A TO 25A)
16
AN1603.1
June 8, 2011
Application Note 1603
Performance Curves
100
EFFICIENCY (%)
95
92
90
92% EFFICIENCY
WITH 20% LOAD
85
80
75
70
65
60
55
50
0
2
10
15
20
25
30
35
40
45
50
55
OUTPUT CURRENT (A)
FIGURE 33. POWER EFFICIENCY vs LOAD (ISL6752 OR ISL6754)
12
12.00
10
ISL6752
11.95
8
VOUT (V)
VOUT (V)
ISL6752
11.90
ISL6754
6
ISL6754
4
11.85
2
0
11.80
0
10
20
30
IOUT (A)
40
FIGURE 34. LOAD REGULATION
17
50
60
0
10
20
30
40
IOUT (A)
50
60
70
80
FIGURE 35. PULSE BY PULSE vs AVERAGE CURRENT LIMIT
AN1603.1
June 8, 2011
PCB Layout
+
Q4
C135
R11
REV.B
L_PHASE
+
Pb
C5
C133
R10
ISL6752_54EVAL1Z
L103
SR_B
T1
T2
Q109
SGND-2
R5
LLN
C8
R33
R32 U108
Q111
Q112
R148
VOUT
D9
SR_EN
D10
R140
12V_RTN
D13
9
8
Q101
R28
R27
R143
Q100
R144
C1
R139
R26 R29
R9
R7
GLR
R17
Q5
C9
R25
C132
D11
R23 C123
C129
U4
C17
SGND-1
R45
R16
R30
C7
R145
R8
C127
D2
Q2
R21
R2
R35
LRN
R6
R4
C121
C20
D6
D5
D8
D7
R3
U1
CR4 R43
CR6
R15
+
+
C2
C15
R36 R44 C13
R34
CR3 R42
C10
R31
Q113
T4
SR_A
T6
C6
R20
R22
U3
J2
J1
1
4
DANGER
PGND-2
OUTLRN
OUTUR
OUTLLN
OUTUL
CS+
OUTLR
OUTLL
DISABLE
VREF
13VDC PGND-1
C136
L102
- THIS EVALUATION UNIT SHOULD BE USED AND OPERATED
ONLY BY PERSONS EXPERIENCED AND KNOWLEDGEABLE IN THE
DESIGN AND OPERATION OF HIGH VOLTAGE POWER CONVERSION
EQUIPMENT.
- USE OF THIS EVALUATION UNIT CONSTITUTES ACCEPTANCE
HIGH VOLTAGE PRESENT OF ALL RISKS INHERENT IN THE OPERATION OF EQUIPMENT
HAVING ACCESSIBLE HAZARDOUS VOLTAGES. CARELESS
ELECTRICAL HAZARD
OPERATION MAY RESULT IN SERIOUS INJURY OR DEATH.
OPERATE WITH EXTREME - USE SAFTY GLASSES OR OTHER SUITABLE EYE PROTECTION.
D3
D4
ISL6752DBEVAL1Z OR ISL6754DBEVAL1Z
+
R_PHASE
+
Q3
C18
7
C22
10
CAUTION
SILKSCREEN TOP
FIGURE 36. SILKSCREEN TOP
C134
Application Note 1603
400VDC_RTN
R14
R24
C14
R18 R19
PGND-3
U2
F1
C11
GLL
CR5
T3
R12
R37 C16
400VDC
Q6
R13
C12
+
+
Q1
P104
D1
+12VOUT
C4
C3
P103
Q108
16
D12
18
Q107
1
AN1603.1
June 8, 2011
PCB Layout
(Continued)
19
Application Note 1603
LAYER 1
FIGURE 37. LAYER 1
AN1603.1
June 8, 2011
PCB Layout
(Continued)
20
Application Note 1603
LAYER 2
FIGURE 38. LAYER 2
AN1603.1
June 8, 2011
PCB Layout
(Continued)
21
Application Note 1603
LAYER 3
FIGURE 39. LAYER 3
AN1603.1
June 8, 2011
PCB Layout
(Continued)
22
Application Note 1603
LAYER 4
FIGURE 40. LAYER 4
AN1603.1
June 8, 2011
Schematics- Main Board, ISL6752/54EVAL1Z
400VDC
F1
VIN+
0464004
C1
33UF
C3
33UF
R45
PGND
C5
0.1UF
C4
33UF
C2
33UF
C18
0.1UF
100
C20
3300PF
VIN-
C121
3300PF
400VDC_RTN
E
2
2
C14
2
CR3
R14
5
3
8
1
BSS138
R16
SS12
SS12
4.99
C16
1UF
ENA
1
7
OUTA
INA
2
6
VDD
GND
3
5
OUTB
INB
4
10
EP
8
IN
C12
1UF
2
ENA
1
7
OUTA
INA
2
6
VDD
GND
3
INB
4
5
OUTB
49.9
OUT
1N4148
300-400V
200KHZ
1
NC
4
NC
5
NC
8
NC
OUT
SR_A
12V
600W 11
12
9
10
PA1650
R3
100
CSOUT
9
GLR
EP
9
R43
R24
1
49.9
CR6
100
Q3
3
R21
SS12
100
10K
ISL89163FBEBZ
10K
CR5
R35
3
CS+
2
ENB
R34
1
Q4
R42
3
P8205
ISL89163FBEBZ
U1
VDD
GLL
7
1N4148
SR_B
10K
R2
100
P8205
CS- J1
ENB
R37
1
D7
8
IN
D8
1
R19
100
8
D6
VDD
T4
8
OUT
13
14
SS12
OUTLL J1
3
OUTLL
OUTLR J1
5
OUTLR
OUTUL J1
7
OUTUL
OUTUR J1
9
OUTUR
VREF J1
2
J1
VREF
14
DISABLE
DISABLE J1
4
J1
8
VDD J1
1
OUT
VDD
D4
13VDC
BIAS
MURS160T3
D3
1.5SMC15AT3G
J1
PGND-1
12
PGND-2
PGND-3
FIGURE 41. MAIN BOARD, PRIMARY, ISL6752_54EVAL1Z
DRAWN BY:
RICHARD GARCIA
DATE:
08/03
Application Note 1603
3
15
16
6
7
U2
R18
7
10K
T2
R36
1N4148
1N4148
D5
R44
4.7
6
T1
2
3
R_PHASE
100
4.99
C13
1UF
CS+
R17
10K
2
CR4
Q2
3
1
P0544
L_PHASE
CS+ J1
3
Q5
C15
1
BSS138
20
R12
20
Q6
1
1000PF
R13
10K
6
1000PF
23
3
3
T3
4
R15
1
Q1
AN1603.1
June 8, 2011
Schematics- Main Board, ISL6752/54EVAL1Z
(Continued)
J2
+12VOUT
OUT
3.3UH
2
VOUT
R10
Q109
C133
2200UF
1.5K
24
4.7UF
C127
3
R8
1
Q108
3
R6
1
1
1
Q107
3
1
R4
1
2
2
SR_B
ES1B
D1
ES1B
D12
IN
SR_B
4.7UF
C7
SR_B
3
+12VOUT
SER2814L-332KL
L103
C134
2200UF
C136
2200UF
C135
2200UF
C132
10UF
P104
R148
1K
R11
1.5K
P103
Q111
1
Q112
1
4.7UF
C129
4.7UF
C8
3
1
R9
3
1
R7
3
1
R5
UUG1C222MNR1MS
1.5K
SGND-2
R22
Q113
1
SGND-1
R20
SR_A
D13
ES1B
SR_A
4
SEC_GND J2
12V_RTN
L102
2
IN
E
1
3.3UH
SER2814L-332KL
LRN
LRN
LLN
1
10V
BAV70
VCC_BAR
3
2
OUTLLN J1
VDD
5
U3
IN
C6
6
OUTLRN J1
13
2
U3
7
1N4148
3
7
PRI
10
1UF
D10
SEC
1
8
C22
Q100 2
BSS138
P0584
D11
EL7212 1UF
3
2K
R143
R23
DNP
R25
R139
1K
SEC
2
3
1
3
1
Q101
BSS138
DNP
2
IN1A
VDD
14
4
IN2A
OUTA
13
5
IN1B
OUTB
12
6
IN2B
VSS
11
7
INVB
RDELB
10K
R32
DNP
R33
DNP
R145
10
9
VREF- FDELB
EP
17
R144
15
3
8
1N4148
16
C11
4
EL7212
4
11
R140
1K
VREF+ FDELA
RDELA
INVA
4.7UF
T6
U108
1
249
OUTLLN
R28
C123
10UF
249
R27
D9
10K
E
OUTLRN
E
E
SR_EN J2
ISLISL89367FRAZ
E
10V
1
VCC_BAR
U4
0
R29
ENB
INA
OUTA
7
3
GND
VDD
6
OUTB
5
C10
INB
9
1000PF
C9
1000PF
4
0
SEC_GND J2
ENA
2
EP
ISL89163FBEBZ
2
AN1603.1
June 8, 2011
E
FIGURE 42. MAIN BOARD, SECONDARY, ISL6752_54EVAL1Z
R30
0
R31
4.7UF
R26
8
C17
SR_EN
1
0
LLN
Application Note 1603
D2
ES1B
2
2
2
1.5K
SR_A
Schematics - Daughter Card
VDD
R29
R8
0
R30
TBD
2
DNP
COLLECTOR
4
EMITTER
3
CATHODE
R32
1K
C12
R33
499
5
4
2
C11
4.75K 0.01UF
3
4
9
J1
5
OUTUL
OUTUR
OUTLLN
15
7
J1
J1
J1
CS
OUTLRN
IOUT
GND
ISL6754AAZA
12
C5
C10
9
13
11
13
11
C15
0.1UF
Q2
THIS PAD
BETWEEN
100PF
1
100PF R39
10K
C17
1K
3
10K
BSS138
2
R35
10K
R34
C16
C18
100PF
2
6.65K
100PF
82PF
100PF
C4
14
OUTLL
OUTLR
OUTUL
OUTUR
J1 OURLLN
J1 OUTLRN
VREF
D5
100PF
C8
100PF
10K
C6
3
16
18
1
R25
DISABLE J1
6.65K
R10
10
33.2
R7
CS- J1
R4
12
33.2
R6
PGND J1
22.1K
10
100
PGND J1
8
499
17
CT
FB
RAMP
7
1K
OUTLL
OUTLR
19
R37
DNP
R17
8
6
R18
499
R12
6
3.48K
R20
R13
20
RTD
RESDEL
5
R24
SS
VADJ
VDD
VREF
VERR
CTBUF
2
R36
1K
R31
R38
100
2 Q1
1
61.9K
U4
MMBT2222LT1
R21
1
15.4K
R9
C2
3
VREF
TP_PRI
PGND
R26
PGND
4
5
U2
3
V+
OUT
1
DRAWN BY:
D3
1
ANODE
2
CATHODE
COLLECTOR
4
1
EMITTER
3
2
V-
TSW-102-08-T-D-RA
J2 SR_ENABLE
J2 SEC_GND
2
0.1UF
EL5120IWT
C9
DNP
4
R15
R27
10K
10K
R14
R23
DNP
DNP
R19
VDD
VREF
PS2701
SEC_GND
AN1603.1
June 8, 2011
PGND
FIGURE 43. DAUGHTER CARD, ISL6754DBEVAL
RELEASED
UPDATED
RICHARD_GA
BY:
BY:
Application Note 1603
0.1UF
VDD
PGND
14
2
PGND
SEC_GND
TSW-107-08-T-D-RA
VDD J1 1
VREF J1 2
CS+ J1
CS J1
D4
1
V-
C14
C13
R28
1K
1
OUT
3
C7
0.1UF
U3
V+
EL5120IWT
0.1UF
DNP
PS2701
R22
C
1 A
2 NC
4
BZX84C6V8LT1
2
D1
3
R3
2.15K
25
SEC_GND J2
ANODE
0.1UF
U1
LMV431AIMF
D2
3
1
1
SGND
1K
R16
1K
R11
C3
DNP
R1
R2
TP_SEC
649
R5
C1
0.1UF
18K
499
0.01UF
3
+12VOUT J2
Schematics - Daughter Card (Continued)
VDD
R29
R8
C2
2
CATHODE
EMITTER
3
R31
1K
C12
R33
499
5
4
EL5120IWT
D4
U3
OUT
1
2
V-
C14
0.01UF
R24
1K
C13
3
C7
0.1UF
V+
0.1UF
DNP
R22
BZX84C6V8LT1
C
D2
PS2701
1
2
A
3
R3
4
Application Note 1603
2.15K
LMV431AIMF
4
SGND J2
DNP
COLLECTOR
0.1UF
U1
1
SGND
1K
R16
ANODE
3
1
2
R5
D5
OPEN
DNP
R2
649
TP_SEC
C1
0.1UF
R11
18K
R1
499
NC
26
0
R30
1K
3
+12VOUT J2
PGND
TSW-107-08-T-D-RA
VDD J1 1
VREF
2
C11
3
DNP
3
14
5
13
7
12
9
OUTLLN
11
11
J1
J1
J1
OUTLRN
CS
GND
ISL6752AAZA
10
13
J1
6
RESDEL
CT
OUTUL
OUTUR
9
U2
4
20K
R15
47UF
EL5120IWT
1
PGND
DISABLE J1
4
AN1603.1
June 8, 2011
FIGURE 44. DAUGHTER CARD, ISL6752DBEVAL1Z
ANODE
2
CATHODE
COLLECTOR
4
1
EMITTER
3
2
2
PGND
PGND
D3
1
V-
C9
Q2
OUT
0.1UF
1
R27
10K
R18
10K
3
1K
2
R34
10K
5
3
V+
C16
R32
10K
100PF
10K
C17
R37
C10
47PF
6.65K
C5
82PF
R7
C4
100PF
47PF
C8
100PF
10K
10
37.4
R10
CS- J1
R6
12
R4
PGND J1
37.4
TP_PRI
C6
VDD
1M
R19
BSS138
14
OUTLL
OUTLR
OUTUL
OUTUR
OURLLN
OUTLRN
VREF
VREF
100
PGND J1
J1
J1
R23
61.9K
R36
15
0.1UF
10K
R14
R21
R17
3.48K
R12
8
OUTLL
OUTLR
VERR
CTBUF
RTD
8
499
16
5
7
R13
VDD
VADJ
VREF
2K
665
2
100
4
6
CS J1
1
D1
2 Q1
PGND
CS+ J1
R28
1
20K
R9
C3
0.1UF
U4
MMBT2222LT1
R20
3
R35
VREF J1
PS2701
TSW-102-08-T-D-RA
J2 SR_ENABLE
J2 SGND
Application Note 1603
Bill of Materials
PART NUMBER
QTY UNITS
REFERENCE
DESIGNATOR
DESCRIPTION
MANUFACTURER
MANUFACTURER PART
PWB-PCB,
ISL6752_54EVAL1Z,
REV B, ROHS
IMAGINEERING INC
ISL6752/54EVAL1ZREVBPC B
C11, C17
CAPACITOR, SMD, 1206,
4.7µF, 16V, 10%, X7R,
ROHS
TDK
C3216X7R1C475K
ea
C5, C18
CAP, SMD, 1812, 0.1µF,
630V, 10%, X7R, ROHS
TDK
C4532X7R2J104K
2
ea
C20, C121
CAP, SMD, 2220, 3300pF, MURATA
250V, 10%, X7R, ROHS
GA355QR7GF332KW01L
H1046-00102-100V10-T
2
ea
C14, C15
CAP, SMD, 0805, 1000pF, VENKEL
100V, 10%, X7R, ROHS
C0805X7R101-102KNE
H1046-00102-50V5-T
2
ea
C9, C10
CAP, SMD, 0805, 1000pF, PANASONIC
50V, 5%, NP0, ROHS
ECU-V1H102JCX
H1046-00105-25V10-T
5
ea
C6, C12, C13, C16,
C22
CAP, SMD, 0805, 1.0µF,
25V, 10%, X5R, ROHS
AVX
08053C105KAT2A
H1065-00106-25V10-T
1
ea
C123, C132
CAP, SMD, 1206, 10µF,
25V, 10%, X5R, ROHS
VENKEL
C1206X5R250-106KNE
H1082-00475-50V10-T
4
ea
C7, C8, C127, C129
CAP, SMD, 1210, 4.7µF,
50V, 10%, X7R, ROHS
MURATA
GRM32ER71H475KA88L
SER2814L-332KL
2
ea
L102, L103
COIL-PWR INDUCTOR,
SMD, 3.3µH, 10%, 48A,
1.2mΩ, ROHS
COILCRAFT
SER2814L-332KL
UUG1C222MNL1ZD
4
ea
C133-C136
CAP, SMD, 16X16.5,
2200µF, 16V, 20%,
AL.EL., ROHS
NICHICON
UUG1C222MNL1ZD
UUG2W330MNL1MS
4
ea
C1-C4
CAP, SMD, 18X21.5,
33µF, 450V, 20%,
ALUM.ELEC, ROHS
NICHICON
UUG2W330MNL1MS
131-4353-00
1
ea
VOUT
CONN-SCOPE PROBE
TEST PT, COMPACT,
PCBMNT, ROHS
TEKTRONIX
131-4353-00
1514-2
6
ea
a) 13VDC, 400VDC,
PGND-1, PGND-2,
DISABLE
CONN-TURRET, TERMINAL KEYSTONE
POST, TH, ROHS
1514-2
1514-2
0
ea
b) 400VDC_RTN
CONN-TURRET, TERMINAL KEYSTONE
POST, TH, ROHS
1514-2
5002
9
ea
a) CS+, VREF, OUTLL, CONN-MINI TEST POINT,
OUTLR, OUTUL, OUTUR VERTICAL, WHITE, ROHS
KEYSTONE
5002
5002
0
ea
b) SR_EN, OUTLLN,
OUTLRN
KEYSTONE
5002
5016-T
13
ea
a) GLL, GLR, LLN, LRN, CONN-COMPACT TEST
SR_A, SR_B, PGND-3, POINT, SMD, ROHS
2, +12VOUT, 12V RTN
KEYSTONE
5016
5016-T
0
ea
b) SGND-1, SGND-
CONN-COMPACT TEST
POINT, SMD, ROHS
KEYSTONE
5016
5016-T
0
ea
c) L_PHASE, R_PHASE CONN-COMPACT TEST
POINT, SMD, ROHS
KEYSTONE
5016
ISL6752/54EVAL1ZREVBPCB
1
ea
C3216X7R1C475K-T
2
ea
C4532X7R2J104K-T
2
GA355QR7GF332KW01L-T
27
CONN-MINI TEST POINT,
VERTICAL, WHITE, ROHS
AN1603.1
June 8, 2011
Application Note 1603
Bill of Materials
PART NUMBER
(Continued)
REFERENCE
DESIGNATOR
QTY UNITS
DESCRIPTION
MANUFACTURER
MANUFACTURER PART
SLW-102-01-S-D
1
ea
J2
CONN-SOCKET STRIP, LP, SAMTEC
2X2, 2.54mm, GOLD/TIN,
ROHS
SLW-102-01-S-D
SLW-107-01-S-D
1
ea
J1
CONN-SOCKET STRIP, LP, SAMTEC
2X7, 2.54mm, GOLD/TIN,
ROHS
SLW-107-01-S-D
1N4148WS-7-F-T
6
ea
D5-D8, D10, D11
DIODE-RECTIFIER, SMD,
SOD-323, 2P, 75V,
150mA, ROHS
BAV70-T
1
ea
D9
DIODE-DUAL, SWITCHING, NXP SEMICONDUCTORS BAV70, 215
SMD, SOT23, 100V,
125mA, ROHS
ES1B-13-F-T
4
ea
D1, D2, D12, D13
DIODE-RECTIFIER, SMD, DIODES INC.
2P, SMA, 100V, 1A, ROHS
ES1B-13-F
MURS160T3G-T
1
ea
D4
DIODE-RECTIFIER, SMD, ON SEMICONDUCTOR
SMB, 2P, 1A, 600V, ROHS
MURS160T3G
SS12T3G-T
4
ea
CR3-CR6
DIODE-SCHOTTKY
RECTIFIER, SMD, SMA,
2P, 20V, 1A, ROHS
ON SEMICONDUCTOR
SS12T3G (T3= T&R)
0464004.DR
1
ea
F1
FUSE, SMD, 12X4.5, 4A,
250V, NANO2 FAST
ACTING, ROHS
LITTELFUSE
0464004.DR
1.5SMC15AT3G-T
1
ea
D3
TVS, UNIDIRECTION, SMD, ON SEMICONDUCTOR
SMC, 1500W, 12.8V
(peak rev) ROHS
EL7212CSZ
1
ea
U3
IC-DUAL CHANNEL
MOSFET DRIVER, 8P,
SOIC, ROHS
INTERSIL
EL7212CSZ
ISL89163FBEBZ
3
ea
U1, U2, U4
IC-6A PWR MOSFET
DRIVER, 8P, EPSOIC,
ROHS
INTERSIL
ISL89163FBEBZ
ISL89367FRTAZ
1
ea
U108
IC-6A MOSFET DRIVER,
12V INPUT, 16P, DFN,
3X5, ROHS
INTERSIL
ISL89367FRTAZ
BSS138LT1G-T
4
ea
Q5, Q6, Q100, Q101
TRANSIST-MOS,
N-CHANNEL, SMD, 3P,
SOT23, 50V, 200mA,
ROHS
ON SEMICONDUCTOR
BSS138LT1G
FDD6670A
6
ea
Q107-Q109, Q111Q113
FAIRCHILD
TRANSISTOR-MOS,
N-CHANNEL, SMD, DPAK,
30V, 66A, ROHS
SPB04N60C3
4
ea
Q1-Q4
INFINEON TECHNOLOGY SPB04N60C3
TRANSIST-MOS,
N-CHANNEL, 3P,
PG-TO263-8, 650V, 4.5A,
ROHS
H2511-00010-1/10W1-T
6
ea
R4-R9
RES, SMD, 0603, 1Ω,
1/10W, 1%, TF, ROHS
PANASONIC
ERJ-3RQF1R0V
H2511-00R00-1/10W-T
2
ea
R26, R29
RES, SMD, 0603, 0Ω,
1/10W, TF, ROHS
VENKEL
CR0603-10W-000T
H2511-01000-1/10W1-T
6
ea
R2, R3, R18, R19,
R21, R24
RES, SMD, 0603, 100Ω,
1/10W, 1%, TF, ROHS
VENKEL
CR0603-10W-1000FT
28
DIODES INC.
1N4148WS-7-F
1.5SMC15AT3G
FDD6670A
AN1603.1
June 8, 2011
Application Note 1603
Bill of Materials
PART NUMBER
(Continued)
REFERENCE
DESIGNATOR
QTY UNITS
DESCRIPTION
MANUFACTURER
MANUFACTURER PART
H2511-01001-1/10W1-T
2
ea
R139, R140
RES, SMD, 0603, 1k,
1/10W, 1%, TF, ROHS
PANASONIC
ERJ-3EKF1001V
H2511-01002-1/10W1-T
4
ea
R34-R37
RES, SMD, 0603, 10k,
1/10W, 1%, TF, ROHS
KOA
RK73H1JT1002F
H2511-02001-1/10W1-T
1
ea
R143
RES, SMD, 0603, 2k,
1/10W, 1%, TF, ROHS
KOA
RK73H1JTTD2001F
H2511-02490-1/10W1-T
2
ea
R27, R28
RES, SMD, 0603, 249Ω,
1/10W, 1%, TF, ROHS
VENKEL
CR0603-10W-2490FT
H2511-049R9-1/10W1-T
2
ea
R42, R43
RES, SMD, 0603, 49.9Ω,
1/10W, 1%, TF, ROHS
VENKEL
CR0603-10W-49R9FT
H2511-DNP
0
ea
R23, R25
RES, SMD, 0603, DNP
PLACEHOLDER, ROHS
H2512-00200-1/8W1-T
2
ea
R12, R15
RES, SMD, 0805, 20Ω,
1/8W, 1%, TF, ROHS
KOA
RK73H2AT20R0F
H2512-004R7-1/8W1-T
1
ea
R44
RES, SMD, 0805, 4.7Ω,
1/8W, 1%, TF, ROHS
YAGEO
RC0805FR-074R7L
H2512-00R00-1/8W-T
2
ea
R30, R31
R30, R31 RES, SMD,
0805, 0Ω, 1/8W, TF,
ROHS
YAGEO
RC0805JR-070RL
H2512-01002-1/8W1-T
4
ea
R13, R17, R144, R145 RES, SMD, 0805, 10k,
1/8W, 1%, TF, ROHS
VENKEL
CR0805-8W-1002FT(PbFREE)
H2512-04R99-1/8W1-T
2
ea
R14, R16
RES, SMD, 0805, 4.99Ω,
1/8W, 1%, TF, ROHS
YAGEO
RC0805FR-074R99L
H2512-DNP
0
ea
R32, R33
RES, SMD, 0805, DNPPLACEHOLDER, ROHS
H2513-01000-1/4W1-T
1
ea
R45
RES, SMD, 1206, 100Ω,
1/4W, 1%, TF, ROHS
STACKPOLE/FCI
RMC1/8 100R 1% T/R
H2513-01001-1/4W1-T
1
ea
R148
RES, SMD, 1206, 1.00k,
1/1%, 4W, TF, ROHS
YAGEO
RC1206FR-071KL
H2515-01501-1W5-T
4
ea
R10, R11, R20, R22
RES, SMD, 2512, 1.5k,
1W, 5%, TF, ROHS
VISHAY/DALE
CRCW25121K50JNEG
G108092LF
1
ea
T1
GCI TECHNOLOGIES
TRANSFORMER-PWR,
CUSTOM, 3.2µH, 20%, TH,
16P, 46X45, ROHS
P0544NL
1
ea
T3
TRANSFORMER-GATE
DRIVE, SMD, 8P, 9X8.6,
8P, 3950µH, ROHS
PULSE
P0544NL
P0584NL
1
ea
T6
TRANSFORMER-GATE
DRIVE, TH, 6P, 450µH,
1:1:1RATIO, ROHS
PULSE
P0584NL
P8205NL-T
2
ea
T2, T4
TRANSFORMERCURRENT SENSE, SMD,
8P, 500µH, 10A, ROHS
PULSE
P8205NL
61215-3B-02500G
2
ea
HS1, HS2
AAVID/FCI
(SEE ASSEMBLY
INSTRUCTIONS)
HEATSINK-BLACK
ANODIZED, 2.5, CUSTOM
CUT, ROHS
29
G108092LF
61215-3B-02500G
AN1603.1
June 8, 2011
Application Note 1603
Bill of Materials
PART NUMBER
(Continued)
QTY UNITS
REFERENCE
DESIGNATOR
DESCRIPTION
MANUFACTURER
MANUFACTURER PART
ISL6752DBEVAL1ZFG
1
ea
BAG & SHIP W/BOARD PWBFG,
ISL6752DBEVAL1Z,
ROHS
INTERSIL
ISL6752DBEVAL1ZFG
ISL6754DBEVAL1ZFG
1
ea
BAG & SHIP W/BOARD PWBFG,
ISL6754DBEVAL1Z,
ROHS
INTERSIL
ISL6754DBEVAL1ZFG
KPA8CTP
2
ea
P103, P104
HDWARE, MTG, CABLE
TERMINAL, 6-14AWG,
LUG & SCREW, ROHS
BERG/FCI
KPA8CTP
10X12-STATIC-BAG
1
ea
Place assy in bag
BAG, STATIC, 10X12, ZIP
INTERSIL
212403-015
BP100-0.005-00-1112-NA
2
ea
HS1, HS2 (SEE
ASSEMBLY
INSTRUCTIONS)
INSULATION-BOND-PLY
5mil ADHESIVE TAPE,
ROHS
BERGQUIST
BP100-0.005-00-1112-NA
LABEL-SERIAL NUMBER
1
ea
LABEL-FOR SERIAL
INTERSIL
NUMBER AND BOM REV #
LABEL-SERIAL NUMBER
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
30
AN1603.1
June 8, 2011