si-6633m ds en

SANKEN ELECTRIC CO., LTD.
SI-6633M
Scope
The present specifications shall apply to a 3 phase brushless motor driver IC, SI-6633M.
The present specifications shall apply to SI-6633M which is performed RoHS instructions.
Outline
Type
Monolithic integrated circuit
Structure
Plastic molded (transfer mold)
3 phase brushless motor driver
Applications
(Trapezoidal Current Control.)
Absolute maximum ratings
Items
Symbol
Condition
Limit
Unit
Power supply voltage
VBB
38
V
Output voltage
VOUT
VBB
V
IOUT(Ave)
±2
A
±4
A
Output current（※）
IOUT(Peak)
tw<500msec/Duty<10%
Logic input voltage
VIN(Logic)
-0.3~5.5
V
Analog voltage
VIN(Analog)
-0.3~6
V
Sense voltage
VSENSE
Power dissipation
PD
±0.5
V
2.9
W
Junction temperature
TJ
150
℃
Storage temperature
Tstg
-40~150
℃
Ambient temperature
TA
-20~85
℃
SK evaluation board
Output current rating may be limited by duty cycle, ambient temperature, and heat sinking.
Under any set of conditions, do not exceed the specified junction temperature (Tj).
Peak current is guaranteed by design.
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SI-6633M
Electrical characteristics
Recommendable Operating Range
Item
Power supply voltage
Logic input voltage
Analog input voltage
Symbol
VBB
VIN(Logic)
VIN(Analog)
Limit
10 to 30
0 to 5.5
0 to 5.5
Unit
V
V
V
Ref input voltage
VRef
0.5 to 5.5
V
Sense voltage
Package temperature
Ambient temperature
VSEN
TC
TA
±0.5
V
℃
℃
105
-20 to 85
Remark
Normal operation
Except for Ref pin
Current accuracy is going down
under 0.5V.
Especially, care should be taken with output current on condition over recommendation range and below absolute
max rating. In this case, enough evaluation is needed with thermal design data below and application note to avoid
the device being over absolute max rating for other item.
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Electrical Characteristic
SI-6633M
(Ta=25°C,VBB=24V，VDD=5V，Unless Otherwise Noted.)
Limit
Item
Symbol
Power supply voltage range
VBB
Charge pump voltage
VCP
6
7.5
Charge pump frequency
fCP
90
120
Power supply current
Min.
Typ.
Max.
10
-
VBBOV
Unit
Condition
V
Motor operation
9
V
Output disable, VCP-VBB voltage
150
kHz
IBB
5
10
15
mA
Output disable
IBBSTBY
-
100
500
µA
VSTBY=2.5V
VBB=38V
IOLKL
-200
-100
-50
µA
VBB=38V、VOUT=0V
IOLKH
50
100
200
µA
VBB=VOUT=38V
MOSFET ON resistance
RDS(on)
0.1
0.2
0.3
Ω
IDS=2.0A、S pin connected to GND
Body diode forward voltage
VSD
0.8
1.1
1.4
V
ISD=2.0A
VSTBYL
0
-
0.8
V
VSTBYH
2.5
-
VDD
V
∆VSTBY
0.1
0.25
0.4
V
ISTBYL
0
±1
±10
µA
ISTBYH
20
50
100
µA
Output leak current
STBY pin input voltage
STBY pin input current
Logic input voltage
Logic input current
Hysteresis
VSTBY=5V
VINPL
0
-
0.8
V
VINPH
3.5
-
VDD
V
∆VINP
1
1.5
2
V
Hysteresis
IINPL
0
±1
±10
µA
VIN=0V
IINPH
0
±1
±10
µA
VIN=5.5V
VREF=0 to 5.5V
REF pin input current
IREF
-5
-0.5
1
µA
REF pin input current
VREF
0.5
-
5.5
V
SEN pin input current
ISEN
0
±2.5
±10
µA
VSEN=0 to 0.5V
Current sensing divider ratio
VSEN/VREF
-10
-
10
%
VREF=5.5V
Current sensing filter time
Enable、Brake、
Dir、SRMD、
Decay、PWM
tLPFSEN
0.6
1.8
3
µs
VCPWML
1.1
1.5
1.9
V
VCPWMH
3
3.5
4
V
CPWM pin frequency
fCPWM
15
25
35
kHz
CPWM=1000pF
CLD pin frequency
fCLD
54
64
74
Hz
CLD=0.1μF
Power supply voltage range
VBB
10
-
VBBOV
V
Motor operation
Charge pump voltage
VCP
6
7.5
9
V
Output disable, VCP-VBB voltage
Charge pump frequency
fCP
90
120
150
kHz
AIN pin input current
IAIN
-1
-0.5
1
µA
AINP、AINN pin, VAIN=0 to 5.5V
VAOENA
-
1.2
VCPWML
V
VAOENAhys
0.05
0.1
0.15
V
AOUT pin max output voltage
VAOUTH
VCPWMH
4
4.45
V
AOUT pin voltage rising
Guaranteed by
Hysteresis
design
Output PWM operating
AOUT pin input voltage range
VAOUTEI
4.5
-
5.5
V
Output 100% ON
AOUT pin max output current
IAOUT
7.5
-
-
mA
VAOUT=0V
CPWM pin threshold voltage
AOUT pin threshold voltage
AOUT pin pull-down resistance
RAOUT
25
32.5
40
kΩ
VAOUT=2.5V
FLAG pin output voltage
VFLAG(ON)
0.1
0.2
0.5
V
IFLAG=2mA
FLAG pin leak current
IFLAG(OFF)
0
-
20
µA
VFLAG=5.5V
FG pin output voltage
VFG(ON)
0.1
0.2
0.5
V
IFG=2mA
FG pin leak current
IFG(OFF)
0
-
20
µA
VFG=5.5V
FLAG
FG
 Typ data is for reference only.
 Negative current is defined as coming out of the specified pin.
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Electrical Characteristic(continued)
Item
VBB under voltage lock out
Over voltage threshold
Over current detect voltage
Over current filter time
Thermal shutdown
Thermal alarm
Symbol
SI-6633M
(T a=25°C,VBB =24V, VDD=5V，Unless Otherwise Noted.)
Limit
Unit
Condition
Min.
Typ.
Max.
VBBUVH
7
7.5
9
V
VBB rising
VBBUVhys
0.1
0.3
0.5
V
Hysteresis
VBBOV
34
35
37.5
V
VBB rising
VBBOVhys
1.5
2
2.5
V
Hysteresis
VOCPLS
1
1.3
1.5
V
OUT-GND voltage, Low side detect
VOCPHS
0.7
1.0
1.3
V
VBB-OUT voltage, High side detect
tLPFOC
-
0.6
tLPFSEN
µs
TTSD
150
165
-
°C
Temperature rising
∆TTSD
-
50
-
°C
Hysteresis
TTA
-
120
-
°C
Guaranteed by
Temperature rising design
∆TTA
-
10
-
°C
Hysteresis
tPDON
-
2.3
-
µs
HALL input to output ON
VCP= VBB+7V
Stop operation
tPDOFF
-
2.1
-
µs
HALL input to output OFF
tPDPWMON
-
1.1
-
µs
PWM input to output ON
tPDPWMOFF
-
0.9
-
µs
PWM input to output OFF
Dead time
tDEAD
100
300
800
ns
Hall input current
IHALL
-2
-0.5
1
µA
Common mode voltage range
VCMR
0.2
-
3.5
V
AC input voltage range
VHALL
60
-
-
mV
Hysteresis
VHYS
-
20
VHALL
mV
Pulse reject filter
tpulse
1
2
3
µs
Propagation delay
VIN=0.2 to 4.2V
Guaranteed by design
 Typ data is for reference only.
 Negative current is defined as coming out of the specified pin.
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SI-6633M
Power dissipation
パッケージ許容損失　ＰＤ［Ｗ]
4
3.5
3
2.5
2
43℃/W
1.5
1
0.5
0
-20
0
20
Ambient Temperature
周囲温度
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40
60
80
100
Ｔa ［℃］
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SI-6633M
Excitation control input (Hall and Logic input)
Truth table
Input
Status
F1
F2
F3
F4
F5
F6
Error
Error
Brake
Disable※2
HallU※1
HallV※1
HallW※1
Enable
Brake
+
+
+
+
X
X
+
+
+
+
X
X
+
+
+
+
X
X
L
L
L
L
L
L
X
X
L
H
H
H
H
H
H
H
H
H
L
X
Output status
DIR=H (L)
OUTU
OUTV
OUTW
H (L)
H (L)
Z
L (H)
L (H)
Z
Z
Z
L
Z
L (H)
Z
H (L)
H (L)
Z
L (H)
Z
Z
L
Z
Z
L (H)
L (H)
Z
H (L)
H (L)
Z
Z
L
Z
※1 HallU、HallV、HallW ： ’+’=H+>H- 、’-’ =H+<H※2 There are conditions for the device to be disable
・ HallU, HallV and HallW are internal logic signal made from HU+, HU-, HV+, HV-, HW+
and HW・ Refer to “10.12 Enable and Brake” for disable operation
Stand-By pin
Truth table
STBY
L
H
Status
Operation mode
Stand-By mode
・ In stand-by mode, some internal circuits are shut down with bias current being cut.
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SI-6633M
FLAG output
Truth table
Status
Normal
Fault
Fault
Output OFF (High impedance)
L
Below are the fault conditions.
① Under voltage lock out for VBB (internal regulator)
② Under voltage lock out for charge pump
③ Overvoltage
④ Thermal alarm
⑤ tOFFOCP after over current detection
⑥ Lock detection
・ Please take care for FLAG output due to the internal circuit may not be fixed with VBB
being low.
FG signal
Timing chart
DIR
HallU
HallV
HallW
FG
・ Refer to “10.1 Hall and Logic input” on HalU, HallV and HallW
・ FG is toggled by each phase changed
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SI-6633M
Internal PWM control
Timing chart
tLPFSen
tLPFSen
CPWM
0.1×REF
拡大
SEN
Enlargement
SEN
フィルタにより無感
Blanking time
by filter
OUTx
OUTx
ON
OFF
（※The value is typical in the timing chart）
・ If not using this function, you should connect SEN pin to GND and put some voltage (from
1V to max in VREF voltage range) to REF pin.
Internal
PWM is active in off time, but the device has blanking time that is almost same as
・
tLPFSen.
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SI-6633M
External PWM control
Timing chart
100%ON期間
100%
On time
4.5V
3.5V
CPWM
AOUT
1.5V
1.2V
Forced
off time
強制オフ期間
1.1V
Forced
off time
強制オフ期間
Out state
OUT状態
Disable
PWM
OFF
PWM
ON
Disable
（※The value is typical in the timing chart）
・ Outputs are disable below 1.2V (typ, the voltage rising) on AOUT pin.
・ The max duty is 95% (typ, design value) due to the forced off time. The forced off time is
active even if not using this function.
・ To make 100% ON duty, you should put the external voltage over 4.5V on AOUT.
However, the voltage range to make 100% ON is from 4.5V to 5.5V.
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SI-6633M
PWM control (PWM and Decay)
Timing chart
Decay
PWM
H/S
OFF
ON
ON
OFF
A相：
A phase
H/S オン
on
H/S
L/S
L/S
ON
OFF
ON
OFF
B相：
B phase
L/S
L/Sオン
on
H/S
L/S
ON
OFF
・ This diagram only shows the relation between PWM pin and output. However, the forced
off time in “10.6 external PWM control” make the outputs be OFF.
・ Please tie to “L” when not using this function.
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SI-6633M
PWM and Synchronous rectification (Decay pin and SRMD pin）
SRMD=’L’（passive mode）
Timing chart
PWMPWMチョッピング
chopping
状態
State
AA相：
phase
H/S オン
H/S
on
ON
OFF
ON
OFF
ON
OFF
ON
H/S ON
L/S ON
H/S ON
L/S ON
OFF
H/S ON
L/S
ON
OFF
H/S ON
L/S ON
H/S ON
L/S ON
H/S ON
OFF
L/S ON
H/S
ON
OFF
L/S ON
OUT pin
OUT端子電圧
Voltage
0V
-40mV
BB相：
phase
L/S オン
L/S
on
Decay=’H’
(Fast Decay)
A phase→BA相→B相
phase
0A
B phase→AB相→A相
phase
BB相：
phase
L/S オン
L/S
on
Decay=’L’
(Slow Decay)
状態
State
L/S ON
A phase→B A相→B相
phase
0A
B
phase→AB相→A相
phase
（※The value is typical in the timing chart）
・ The device stop the synchronous rectification in PWM off time if the voltage on OUT pin,
where low side is ON, is over -40mV (typ, room temp).
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SI-6633M
SRMD=’H’（Active mode）
Timing chart
PWMPWMチョッピング
chopping
状態
State
AA相：
phase
H/S オン
H/S
on
ON
OFF
ON
OFF
ON
OFF
ON
H/S ON
L/S ON
H/S ON
L/S ON
H/S ON
L/S ON
H/S ON
L/S ON
H/S ON
L/S ON
H/S ON
L/S ON
H/S ON
L/S ON
H/S ON
L/S ON
H/S ON
L/S ON
H/S ON
L/S ON
H/S ON
OUT pin
OUT端子電圧
Voltage
0V
-40mV
Decay=’H’
(Fast Decay)
BB相：
phase
L/S オン
L/S
on
状態
State
A相→B相
0V
B相→A相
State
状態
A
phase OUT pin
A相：
H/S オン
H/S
on OUT端子電圧
Voltage
0V
-40mV
Decay=’L’
(Slow Decay)
B
phase
B相：
L/S オン
L/S
on
State
状態
L/S ON
A相→B相
0A
B相→A相
（※The value is typical in the timing chart）
・ Synchronous rectification is active in PWM OFF (current recirculation) without monitor
on OUT pin.
・ In this mode, since the excitation mode is not changed even if current recirculation is
finished, the condition of the device is below.
 Slow Decay: Same as short brake
 Fast Decay: Reverse current starts to flow.
・ In the application where not using internal PWM with fast decay, the device gets OCP
protection with long term of synchronous rectification due to the reverse current get large.
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SI-6633M
Disable function for synchronous rectification (Fast decay only)
Timing chart
PWMチョッピング
PWM
chopping
ON
OFF
ON
OFF
ON
OFF
ON
OFF
0
1
CPWM
内部カウント
Internal
Count
H/S
0
H/S
BB相：
phase
L/S オン
L/S
on
L/S
2 3
0
1
2
0
1
2
3
4
5
6
7
ON
OFF
AA相：
phase
H/S オン
H/S on
L/S
1
ON
OFF
ON
OFF
ON
OFF
・ The device stops synchronous rectification when PWM OFF keeps for 7 cycles of CPWM.
・ Synchronous rectification is not activated when in brake mode.
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SI-6633M
Over current protection
Timing chart
出力OFF
Outputs
Outputs
出力OFF
H/S OUTx
1.25V
VBB-0.9V
L/S OUTx
CPWM
内部カウント
Internal
Count
FL
0
出力’Z’
Output
1
2
3
126
127
0
1
2
出力’L’
Output
（※The value is typical in the timing chart）
・ After OCP function is detected, outputs are disabled for 128 cycles of CPWM. After the
disable time (128cycles of CPWM) is finished, the device automatically operates again
・ The trigger for off timer count and release of FL output is at the top of CPWM oscillation
waveform.
・ The trigger for release of off timer count is at the bottom of CPWM oscillation.
・ There is time difference between release for FL and actual output on.
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SI-6633M
Motor lock
Timing chart
RST
CLD
内部カウント
Internal
Count
0
1
2
0
1
2
出力’Z’
Output
FLAG
127
128
0
1
Output
出力’L’
COSC
出力
Output
ON
OFF
ON
・ Lock detection is active in operation only (Enable=L and Brake=H)
・ The device recognizes lock condition if RST signal (H) is not for about 128 cycles of CLD.
・ RST means internal signal showing release lock condition as in hall input changing. Please
refer to timing chart in 10.12 Enable and Brake, or refer to 11.9 Lock detect.
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SI-6633M
Enable and Brake
Timing chart
Enable
Brake
CPWM
1
LD counter Operation
動作
LDカウンター
動作状態
operational
state
2
Reset
リセット
回転
Rotate
1
Operation
動作
Reset
リセット
ブレーキ
Blake
2
Operation
動作
3
4
1
Reset
リセット
回転
Rotate
Operation
動作
Disable
2
Reset
リセット
回転
Rotate
Disable
・ Enable pin has two functions with priority below.
① Reset for lock counter
 Lock counter is reset for Enable being high.
② Enable/Disable operation for output
 The device makes output disable at 4th bottom on CPWM oscillation waveform
after down-edge of Enable signal.
 The device makes output enable at the first on trigger (the bottom of CPWM
wave from) after Enable pin changing from “H” to “L”.
・ Brake signal is neglected for Enable being high.
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SI-6633M
５ Block diagram (Connection diagram)
Internal functional block diagram
Int. Reg 1
(Logic)
Int. Reg 2
(Analog)
VBB
OVP
CPL
STBY_IN
CPH
CP
STBY
Charge Pump
HUP
UVLO
TSD&TA
HUM
HVP
HVM
Gate
Drive
Hall Amp
&
Comm Logic
OutU
OC&NV
Detect
HWP
HWM
FLAG
Gate
Drive
Control Logic
OutV
Dir
Brake
OC&NV
Detect
Enable
FG
Gen
FG
Gate
Drive
Lock Detect
OutW
OCP
Timer
SRMD
PWM
OC&NV
Detect
PWM
&SR
Control
Logic
Decay
S
AINP
External
PWM
SEN
REF
GND
GND
CPWM
CLD
AOUT
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Internal
PWM
PWM
OSC
AINN
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SI-6633M
Pin Assignment (Terminal Functions)
№
Pin name
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
HWM
HWP
HVM
HVP
HUM
HUP
Decay
SRMD
FLAG
CLD
STBY
GND
VBB
VBB
CP
CPH
CPL
AOUT
AINN
AINP
CPWM
FG
Enable
PWM
Dir
Brake
REF
OutW
N.C.
GND
SEN
S
N.C.
OutV
N.C.
OutU
Hall input WHall input W+
Hall input VHall input V+
Hall input UHall input U+
Select for decay mode
Select for synchronous rectification
Output for protection detected
Setting for lock detection timer
Stand-by input
Ground
Motor power supply
Motor power supply
Reservoir pin for charge pump
Pumping for charge pump - High
Pumping for charge pump - Low
Amplifier output and 100% ON input
Minus pin for amplifier input
Plus pin for amplifier input
Setting pin for PWM frequency
Output for FG signal
Reset for lock counter and Enable input
External PWM control input
Direction input
Brake input
Analog input for internal PWM current control
Output for W phase
No Connection
Ground
Current sensing input
Source pin
No Connection
Output for V phase
No Connection
Output for U phase
※Two GND pins should be connected together to ground line on PCB, two VBB pins should be
connected together to VBB line.
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SI-6633M
121022
OutV
NC
S
SEN
GND
35
34
33
32
31
30
OutW
NC
36
NC
OutU
Pin Assignment Diagram
2
9
2
8
HWM
1
27
REF
HWP
2
26
20
Brake
HVM
3
25
Dir
HVP
4
24
PWM
HUM
5
23
Enable
HUP
6
22
FG
Decay
7
21
CPWM
SRMD
8
20
AINP
FLAG
9
19
AINN
12
13
14
15
16
STBY
GND
VBB
VBB
CP
CPH
1
7
1
8
AOUT
11
CPL
10
CLD
SI-6633M
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SI-6633M
６ Example application circuit(Evaluation Board Circuit)
VDD=4.5～5.5V
VBB=10～30V
C3
15
13
CPL
C1
VBB
16
VBB
17
R1
C2
CP
CPH
C4
C9
14
36
FLAG
OutU
9
D1
STBY
11
R2
34
PWM
OutV
24
R3
Brake
26
R4
28
Dir
OutW
25
R5
Decay
7
R6
HUP
8
R7
VDD
6
SRMD
23
Hall
5
SI-6633M
Enable
HUM
4
HVP
Hall
3
FG
HVM
22
2
AOUT
HWP
18
Hall
1
AINN
HWM
19
AINP
20
VAINP
32
C6
S
31
REF
SEN
27
12
30
GND
GND
CLD
21
CPWM
C5
CLD
VREF
10
Rs
CPWM
Component value for reference
C1
C2※1
C3
C4
C5
C6
： 100µF/50V
： 0.1µF/50V
： 0.1µF/16V
： 0.1µF/50V
： (option)
： (option)
R1
R2
R3
R4
R5
R6
R7
： 1kΩ
： 10kΩ
： 10kΩ
： 10kΩ
： 10kΩ
： 10kΩ
： 10kΩ
： 0.1µF
CLD※1
CPWM※1 ： 1000pF
： 0.1Ω
Rs※1※2
※1：These components should be mounted as close to the device as possible.
※2：Care should be taken with power dissipation.
☆Precaution to avoid the noise on VDD line.
Switching noise from PCB traces, where high current flows, to the VDD line should be minimized
because the noise level more than 0.5V on the VDD line may cause malfunctioning operation.
The tip for avoiding such problem is to separate the logic GND (S-GND) and the power GND (P-GND) on
a PCB, and then connect them together at IC GND pin.
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SI-6633M
７ Package information
・
7-1 Package type, physical dimensions and recommendation foot print
Recommended foot print (red line)
Dimensions in millimeters
Material of terminal: Cu
Treatment of terminal : Ni + Pd +Au (Pb Free)
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・
SI-6633M
７-２ Appearance
The body shall be clean and shall not bear any stain, rust or flaw.
・
７-３ Marking
The type number and lot number shall be clearly marked by laser so that cannot be erased easily.
・
７-4 Blanding
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SI-6633M
８ Packing specifications
８－１．Container/Material/The number of parts per reel
Container is taping. the number of parts is 2500pcs per reel.
Remainder is packed with combination with next lot.
８－２．The material of taping
Material
Emboss tape
The width of tape : 16mm
Reel
laminate bag
Inner packing figure
φ330 [mm]
Size : 0.075×380× 450 [mm]
Size : 340×360× 55 [mm]
Outer packing figure
Size : 350×370×230 [mm]
4 reels(max) per 1 outer box
８－３．Emboss tape diagram
IC mounted
Trailer
Over 50pcs of vacant pocket
Reader
Over 50pcs of vacant pocket
※It is heat-sealed with cover tape in reader and trailer.
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SI-6633M
８－４．Dimension, material and diagram
８－４－１．Emboss tape
Ao＝6.30
Bo＝6.30
Ko＝1.10
（単位 ｍｍ）
８－４－２．Reel
Tape width：16.0mmm
W1 ：17.5±1.0 mm
W2 ：21.5±1. 0mm
Detail of shaft hole
Dimension in millimeter
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SI-6633M
・８－５ Storage condition
１． Storage environment is below.
Temperature: 5 degrees-30 degrees
Humidity: 90% or below
Storage limitation is within 12month from packing date
２．If the above storage condition (8-5.1) is expired, the device is needed to have baking with 125 dgerees for 20
hours. Also, Tape and reel are not guaranteed with the temperature and time condition.
If the device should be baked, it is needed to use container with “heatproof” or temperture to cover baking
condition. And the container is needed to have static electricity control.
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SI-6633M
９ Cautions and warnings
Logic inputs/output (PWM, Dir, Decay, SRMD, FG, FL, Break, Enable, STBY)
・Be sure to prevent the logic inputs(PWM, Dir, Decay, SRMD, Break, Enable, STBY) from being "OPEN".
If some of the logic inputs are not used, be sure to connect them to VDD or GND.
※In case some of the logic inputs stay "OPEN", a malfunction may occur due to external noises.
・When the logic output(FG, FL) is not used, be sure to keep it "OPEN" or Gnd.
※In case it is connected to VDD, it may cause the device's deterioration or/and breakdown.
About the protection circuit operation
This product has Two protection circuits (motor coil short-circuit and overheating).
These protection circuits work with detecting the thing that excessive energy joins the driver.
Therefore, it is not possible to protect it when the energy caused by the motor coil short-circuit is
outside the tolerance of the driver.
Notice
This driver has MOS inputs. Please notice as following contents.
・When static electricity is a problem, care should be taken to properly control
the room humidity. This is particularly true in the winter when static
electricity is most troublesome.
・Care should be taken with device leads and with assembly sequencing to avoid
applying static charges to IC leads. PC board pins should be shorted together
to keep them at the same potential to avoid this kind of trouble.
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SI-6633M
10. other
 Application and operation examples described in this document are quoted for the sole purpose of reference for the use of the
products herein and Sanken can assume no responsibility for any infringement of industrial property rights, intellectual property
rights or any other rights of Sanken or any third party which may result from its use.
 Although Sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure and defect of
semiconductor products at a certain rate is inevitable. Users of Sanken products are requested to take, at their own risk,
preventative measures including safety design of the equipment or systems against any possible injury, death, fires or damages to
the society due to device failure or malfunction.
 Sanken products listed in this document are designed and intended for the use as components in general purpose electronic
equipment or apparatus (home appliances, office equipment, telecommunication equipment, measuring equipment, etc.). Please
return to us this document with your signature(s) or seal(s) prior to the use of the products herein.
When considering the use of Sanken products in the applications where higher reliability is required (transportation equipment
and its control systems, traffic signal control systems or equipment, fire/crime alarm systems, various safety devices, etc.), please
contact your nearest Sanken sales representative to discuss, and then return to us this document with your signature(s) or seal(s)
prior to the use of the products herein.
The use of Sanken products without the written consent of Sanken in the applications where extremely high reliability is required
(aerospace equipment, nuclear power control systems, life support systems, etc.) is strictly prohibited.
 In the case that you use our semiconductor devices or design your products by using our semiconductor devices, the reliability
largely depends on the degree of derating to be made to the rated values. Derating may be interpreted as a case that an operation
range is set by derating the load from each rated value or surge voltage or noise is considered for derating in order to assure or
improve the reliability. In general, derating factors include electric stresses such as electric voltage, electric current, electric power
etc., environmental stresses such as ambient temperature, humidity etc. and thermal stress caused due to self-heating of
semiconductor devices. For these stresses, instantaneous values, maximum values and minimum values must be taken into
consideration.
In addition, it should be noted that since power devices or IC’s including power devices have large self-heating value, the degree
of derating of junction temperature (Tj) affects the reliability significantly.

When using the products specified herein by either (i) combining other products or materials therewith or (ii) physically,
chemically or otherwise processing or treating the products, please duly consider all possible risks that may result from all such
uses in advance and proceed therewith at your own responsibility.

Anti radioactive ray design is not considered for the products listed herein.
 Sanken assumes no responsibility for any troubles, such as dropping products caused during
transportation out of Sanken’s distribution network.
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