Download the MAVRK PCB Layout Design Guide (PDF)

7/8/2011
MAVRK
PCB LAYOUT DESIGN GUIDE,
MAVRK (MCU/AFE/SCI)
Originator: Brian Shaffer
Designer: Dawn Ritz
Checker: John McDowell
Code Ident
Date: 03/16/11
Date: 03/16/11
Date: 03/16/11
Engineer: Brian Shaffer
Approved: Mike Claassen
Released: HPA MAVRK
Document number
0000001
Rev
B
Date: 03/16/11
Date: 03/16/11
Date: 03/16/11
Sheet 1 of 5
Texas Instruments
1.
PURPOSE
1.1.
2.
This document is intended to serve as a basic design guide. This is designed to help
identify design standards used on MAVRK devices.
SCOPE
2.1.
3.
MAVRK
To give the user the basic PCB Layout design guidelines for MAVRK devices.
INSTRUCTIONS
3.1.
Knowing the modular type. – use the table 4.1 to identify the correct template to use.
3.2.
Follow IPC-6012 Class II standards unless otherwise specified.
3.3.
Spacing Requirements
.004”/.004” minimum line/space, .008”/.008” preferred.
.005” annular ring required. (If a .004” annular ring is needed state that teardrops and
breakouts are allowed)
Minimum Aspect Ratio is 8:1
BGA Requirements:
1.0mm >= uses offset through hole vias where needed (allow at least a 2 mil
solder dam between via and pad)
0.8mm = may use via in pad – must be filled
0.8mm < the use of MicroVias is allowed.
3.4.
Board Stack-up
4 Layer Stack up used for all modules
Layer 1 – Analog Routing and Sensitive signals (ex. Digital CLK)
Layer 2 – GND Plane
Layer 3 – Interconnect Signal Routing
North half of board is reserved for Digital
South half of board is reserved for Analog
(Example shown in each template)
Layer 4 – Digital Routing
Material – 180Tg 370HR or Equivalent
Thickness - .062” ±5%
3.5.
Board Placement
Top (Layer 1) Side – All showcased parts, Test Points, LEDs, Jumpers, etc…
Bottom (Layer 4) Side – (overflow placement)
3.6.
Board Edge Requirements
Minimum of .015” clearance on all layers
Outer layers require a .020” GND ring of exposed metal along the board outline used
for ESD (This GND ring should not tie to any components.)
Code Ident
Document number
0000001
Sheet 2 of 5
Texas Instruments
4.
MAVRK
3.7.
All boards should be compliant to Lead Free, RoHS and REACH standards
3.8.
Revision of Projects
Proto-Types start at REV 1.0
At each review the revision will increment
REV 1.1, 1.2, 1.3, etc.
At each fabrication the revision will increment
REV 2.x, 3.x, etc…
Once we Release To Manufacture (RTM) start with
REV A, B, C, etc…
3.9.
If a part does not exist in our library provided
Create the symbol and footprint
Footprint Creation should follow IPC-782 and include
Part height
Placement boundary (.010” over actual part size)
Part Specific notes should be on Layer -Package Geometry Display_Top
Submit to MAVRK team for approval
Libraries are located:
\\PCB_LIBRARY\
NOTES
4.1.
Artwork Generation – Layers Defined as follows:
Layer 1
XXXXXXX-L1
Layer 2
XXXXXXX-L2
Layer 3
XXXXXXX-L3
Layer 4
XXXXXXX-L4
SolderMask Top
XXXXXXX-SMT
SolderMask Bottom
XXXXXXX-SMB
SolderPaste Top
XXXXXXX-SPT
SolderPaste Bottom
XXXXXXX-SPB
Silkscreen Top
XXXXXXX-SST
Silkscreen Bottom
XXXXXXX-SSB
Fabrication Drawing
XXXXXXX-FAB
Assembly Top Drawing
XXXXXXX-ASSY1
Assembly Bottom Drawing
XXXXXXX-ASSY2
"XXXXXXX" represents the EDGE number provided for each project by the MAVRK team
Code Ident
Document number
0000001
Sheet 3 of 5
Texas Instruments
4.2.
MAVRK
Generate
ODB++ and Gerber data (2.5, 274X)
XXXXXXX_PartName_SCH.pdf
XXXXXXX_PartName_FAB.pdf
XXXXXXX_PartName_ASSY1.pdf
XXXXXXX_PartName_ASSY2.pdf
XXXXXXX_PartName_TopView.pdf
XXXXXXX_PartName_BottomView.pdf
XXXXXXX_PartName_BOM.xls
XXXXXXX_PartName_GERBER.zip
TABLE 4.1 – Template Chart
Module Type
Template Name
AFE
AFE-TEMPLATE-MVK
MCU
MCU-TEMPLATE-MVK
MicroMVK -Power
U-POWER-MVK
MicroMVK -Receiver
U-RECEIVER-MVK
MicroMVK -Sensor
U-SENSOR-MVK
Motherboard
MB-PRO-MVK
PMU
PMU-TEMPLATE-MVK
RF
RF-TEMPLATE-MVK
SCI
SCI-TEMPLATE-MVK
AFE SubModule
SMA-TEMPLATE-MVK
SCI SubModule
SMS-TEMPLATE-MVK
PMU SubModule
SMP-TEMPLATE-MVK
Code Ident
Document number
0000001
Sheet 4 of 5
Texas Instruments
Revision
A
B
Code Ident
MAVRK
Description
Initial Release Brian Shaffer 3/18/11
Added RTM note for revision
Document number
0000001
Sheet 5 of 5
Similar pages