an1629

Application Note 1629
Author: Ajmal Godil
ISL9492 Quick Start Guide
1. Install the ISL9492 Evaluation Board Installer from
Intersil’s website ISL9492_eval_installer_1_0.exe. This
program allows the USB bus to talk to Intersil's I2C
evaluation board, which communicates to the ISL9492
LNB board.
2. Install the ISL9492 USB I2C Driver Installer islusbi2c_driver_installer_1_0.exe. This program provides
the GUI (graphical user interface) to control the various
commands on the ISL9492 via I2C.
3. After installing program, go to 'start' menu in Windows, 'all
programs', 'Intersil', 'ISL9492', and select 'ISL9492 Eval'.
The screen should look similar to Figure 1.
FIGURE 1. CONTROL SOFTWARE WINDOW
4. Go to Device Select and choose ISL9492 from the
dropdown menu. The screen should look like Figure 2.
FIGURE 2. LNB CONTROLLER WINDOW
March 21, 2011
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Application Note 1629
5. Apply a +12V supply to VCC and GND to the Return post on the
ISL9492QFNEVAL1 evaluation board. Connect a USB
connector and one end of the 4-wire connector to the I2C
daughter board. The other end of the 4-wire connector goes to
the ISL9492QFNEVAL1 evaluation board, jumper J1 as shown
in Figure 3.
6. Choose 'Open Device' from the GUI. The "USB Attach" and
"USB Device Handle" buttons should have turned green
indicating that the GUI is communicating with the
ISL9492QFNEVAL1 evaluation board.
FIGURE 3. ISL9492QFNEVAL1 EVALUATION BOARD CONNECTION
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Application Note 1629
FIGURE 4. ISL9492 SINGLE LNB CONTROLLER
7. The green trace in Figure 5 shows the soft-start time of VLNB
to be approximately 24ms after the EN and DLIN bits in
register 4 were toggled high. For a comprehensive description
of system registers and I2C commands, please refer to the
ISL9492 datasheet.
Figure 6 shows the 22kHz tone on VLNB output at 13.3V from
12VIN with 700mA of resistive load current after ENT and TTH
bits in register 2 are toggled high. Use of active load during this
test is not recommended due to high input capacitance, which
could potentially distort the output tone signal.
FIGURE 5. VLNB SOFT-START TIME
FIGURE 6. 22kHz VLNB OUTPUT AT 13.3V
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Application Note 1629
ISL9492 Layout Guideline
D3
SS25
R10
100
220NF/50V C18
D1
B230A
2
C9 5
1µF/25V
L4
VSWSNS
ABYP
U1
VSW
L3
1µH
CPSWOUT
28
CPVOUT
27
C4
MMZ2012S102A
VSW 26
0.047µF/50V
7
DRAIN
10µH L1
CDR7D43MN-100
P1
VCC
6
P2
RETURN
+C1
100µF/35V
VCC
DGATE
23
LDO_SGND
LDO_SGND
1µF/25V 10
C14
DBYPP
ISL9492
8,9 PGND
P9
SVTOP
R11
0
TDIN
14
VOUT
24
TCAP
ADDRO
FLT
12
R8
0
13
R9
0
Middle or bottom GND layer
Connects to top GND connection with 610 vias to form a star GND connection
D4
SS25
22
ADDR1
VOUT
C10
0.1µF/50V
C8
0.22µF/10V
R12
TDIN
100
L2
220µH
R1
15
C11
R6
3.3k
5SMC22A(TVS)
D2
OPEN
21
P5
R2 100k
R3 100k
P8
FLT
TDOUT
15
EXTM
19
P6
EXTM
TXT
SCL
18
17
P7
TXT
SDA
16
SVTOP
0.01µF/50V
C7
LNB_POWER P3
R5
100
R4
100
TD_OUT
LNB
POWER
SP1
SCOPEPROBE
C12
0.01µF/50V
11
P16
ADDR_1
D
NDS356AP
Q1
25
20
Top GND connection
ADDR_O
G
Drops into
middle or
bottom GND
plane
S
C6
1µF/25V
P15
C16 C3
0.1µF 10µF/35V
CPVOUT
C15
0.1µF/50V 100µF/
35V
1
CPSWIN
+C2
2200PF/50V
C5
NC
4
NC
3
Open C17
P10 3.3V EXTERNAL
C13
0.1µF/25V P11
GND
1
2
3
4
J1
SCL
GND
GND
SDA
I2C
FIGURE 7. ISL9492 STAR GROUND CONNECTION ILLUSTRATION
It is highly recommended to connect GND of C1, C6, C14, C2,
C15, pins 8 and 9 in a tight formation on the top layer as shown
in red circles in Figure 7 and needs to be returned back to the
input power supply GND post, which is on the bottom left of
ISL9492 board . The ground side of the components in green
circles along with the epad can be dropped to the internal ground
plane which connects to the top ground plane with 8-10 vias near
C1 to form a star ground connection.
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Application Note 1629
Evaluation Board Schematic
D3
SS25
4 NC
3 NC
7
P1
LDO_SGND
LDO_SGND
25
20
TDIN
14
PGND
ADDRO
12
R8
0
13
R9
0
ADDR1
TDOUT
24
21
15
TDIN
0.01µF/50V
C7
LNB_POWER P3
LNB
POWER
R6
SP1
D2
3.3k C12
SCOPEPROBE
P4
5SMC22A(TVS)
GND
100
L2
220µH
R1
15
C11
OPEN
P5
R2 100k
R3 100k
FLT
P8
TD_OUT
EXTM
19
P6
EXTM
TXT
SCL
18
17
P7
TXT
SDA
16
SVTOP
R5
100
R4
100
0.01µF/50V
11
ISL9492
DBYPP
VOUT
FLT
P9
NDS356AP
R12
VOUT
C10
D4
0.1µF/
SS25
50V
22
TCAP
C8 0.22µF/10V
BST_SGND
10
R11
0
P1
6
Q1
G
S
9
C14
1µF/25V
DGATE
23
VCC
C6
1µF/25V
8
SVTOP
26
C16 C3
0.1µF 10µF/35V
DRAIN
P2
ADDR_1
C4
D
6
+C1
100µF/35V
P15
ADDR_O
27
CPVOUT
10µH L1
CDR7D43MN-100
VCC
RETURN
28
CPSWOUT
VSW
VSW
L3
1µH
CPVOUT
C15
0.1µF/50V 100µF/
35V
U1
0.047µF/50V
+C2
R10
2
VSWSNS
100
C9 5
ABYP
220NF/50V C18 1µF/25V
L4
D1
B230A
MMZ2012S102A
C5
2200PF/50V
1
CPSWIN
OPEN C17
3.3V
P10
EXTERNAL
C13
0.1µF/25V P11
GND
1
2
3
4
J1
SCL
GND
GND
SDA
I2C
FIGURE 8. ISL9492QFNEVAL1 EVALUATION BOARD SCHEMATIC
Layout Guidelines
Since the ISL9492 has an integrated high power boost, careful
attention has to be paid to the layout which are outlined as
follows for a 4-layer and a 2-layer board:
1. Boost input capacitor (C1, C6), output boost capacitors (C2,
C15), inductor (L1), Schottky diode D1 should be placed
together in a nice tight layout. The ground connection of C1,
C2, C15, C6, ISL9492 pins 8, 9 and C14 should go directly to
the GND input supply as shown in Figure 9.
5. The bottom layer is used to connect output power post to D3,
which connects back to C2 (see Figure 12).
6. C1, C2, C15, C6 and pins 8 and 9 are in a tight configuration
with GNDs connected to input power post GND. All other
components going to GND are dropped directly to the second
GND plane. The second layer is connected to the top GND
layer right next to C1 ground connection as shown in
Figures 13 and 14.
2. C3, C16 and C10 ground connection is returned directly to
pin 25, LDO-SGND (see Figure 9). Ground connection of L4,
C18, C8, C4, and pin 20, are dropped directly to an internal
ground island (see Figure 10). This layer is connected to the
ground plane at C1 ground connection.
3. D4 is connected directly across pins 23 and 25. D2 and VLNB
return post are returned back to the internal ground island as
described in point 2.
4. ISL9492's EPAD is connected to an internal ground plane.
This ground plane is connected to the top layer with multiple
vias right under C1 and C2 ground connection (see Figure 11).
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Application Note 1629
4 and 2 Layer Demo Board Layout Examples
FIGURE 9. 4 LAYER - TOP
C18
L4
C8
FIGURE 10. 4 LAYER - INNER GROUND
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Application Note 1629
4 and 2 Layer Demo Board Layout Examples (Continued)
EPAD
FIGURE 11. 4 LAYER - INTERNAL LAYER 3 SHOWING EPAD CONNECTION
FIGURE 12. LAYER 4
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Application Note 1629
4 and 2 Layer Demo Board Layout Examples (Continued)
FIGURE 13. 2 LAYER - TOP
FIGURE 14. 2 LAYER - BOTTOM
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Application Note 1629
ISL9492QFNEVAL1 Bill of Materials
PART TYPE
DESIGNATOR
FOOTPRINT
0.01µF/50V
C12
603
0.01µF/50V
C7
603
0.047µF/50V
C4
805
0.1µF/25V
C13
603
0.1µF/25V
C16
603
0.1µF/50V
C10
603
0.1µF/50V
C15
603
0.22µF/10V
C8
603
100µF/35V
C2
11.5x8 Aluminum
100µF/35V
C1
11.5x8 Aluminum
10µF/35V
C3
1210
10µH
L1
CDR7D43
1µF/25V
C14
805
1µF/25V
C6
805
1µF/25V
C9
805
1µH
L3
1008PS
2200PF/50V
C5
603
220NF/50V
C18
805
220µH
L2
DS3316
5SMC22A(TVS)
D2
DO-403A
B230A
D1
DO-214
LNB
P3
POWERPOST
MMZ1608S102AT
L4
603
NDS356AP
Q1
SOT-23
Open
C11
603
Open
C17
805
SS25
D3
DO-214
SS25
D4
DO-214
0
R11
603
0
R8
603
0
R9
603
15
R1
603
100
R10
603
100
R12
603
100
R4
603
100
R5
603
100k
R2
603
100k
R3
603
3.3k
R6
1210
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
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