an1903

Application Note 1903
Author: Sameer Dash
ISL91108IIA-EVZ/ISL91108IIN-EVZ Evaluation Board
User Guide
Evaluation Board Features
TABLE 3. DESCRIPTION OF JUMPERS
JUMPER
DESCRIPTION
• Input voltage rating from 1.8V to 5.5V
J3
• Resistor programmable output voltage on the
ISL91108IIA-EVZ evaluation board
Jumper to select EN input logic state. Set EN = VIN to
enable device, or set EN = GND to disable device.
J4
Jumper to select MODE input logic state. Set
MODE = VIN to enable auto-PFM mode, or set
MODE = GND to select forced PWM mode.
• ISL91108 high efficiency buck-boost regulator
• Fixed 3.3V output voltage on the ISL91108IIN-EVZ
evaluation board
To use external sync feature, remove this jumper and
apply an external clock between 2.75MHz and
3.25MHz on the center pin on the J4 header.
• Up to 1.5A output current (PVIN = 3.0V, VOUT = 3.3V)
• 2.5MHz switching frequency
• Jumper selectable EN (enabled/disabled)
Quick Setup Guide
• Jumper selectable MODE (auto-PFM/forced-PWM)
• Connectors, testpoints, and jumpers for easy evaluation
1. Install jumper on J3, shorting EN to VIN.
2. Install jumper on J4, shorting MODE to VIN.
Required Equipment
• Power supply capable of delivering up to 5.5V and 4A
3. Connect power supply to J1, with voltage setting between
1.8V and 5.5V.
• Electronic load
4. Connect electronic load to J2.
• Multimeter to measure voltages and currents
5. Place scope probes on VOUT testpoint, and other testpoints
of interest.
• Oscilloscope
6. Turn on the power supply.
Testpoints, Connectors, and
Jumpers
7. Monitor the output voltage startup sequence on the
scope. The waveforms will look similar to that shown in
Figures 1 and 2.
8. Turn on the electronic load.
TABLE 1. DESCRIPTION OF TEST POINTS
TEST POINT(S)
9. Measure the output voltage with the voltmeter. The voltage
should regulate within data sheet spec limits.
DESCRIPTION
TP1
LX1 (Input side of power inductor)
TP2
LX2 (Output side of power inductor)
TP3
VOUT
10. To determine efficiency, measure input and output voltages
at the Kelvin sense testpoints (S+ and S-) which are part of
J1 and J2 headers. The bench power supply can be
connected to the PVIN and GND headers on J1. The
electronic load can be connected to the VOUT and GND
headers on J2. Measure the input and output currents.
Calculate efficiency based on these measurements.
TABLE 2. DESCRIPTION OF CONNECTORS
CONNECTOR
DESCRIPTION
J1
Header for connecting input power. Includes S+ and Ssense lines.
J2
Header for connecting external load. Includes S+ and
S- sense lines.
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11. To test external sync, remove the jumper at J4, then apply
an external clock between 2.75MHz and 3.25MHz on the
MODE input (the center pin of header J4).
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Application Note 1903
Typical Start-up Waveforms
Output Voltage Programming
The ISL91108IIA-EVZ evaluation board uses resistors to program
the output voltage. To change the output voltage, resistor R1
should be removed and replaced with a resistor value
corresponding to the desired output voltage, as shown in Table 4.
A precision resistor with 1% tolerance should be used.
LX1
2V/DIV
LX2
2V/DIV
TABLE 4. OUTPUT VOLTAGE PROGRAMMING
VOUT
2V/DIV
EN
2V/DIV
400µs/DIV
VIN = 2V
VOUT = 3.3V
IOUT = 200mA
FIGURE 1. ISL91108 START-UP WITH VIN = 2V and VOUT = 3.3V
DESIRED OUTPUT VOLTAGE
(V)
R1 RESISTOR VALUE
(kΩ)
2.0
90.9
2.5
127
3.0
165
3.3
187
3.6
210
4.0
243
4.5
280
5.0
316
LX1
2V/DIV
LX2
2V/DIV
VOUT
2V/DIV
EN
2V/DIV
400µs/DIV
VIN = 4V
VOUT = 3.3V
IOUT = 200mA
FIGURE 2. ISL91108 START-UP WITH VIN = 4V and VOUT = 3.3V
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Application Note 1903
ISL91108IIA-EVZ Evaluation Board Schematic
FIGURE 3. ISL91108IIA-EVZ EVALUATION BOARD SCHEMATIC
TABLE 5. ISL91108IIA-EVZ EVALUATION BOARD BILL OF MATERIALS
ITEM#
QTY
DESIGNATORS
PART TYPE
FOOTPRINT
1
1
U1
ISL91108IIAZ
W4x5.20
WLCSP
2
1
L1
1µH
3
1
C1
330µF
7343
Capacitor, Tantalum
4
2
C2, C3
10µF/16V/X5R
0603
Capacitor, Ceramic, GRM188R61C106MA73D
Murata
5
2
C4, C5
22µF/10V/X5R
0603
Capacitor, Ceramic, GRM188R61A226M
Murata
6
1
C6
22pF/50V/NP0
0402
Capacitor, Generic
ANY
7
1
C7
0.1µF
0402
Capacitor, Generic
ANY
8
1
R1
187kΩ, 1%
0402
Resistor, Generic
ANY
9
1
R2
60.4kΩ, 1%
0402
Resistor, Generic
ANY
10
2
R3, R4
1MΩ, 5%
0603
Resistor, Generic
ANY
11
2
J1, J2
HDR-6
HDR-6
Vert. Pin Header, 6-Pin, 0.1” Spacing, Generic
ANY
12
2
J3, J4
HDR-3
HDR-3
Vert. Pin Header, 3-Pin, 0.1” Spacing, Generic
ANY
13
3
TP1, TP2, TP3
SCOPEPROBE
SCOPEPROBE
3
DESCRIPTION
Intersil ISL91108 Buck-Boost Regulator with
Adjustable Output Voltage
3.2mmx2.5mm Power Inductor DFE322512C, 4.6A, 34mΩ
Test Point, Scope Probe 131-5031-00
VENDORS
INTERSIL
TOKO
ANY
TEKTRONIX
AN1903.1
March 11, 2014
Application Note 1903
ISL91108IIN-EVZ Evaluation Board Schematic
FIGURE 4. ISL91108IIN-EVZ EVALUATION BOARD SCHEMATIC
TABLE 6. ISL91108IIN-EVZ EVALUATION BOARD BILL OF MATERIALS
ITEM#
QTY
DESIGNATORS
PART TYPE
FOOTPRINT
1
1
U1
ISL91108IINZ
W4x5.20
WLCSP
2
1
L1
1µH
3
1
C1
330µF
7343
Capacitor, Tantalum
4
2
C2, C3
10µF/16V/X5R
0603
Capacitor, Ceramic, GRM188R61C106MA73D
Murata
5
2
C4, C5
22µF/10V/X5R
0603
Capacitor, Ceramic, GRM188R61A226M
Murata
6
1
C6
DNP
0402
7
1
C7
0.1µF
0402
Capacitor, Generic
ANY
8
1
R1
0Ω
0402
Resistor, Generic
ANY
9
1
R2
DNP
0402
10
2
R3, R4
1MΩ, 5%
0603
Resistor, Generic
ANY
11
2
J1, J2
HDR-6
HDR-6
Vert. Pin Header, 6-Pin, 0.1” Spacing, Generic
ANY
12
2
J3, J4
HDR-3
HDR-3
Vert. Pin Header, 3-Pin, 0.1” Spacing, Generic
ANY
13
3
TP1, TP2, TP3
SCOPEPROBE
SCOPEPROBE
4
DESCRIPTION
Intersil ISL91108 Buck-Boost Regulator with
Fixed 3.3V Output Voltage
3.2mmx2.5mm Power Inductor DFE322512C, 4.6A, 34mΩ
VENDORS
INTERSIL
TOKO
ANY
ANY
ANY
Test Point, Scope Probe 131-5031-00
TEKTRONIX
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Application Note 1903
ISL91108 Evaluation Board Layout
FIGURE 5. ISL91108 EVALUATION BOARD LAYOUT
FIGURE 6. TOP LAYER
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Application Note 1903
ISL91108 Evaluation Board Layout (Continued)
FIGURE 7. MID LAYER
FIGURE 8. MID LAYER 2
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Application Note 1903
ISL91108 Evaluation Board Layout (Continued)
FIGURE 9. BOTTOM LAYER
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
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