DATASHEET

HIP2101
Data Sheet
November 12, 2015
100V/2A Peak, Low Cost, High Frequency
Half Bridge Driver
The HIP2101 is a high frequency, 100V Half Bridge
N-Channel power MOSFET driver IC. It is equivalent to the
HIP2100 with the added advantage of full TTL/CMOS
compatible logic input pins. The low-side and high-side gate
drivers are independently controlled and matched to 13ns.
This gives users total control over dead-time for specific
power circuit topologies. Undervoltage protection on both the
low-side and high-side supplies force the outputs low. An onchip diode eliminates the discrete diode required with other
driver ICs. A new level-shifter topology yields the low-power
benefits of pulsed operation with the safety of DC operation.
Unlike some competitors, the high-side output returns to its
correct state after a momentary undervoltage of the highside supply.
PART NUMBER
PACKAGE
8 Ld SOIC
PKG.
DWG. #
HIP2101IB (No
longer available,
recommended
replacement:
HIP2101IBZ)
-40 to 125
HIP2101IBZ (Note 1)
-40 to 125
8 Ld SOIC (Pb-free) M8.15
HIP2101EIB (No
longer available,
recommended
replacement:
HIP2101EIBZ)
-40 to 125
8 Ld EPSOIC
M8.15C
HIP2101EIBZ
(Note 1)
-40 to 125
8 Ld EPSOIC
(Pb-free)
M8.15C
HIP2101IRZ (Note 1)
-40 to 125
16 Ld 5x5 QFN
(Pb-free)
L16.5x5
12 Ld 4x4 DFN
(Pb-free)
L12.4x4A
HIP2101IR4Z
(Note 1)
Features
• Drives N-Channel MOSFET Half Bridge
• SOIC, EPSOIC, QFN and DFN Package Options
• SOIC, EPSOIC and DFN Packages Compliant with 100V
Conductor Spacing Guidelines of IPC-2221
• Pb-free Product Available (RoHS Compliant)
• Bootstrap Supply Max Voltage to 114VDC
• On-Chip 1 Bootstrap Diode
• Fast Propagation Times for Multi-MHz Circuits
• Drives 1000pF Load with Rise and Fall Times Typ. 10ns
• TTL/CMOS Input Thresholds Increase Flexibility
• Independent Inputs for Non-Half Bridge Topologies
• No Start-Up Problems
Ordering Information
TEMP.
RANGE (°C)
FN9025.9
M8.15
• Outputs Unaffected by Supply Glitches, HS Ringing Below
Ground, or HS Slewing at High dv/dt
• Low Power Consumption
• Wide Supply Range
• Supply Undervoltage Protection
• 3 Output Driver Resistance
-40 to 125
• QFN/DFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Applications
• Telecom Half Bridge Power Supplies
• Avionics DC-DC Converters
• Two-Switch Forward Converters
• Active Clamp Forward Converters
NOTES:
1. Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020C.
2. Add “T” suffix for Tape and Reel packing option.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas LLC
Copyright © Intersil Americas LLC 2004, 2015. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
HIP2101
Pinouts
3
6
LI
HS
4
5
HI
1
12 LO
NC
2
11 VSS
NC
3
10 NC
HB
4
HO
HS
EPAD
NC
HO
VDD
16
15
14
13
NC 1
12 NC
HB 2
NC
5
8
LI
HO 3
10 LI
6
7
HI
NC 4
9
EPAD
5
6
7
8
NOTE: EPAD = Exposed PAD.
Application Block Diagram
+12V
+100V
SECONDARY
CIRCUIT
VDD
HB
DRIVE
HI
LI
CONTROL
HI
PWM
CONTROLLER
HO
HS
DRIVE
LO
HIP2101
VSS
2
11 VSS
9
NC
VSS
EPAD
LO
7
HI
LO
2
VDD
8
HB
HS
1
HIP2101 (QFN)
TOP VIEW
NC
VDD
HIP2101IR4 (DFN)
TOP VIEW
NC
HIP2101 (SOIC, EPSOIC)
TOP VIEW
LO
REFERENCE
AND
ISOLATION
NC
HIP2101
Functional Block Diagram
HB
VDD
UNDER
VOLTAGE
HO
LEVEL SHIFT
DRIVER
HS
HI
UNDER
VOLTAGE
LO
DRIVER
LI
VSS
EPAD (EPSOIC, QFN and DFN PACKAGES ONLY)
*EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For
best thermal performance connect the EPAD to the PCB power ground plane.
+48V
+12V
PWM
SECONDARY
CIRCUIT
HIP
2101
ISOLATION
FIGURE 1. TWO-SWITCH FORWARD CONVERTER
+48V
SECONDARY
CIRCUIT
+12V
PWM
HIP
2101
ISOLATION
FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE CLAMP
3
HIP2101
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD, VHB-VHS (Notes 3, 4) . . . . . . . . -0.3V to 18V
LI and HI Voltages (Note 4) . . . . . . . . . . . . . . . . . . . . . -0.3V to 7.0V
Voltage on LO (Note 4) . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Voltage on HO (Note 4) . . . . . . . . . . . . . . . VHS -0.3V to VHB +0.3V
Voltage on HS (Continuous) (Note 4) . . . . . . . . . . . . . . -1V to 110V
Voltage on HB (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +118V
Average Current in VDD to HB diode . . . . . . . . . . . . . . . . . . . 100mA
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 (1kV)
Thermal Resistance (Typical)
Maximum Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . +9V to 14.0VDC
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
Voltage on HB . . VHS +8V to VHS +14.0V and VDD -1V to VDD +100V
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
JA (°C/W)
JC (°C/W)
SOIC (Note 5) . . . . . . . . . . . . . . . . . . .
95
N/A
EPSOIC (Note 6) . . . . . . . . . . . . . . . . .
40
3.0
QFN (Note 6) . . . . . . . . . . . . . . . . . . . .
37
6.5
DFN (Note 6) . . . . . . . . . . . . . . . . . . . .
40
3.0
Max Power Dissipation at 25oC in Free Air (SOIC, Note 5) . . . . 1.3W
Max Power Dissipation at 25oC in Free Air (EPSOIC, Note 6). . 3.1W
Max Power Dissipation at 25oC in Free Air (QFN, Note 6). . . . . 3.3W
Storage Temperature Range . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . -55°C to 150°C
Lead Temperature (Soldering 10s - SOIC Lead Tips Only) . . 300°C
For Recommended soldering conditions see Tech Brief TB389.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied.
NOTES:
3. The HIP2101 is capable of derated operation at supply voltages exceeding 14V. Figure 16 shows the high-side voltage derating curve for this
mode of operation.
4. All voltages referenced to VSS unless otherwise specified.
5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. JC, the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified
TJ = -40°C TO
125°C
TJ = 25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
SUPPLY CURRENTS
VDD Quiescent Current
IDD
LI = HI = 0V
-
0.3
0.45
-
0.6
mA
VDD Operating Current
IDDO
f = 500kHz
-
1.7
3.0
-
3.4
mA
Total HB Quiescent Current
IHB
LI = HI = 0V
-
0.1
0.15
-
0.2
mA
Total HB Operating Current
IHBO
f = 500kHz
-
1.5
2.5
-
3
mA
HB to VSS Current, Quiescent
IHBS
VHS = VHB = 114V
-
0.05
1.5
-
10
A
HB to VSS Current, Operating
IHBSO
f = 500kHz
-
0.7
-
-
-
mA
INPUT PINS
Low Level Input Voltage Threshold
VIL
0.8
1.65
-
0.8
-
V
High Level Input Voltage Threshold
VIH
-
1.65
2.2
-
2.2
V
RI
-
200
-
100
500
k
VDD Rising Threshold
VDDR
7
7.3
7.8
6.5
8
V
VDD Threshold Hysteresis
VDDH
-
0.5
-
-
-
V
HB Rising Threshold
VHBR
6.5
6.9
7.5
6
8
V
HB Threshold Hysteresis
VHBH
-
0.4
-
-
-
V
Input Pulldown Resistance
UNDER VOLTAGE PROTECTION
4
HIP2101
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified (Continued)
TJ = -40°C TO
125°C
TJ = 25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
BOOT STRAP DIODE
Low-Current Forward Voltage
VDL
IVDD-HB = 100A
-
0.45
0.70
-
0.7
V
High-Current Forward Voltage
VDH
IVDD-HB = 100mA
-
0.7
0.92
-
1
V
Dynamic Resistance
RD
IVDD-HB = 100mA
-
0.8
1
-
1.5

LO GATE DRIVER
Low Level Output Voltage
VOLL
ILO = 100mA
-
0.25
0.3
-
0.4
V
High Level Output Voltage
VOHL
ILO = -100mA, VOHL = VDD-VLO
-
0.25
0.3
-
0.4
V
Peak Pullup Current
IOHL
VLO = 0V
-
2
-
-
-
A
Peak Pulldown Current
IOLL
VLO = 12V
-
2
-
-
-
A
Low Level Output Voltage
VOLH
IHO = 100mA
-
0.25
0.3
-
0.4
V
High Level Output Voltage
VOHH
IHO = -100mA, VOHH = VHB-VHO
-
0.25
0.3
-
0.4
V
Peak Pullup Current
IOHH
VHO = 0V
-
2
-
-
-
A
Peak Pulldown Current
IOLH
VHO = 12V
-
2
-
-
-
A
HO GATE DRIVER
Switching Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified
PARAMETERS
SYMBOL
TEST
CONDITIONS
TJ = -40°C
TO 125°C
TJ = 25°C
MIN
TYP
MAX
MIN
MAX
UNITS
Lower Turn-Off Propagation Delay (LI Falling to LO Falling)
tLPHL
-
25
43
-
56
ns
Upper Turn-Off Propagation Delay (HI Falling to HO Falling)
tHPHL
-
25
43
-
56
ns
Lower Turn-On Propagation Delay (LI Rising to LO Rising)
tLPLH
-
25
43
-
56
ns
Upper Turn-On Propagation Delay (HI Rising to HO Rising)
tHPLH
-
25
43
-
56
ns
Delay Matching: Lower Turn-On and Upper Turn-Off
tMON
-
2
13
-
16
ns
Delay Matching: Lower Turn-Off and Upper Turn-On
tMOFF
-
2
13
-
16
ns
Either Output Rise/Fall Time
tRC,tFC
CL = 1000pF
-
10
-
-
-
ns
Either Output Rise/Fall Time (3V to 9V)
tR,tF
CL = 0.1F
-
0.5
0.6
-
0.8
us
Either Output Rise Time Driving DMOS
tRD
CL = IRFR120
-
20
-
-
-
ns
Either Output Fall Time Driving DMOS
tFD
CL = IRFR120
-
10
-
-
-
ns
Minimum Input Pulse Width that Changes the Output
tPW
-
-
-
-
50
ns
Bootstrap Diode Turn-On or Turn-Off Time
tBS
-
10
-
-
-
ns
5
HIP2101
Pin Descriptions
SYMBOL
DESCRIPTION
VDD
Positive Supply to lower gate drivers. De-couple this pin to VSS. Bootstrap diode connected to HB.
HB
High-Side Bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin.
Bootstrap diode is on-chip.
HO
High-Side Output. Connect to gate of High-Side power MOSFET.
HS
High-Side Source connection. Connect to source of High-Side power MOSFET. Connect negative side of bootstrap capacitor to
this pin.
HI
High-Side input.
LI
Low-Side input.
VSS
Chip negative supply, generally will be ground.
LO
Low-Side Output. Connect to gate of Low-Side power MOSFET.
EPAD
Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
Timing Diagrams
LI
HI
HI,
LI
tHPLH ,
tLPLH
tHPHL,
tLPHL
LO
tMOFF
tMON
HO,
LO
HO
FIGURE 3.
FIGURE 4.
Typical Performance Curves
3.500
4.000
3.500
2.500
2.000
1.500
-40°C
1.000
25°C
2.000
1.500
-40°C
1.000
0.500
0.500
0.000
150°C, 125°C
2.500
IHBO (mA)
IDDO (mA)
3.000
150°C
125°C
25°C
3.000
0.000
10
30
50
90 200 400
70
FREQUENCY (kHz)
600
800
1000
10
30
50
90
200
FIGURE 5. OPERATING CURRENT vs FREQUENCY
400
FREQUENCY (kHz)
FIGURE 5B.
FIGURE 5A.
6
70
600
800
1000
HIP2101
Typical Performance Curves
(Continued)
500
10
VHB = VDD = 9V
VOHL, VOHH (mV)
400
T = 150°C
T = -40°C
T = 125°C
T = 25°C
IHBSO (mA)
1
0.1
VHB = VDD = 12V
VHB = VDD = 14V
300
200
0.01
10
100
FREQUENCY (kHz)
100
-50
1000
100
150
FIGURE 7. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE
7.6
500
VHB = VDD = 9V
7.4
VHB = VDD = 12V
400
VHBR, VDDR (V)
VHB = VDD = 14V
300
200
VDDR
7.2
7.0
VHBR
6.8
100
-50
0
50
100
6.6
-50
150
0
TEMPERATURE (°C)
100
150
30
tLPLH, tLPHL, tHPLH, tHPHL (ns)
0.54
0.5
VDDH
0.46
0.42
0.38
VHBH
0.34
0.3
-50
50
TEMPERATURE (°C)
FIGURE 9. UNDERVOLTAGE LOCKOUT THRESHOLD vs
TEMPERATURE
FIGURE 8. LOW LEVEL OUTPUT VOLTAGE vs
TEMPERATURE
VHBH, VDDH (mV)
50
TEMPERATURE (°C)
FIGURE 6. HB TO VSS OPERATING CURRENT vs
FREQUENCY
VOLL, VOLH (mV)
0
0
50
TEMPERATURE (°C)
100
FIGURE 10. UNDERVOLTAGE LOCKOUT HYSTERESIS vs
TEMPERATURE
7
150
tHPHL
tHPLH
tLPHL
25
tLPLH
20
15
-50
0
50
TEMPERATURE (°C)
100
150
FIGURE 11. PROPAGATION DELAYS vs TEMPERATURE
HIP2101
(Continued)
2.5
2.5
2.0
2.0
1.5
1.5
ILO, IHO (A)
IHO , ILO (A)
Typical Performance Curves
1.0
0.5
0
0.5
0
2
4
6
VHO , VLO (V)
8
10
0
12
FIGURE 12. PEAK PULLUP CURRENT vs OUTPUT VOLTAGE
0
2
4
6
VLO, VHO (V)
8
10
FIGURE 13. PEAK PULLDOWN CURRENT vs OUTPUT
VOLTAGE
1
60
0.1
50
0.01
40
IHB vs VHB
IDD , IHB (A)
FORWARD CURRENT (A)
1.0
0.001
110-4
20
10
110-5
110-6
0.3
IDD vs VDD
30
0
0.4
0.5
0.6
0.7
0.8
0
FORWARD VOLTAGE (V)
FIGURE 14. BOOTSTRAP DIODE I-V CHARACTERISTICS
5
10
VDD , VHB (V)
FIGURE 15. QUIESCENT CURRENT vs VOLTAGE
120
VHS TO VSS VOLTAGE (V)
100
80
60
40
20
0
12
14
15
VDD TO VSS VOLTAGE (V)
FIGURE 16. VHS VOLTAGE vs VDD VOLTAGE
8
15
16
12
HIP2101
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
CHANGE
November 12, 2015
FN9025.9
- Updated Ordering Information Table on page 1.
- Added Revision History.
- Added About Intersil Verbiage.
- Updated POD L12.4X4A to latest revision changes are as follow:
Updated to new POD format by removing table listing dimensions and moving dimensions onto
drawing.
Added Typical Recommended Land Pattern.
Bottom View changed "3.2 REF" TO "2.5 REF"
Typical Recommended Land Pattern changed "3.80" to "3.75"
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or
ends).
- Updated POD M8.15 to latest revision changes are as follow:
Updated to new POD format by removing table and moving dimensions onto drawing and adding land
pattern.
Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
Changed Note 1 "1982" to "1994"
- Updated POD M8.15C to most current version.
Removed "u" symbol from drawing (overlaps the "a" on Side View).
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
9
HIP2101
Package Outline Drawing
L12.4x4A
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 3/15
2.5 REF
4.00
A
PIN #1 INDEX AREA
10X 0.50 BSC
6
B
6
1
12X 0 . 45
6
PIN 1
INDEX AREA
4.00
1.58
0.15
(4X)
12
7
TOP VIEW
0.10 M C A B
0.05 M C
4 12 X 0.25
2.80
BOTTOM VIEW
( 2.80 )
SEE DETAIL "X"
1.00 MAX
( 12 X 0.65 )
0.10 C
BASE PLANE C
SIDE VIEW
( 3.75)
SEATING PLANE
0.08 C
( 1.58)
0 . 2 REF
C
( 10X 0 . 5 )
0 . 00 MIN.
0 . 05 MAX.
( 12X 0 . 25)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Lead width applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
6.
Tiebar shown (if present) is a non-functional feature and may
be located on any of the 4 sides (or ends).
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
10
HIP2101
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.5x5
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHB ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
9
A3
b
0.20 REF
0.28
D
0.40
5, 8
5.00 BSC
D1
D2
0.33
9
-
4.75 BSC
2.55
2.70
9
2.85
7, 8
E
5.00 BSC
-
E1
4.75 BSC
9
E2
2.55
e
2.70
2.85
7, 8
0.80 BSC
-
k
0.25
-
-
-
L
0.35
0.60
0.75
8
L1
-
-
0.15
10
N
16
Nd
2
4
3
Ne
4
4
3
P
-
-
0.60
9

-
-
12
9
Rev. 2 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P &  are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
11
HIP2101
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
12
HIP2101
Small Outline Exposed Pad Plastic Packages (EPSOIC)
M8.15C
N
INDEX
AREA
H
0.25(0.010) M
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE
B M
E
INCHES
-B-
1
2
SYMBOL
3
TOP VIEW
L
SEATING PLANE
-A-
A
D
-C-

e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
B S
SIDE VIEW
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.056
0.066
1.43
1.68
-
A1
0.001
0.005
0.03
0.13
-
B
0.0138
0.0192
0.35
0.49
9
C
0.0075
0.0098
0.19
0.25
-
D
0.189
0.196
4.80
4.98
3
E
0.150
0.157
3.811
3.99
4
e
h x 45°
MIN
0.050 BSC
1.27 BSC
-
H
0.230
0.244
5.84
6.20
-
h
0.010
0.016
0.25
0.41
5
L
0.016
0.035
0.41
0.89
6
8°
0°
N

8
0°
8
7
8°
-
P
-
0.126
-
3.200
11
P1
-
0.099
-
2.514
11
Rev. 1 6/05
NOTES:
1
2
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
3
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
P1
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
N
P
BOTTOM VIEW
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
Similar pages