DATASHEET

HIP0050
TM
0.3A/50V Octal Low Side Power Driver with
Serial Bus Control and Over-Current Fault Flag
December 1996
Features
Description
• Octal NDMOS Output Drivers in a High Voltage
Power BiMOS Process
- Each Capable of Sinking 300mA
- Low Idle and Standby Current
The HIP0050 is a logic controlled, eight channel Octal Low Side
Power Driver. As shown in the block diagram, the outputs are controlled via the serial data interface which allows the data to be
shifted out, allowing control of other cascaded serial devices. If an
Over-Current (OC) short circuit exists in one output, it may be independently shutdown while the other outputs remain in operation.
When a shorted output is latched off, it may be turned back on
when the next serial input data is latched. A fault flag (FLT) is set
to a low status to indicate current-limited shutdown. The outputs
are independently latched off when an OC fault is detected. The
fault latch is cleared on the next data strobe. Over-Temperature
(OT) shutdown is provided with hysteresis to force global shutdown of all output drivers. Shutdown is maintained until the on-chip
temperature falls below the minimum hysteresis threshold point.
• Over-Stress Protection - Each Output:
- Over-Current Latch Off . . . . . . . . . 300mA Min
- Over-Voltage Clamp . . . . . . . . . . . . . . . 50V Typ
• Thermal Shutdown with Hysteresis
• Serial Data Input, Parallel Output Power Drive
• Short Circuit Latch Off for Each Output
• Common Enable for Output Drivers and
Data Storage Register
• Ambient Operating
Temperature Range. . . . . . . . . . . . .-40 oC to 85oC
- Optional 125oC Maximum Ambient Operating
Temperature Range (Dissipation Limited)
Applications
• Automotive and Industrial Systems
• Solenoids, Relays and Lamp Drivers
• Logic and µP Controlled Drivers
• Robotic Controls
The HIP0050 is fabricated in a Power BiMOS IC process, and is
intended for use in automotive and other applications having a
wide range of temperature and electrical stress conditions. It is
particularly suited for driving lamps, displays, relays, and solenoids in
applications where low operating power, high breakdown voltage,
and high output current at high temperature is required. Higher
current needs can be met by paralleling adjacent output drivers.
Ordering Information
PART
NUMBER
TEMP.
RANGE ( oC)
PACKAGE
PKG. NO.
HIP050IP
-40 to 85
20 Ld PDIP
E20.3
HIP0050IB
-40 to 85
24 Ld SOIC
M24.3
Pinouts
HIP0050
(SOIC)
TOP VIEW
HIP0050
(PDIP)
TOP VIEW
DR2
1
DR3
2
19 DR0
FLT
3
18 SI
EN
4
17 VCC
GND
5
16 GND
GND
6
15 GND
STR
7
14 LGND
SCK
8
13 SO
DR4
9
12 DR7
DR5 10
11 DR6
20 DR1
DR2 1
24 DR1
DR3 2
23 DR0
FLT
3
EN 4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
22 SI
21 VCC
GND
5
20 GND
GND
6
19 GND
GND
7
18 GND
GND
8
17 GND
STR
9
16 LGND
SCK 10
15 SO
DR4 11
14 DR7
DR5 12
13 DR6
FN4034.1
HIP0050
Block Diagram
OUTPUT DRIVER
(CHANNEL 1 OF 8)
(ENABLE)
EN
DR#0
(STROBE)
STR
Q0
SI
LATCH
SERIAL
(SPI)
Q1
INPUT
REGISTER
(DATA IS
PARALLEL
OUTPUT
LATCHED
WHEN
SCK
OUTPUT
OC
Q2
SHUT-
POR
Q3
DOWN
Q4
Q5
Q6
STROBED)
SO
Q7
OVER-TEMPERATURE
SHUTDOWN W/HYS
FLT
S
R
FAULT
LATCH
Output Control Logic Table
STROBE
8-BIT SERIAL DATA (LATCHED)
OUTPUT
D1
D2
D3
D4
D5
D6
D7
D8
DR1
DR2
DR3
DR4
DR5
DR6
DR7
DR8
0
0
0
0
0
0
0
0
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
1
0
0
0
0
0
0
0
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
1
1
0
0
0
0
0
0
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
1
1
1
0
0
0
0
0
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
1
1
1
1
0
0
0
0
ON
ON
ON
ON
OFF
OFF
OFF
OFF
0
0
0
0
1
1
1
1
OFF
OFF
OFF
OFF
ON
ON
ON
ON
1
1
1
1
1
1
1
1
ON
ON
ON
ON
ON
ON
ON
ON
2
HIP0050
Absolute Maximum Ratings
Thermal Information
Output Voltage, VOUT (Note 1) . . . . . . . . . . . . . . . . . . . -0.3V to VOC
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
Logic Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Max Output Load Current, ILOAD (Per Output, Note 2). . . . . . . . . ICL
Max. Output Load Current, ILOAD (All Outputs ON, Note 2) . . . . . 2A
Operating Ambient Temperature Range, TA . . . . . . . . -40oC to 85oC
Operating Junction Temperature Range. . . . . . . . . . -40oC to 150oC
Storage Temperature Range, TSTG . . . . . . . . . . . . . -55oC to 150oC
Maximum Lead Temperature (Soldering 10s Max). . . . . . . . . 300oC
(Lead Tips Only)
θJC (oC/W)†
Package
θJA (oC/W) ††
0
2
PDIP . . . . . . . . . . . . .
10
50
35
SOIC . . . . . . . . . . . . .
10
60
40
† Versus Additional Square Inches 1oz. copper on PCB.
†† Standard Test Board, 0.002 diameter T/C located at lead
shoulder, middle lead.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Power Output Driver Voltage Range . . . . . . . . . . . . . . . . . 0 to VOC
Power Output Driver Current Load, IDR . . . . . . . . . . . . . . . 0 to ICL
Typical Output rDSON Channel Resistance . . . . . . . . . . . . . . . . 2Ω
Typical Output Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4µs
Typical Output Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µs
Typical Logic Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . +5V
ICC Supply Current, with 200mA each Output . . . . . . . . . . . . 2mA
ICC Supply Current, with No Load . . . . . . . . . . . . . . . . . . . . . 2mA
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5V
Electrical Specifications
PARAMETER
VCC = 4.5V to 5.5V, VBATT = 8V to 16V, TA = -40oC to 85oC; Unless Otherwise Specified
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
-
2
4.0
Ω
300
-
500
mA
42
50
58
V
-
25
-
mJ
OUTPUTS DRIVERS (DR0 TO DR7)
Output Channel Resistance
rDSON
Output Current = 200mA, TA = 85oC
Output Over-Current Shutdown
Threshold
ICL
Output Clamping Voltage
VOC
Outputs OFF
EOC
1ms Single Pulse Width, TA = 25oC,
(Refer to Figure 2 for SOA).
Output OFF Leakage Current
IOFF
Output Voltage = 40V, TA = 85oC
-
-
10
µA
Output Rise Time
tRISE
Load = 75Ω, 0.01µF (Parallel)
0.5
4
30
µs
Output Fall Time
tFALL
Load = 75Ω, 0.01µF (Parallel)
0.5
10
30
µs
Output Delay from Strobe, High
to Low Output Transition
tDHL
1
4
10
µs
Output Delay from Strobe, Low to
High Output Transition
tDLH
0.2
2.6
10
µs
Output Clamping Energy
LOGIC SUPPLY
Logic Supply Current, Loaded
ICC
All Outputs ON, 0.2A Load Per Output
-
2
4
mA
Logic Supply Current, No Load
ICC
All Outputs OFF
-
2
4
mA
All Outputs OFF
3.5
-
4
V
Logic Supply Under-Voltage
Reset Threshold
LOGIC INPUTS (EN, SI, SCK, STR)
Threshold Voltage at Falling
Edge
VT -
VCC = 5V ±10%
0.2VCC
0.3VCC
-
V
Threshold Voltage at Rising
Edge
VT +
VCC = 5V ±10%
-
0.6VCC
0.7VCC
V
Hysteresis Voltage
VH
VT + - VT -
0.85
1.4
2.25
V
Leakage Current
I LIN
-10
-
10
µA
fSCK
-
-
1.6
MHz
tW(SCKH)
-
27
175
ns
SERIAL DATA CLOCK (SCK) (Refer to Figure 1 for Waveform Detail)
Frequency
Pulse Width High
3
HIP0050
Electrical Specifications
VCC = 4.5V to 5.5V, VBATT = 8V to 16V, TA = -40oC to 85oC; Unless Otherwise Specified (Continued)
PARAMETER
Pulse Width Low
SYMBOL
CONDITIONS
t W(SCKL)
MIN
TYP
MAX
UNITS
-
27
175
ns
SERIAL DATA IN (SI) (Refer to Figure 1 for Waveform Detail)
Input Setup Time
t SUI
-
1.1
75
ns
Input Hold Time
THI
-
1.5
75
ns
Strobe Pulse Width
t W(S)
-
12
150
ns
Clock to Strobe Delay
t D(CS)
-
5
75
ns
-
0.2
0.4
V
3.7
4.4
-
V
75
260
500
ns
STROBE (STR)
SERIAL DATA OUT (SO) (Refer to Figure 1 for Waveform Detail)
Low Level Output Voltage
VOL
Sink Current = 1.6mA
High Level Output Voltage
VOH
Source Current = -1.6mA
Propagation Delay
t P(CD)
PROTECTION PARAMETERS
Fault Output (FLT) Low
VOL
Over-Temp. (OT) Shutdown
TSD
OT Shutdown Hysteresis
Sink Current = 1.6mA
-
-
0.4
145
155
165
5
TH
10
20
V
o
C
oC
NOTES:
1. The MOSFET Output Drain is internally clamped with a Drain-to-Gate Zener Diode that turns on the MOSFET; holding the drain at the
output clamp voltage VOC.
2. The HIP0050 Output Drive is protected by an internal current shutdown. The ICL over-current shutdown threshold parameter specification
defines the maximum current. The minimum limit for this threshold is 300mA. The maximum current with all outputs ON may be further
limited by dissipation.
3. Package dissipation is based on thermal resistance capability in a normal operating environment. The junction to ambient thermal resistance values are defined here as a PC Board mounted device with minimal copper. Due to the heat conducting capability of the DIP and
SOIC package lead frames, 35oC/W thermal resistance can be achieved with approximately 2 square inches of 1 oz. copper PC Board
area. The junction to lead thermal resistance values are based on measurements from the chip to the ground leads of the package.
t W(SCK)
t W(SCK)
SCK (CLOCK)
t SUI
t HI
SI (SERIAL DATA IN)
t W(S)
t D(CS)
STR (STROBE)
t D(HL)
t D(LH)
90%
DRx (POWER OUTPUT DRIVER)
10%
t P(CD)
SO (SERIAL DATA OUT)
FIGURE 1. LOGIC TIMING CONTROL WAVEFORMS
4
t FALL , t RISE
HIP0050
Pin Descriptions
VCC Power Pin
DR0 - DR7 Outputs 0 Thru 7
The VCC pin is the positive 5V logic voltage supply input for
the IC. The normal operating voltage range is 4.5V to 5.5V.
When switched on, the POR forces all outputs off.
The drain output pins of the DMOS Power Drivers are capable of sinking 300mA. Each output has short circuit protection to
independently shutdown the output under excessive high load
current conditions.
SCK Serial Clock Pin
FLT Fault Flag
SCK is the clock input for the SPI Interface. Output ON/OFF
control data is clocked into an eight stage shift register on
the rising edge of an external clock. This input has a Schmitt
trigger.
The fault flag pin indicates an over-current in any one of the
output drivers. (It is not an indicator for the thermal shutdown
mode.) The FLT output is active low and can sink 1.6mA
when activated. When latched low, it will remain latched until
the next data strobe.
SI Serial Data In Pin
SI is the Serial Data Input Pin for the SPI Interface. The eight
power outputs are controlled by the serial data via the output
data buffer. This input has a Schmitt Trigger.
EN Enable Pin
The enable pin is an active low enable function for all eight
output drivers. When EN is high, drive from the output data
buffer is held low and all output drivers are disabled. When
EN is low, the output drivers are enabled and data in the 8-bit
shift register is transparent to the output data buffer. This input
has a Schmitt trigger.
STR Strobe Pin for the SPI Interface
When the STR Pin is high, data from the 8-bit shift register is
passed into the output data buffers where it controls the ONOFF state of each output driver. The data is latched in the
output data buffers when STR goes low. This input has a
Schmitt trigger.
LGND and GND Pins
The LGND Pin is the 5V Logic Supply Ground for the IC and
GND is a common ground for the power output drivers.
SO Serial Data Out Pin
The serial data out allows other ICs to be serially cascaded.
For example, a 10-bit LED driver may be located behind the
HIP0050. A controlling microprocessor may then clock out
18-bits of information and simultaneously strobe both parts.
The cascaded ICs may be the same or different from the
HIP0050.
1000
ENERGY (mJ)
100
SAFE OPERATING AREA
BELOW LINE
10
1
0.1
1
10
100
TIME (ms)
FIGURE 2. MAXIMUM SINGLE PULSE ENERGY SAFE OPERATING AREA FOR EACH CLAMPED OUTPUT DRIVER, TA = 25o C
5
HIP0050
Dual-In-Line Plastic Packages (PDIP)
E20.3 (JEDEC MS-001-AD ISSUE D)
N
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
SYMBOL
-B-AE
D
BASE
PLANE
A2
-C-
SEATING
PLANE
A
L
D1
e
B1
D1
B
0.010 (0.25) M
A1
eC
C A B S
MILLIMETERS
MIN
MAX
MIN
MAX
NOTES
A
-
A1
0.015
0.210
-
5.33
4
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.55
1.77
8
eA
C
0.008
0.014
0.204
0.355
-
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
D
0.980
1.060
24.89
26.9
5
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
6
eB
-
0.430
-
10.92
7
L
0.115
0.150
2.93
3.81
4
N
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
20
20
9
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
6
HIP0050
Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
N
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
MIN
MILLIMETERS
MAX
MIN
MAX
NOTES
-B1
2
3
L
SEATING PLANE
-A-
h x 45 o
A
D
-C-
A1
B
0.25(0.010) M C A M
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.020
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.5985
0.6141
15.20
15.60
3
E
0.2914
0.2992
7.40
7.60
4
e
µα
e
A
A1
C
0.10(0.004)
B S
0.05 BSC
-
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
α
NOTES:
1.27 BSC
H
24
0o
24
7
8o
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
7
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