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ADS54J66
SBAS745A – NOVEMBER 2015 – REVISED DECEMBER 2015
ADS54J66 Quad-Channel, 14-Bit, 500-MSPS ADC with Integrated DDC
1 Features
3 Description
•
•
•
•
•
•
•
The ADS54J66 is a low-power, wide-bandwidth, 14bit, 500-MSPS, quad-channel, telecom receiver
device. The ADS54J66 supports a JESD204B serial
interface with data rates up to 10 Gbps with one lane
per channel. The buffered analog input provides
uniform input impedance across a wide frequency
range and minimizes sample-and-hold glitch energy.
The ADS54J66 provides excellent spurious-free
dynamic range (SFDR) over a large input frequency
range with very low power consumption. The digital
signal processing block includes complex mixers
followed by low-pass filters with decimate-by-2 and -4
options supporting up to 200-MHz receive bandwidth.
1
•
•
•
•
•
Quad Channel
14-Bit Resolution
Maximum Clock Rate: 500 MSPS
Input Bandwidth (3 dB): 900 MHz
On-Chip Dither
Analog Input Buffer with High-Impedance Input
Output Options:
– Rx: Decimate-by-2 and -4 Options with
Low-Pass Filter
– 200-MHz Complex Bandwidth or 100-MHz
Real Bandwidth Support
– DPD FB: 500 MSPS
1.9-VPP Differential Full-Scale Input
JESD204B Interface:
– Subclass 1 Support
– 1 Lane per ADC Up to 10 Gbps
– Dedicated SYNC Pin for Pair of Channels
Support for Multi-Chip Synchronization
72-Pin VQFN Package (10 mm × 10 mm)
Key Specifications:
– Power Dissipation: 675 mW/ch
– Spectral Performance (Un-Decimated)
– fIN = 190 MHz IF at –1 dBFS:
– SNR: 69.5 dBFS
– NSD: –153.5 dBFS/Hz
– SFDR: 86 dBc (HD2, HD3),
93 dBFS (Non HD2, HD3)
– fIN = 370 MHz IF at –3 dBFS:
– SNR: 68.5 dBFS
– NSD: –152.5 dBFS/Hz
– SFDR: 81 dBc (HD2, HD3),
86 dBFS (Non HD2, HD3)
2 Applications
The JESD204B interface reduces the number of
interface lines, thus allowing high system integration
density. An internal phase-locked loop (PLL)
multiplies the incoming analog-to-digital converter
(ADC) sampling clock to derive the bit clock, which is
used to serialize the 14-bit data from each channel.
Device Information(1)
PART NUMBER
PACKAGE
ADS54J66
BODY SIZE (NOM)
VQFN (72)
10.00 mm x 10.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
INAP,
INAM
Digital Block
Interleaving
Correction
14-Bit
ADC
2x
4x
INBP,
INBM
Digital Block
Interleaving
Correction
14-Bit
ADC
JESD204B
2x
K x fS / 16
TRIGAB
TRIGCD
TRDYAB
SYSREFP,
SYSREFM
TRDYCD
CLKINP,
CLKINM
PLL
x10, x20
SYNCbAB
SYNCbCD
INCP,
INCM
Digital Block
Interleaving
Correction
14-Bit
ADC
Digital Block
Interleaving
Correction
14-Bit
ADC
DCP,
DCM
2x
JESD204B
4x
K x fS / 16
DDP,
DDM
2x
fS / 8
Configuration
Registers
SCLK
SEN
SDIN
SDOUT
INDP,
INDM
RESET
SCAN_EN
Radar and Antenna Arrays
Broadband Wireless and Digitizers
Cable CMTS, DOCSIS 3.1 Receivers
Communications Test Equipment
Microwave Receivers
Software Defined Radio (SDR)
DBP,
DBM
fS / 8
fS / 4
•
•
•
•
•
•
DAP,
DAM
fS / 4
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS54J66
SBAS745A – NOVEMBER 2015 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
AC Performance ...................................................... 8
Digital Characteristics ............................................. 10
Timing Characteristics............................................. 11
Typical Characteristics: General (DDC Mode-8)..... 12
Typical Characteristics: Mode 2............................ 19
Typical Characteristics: Mode 0............................ 20
Detailed Description ............................................ 21
7.1 Overview ................................................................. 21
7.2
7.3
7.4
7.5
7.6
8
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
Register Maps .........................................................
21
22
23
31
41
Application and Implementation ........................ 69
8.1 Application Information............................................ 69
8.2 Typical Application .................................................. 73
9 Power Supply Recommendations...................... 74
10 Layout................................................................... 75
10.1 Layout Guidelines ................................................. 75
10.2 Layout Example .................................................... 75
11 Device and Documentation Support ................. 76
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
76
76
76
76
12 Mechanical, Packaging, and Orderable
Information ........................................................... 76
4 Revision History
Changes from Original (November 2015) to Revision A
Page
•
Changed Table 8: changed several comments, added rows .............................................................................................. 29
•
Changed Figure 84: changed last value of JESD bank page address ............................................................................... 41
•
Changed Table 15: changed ADC page registers 5Fh to 6Dh............................................................................................. 42
•
Changed description of decimation mode 0 to mode 4 in Example Register Writes section: deleted (default) ................. 44
•
Changed Register 5Fh, Register 60h, and Register 61h .................................................................................................... 51
•
Changed Register 6Ch and Register 6Dh ........................................................................................................................... 52
•
Changed Start-Up Sequence section .................................................................................................................................. 69
2
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SBAS745A – NOVEMBER 2015 – REVISED DECEMBER 2015
5 Pin Configuration and Functions
SYNCbCDP
SYNCbCDM
IOVDD
DDP
DDM
DGND
DCP
DCM
IOVDD
DGND
DBM
DBP
DGND
DAM
DAP
IOVDD
SYNCbABM
SYNCbABP
RMP Package
72-Pin VQFN
Top View
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
50
PDN
SCLK
6
49
RES
SEN
7
48
RESET
DVDD
8
47
DVDD
AVDD
9
GND Pad
46
AVDD
AVDD3V
10
(Back Side)
45
AVDD3V
SDOUT
11
44
AVDD
AVDD
12
43
AVDD
INDP
13
42
INAP
INDM
14
41
INAM
AVDD
15
40
AVDD
AVDD3V
16
39
AVDD3V
AVDD
17
38
AVDD
INCM
18
37
INBM
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
INBP
5
AVDD
SDIN
SYSREFM
IOVDD
SYSREFP
51
AGND
4
AVDD3V
IOVDD
AVDD
DGND
AGND
52
CLKINM
3
CLKINP
DGND
AGND
NC
AVDD
53
AVDD3V
2
NC
NC
NC
NC
AGND
54
AVDD
1
INCP
NC
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Pin Functions
PIN
NAME
NUMBER
I/O
DESCRIPTION
INPUT, REFERENCE
INAM
41
INAP
42
INBM
37
INBP
36
INCM
18
INCP
19
INDM
14
INDP
13
I
Differential analog input pins for channel A
I
Differential analog input pins for channel B
I
Differential analog input pins for channel C
I
Differential analog input pins for channel D
I
Differential clock input pins for the ADC
I
External sync input pins
O
JESD204B Serial data output pins for channel A
O
JESD204B Serial data output pins for channel B
O
JESD204B Serial data output pins for channel C
O
JESD204B Serial data output pins for channel D
1, 2, 22, 23, 53,
54
–
Do not connect
PDN
50
I/O
RES
49
–
Reserve pin. Connect to GND
RESET
48
I
Hardware reset. Active high. This pin has an internal 150-kΩ pulldown resistor.
SCLK
6
I
Serial interface clock input
CLOCK, SYNC
CLKINM
28
CLKINP
27
SYSREFM
34
SYSREFP
33
CONTROL, SERIAL
DAM
59
DAP
58
DBM
62
DBP
61
DCM
65
DCP
66
DDM
68
DDP
69
NC
Power down. Can be configured via SPI register setting.
SDIN
5
I
Serial interface data input.
SDOUT
11
O
Serial interface data output.
SEN
7
I
Serial interface enable
SYNCbABM
56
SYNCbABP
55
I
Synchronization input pins for JESD204B port channel A, B. Can be configured via SPI to
SYNCb signal for all four channels. Needs external termination.
SYNCbCDM
71
SYNCbCDP
72
I
Synchronization input pins for JESD204B port channel C, D. Can be configured via SPI to
SYNCb signal for all four channels. Needs external termination.
4
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Pin Functions (continued)
PIN
NAME
NUMBER
I/O
DESCRIPTION
POWER SUPPLY
AGND
21, 26, 29, 32
I
Analog ground
AVDD
9, 12, 15, 17,
20, 25, 30, 35,
38, 40, 43, 44,
46
I
Analog 1.9-V power supply
AVDD3V
10, 16, 24, 31,
39, 45
I
Analog 3 V for analog buffer
DGND
3, 52, 60, 63, 67
I
Digital ground
DVDD
8, 47
I
Digital 1.9-V power supply
IOVDD
4, 51, 57, 64, 70
I
Digital 1.15-V power supply for the JESD204B transmitter
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage range
MIN
MAX
AVDD3V
–0.3
3.6
AVDD
–0.3
2.1
DVDD
–0.3
2.1
IOVDD
–0.2
1.4
Voltage between AGND and DGND
Voltage applied to input pins
V
–0.3
0.3
INAP, INBP, INAM, INBM, INCP, INDP, INCM, INDM
–0.3
3
CLKINP, CLKINM
–0.3
AVDD + 0.3
SYSREFP, SYSREFM
–0.3
AVDD + 0.3
SCLK, SEN, SDIN, RESET, SPI_MODE,
SYNCbABP, SYNCbABM, SYNCbCDP,
SYNCbCDM, PDN
–0.2
2
–65
150
Storage temperature, Tstg
(1)
UNIT
V
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
VALUE
UNIT
±1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
AVDD3V
Supply voltage range
Analog inputs
2.85
3
3.6
1.8
1.9
2
DVDD
1.8
1.9
2
IOVDD
1.1
1.15
1.2
Differential input voltage range
1.9
Input common-mode voltage
Input clock amplitude differential
(VCLKP – VCLKM)
(1)
(2)
250
1.5
LVPECL, ac-coupled
1.6
LVDS, ac-coupled
0.7
Operating free-air, TA
45%
Operating junction, TJ
MHz
VPP
50%
55%
105 (2)
125
–40
V
V
500
Sine wave, ac-coupled
UNIT
VPP
2.0 ± 0.025
Input device clock duty cycle, default after reset
Temperature
MAX
AVDD
Input clock frequency, device clock frequency
Clock inputs
NOM
85
ºC
SYSREF must be applied for the device initialization.
Prolonged use above this junction temperature can increase the device failure-in-time (FIT) rate.
6.4 Thermal Information
ADS54J66
THERMAL METRIC (1)
RMP (VQFNP)
UNIT
72 PINS
RθJA
Junction-to-ambient thermal resistance
22.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
5.1
°C/W
RθJB
Junction-to-board thermal resistance
2.4
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
2.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.4
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling frequency =
500 MSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF
≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
500
MSPS
GENERAL
ADC sampling rate
Resolution
14
Bits
POWER SUPPLY
AVDD3V
3-V analog supply
2.85
3
3.6
V
AVDD
DVDD
1.9-V analog supply
1.8
1.9
2
V
1.9-V digital supply
1.8
1.9
2
V
IOVDD
1.15-V SERDES supply
1.1
1.15
1.2
IAVDD3V
3-V analog supply current
370-MHz, full-scale input on all four channels
340
mA
IAVDD
1.9-V analog supply current
370-MHz, full-scale input on all four channels
365
mA
2x decimation (4 channels), 370 MHz, full-scale
input on all four channels
190
DDC mode-8 (no decimation), 370 MHz,
full-scale input on all four channels
184
DDC mode-8 (no decimation), 370 MHz,
full-scale input on all four channels
533
2x decimation (4 channels), 370 MHz, full-scale
input on all four channels
2.68
DDC mode-8 (no decimation), 370 MHz,
full-scale input on all four channels
2.67
Full-scale input on all four channels
250
mW
1.9
VPP
IDVDD
IIOVDD
Pdis
1.9-V digital supply current
1.15-V SERDES supply
current
Total power dissipation
Global power-down power
dissipation
V
mA
mA
W
ANALOG INPUTS
Differential input full-scale
voltage
Input common-mode voltage
Differential input resistance
At fIN = 370 MHz
Differential input capacitance
At fIN = 370 MHz
Analog input bandwidth (3 dB)
2.0
V
0.5
kΩ
2.5
pF
900
MHz
ISOLATION
Crosstalk (1) isolation between
near channels
(channels A and B are near to
each other, channels C and D
are near to each other)
Crosstalk (1) isolation between
far channels
(channels A and B, and
channels C and D are far
channels)
fIN = 10 MHz
105
fIN = 100 MHz
104
fIN = 170 MHz
96
fIN = 270 MHz
97
fIN = 370 MHz
93
fIN = 470 MHz
85
fIN = 10 MHz
110
fIN = 100 MHz
107
fIN = 170 MHz
96
fIN = 270 MHz
97
fIN = 370 MHz
95
fIN = 470 MHz
94
dBFS
dBFS
CLOCK INPUT
Internal clock biasing
(1)
CLKINP and CLKINM pins are connected to
internal biasing voltage through 400 Ω
1.15
V
Crosstalk is measured with a –1-dBFS input signal on aggressor channel and no input on the victim channel.
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6.6 AC Performance
over operating free-air temperature range (unless otherwise noted)
PARAMETER
SNR
Signal-to-noise ratio
TEST CONDITIONS
NO DECIMATION,
500-MSPS OUTPUT
(DDC Mode 8)
DECIMATE-BY-2,
250-MSPS OUTPUT
(DDC Mode 2)
MIN
MIN
70.5
74
fIN = 190 MHz, AIN = –1 dBFS
69.5
73.2
70.3
73.6
69
72.6
fIN = 190 MHz, AIN = –3 dBFS
65.6
fIN = 300 MHz
72
68.4
71.5
fIN = 470 MHz
67.5
70.7
fIN = 10 MHz
154.8
155.1
fIN = 70 MHz
154.5
155
fIN = 190 MHz, AIN = –1 dBFS
153.5
154.2
fIN = 190 MHz, AIN = –3 dBFS
SFDR
Signal-to-noise and
distortion ratio
Spurious-free dynamic
range
149.6
154.3
154.6
fIN = 300 MHz
153
153.6
fIN = 350 MHz
152.7
153
148.6
152.4
152.5
fIN = 470 MHz
151.5
151.7
fIN = 10 MHz
70.7
73.9
fIN = 70 MHz
70.4
73.9
fIN = 190 MHz, AIN = –1 dBFS
69.4
73.1
fIN = 190 MHz, AIN = –3 dBFS
70.2
73.5
fIN = 300 MHz
68.9
72.5
fIN = 350 MHz
68.6
71.7
fIN = 370 MHz
68.2
fIN = 470 MHz
66.9
69.7
fIN = 10 MHz
89
88
fIN = 70 MHz
87
95
fIN = 190 MHz, AIN = –1 dBFS
86
97
88
96
82
94
82
82
fIN = 190 MHz, AIN = –3 dBFS
78
fIN = 300 MHz
fIN = 350 MHz
fIN = 370 MHz
75
73
fIN = 10 MHz
89
91
fIN = 70 MHz
94
103
86
101
88
HD2
101
fIN = 300 MHz
82
97
fIN = 350 MHz
82
82
fIN = 190 MHz, AIN = –3 dBFS
fIN = 370 MHz
78
75
fIN = 470 MHz
8
dBFS/Hz
dBFS
dBc
74
dBc
81
73
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dBFS
81
fIN = 470 MHz
fIN = 190 MHz, AIN = –1 dBFS
Second-order harmonic
distortion
MAX
74.1
68.7
64.6
fIN = 370 MHz
SINAD
TYP
fIN = 70 MHz
fIN = 370 MHz
Noise spectral density
MAX
70.8
fIN = 350 MHz
NSD
TYP
fIN = 10 MHz
UNIT
74
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AC Performance (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
HD3
Third-order harmonic
distortion
TEST CONDITIONS
NO DECIMATION,
500-MSPS OUTPUT
(DDC Mode 8)
DECIMATE-BY-2,
250-MSPS OUTPUT
(DDC Mode 2)
MIN
MIN
TYP
fIN = 70 MHz
87
99
fIN = 190 MHz, AIN = –1 dBFS
98
100
97
98
95
100
90
96
fIN = 190 MHz, AIN = –3 dBFS
78
fIN = 300 MHz
fIN = 370 MHz
Spurious-free
dynamic range
(excluding HD2, HD3)
75
83
83
94
98
fIN = 70 MHz
94
95
fIN = 190 MHz, AIN = –1 dBFS
93
97
IMD3
Total harmonic distortion
Two-tone, third-order
intermodulation distortion
87
93
96
fIN = 300 MHz
92
94
fIN = 350 MHz
91
94
80
87
93
fIN = 10 MHz
88
86
fIN = 70 MHz
85
92
fIN = 190 MHz, AIN = –1 dBFS
85
92
fIN = 190 MHz, AIN = –3 dBFS
86
91
fIN = 300 MHz
81
89
fIN = 350 MHz
79
82
fIN = 370 MHz
78
fIN = 470 MHz
72
fIN = 185 MHz, fIN = 190 MHz,
AIN = –7 dBFS
89
fIN = 365 MHz, fIN = 370 MHz,
AIN = –7 dBFS
82
fIN = 465 MHz, fIN = 470 MHz,
AIN = –7 dBFS
77
dBc
73
dBFS
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dBc
90
fIN = 470 MHz
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dBc
85
fIN = 10 MHz
fIN = 190 MHz, AIN = –3 dBFS
MAX
88
fIN = 470 MHz
fIN = 370 MHz
THD
TYP
93
fIN = 350 MHz
Non
HD2,
HD3
MAX
fIN = 10 MHz
UNIT
9
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6.7 Digital Characteristics
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500 MSPS,
50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless
otherwise noted)
PARAMETER
DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, PDN)
TEST CONDITIONS
MIN
0.8
VIH
High-level input voltage
All digital inputs support 1.2-V and 1.8-V logic levels
VIL
Low-level input voltage
All digital inputs support 1.2-V and 1.8-V logic levels
IIH
High-level input current
IIL
Low-level input current
TYP
MAX
UNIT
(1)
V
0.4
SEN
0
RESET, SCLK, SDIN, PDN
µA
100
SEN
50
RESET, SCLK, SDIN, PDN
V
µA
0
DIGITAL INPUTS (SYSREFP, SYSREFM, SYNCbABM, SYNCbABP, SYNCbCDM, SYNCbCDP)
VD
Differential input voltage
V(CM_DIG)
Common-mode voltage for SYSREF
0.35
0.45
1.4
V
1.3
V
DVDD
V
DIGITAL OUTPUTS (SDOUT, PDN)
VOH
High-level output voltage
VOL
Low-level output voltage
DVDD –
0.1
0.1
V
DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM) (2)
VOD
Output differential voltage
VOC
Output common-mode voltage
Transmitter short-circuit current
zos
(2)
10
Transmitter pins shorted to any voltage between
–0.25 V and 1.45 V
Single-ended output impedance
Output capacitance
(1)
With default swing setting
Output capacitance inside the device,
from either output to ground
700
mVPP
450
mV
–100
100
mA
50
Ω
2
pF
The RESET, SCLK, SDATA, and PDN pins have a 20-kΩ (typical) internal pulldown resistor to ground, and the SEN pin has a 20-kΩ
(typical) pull up resistor to IOVDD.
50-Ω, single-ended external termination to IOVDD.
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6.8 Timing Characteristics
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500 MSPS,
50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless
otherwise noted)
MIN
TYP
MAX
UNIT
SAMPLE TIMING CHARACTERISTICS
Aperture delay
0.75
1.6
Aperture delay matching between two channels on the same device
ns
±70
Aperture delay matching between two devices at the same temperature and supply voltage
ps
±270
ps
Aperture jitter
135
fS rms
Wake-up time to valid data after coming out of global power-down
150
µs
Data latency : ADC sample to digital output
77
Input clock
cycles
OVR latency: ADC sample to OVR bit
44
Input clock
cycles
4
ns
(1)
tPDI
Clock propagation delay: input clock rising edge cross-over to output clock rising edge crossover
tSU_SYSREF
Setup time for SYSREF, referenced to input clock rising edge
300
tH_SYSREF
Hold time for SYSREF, referenced to input clock rising edge
100
900
ps
ps
JESD OUTPUT INTERFACE TIMING CHARACTERISTICS
Unit interval
100
400
ps
Serial output data rate
2.5
10
Gbps
Total jitter for BER of 1E-15 and lane rate = 10 Gbps
26
Random jitter for BER of 1E-15 and lane rate = 10 Gbps
tR, tF
(1)
0.75
ps
ps rms
Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps
12
ps, pk-pk
Data rise time, data fall time: rise and fall times measured from 20% to 80%, differential output
waveform, 2.5 Gbps ≤ bit rate ≤ 10 Gbps
35
ps
Overall ADC latency = data latency + tPDI.
N+1
N+2
N
Sample
tPD
Data Latency: 77 Clock Cycles
CLKINP
CLKINM
DAP, DAM
DBP, DBM
DCP, DCM
DDP, DDM
D20
Sample N-1
D1
Sample N
D20
Sample N+1
Figure 1. Latency Timing Diagram
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6.9 Typical Characteristics: General (DDC Mode-8)
0
0
-20
-20
Amplitude (dBFS)
Amplitude (dBFS)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling frequency =
500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise noted)
-40
-60
-80
-40
-60
-80
-100
-100
-120
-120
0
50
100
150
Input Frequency (MHz)
200
0
250
fIN = 10 MHz , AIN = –1 dBFS,
SNR = 71 dBFS, SFDR = 89 dBc, SFDR = 89 dBc (non 23)
0
-20
-20
Amplitude (dBFS)
Amplitude (dBFS)
200
250
D002
Figure 3. FFT for 140-MHz Input Signal
0
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
0
50
100
150
Input Frequency (MHz)
200
250
0
50
D003
fIN = 190 MHz , AIN = –1 dBFS,
SNR = 69.4 dBFS, SFDR = 88 dBc, SFDR = 96 dBc (non 23)
100
150
Input Frequency (MHz)
200
250
D004
fIN = 230 MHz , AIN = –1 dBFS,
SNR = 69.4 dBFS, SFDR = 85 dBc, SFDR = 96 dBc (non 23)
Figure 4. FFT for 190-MHz Input Signal
Figure 5. FFT for 230-MHz Input Signal
0
0
-20
-20
Amplitude (dBFS)
Amplitude (dBFS)
100
150
Input Frequency (MHz)
fIN = 140 MHz , AIN = –1 dBFS,
SNR = 70 dBFS, SFDR = 88 dBc, SFDR = 91 dBc (non 23)
Figure 2. FFT for 10-MHz Input Signal
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
0
50
100
150
Input Frequency (MHz)
200
250
0
D005
fIN = 300 MHz , AIN = –3 dBFS,
SNR = 69.4 dBFS, SFDR = 80 dBc, SFDR = 95 dBc (non 23)
50
100
150
Input Frequency (MHz)
200
250
D006
fIN = 370 MHz , AIN = –3 dBFS,
SNR = 68.4 dBFS, SFDR = 84 dBc, SFDR = 86 dBc (non 23)
Figure 6. FFT for 300-MHz Input Signal
12
50
D001
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Figure 7. FFT for 370-MHz Input Signal
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Typical Characteristics: General (DDC Mode-8) (continued)
0
0
-20
-20
Amplitude (dBFS)
Amplitude (dBFS)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling frequency =
500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise noted)
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
0
50
100
150
Input Frequency (MHz)
200
250
0
50
D007
fIN = 470 MHz , AIN = –3 dBFS,
SNR = 67.4 dBFS, SFDR = 73 dBc, SFDR = 80 dBc (non 23)
250
D008
Figure 9. FFT for Two-Tone Input Signal
0
0
-20
-20
Amplitude (dBFS)
Amplitude (dBFS)
200
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD = 89 dBFS,
each tone at –7 dBFS
Figure 8. FFT for 470-MHz Input Signal
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
0
50
100
150
Input Frequency (MHz)
200
250
0
50
D009
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD = 103 dBFS,
each tone at –36 dBFS
100
150
Input Frequency (MHz)
200
250
D010
fIN1 = 370 MHz, fIN2 = 365 MHz, IMD = 81.7 dBFS,
each tone at –7 dBFS
Figure 10. FFT for Two-Tone Input Signal
Figure 11. FFT for Two-Tone Input Signal
0
0
-20
-20
Amplitude (dBFS)
Amplitude (dBFS)
100
150
Input Frequency (MHz)
-40
-60
-80
-40
-60
-80
-100
-100
-120
-120
0
50
100
150
Input Frequency (MHz)
200
250
0
50
D011
fIN1 = 370 MHz, fIN2 = 365 MHz, IMD = 102 dBFS,
each tone at –36 dBFS
Figure 12. FFT for Two-Tone Input Signal
100
150
Input Frequency (MHz)
200
250
D012
fIN1 = 470 MHz, fIN2 = 465 MHz, IMD = 76.7 dBFS,
each tone at –7 dBFS
Figure 13. FFT for Two-Tone Input Signal
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Typical Characteristics: General (DDC Mode-8) (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling frequency =
500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise noted)
0
-88
-90
-20
Amplitude (dBFS)
-92
IMD (dBFS)
-40
-60
-80
-94
-96
-98
-100
-100
-102
-120
0
50
100
150
Input Frequency (MHz)
200
-104
-35
250
-31
D013
fIN1 = 470 MHz, fIN2 = 465 MHz, IMD = 98.8 dBFS,
each tone at –36 dBFS
-27
-23
-19
-15
Each Tone Amplitude (dBFS)
-11
-7
D014
fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 14. FFT for Two-Tone Input Signal
Figure 15. Intermodulation Distortion vs Input Amplitude
-80
-74
-84
-80
IMD (dBFS)
IMD (dBFS)
-88
-92
-86
-92
-96
-98
-100
-104
-35
-31
-27
-23
-19
-15
Each Tone Amplitude (dBFS)
-11
-104
-35
-7
-31
D015
fIN1 = 365 MHz, fIN2 = 370 MHz
-7
D016
Figure 17. Intermodulation Distortion vs Input Amplitude
96
96
Ain = -1 dBFS
Ain = -3 dBFS
93
Interleaving Spur (dBc)
92
SFDR (dBc)
-11
fIN1 = 465 MHz, fIN2 = 470 MHz
Figure 16. Intermodulation Distortion vs Input Amplitude
88
84
80
90
87
84
81
76
78
72
0
40
80 120 160 200 240 280 320 360 400 440 480
Input Frequency (MHz)
D017
0
40
Figure 18. Spurious-Free Dynamic Range vs
Input Frequency
14
-27
-23
-19
-15
Each Tone Amplitude (dBFS)
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80 120 160 200 240 280 320 360 400 440 480
Input Frequency (MHz)
D018
Figure 19. IL Spur vs Input Frequency
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Typical Characteristics: General (DDC Mode-8) (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling frequency =
500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise noted)
71.5
72
AIN = -1 dBFS
AIN = -3 dBFS
71.2
SNR (dBFS)
SNR (dBFS)
70.5
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
69.5
68.5
67.5
AVDD = 1.95 V
AVDD = 2 V
70.4
69.6
68.8
66.5
0
40
68
-40
80 120 160 200 240 280 320 360 400 440 480
Input Frequency (MHz)
D019
-15
10
35
Temperature (°C)
60
85
D020
fIN = 190 MHz, AIN = –1 dBFS
Figure 20. Signal-to-Noise Ratio vs Input Frequency
Figure 21. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
72
93
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.95 V
AVDD = 2 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
71
AVDD = 1.95 V
AVDD = 2 V
SNR (dBFS)
SFDR (dBc)
91
89
70
69
68
87
67
85
-40
-15
10
35
Temperature (°C)
60
66
-40
85
-15
D021
fIN = 190 MHz, AIN = –1 dBFS
10
35
Temperature (°C)
60
85
D022
fIN = 370 MHz, AIN = –3 dBFS
Figure 22. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
Figure 23. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
71.4
84
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
AVDD = 1.95 V
AVDD = 2 V
71
DVDD = 1.9 V
DVDD = 1.95 V
DVDD = 2 V
SNR (dBFS)
SFDR (dBc)
83
82
70.6
70.2
81
69.8
80
-40
-15
10
35
Temperature (°C)
60
85
69.4
-40
D023
fIN = 370 MHz, AIN = –3 dBFS
-15
10
35
Temperature (°C)
60
85
D024
fIN = 190 MHz, AIN = –1 dBFS
Figure 24. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
Figure 25. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
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Typical Characteristics: General (DDC Mode-8) (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling frequency =
500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise noted)
92
71
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
91
DVDD = 1.9 V
DVDD = 1.95 V
DVDD = 2 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
DVDD = 1.95 V
DVDD = 2 V
SNR (dBFS)
SFDR (dBc)
70
90
89
69
88
68
87
86
-40
-15
10
35
Temperature (°C)
60
67
-40
85
-15
D025
fIN = 190 MHz, AIN = –1 dBFS
60
85
D026
fIN = 370 MHz, AIN = –3 dBFS
Figure 26. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
Figure 27. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
72.2
84
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
DVDD = 1.95 V
DVDD = 2 V
AVDD3V = 2.85 V
AVDD3V = 3 V
AVDD3V = 3.1 V
AVDD3V = 3.2 V
71.7
SNR (dBFS)
83
SFDR (dBc)
10
35
Temperature (°C)
82
AVDD3V = 3.3 V
AVDD3V = 3.4 V
AVDD3V = 3.5 V
AVDD3V = 3.6 V
71.2
70.7
70.2
81
69.7
80
-40
-15
10
35
Temperature (°C)
60
69.2
-40
85
fIN = 370 MHz, AIN = –3 dBFS
85
D028
73
AVDD3V = 2.85 V
AVDD3V = 3 V
AVDD3V = 3.1 V
AVDD3V = 3.2 V
91
AVDD3V = 3.3 V
AVDD3V = 3.4 V
AVDD3V = 3.5 V
AVDD3V = 3.6 V
90
89
70
69
87
68
10
35
Temperature (°C)
60
85
AVDD3V = 3.3 V
AVDD3V = 3.4 V
AVDD3V = 3.5 V
AVDD3V = 3.6 V
71
88
-15
AVDD3V = 2.85 V
AVDD3V = 3 V
AVDD3V = 3.1 V
AVDD3V = 3.2 V
72
SNR (dBFS)
SFDR (dBc)
60
Figure 29. Signal-to-Noise Ratio vs
AVDD3V Supply and Temperature
92
67
-40
D029
fIN = 190 MHz, AIN = –1 dBFS
-15
10
35
Temperature (°C)
60
85
D030
fIN = 370 MHz, AIN = –3 dBFS
Figure 30. Spurious-Free Dynamic Range vs
AVDD3V Supply and Temperature
16
10
35
Temperature (°C)
fIN = 190 MHz, AIN = –1 dBFS
Figure 28. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
86
-40
-15
D027
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Figure 31. Signal-to-Noise Ratio vs
AVDD3V Supply and Temperature
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Typical Characteristics: General (DDC Mode-8) (continued)
74
84
AVDD3V = 2.85 V
AVDD3V = 3 V
AVDD3V = 3.1 V
AVDD3V = 3.2 V
SNR (dBFS)
SFDR (dBc)
83
AVDD3V = 3.3 V
AVDD3V = 3.4 V
AVDD3V = 3.5 V
AVDD3V = 3.6 V
82
72
150
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS) 125
70
100
68
75
66
50
SFDR (dBc,dBFS)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling frequency =
500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise noted)
81
10
35
Temperature (°C)
60
64
-70
85
25
-60
-50
D031
fIN = 370 MHz, AIN = –3 dBFS
120
69.5
90
68
60
66.5
30
-40
-30
Amplitude (dBFS)
-20
-10
110
73
100
71
90
69
80
67
70
65
0.2
0
D033
Figure 34. Performance vs Amplitude
Figure 35. Performance vs Clock Amplitude
125
73
95
SNR
SFDR
72
100
69
75
66
50
63
25
0
2.2
SNR (dBFS)
SNR
SFDR
SFDR (dBc)
SNR (dBFS)
D034
fIN = 190 MHz, AIN = –1 dBFS
75
0.6
1
1.4
1.8
Differential Clock Amplitude (Vpp)
60
2.2
0.6
1
1.4
1.8
Differential Clock Amplitude (Vpp)
fIN = 370 MHz
60
0.2
D032
SNR
SFDR
0
-50
0
75
SNR (dBFS)
71
-60
-10
Figure 33. Performance vs Amplitude
SFDR (dBc,dBFS)
SNR (dBFS)
72.5
180
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS) 150
65
-70
-20
fIN = 190 MHz
Figure 32. Spurious-Free Dynamic Range vs
AVDD3V Supply and Temperature
74
-40
-30
Amplitude (dBFS)
SFDR (dBc)
-15
72
90
71
85
70
80
69
75
68
30
35
D035
fIN = 370 MHz, AIN = –3 dBFS
40
45
50
55
60
Input Clock Duty Cycle (%)
65
SFDR (dBc)
80
-40
70
70
D036
fIN = 190 MHz, AIN = –1 dBFS
Figure 36. Performance vs Clock Amplitude
Figure 37. Performance vs Clock Duty Cycle
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Typical Characteristics: General (DDC Mode-8) (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling frequency =
500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise noted)
0
71
90
SNR
SFDR 87
70
84
69
81
68
78
67
75
66
72
-100
69
70
-120
65
30
35
40
45
50
55
60
Input Clock Duty Cycle (%)
65
Amplitude (dBFS)
-20
SFDR (dBc)
SNR (dBFS)
72
-40
-60
-80
0
50
D037
fIN = 370 MHz, AIN = –3 dBFS
100
150
Input Frequency (MHz)
200
250
D038
fIN = 190 MHz , AIN = –1 dBFS
SFDR = 49 dBc, fPSRR = 5 MHz, APSRR = 50 mVPP
Figure 39. Power-Supply Rejection Ratio FFT for
Test Signal on AVDD Supply
Figure 38. Performance vs Clock Duty Cycle
-10
0
PSRR with 50-mVPP Signal on AVDD
PSRR with 50-mVPP Signal on AVDD3V
-15
-20
Amplitude (dBFS)
-20
PSRR (dB)
-25
-30
-35
-40
-40
-60
-80
-45
-100
-50
-55
-120
0
50
100
150
200
250
Frequency of Signal on Supply (MHz)
300
0
fIN = 190 MHz, AIN = –1 dBFS
100
150
Input Frequency (MHz)
200
250
D040
fIN = 190 MHz , AIN = –1 dBFS
SFDR = 81 , fCMRR = 5 MHz, ACMRR = 50 mVPP
Figure 41. Common-Mode Rejection Ratio FFT
Figure 40. Power-Supply Rejection Ratio vs Supplies
4
-20
Power Consumption (W)
-25
-30
CMRR (dB)
50
D039
-35
-40
-45
-50
3.2
AVDD_Power (W)
DVDD_Power (W)
AVDD3V_Power (W)
IOVDD_Power (W)
TotalPower (W)
2.4
1.6
0.8
-55
-60
0
50
100
150
200
250
Frequency of Input Common-Mode Signal (MHz)
300
0
250
D041
300
350
400
Sampling Speed (MSPS)
450
500
D042
fIN = 190 MHz, AIN= –1 dBFS
50-mVPP test signal on input common-mode
Figure 42. Common-Mode Rejection Ratio
18
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Figure 43. Power vs Chip Clock
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6.10 Typical Characteristics: Mode 2
0
0
-20
-20
Amplitude (dBFS)
Amplitude (dBFS)
low-pass or high-pass decimation-by-2 filter selected as per input frequency; typical values are at TA = 25°C, full temperature
range is from TMIN = –40°C to TMAX = 85°C, ADC sampling frequency = 500 MSPS, 14-bit resolution, no decimation filter, 50%
clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF ≤ 250 MHz, and
–3-dBFS differential input for IF > 250 MHz (unless otherwise noted)
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
0
25
50
75
Input Frequency (MHz)
100
125
0
fIN = 100 MHz, AIN = –1 dBFS,
SNR = 74.1 dBFS, SFDR = 98 dBc, SFDR = 100 dBc (non 23)
50
75
Input Frequency (MHz)
100
125
D044
fIN = 150 MHz, AIN = –1 dBFS,
SNR = 73.8 dBFS, SFDR = 99 dBc, SFDR = 99 dBc (non 23)
Figure 44. FFT for 100-MHz Input Signal
Figure 45. FFT for 150-MHz Input Signal
0
0
-20
-20
Amplitude (dBFS)
Amplitude (dBFS)
25
D043
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
0
25
50
75
Input Frequency (MHz)
100
125
0
D045
fIN = 185 MHz, AIN = – 1 dBFS,
SNR = 73.2 dBFS, SFDR = 98 dBc, SFDR = 98 dBc (non 23)
25
50
75
Input Frequency (MHz)
100
125
D045
fIN = 230 MHz, AIN = –1 dBFS,
SNR = 72.4 dBFS, SFDR = 91 dBc, SFDR = 98 dBc (non 23)
Figure 46. FFT for 185-MHz Input Signal
Figure 47. FFT for 230-MHz Input Signal
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6.11 Typical Characteristics: Mode 0
0
0
-20
-20
Amplitude (dBFS)
Amplitude (dBFS)
low-pass decimation-by-2 filter selected, complex FFT plotted, mixer frequency 125 MHz; typical values are at TA = 25°C, full
temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling frequency = 500 MSPS, 14-bit resolution, no
decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input
for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise noted)
-40
-60
-80
-60
-80
-100
-100
-120
-125
-40
-75
-25
25
Input Frequency (MHz)
75
-120
-125
125
-75
-25
25
Input Frequency (MHz)
D047
fIN = 270 MHz, AIN = –3 dBFS,
SNR = 69.5 dBFS, SFDR = 83 dBc, SFDR = 87 dBc (non 23)
75
125
D048
fIN = 370 MHz, AIN = –3 dBFS,
SNR = 68.1 dBFS, SFDR = 82 dBc, SFDR = 82 dBc (non 23)
Figure 48. FFT for 270-MHz Input Signal
Figure 49. FFT for 370-MHz Input Signal
0
Amplitude (dBFS)
-20
-40
-60
-80
-100
-120
-125
-75
-25
25
Input Frequency (MHz)
75
125
D049
fIN = 470 MHz, AIN = –3 dBFS,
SNR = 66.3 dBFS, SFDR = 75 dBc, SFDR = 75 dBc (non 23)
Figure 50. FFT for 470-MHz Input Signal
20
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7 Detailed Description
7.1 Overview
The ADS54J66 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The
ADS54J66 supports the JESD204B serial interface with data rates up to 10 Gbps supporting one lane per
channel. The buffered analog input provides uniform input impedance across a wide frequency range and
minimizes sample-and-hold glitch energy. The ADS54J66 provides excellent spurious-free dynamic range
(SFDR) over a large input frequency range with very low power consumption. The device digital block includes a
2x and 4x decimation low-pass filter with fS / 4 and k × fS / 16 mixers to support a receive bandwidth up to 200
MHz for use as a Digital Pre-Distortion (DPD) observation receiver.
The JESD204B interface reduces the number of interface lines allowing high system integration density. An
internal phase locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock which is used
to serialize the 14-bit data from each channel.
7.2 Functional Block Diagram
INAP,
INAM
2x
Digital Block
Interleaving
Correction
14-Bit
ADC
4x
INBP,
INBM
JESD204B
2x
Digital Block
Interleaving
Correction
14-Bit
ADC
DAP,
DAM
FS / 4
K x FS / 16
DBP,
DBM
FS / 8
SYSREFP,
SYSREFM
CLKINP,
CLKINM
PLL
x10/x20
SYNCbAB
SYNCbCD
INCP,
INCM
Digital Block
Interleaving
Correction
14-Bit
ADC
DCP, DCM
2x
FS / 4
INDP,
INDM
4x
Digital Block
Interleaving
Correction
14-Bit
ADC
JESD204B
K x FS / 16
DDP, DDM
2x
FS / 8
SDOUT
SEN
SDIN
SCLK
RESET
SCAN_EN
Configuration
Registers
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7.3 Feature Description
7.3.1 Analog Inputs
The ADS54J66 analog signal inputs are designed to be driven differentially. The analog input pins have internal
analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high
impedance input across a very wide frequency range to the external driving source which enables great flexibility
in the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer also helps
isolate the external driving circuit from the internal switching currents of the sampling circuit, thus resulting in a
more constant SFDR performance across input frequencies.
The common-mode voltage of the signal inputs is internally biased to 1.9 V using 600-Ω resistors which allows
for ac coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM +
0.475 V) and (VCM – 0.475 V), resulting in a 1.9-VPP (default) differential input swing. The input sampling circuit
has a 3-dB bandwidth that extends up to 900 MHz.
7.3.2 Recommended Input Circuitry
In order to achieve optimum ac performance the circuitry shown in Figure 51 is recommended at the analog
inputs.
T1
T2
0.1 PF
10 :
INxP
0.1 PF
0.1 PF
25 :
25 :
RIN
3.3 pF
CIN
25 :
25 :
INxM
1:1
1:1
0.1 PF
10 :
Device
Figure 51. Analog Input Driving Circuit
22
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7.4 Device Functional Modes
7.4.1 Digital Features
The ADS54J66 supports decimation-by-2 and -4 and un-decimated output. The four channels can be configured
as pairs (A, B and C, D; however, the same decimation factor must be chosen for all four channels).
Figure 52 shows signal processing done in the digital down-conversion (DDC) block of the ADS54J66. Table 1
shows available modes of operation for this block.
I Data
Filter
N
IL Engine
Real Data
Channel x
0
2
4
5
6
7
8
cos (2Snfmix2 / fS )
cos (2Snfmix1 / fS )
500-MSPS
Data, x(n)
2
sin (2Snfmix1 / fS )
Upscaled
Zero-Padded
Data
sin (2Snfmix2 / fS )
To JESD
Encoder
N
Filter
Q Data
Default 14-Bit
Mode
Default 14-Bit Data
Mode
Selection
Figure 52. Digital Down-Conversion Block Diagram
Table 1. Overview of Operating Modes
OPERATING
MODE
BANDWIDTH
DIGITAL
MIXER
DECIMATION
0
±fS / 4
2
–
4
MAX
OUTPUT
RATE
491 MSPS
368 MSPS
OUTPUT
FORMAT
2
200 MHz
150 MHz
Complex
250 MSPS
2
100 MHz
75 MHz
Real
250 MSPS
N × fS / 16
2
100 MHz
75 MHz
Real
250 MSPS
N × fS / 16
2
200 MHz
150 MHz
Complex
250 MSPS
6
N × fS / 16
4
100 MHz
75 MHz
Complex
125 MSPS
7
N × fS / 16
2
100 MHz
75 MHz
Real
500 MSPS
–
–
245.76 MHz
184.32 MHz
Real
500 MSPS
5
8
DESCRIPTION
Decimation
No decimation
Table 2 shows characteristics of different blocks of DDC signal processing blocks active in different modes.
Table 2. Features of DDC Block in Different Modes
MODE
fmix1
FILTER AND DECIMATION
fmix2
OUTPUT
0
fS / 4
LPF cutoff at fS / 4, decimation-by-2
Not used
I, Q data at 250 MSPS each are given out
2
Not used
LPF or HPF cutoff at fS / 4, decimation-by-2
Not used
Straight 250 MSPS data are given out
4
k fS / 16
LPF cutoff at fS / 8, decimation-by-2
fS / 8
Real data at 250 MSPS are given out
5
k fS / 16
LPF cutoff at fS / 8, decimation-by-2
Not used
I, Q data at 250 MSPS each are given out
6
k fS / 16
LPF cutoff at fS / 8, decimation-by-4
Not used
I, Q data at 125 MSPS each are given out
7
k fS / 16
LPF cutoff at fS8, decimation-by-2
fS / 8
Real data are up-scaled, zero-padded and given
out at 500 MSPS
Default
Not used
Not used
Not used
Straight 500-MSPS, 14-bit data are given out
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7.4.2 Mode 0, Decimation-by-2 with IQ Outputs for up to 220 MHz of IQ Bandwidth
In this configuration, the DDC block includes a fixed frequency ±fS / 4 complex digital mixer preceding the digital
filter, so the IQ passband is approximately ±110 MHz (3 dB) centered at fS / 4. Mixing with +fS / 4 inverts the
spectrum. The stop-band attenuation is approximately 90 dB and the pass-band flatness is ±0.1 dB. Figure 53
shows mixing operation in DDC mode 0. Table 3 shows corner frequencies of decimation filter in DDC mode 0.
Figure 54 and Figure 55 show frequency response of the filter.
±fS / 4
IQ:
500 MSPS
500 MSPS
14-Bit
ADC
IQ:
250 MSPS
2x
fS / 4
fS / 2
fS / 4
Figure 53. Mixing in Mode 0
CORNERS
LOW PASS
–0.1 dB
0.204 × fS
–0.5 dB
0.211 × fS
–1 dB
0.216 × fS
–3 dB
0.226 × fS
20
0.5
0
0
-20
-0.5
Magnitude (dB)
Magnitude (dB)
Table 3. Filter Specification Details, Mode 0
-40
-60
-1.5
-80
-2
-100
-2.5
-120
-3
0
0.1
0.2
0.3
Frequency Response
0.4
0.5
0
0.05
D052
Figure 54. Frequency Response of Filter in Mode 0
24
-1
0.1
0.15
Frequency Response
0.2
0.25
D053
Figure 55. Zoomed View of Frequency Response
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7.4.3 Mode 2, Decimation-by-2 for up to 110 MHz of Real Bandwidth
In this configuration, the DDC block only includes a 2x decimation filter (high pass or low pass) with real outputs.
The pass band is approximately 110 MHz (3 dB). Figure 56 shows the filtering operation in DDC mode 2. Table 4
shows corner frequencies of decimation filter in DDC mode 2. Figure 57 and Figure 58 show frequency response
of the filter.
500 MSPS
14-Bit
ADC
250 MSPS
2x
fS / 4
fS / 2
fS / 4
Figure 56. Filtering in Mode 2
CORNERS
LOW PASS
HIGH PASS
–0.1 dB
0.204 × fS
0.296 × fS
–0.5 dB
0.211 × fS
0.290 × fS
–1 dB
0.216 × fS
0.284 × fS
–3 dB
0.226 × fS
0.274 × fS
20
0.5
0
0
-20
-0.5
Magnitude (dB)
Magnitude (dB)
Table 4. Filter Specification Details, Mode 2
-40
-60
-1
-1.5
-80
-2
-100
-2.5
-120
-3
0
0.05
0.1
0.15 0.2 0.25 0.3 0.35
Frequency Response
0.4
0.45
0.5
0
0.05
D056
Figure 57. Frequency Response for Decimate-by-2
Low-Pass and High-Pass Filter (in Mode 2)
0.1
0.15
Frequency Response
0.2
0.25
D057
Figure 58. Zoomed View of Frequency Response
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7.4.4 Modes 4 and 7, Decimation-by-2 with Real Outputs for up to 110 MHz of Bandwidth
In this configuration, the DDC block includes a selectable N × fS / 16 complex digital mixer (N from –8 to +7)
preceding the decimation-by-2 digital filter also with an IQ passband of approximately ±55 MHz (3 dB) centered
at N × fS / 16. A positive value for N inverts the spectrum. In addition, a fS / 8 complex digital mixer is added after
the decimation filter transforming the output back to real format and centers the output spectrum within the
Nyquist zone.
In addition, the ADS54J66 supports a 0-pad feature where a sample with value = 0 is added after each sample.
In this way the output data rate is interpolated to 500 MSPS (real) with a second image inverted at fS / 2 – fIN.
The stop-band attenuation is approximately 90 dB for in-band aliases from negative frequencies and
approximately 55 dB for out-of-band aliases. The passband flatness is ±0.1 dB. Figure 59 shows the filtering
operation in DDC mode 4 and 7. Table 5 shows corner frequencies of decimation filter in DDC mode 4 and 7.
Figure 60 and Figure 61 show frequency response of the filter.
2nd Image
fS / 8
N x fS / 16
500 MSPS
14-Bit
ADC
fS / 8
0 Pad
IQ:
500 MSPS
IQ: 250 MSPS
Real:
500 MSPS
Real:
250 MSPS
2x
fS / 4
fS / 2
Example
:
N= -4
fS / 8
fS / 4
fS / 2
0
fS / 8
fS / 4
fS / 4
Figure 59. Mixing and Filtering in Modes 4 and 7
CORNERS
LOW PASS
–0.1 dB
0.102 × fS
–0.5 dB
0.105 × fS
–1 dB
0.108 × fS
–3 dB
0.113 × fS
20
0.5
0
0
-20
-0.5
Magnitude (dB)
Magnitude (dB)
Table 5. Filter Specification Details, Modes 4 and 7
-40
-60
-1.5
-80
-2
-100
-2.5
-3
-120
0
0.05
0.1
0.15
Frequency Response
0.2
0.25
0
0.05
D050
Figure 60. Frequency Response for Decimate-by-2,
Low-Pass Filter (in Modes 4 and 7)
26
-1
0.1
0.15
Frequency Response
0.2
0.25
D051
Figure 61. Zoomed View of Frequency Response
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7.4.5 Mode 5, Decimation-by-2 with IQ Outputs for up to 110 MHz of IQ Bandwidth
In this configuration, the DDC block includes a selectable N × fS / 16 complex digital mixer (N from –8 to +7)
preceding the decimation-by-2 digital filter, so the IQ passband is approximately ±55 MHz (3 dB) centered at N ×
fS / 16. A positive value for N inverts the spectrum.
The stop-band attenuation is approximately 90 dB for in-band aliases from negative frequencies. The pass-band
flatness is ±0.1 dB. Figure 62 shows the filtering operation in DDC mode 5. Table 6 shows corner frequencies of
decimation filter in DDC mode 5. Figure 63 and Figure 64 show frequency response of the filter. Figure 62 shows
the filtering operation in DDC mode 5. Table 6 shows corner frequencies of decimation filter in DDC mode 5.
Figure 63 and Figure 64 show frequency response of the filter.
N x fS / 16
IQ:
250 MSPS
IQ:
500 MSPS
500 MSPS
14-Bit
ADC
2x
Example:
N = -4
fS / 4
fS / 2
fS / 8
fS / 4
Figure 62. Mixing and Filtering in Mode 5
CORNERS
LOW PASS
–0.1 dB
0.102 × fS
–0.5 dB
0.105 × fS
–1 dB
0.108 × fS
–3 dB
0.113 × fS
20
0.5
0
0
-20
-0.5
Magnitude (dB)
Magnitude (dB)
Table 6. Filter Specification Details, Mode 5
-40
-60
-1
-1.5
-80
-2
-100
-2.5
-3
-120
0
0.05
0.1
0.15
Frequency Response
0.2
0.25
0
0.05
D050
Figure 63. Frequency Response for Decimate-by-2,
Low-Pass Filter (In Mode 5)
0.1
0.15
Frequency Response
0.2
0.25
D051
Figure 64. Zoomed View of Frequency Response
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7.4.6 Mode 6, Decimation-by-4 with IQ Outputs for up to 110 MHz of IQ Bandwidth
In this configuration, the DDC block includes a selectable N × fS / 16 complex digital mixer (n from –8 to +7)
preceding the decimation-by-4 digital filter, so the IQ passband is approximately ±55 MHz (3 dB) centered at N ×
fS / 16. A positive value for N inverts the spectrum. Figure 65 shows the filtering operation in DDC mode 6.
Table 7 shows corner frequencies of decimation filter in DDC mode 6. The decimation-by-4 filter is a cascade of
two decimation-by-2 filters with frequency response shown in Figure 66 and Figure 67.
The stop-band attenuation is approximately 90 dB for in-band aliases from negative frequencies and
approximately 55 dB for out-of-band aliases. The pass-band flatness is ±0.1 dB.
N x fS / 16
IQ:
250 MSPS
IQ:
500 MSPS
500 MSPS
14-Bit
ADC
2x
IQ:
125 MSPS
2x
Example:
N= 6
3 fS / 8
fS / 4
fS / 2
fS / 8
fS / 4
Figure 65. Mixing and Filtering in Mode 6
CORNERS
LOW PASS
–0.1 dB
0.102 × fS
–0.5 dB
0.105 × fS
–1 dB
0.108 × fS
–3 dB
0.113 × fS
20
0.5
0
0
-20
-0.5
Magnitude (dB)
Magnitude (dB)
Table 7. Filter Specification Details, Mode 6
-40
-60
-1.5
-80
-2
-100
-2.5
-3
-120
0
0.05
0.1
0.15
Frequency Response
0.2
0.25
0
0.05
D050
Figure 66. Frequency Response for Decimate-by-2,
Low-Pass Filter (in Mode 6)
28
-1
0.1
0.15
Frequency Response
0.2
0.25
D051
Figure 67. Zoomed View of Frequency Response
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7.4.7 Overrange Indication
The ADS54J66 provides a fast overrange indication (FOVR) that can be presented in the digital output data
stream via SPI configuration. When the FOVR indication is embedded in the output data stream, it replaces the
LSB (normal 0) of the 16 bit going to the 8b/10b encoder as shown in Figure 68.
One threshold is set per channel pair A, B and C, D.
14-Bit Data Output
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0,
OVR
16-Bit Data Going Into 8b/10b Encoder
Figure 68. Timing Diagram for FOVR
The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and it gets
presented after just 44 input clock cycles enabling a quicker reaction to an overrange event.
The input voltage level at which the overload is detected is referred to as the threshold. It is programmable using
the FOVR THRESHOLD bits.
The input voltage level that fast OVR is triggered is:
Full-scale × [the decimal value of the FOVR threshold bits] / 255)
The default threshold is E3h (227), corresponding to a threshold of –1 dBFS.
In terms of full-scale input, the fast OVR threshold can be calculated as shown in Equation 1:
20 × log (<FOVR Threshold> / 255).
(1)
Table 8 is an example register write to set the FOVR threshold for all four channels.
Table 8. Register Sequence for FOVR Configuration
ADDRESS
DATA
COMMENT
11h
80h
Go to master page
59h
20h
Set the ALWAYS WRITE 1 bit. This bit configures the
OVR signal as fast OVR.
11h
FFh
Go to ADC page
5Fh
FFh
Set FOVR threshold for all channels to 255
4004h
68h
4003h
00h
60ABh
01h
70ABh
01h
60ADh
03h
70ADh
03h
6000h
01h
7000h
01h
6000h
00h
7000h
00h
Go to main digital page of the JESD bank
Enable bit D0 overwrite
Select FOVR to replace bit D0
Pulse the IL RESET register bit. Register writes in
main digital page take effect when the IL RESET
register bit is pulsed.
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7.4.8 Power-Down Mode
The ADS54J66 provides a highly-configurable power-down mode. Power-down can be enabled using the PDN
pin or SPI register writes.
A power-down mask can be configured that allows a trade-off between wake-up time and power consumption in
power-down mode. Two independent power-down masks can be configured: MASK 1 and MASK 2, as shown in
Table 9. See the master page registers in Table 15 for further details.
Table 9. Register Address for Power-Down Modes
REGISTER
ADDRESS
A[7:0] (Hex)
REGISTER DATA
COMMENT
7
6
5
4
3
2
0
0
1
0
MASTER PAGE (80h)
20
MASK 1
21
23
MASK 2
24
PDN ADC CHAB
PDN BUFFER CHCD
PDN ADC CHAB
PDN BUFFER CHCD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PDN MASK
0
0
0
0
OVERRIDE
PDN PIN
PDN MASK
SEL
53
0
MASK
SYSREF
55
0
0
CONFIG
0
PDN ADC CHCD
PDN BUFFER CHAB
GLOBAL
PDN
26
PDN ADC CHCD
PDN BUFFER CHAB
To save power, the device can be put in complete power down by using the GLOBAL PDN register bit. However,
when JESD link must remain up when putting the device in power down, the ADC and analog buffer can be
powered down by using the PDN ADC CHx and PDN BUFFER CHx register bits after enabling the PDN MASK
register bit. The PDN MASK SEL register bit can be used to select between MASK 1 or MASK 2. Table 10
shows power consumption for different combinations of the GLOBAL PDN, PDN ADC CHx, and PDN BUFF CHx
register bits.
Table 10. Power Consumption in Different Power-Down Settings
REGISTER BIT
COMMENT
IAVDD3V
(mA)
IAVDD
(mA)
IDVDD
(mA)
IIOVDD
(mA)
TOTAL
POWER
(W)
Default
After reset, with a full-scale input signal to
both channels
0.340
0.365
0.184
0.533
2.675
GBL PDN = 1
The device is in complete power-down
state
0.002
0.006
0.012
0.181
0.247
GBL PDN = 0,
PDN ADC CHx = 1
(x = AB or CD)
The ADCs of one pair of channels are
powered down
0.277
0.225
0.123
0.496
2.063
GBL PDN = 0,
PDN BUFF CHx = 1
(x = AB or CD)
The input buffers of one pair of channels
are powered down
0.266
0.361
0.187
0.527
2.445
GBL PDN = 0,
PDN ADC CHx = 1,
PDN BUFF CHx = 1
(x = AB or CD)
The ADCs and input buffers of one pair of
channels are powered down
0.200
0.224
0.126
0.492
1.830
GBL PDN = 0,
PDN ADC CHx = 1,
PDN BUFF CHx = 1
(x = AB and CD)
The ADCs and input buffers of all channels
are powered down
0.060
0.080
0.060
0.448
0.960
30
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7.5 Programming
7.5.1 Device Configuration
The ADS54J66 can be configured using a serial programming interface, as described in this section. In addition,
the device has one dedicated parallel pin (PDN) for controlling the power-down modes. The ADS54J66 supports
a 24-bit (16-bit address, 8-bit data) SPI operation and uses paging (see the Detailed Register Information
section) to access all register bits. Figure 69 shows timing diagram for serial interface signals. SPI registers are
grouped in two banks with each bank containing different pages (see Figure 84).
First 4 MSBs of 16-bit address are special bits carrying information about register bank, page and channel to be
programmed. Table 11 lists the purpose of each special bit.
Register Address[11:0]
SDIN
R/W
M
P
CH
A11
A10
A9
A8
A7
A6
A5
A4
Register Data[7:0]
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
tDH
tSCLK
tDSU
SCLK
tSLOADS
tSLOADH
SEN
RESET
Figure 69. Serial Interface Timing Diagram
Table 11. Programing Details of Serial Interface
SPI BITS
DESCRIPTION
OPTIONS
Read/write bit
0 = SPI write
1 = SPI read back
M
SPI bank access
0 = Analog SPI bank (master and ADC page)
1 = Digital SPI bank (main digital, analog JESD, and
digital JESD pages)
P
JESD page selection bit
0 = Page access
1 = Register access
SPI access for a specific channel of the digital SPI
bank
0 = Channel AB
1 = Channel CD
By default, both channels are being addressed.
SPI address bits
—
SPI data bits
—
R/W
CH
ADDR [11:0]
DATA [7:0]
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7.5.1.1 Details of the Serial Interface
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock) and SDIN (serial interface data) pins. Serially shifting bits into the
device is enabled when SEN is low. Serial data on SDIN are latched at every SCLK rising edge when SEN is
active (low). The interface can function with SCLK frequencies from 5 MHz down to very low speeds (of a few
hertz) and also with a non-50% SCLK duty cycle.
Figure 74 shows timing requirements for serial interface signals.
Table 12. Serial Interface Timing Requirements (1)
MIN
MAX
UNIT
> dc
20
MHz
fSCLK
SCLK frequency (equal to 1 / tSCLK)
tSLOADS
SEN to SCLK setup time
25
ns
tSLOADH
SCLK to SEN hold time
25
ns
tDSU
SDATA setup time
25
ns
tDH
SDATA hold time
25
ns
(1)
Typical values are at 25°C. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = 100°C,
AVDD3V = 3 V, AVDD = 1.9 V, and DRVDD = 1.8 V, unless otherwise noted.
7.5.1.2 Serial Register Write: Analog Bank
The analog SPI bank contains of two pages (the master and ADC page). The internal register of the ADS54J66
analog SPI bank can be programmed by:
1. Drive the SEN pin low.
2. Initiate a serial interface cycle specifying the page address of the register whose content must be written.
– Master page: write address 0011h with 80h.
– ADC page: write address 0011h with 0Fh.
3. Write the register content as shown in Figure 70. When a page is selected, multiple writes into the same
page can be done.
SDIN
0
0
0
0
R/W
M
P
CH
Register Address[11:0]
A11
A10
A9
A8
A7
A6
A5
A4
Register Data[7:0]
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SEN
RESET
Figure 70. Serial Register Write Timing Diagram
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7.5.1.3 Serial Register Readout: Analog Bank
The content from one of the two analog banks can be read out by:
1. Drive the SEN pin low.
2. Select the page address of the register whose content must be read.
– Master page: write address 0011h with 80h.
– ADC page: write address 0011h with 0Fh.
3. Set the R/W bit to 1 and write the address to be read back.
4. Read back the register content on the SDOUT pin, as shown in Figure 71. When a page is selected, multiple
read backs from the same page can be done.
SDIN
1
0
0
0
R/W
M
P
CH
Register Address[11:0]
A11
A10
A9
A8
A7
A6
A5
A4
Register Data[7:0] = XX
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SEN
RESET
SDOUT
SDOUT[7:0]
Figure 71. Serial Register Read Timing Diagram
7.5.1.4 JESD Bank SPI Page Selection
The JESD SPI bank contains five pages (main digital, interleaving engine, decimation filter, JESD digital, and
JESD analog). The individual pages can be selected following these steps:
1. Drive the SEN pin low.
2. Set the M bit to 1 and specify the page with two register writes (Note: the P bit is set to 0)
– Write address 4003h with 00h (LSB byte of the page address)
– Write address 4004h MSB byte of the page address
spacer
– Main digital page: write address = 4004h with 68h (default)
– Digital JESD page: write address = 4004h with 69h
– Analog JESD page: write address = 4004h with 6Ah
– Interleaving engine page: write address = 4004h with 61h
– Decimation filter page: write address = 4004h with 61h and 4003h with 41h
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Figure 72 shows the serial interface signals when pages in the JESD bank are being accessed. Note that the P
bit is set to 0.
SDIN
0
1
0
0
R/W
M
P
CH
Register Address[11:0]
A11
A10
A9
A8
A7
A6
A5
A4
Register Data[7:0]
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SEN
RESET
Figure 72. SPI Timing Diagram for Accessing a Page in the JESD Bank
7.5.1.5 Serial Register Write: Digital Bank
The ADS54J66 is a quad-channel device and the JESD204B portion is configured individually for two channels
(A, B and C, D) using the CH bit. Note that the P bit must be set to 1 for register writes.
1. Drive the SEN pin low.
2. Select the JESD bank page (Note: M bit = 1, P bit = 0)
– Write address 4003h with 00h
– Main digital page: write address = 4004h with 68h (default)
– Digital JESD page: write address = 4004h with 69h
– Analog JESD page: write address = 4004h with 6Ah
– Interleaving Engine page: write address = 4004h with 61h
– Decimation Filter page: write address = 4004h with 61h and 4003h with 41h
3. Set the M and P bit to 1 and select channels A, B (CH = 0) or C, D (CH = 1) and write the register content.
When a page is selected, multiple writes into the same page can be done.
By default, register writes are applied to both channel pairs (broadcast mode). To disable broadcast mode
and enable individual channel writes, write address 4005h with 01h (default is 00h).
Figure 73 shows the serial interface signals when a register in the desired page of the JESD bank is
programmed (note that the P bit must be set to 1 in this step).
SDIN
0
1
1
0
R/W
M
P
CH
Register Address[11:0]
A11
A10
A9
A8
A7
A6
A5
A4
Register Data[7:0]
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SEN
RESET
Figure 73. SPI Timing Diagram for Writing a Register in the JESD Bank (After Page is Accessed)
7.5.1.6 Individual Channel Programming
By default, register writes are applied to both channels in a group (for example, the register writes are applied to
channels A and B if the CH bit is 0, or the register writes are applied to channels C and D if the CH bit is 1). This
form of programming is referred to as broadcast mode.
For pages located in the JESD bank, the device gives flexibility to program each channel individually. To enable
individual channel writes, write address 4005h with 01h (default is 00h).
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7.5.1.7 Serial Register Readout: JESD Bank
SPI read out of content in one of the three digital banks can be accomplished with the following steps:
1. Drive the SEN pin low.
2. Select the digital bank page (Note: M bit = 1, P bit = 0)
– Write address 4003h with 00h
– Main digital page: write address = 4004h with 68h
– Digital JESD page: write address = 4004h with 69h
– Analog JESD page: write address = 4004h with 6Ah
– Interleaving engine page: write address = 4004h with 61h
– Decimation filter page: write address = 4004h with 61h and 4003h with 41h
3. Set the R/W bit, M and P bit to 1 and select channels A, B or C, D and write the address to be read back.
4. Read back register content on the SDOUT pin. When a page is selected, multiple read backs from the same
page can be done.
Figure 74 shows the serial interface signals when the contents of a register in the desired page of the JESD
bank are being read-back (note that the P bit must be set to 1 in this step).
SDIN
1
1
1
0
R/W
M
P
CH
Register Address[11:0]
A11
A10
A9
A8
A7
A6
A5
A4
Register Data[7:0] = XX
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SEN
RESET
SDOUT
SDOUT[7:0]
Figure 74. Serial Register Read Timing Diagram
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7.5.2 JESD204B Interface
The ADS54J66 supports device subclass 1 with a maximum output data rate of 10 Gbps for each serial
transmitter. Figure 75 shows JESD20B block inside ADS54J66.
An external SYSREF signal is used to align all internal clock phases and the local multi frame clock to a specific
sampling clock edge. This process allows synchronization of multiple devices in a system and minimizes timing
and alignment uncertainty. The ADS54J66 supports single (for all four JESD links) or dual (for channel A, B and
C, D) SYNCb inputs and can be configured via SPI as shown in Figure 76.
JESD204B Block
Transport Layer
Link Layer
Frame Data
Mapping
8b/10b
Encoding
Scrambler
1+x14+x15
DX
Comma Characters
Initial Lane Alignment
Test Patterns
SYNCb
Figure 75. JESD Interface Block Diagram
SYSREF
SYNCbAB
INA
JESD
204B
JESD204B
DA
INB
JESD
204B
JESD204B
DB
INC
JESD
204B
JESD204B
DC
IND
JESD
204B
JESD204B
DD
Sample Clock
SYNCbCD
Figure 76. JESD204B Transmitter Block
Depending on the ADC sampling rate, the JESD204B output interface can be operated with one lane per
channel. The JESD204B setup and configuration of the frame assembly parameters is handled via SPI interface.
The JESD204B transmitter block consists of the transport layer, the data scrambler and the link layer. The
transport layer maps the ADC output data into the selected JESD204B frame data format and manages if the
ADC output data or test patterns are being transmitted. The link layer performs the 8b/10b data encoding as well
as the synchronization and initial lane alignment using the SYNC input signal. Optionally data from the transport
layer can be scrambled.
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7.5.2.1 JESD204B Initial Lane Alignment (ILA)
The initial lane alignment process is started by the receiving device by de-asserting the SYNCb signal. Upon
detecting a logic low on the SYNC input pins, the ADS54J66 starts transmitting comma (K28.5) characters to
establish code group synchronization as shown in Figure 77.
When synchronization is completed the receiving device re-asserts the SYNCb signal and the ADS54J66 starts
the initial lane alignment sequence with the next local multi frame clock boundary. The ADS54J66 transmits four
multi-frames each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame
start and end symbols and the second multi-frame also contains the JESD204 link configuration data.
SYSREF
LMFC Clock
LMFC Boundary
Multi
Frame
SYNCb
Transmit Data
xxx
K28.5
Code Group
Synchronization
K28.5
ILA
Initial Lane Alignment
ILA
DATA
DATA
Data Transmission
Figure 77. ILA Sequence
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7.5.2.2 JESD204B Frame Assembly
The JESD204B standard defines the following parameters:
• L is the number of lanes per link.
• M is the number of converters per device.
• F is the number of octets per frame clock period.
• S is the number of samples per frame.
Table 13 lists the available JESD204B formats and valid ranges for the ADS54J66. The ranges are limited by the
Serdes line rate and the maximum ADC sample frequency.
Table 13. Available JESD204B Formats and Valid Ranges for the ADS54J66
L
M
F
S
OPERATING
MODE
DIGITAL MODE
OUTPUT
FORMAT
JESD
MODE (1)
JESD PLL
MODE (2)
MAX ADC
OUTPUT
RATE (MSPS)
MAX fSERDES
(Gbps)
4
8
4
1
0,5
2x decimation
Complex
40x
40x
250
10.0
4
4
2
1
2,4
2x decimation
Real
20x
20x
250
5.0
2
4
4
1
2,4
2x decimation
Real
40x
40x
250
10.0
4
8
4
1
6
4x decimation
Complex
40x
20x
125
5.0
2
8
8
1
6
4x decimation
Complex
80x
40x
125
10.0
4
4
2
1
7
2x decimation with
0-pad
Real
20x
40x
500
10.0
4
4
2
1
8
No decimation
Real
20x
40x
500
10.0
(1)
(2)
In register 01h of the JESD digital page.
In register 16h of the JESD analog page.
The detailed frame assembly is shown in Table 14.
Table 14. Detailed Frame Assembly
LMFS = 4841
DA
LMFS = 4421
AI0[15:8]
AI0[7:0]
AQ0[15:8]
AQ0[7:0]
A0[15:8]
A0[7:0]
A1[15:8]
A1[7:0]
A0[15:8]
A0[7:0]
0000
0000
0000
0000
BI0[15:8]
BI0[7:0]
BQ0[15:8]
BQ0[7:0]
B0[15:8]
B0[7:0]
B1[15:8]
B1[7:0]
B0[15:8]
B0[7:0]
0000
0000
0000
0000
CI0[15:8]
CI0[7:0]
CQ0[15:8]
CQ0[7:0]
C0[15:8]
C0[7:0]
C1[15:8]
C1[7:0]
C0[15:8]
C0[7:0]
0000
0000
0000
0000
DI0[15:8]
DI0[7:0]
DQ0[15:8]
DQ0[7:0]
D0[15:8]
D0[7:0]
D1[15:8]
D1[7:0]
D0[15:8]
D0[7:0]
0000
0000
0000
0000
DB
A0[15:8]
A0[7:0]
B0[15:8]
B0[7:0]
AI0[15:8]
AI0[7:0]
AQ0[15:8]
AQ0[7:0]
BI0[15:8]
BI0[7:0]
BQ0[15:8]
BQ0[7:0]
DC
C0[15:8]
C0[7:0]
D0[15:8]
D0[7:0]
CI0[15:8]
CI0[7:0]
CQ0[15:8]
CQ0[7:0]
DI0[15:8]
DI0[7:0]
DQ0[15:8]
DQ0[7:0]
DB
DC
DD
LMFS = 2441
38
LMFS = 4421 (0-Pad)
LMFS = 2881
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7.5.2.3 JESD Output Switch
The ADS54J66 provides a digital cross point switch in the JESD204B block which allows internal routing of any
output of the two ADCs within one channel pair to any of the two JESD204B serial transmitters in order to ease
layout constraints. The cross-point switch routing is configured via SPI (address 21h in the JESD digital page, as
shown in Figure 78).
JESD Switch
ADCA
DAP,
DAM
ADCB
DBP,
DBM
JESD Switch
ADCC
DCP,
DCM
ADCD
DDP,
DDM
Figure 78. Switching the Output Lanes
7.5.2.3.1 SERDES Transmitter Interface
Each of the 10 Gbps serdes transmitter outputs requires ac coupling between transmitter and receiver. The
differential pair must be terminated with 100 Ω as close to the receiving device as possible to avoid unwanted
reflections and signal degradation as shown in Figure 79.
0.1 PF
DAP, DAB,
DAC, DAP
Rt = ZO
Transmission Line,
Zo
VCM
Receiver
Rt = ZO
DAM, DAB,
DAC, DAM
0.1 PF
Figure 79. SERDES Transmitter Connection to Receiver
7.5.2.3.2 SYNCb Interface
The ADS54J66 supports single (either SYNCb input controls all four JESD204B links) or dual (one SYNCb input
controls two JESD204B lanes (DA, DB and DC, DD) SYNCb control. When using single SYNCb control, connect
the unused input to differential logic low (SYNCbxxP = 0 V, SYNCbxxM = IOVDD).
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7.5.2.3.3 Eye Diagram
Figure 80 to Figure 83 show the serial output eye diagrams of the ADS54J66 at 5 Gbps and 10 Gbps with default
and increased output voltage swing against the JESD204B mask.
40
Figure 80. Eye at 5-Gbps Bit Rate with
Default Output Swing
Figure 81. Eye at 5-Gbps Bit Rate with
Increased Output Swing
Figure 82. Eye at 10-Gbps Bit Rate with
Default Output Swing
Figure 83. Eye at 10-Gbps Bit Rate with
Increased Output Swing
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7.6 Register Maps
The conceptual diagram of the serial registers is shown in Figure 84.
SPI Cycle Initiated
M, P, CH Bits Decoder
M=0
M=1
Analog Page Selection
JESD Bank Page Address
Value 6800h
Addr 20h
Addr 74h
Master Page
[PDN, OVR,
DC Coupling]
Addr 59h
Addr 18h
Addr 0h
Main Digital
Page
[Nyquist Zone,
OVR Select]
ADC Page
[Test Patterns,
Fast OVR]
Addr 78h
Addr F7h
Value 6100h
Decimation
Filter Page
[Signal
Processing
Modes 0 to 8]
Addr 02h
Value 6900h
Addr 0h
Addr 00h
IL Engine Page
[Engine Bypass,
DC Correction]
Addr 68h
Value 6141h
Addr 12h
JESD Analog
Page
[PLL Config,
Output Swing,
Pre-Emphasis]
JESD Digital
Page
[JESD Config]
Addr 22h
Value 6A00h
Addr 1Bh
Figure 84. Serial Interface Registers
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Register Maps (continued)
7.6.1 Detailed Register Information
The ADS54J66 contains two main SPI banks. The analog SPI bank gives access to the ADC cores and the digital SPI bank controls the serial interface.
The analog SPI bank is divided into two pages (master and ADC) and the digital SPI bank is divided into five pages (main digital, interleaving engine,
decimation filter, JESD digital, and JESD analog; see Figure 84). Table 15 gives a summary of all programmable registers in the pages of different banks
in the ADS54J66.
Table 15. Register Map
REGISTER ADDRESS
A[7:0] (Hex)
REGISTER DATA
7
6
5
4
3
2
1
0
RESET
0
0
0
0
0
0
RESET
0
0
DIS BROADCAST
0
0
GENERAL REGISTERS
0
3
JESD BANK PAGE SEL [7:0]
4
5
JESD BANK PAGE SEL [15:8]
0
0
0
0
11
0
ANALOG PAGE SELECTION [7:0]
MASTER PAGE (80h)
20
PDN ADC CHAB
21
PDN ADC CHCD
PDN BUFFER CHCD
PDN BUFFER CHAB
23
0
0
PDN ADC CHAB
24
PDN ADC CHCD
0
0
0
0
26
GLOBAL PDN
PDN BUFFER CHCD
OVERRIDE PDN PIN
PDN MASK SEL
0
0
0
0
0
3A
0
BUFFER CURR
INCREASE
0
0
0
0
0
0
39
PDN BUFFER CHAB
0
0
0
0
0
0
53
CLK DIV
ALWAYS WRITE 1
MASK SYSREF
0
0
0
0
0
0
55
0
0
0
PDN MASK
0
0
0
0
56
0
0
0
0
INPUT BUFF CURR EN
0
0
0
59
0
0
ALWAYS WRITE 1
0
0
0
0
0
60
PULSE BIT CHC
0
0
0
0
0
0
0
61
0
0
0
0
HD3 NYQ2 CHCD
0
0
PULSE BIT CHD
6C
PULSE BIT CHA
0
0
0
0
0
0
0
6D
0
0
0
0
HD3 NYQ2 CHAB
0
0
PULSE BIT CHB
0
0
0
0
0
0
0
0
ADC PAGE (0Fh)
5F
FOVR THRESH
74
TEST PATTERN ON CHANNEL
75
76
CUSTOM PATTERN 1 [13:6]
CUSTOM PATTERN 1 [5:0]
77
78
42
CUSTOM PATTERN 2 [13:6]
CUSTOM PATTERN 2 [5:0]
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Register Maps (continued)
Table 15. Register Map (continued)
REGISTER DATA
REGISTER ADDRESS
A[7:0] (Hex)
7
6
5
4
3
2
0
1
0
INTERLEAVING ENGINE PAGE (6100h)
18
0
0
0
0
0
68
0
0
0
0
0
1
0
0
0
0
DDC MODE6 EN1
2
0
0
CHA/D HPF EN
CHA/D COARSE MIX
IL BYPASS
DC CORR DIS
0
DECIMATION FILTER PAGE (6141h)
0
CHB/C FINE MIX
DDC MODE
ALWAYS WRITE 1
CHB/C HPF EN
CHB/C COARSE MIX
CHA/D FINE MIX
MAIN DIGITAL PAGE (6800h)
0
0
0
0
0
0
42
0
0
0
0
0
0
0
IL RESET
NYQUIST ZONE
4E
CTRL NYQUIST ZONE
0
0
0
0
0
0
0
AB
0
0
0
0
0
0
0
OVR EN
AD
0
0
0
0
F7
0
0
0
0
0
0
0
DIG RESET
0
CTRL K
JESD MODE EN
DDC MODE6 EN2
TESTMODE EN
0
LANE ALIGN
FRAME ALIGN
1
SYNC REG
SYNC REG EN
SYNCB SEL AB/CD
0
DDC MODE6 EN3
0
LINK LAYER RPAT
LMFC MASK RESET
0
OVR ON LSB
JESD DIGITAL PAGE (6900h)
2
LINK LAYER TESTMODE
3
FORCE LMFC COUNT
5
SCRAMBLE EN
0
0
6
0
0
0
19
0
0
0
0
RELEASE ILANE SEQ
0
0
0
0
0
FRAMES PER MULTI FRAME (K)
0
LC [27:24]
LC [23:16]
1B
LC [15:8]
1C
LC [7:0]
0
0
0
0
HC [27:24]
1E
HC [23:16]
1F
HC [15:8]
20
HC [7:0]
21
22
0
LMFC COUNT INIT
1A
1D
TX LINK DIS
JESD MODE
OUPUT CHA MUX SEL
0
OUTPUT CHB MUX SEL
0
0
OUTPUT CHC MUX SEL
0
OUT CHA INV
OUTPUT CHD MUX SEL
OUT CHB INV
OUT CHC INV
OUT CHD INV
0
JESD ANALOG PAGE (6A00h)
12
SEL EMP LANE A/D
0
13
SEL EMP LANE B/C
0
16
0
1B
0
JESD SWING
0
0
0
0
0
0
0
0
JESD PLL MODE
0
0
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7.6.2 Example Register Writes
Global power down:
ADDRESS
DATA
11h
80h
Set master page
COMMENT
00h26
80h
Set global power down
Change decimation mode 0 to mode 4 adjusting both the LMFS configuration (LMFS = 4841 to 4421) as well as
serial output data rate (10 Gbps to 5 Gbps):
44
ADDRESS
DATA
COMMENT
4004h
69h
4003h
00h
6000h
40h
Enables JESD mode overwrite
6001h
01h
Select digital to 20x mode
4004h
6Ah
Select analog JESD page
6016h
00h
Set serdes PLL to 20x mode
4004h
61h
4003h
41h
6000h
CCh
Select mode 4
Digital mixer for channel AB set to –4 (fS / 4)
6002h
0Ch
Digital mixer for channel CD set to –4 (fS / 4)
Select digital JESD page
Select decimation filter page
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7.6.3 Register Descriptions
7.6.3.1 General Registers
7.6.3.1.1 Register 0h (offset = 0h) [reset = 0h]
Figure 85. Register 0h
7
RESET
R/W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
RESET
R/W-0h
2
1
0
2
1
0
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 16. Register 0h Field Description
(1)
Bit
Name
Type
Reset
Description
7 (1)
RESET
R/W
0h
0 = Normal operation
1 = Internal software reset, clears back to 0
6-0
0
W
0h
Must write 0.
0 (1)
RESET
R/W
0h
0 = Normal operation
1 = Internal software reset, clears back to 0
Both bits (7, 0) must be set simultaneously to exercise reset.
7.6.3.1.2 Register 3h, 4h (offset = 3h, 4h) [reset = 0h]
Figure 86. Register 3h
7
6
5
4
3
JESD BANK PAGE SEL [7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 87. Register 4h
7
6
5
4
3
JESD BANK PAGE SEL [16:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 17. Register 3h, 4h Field Description
Bit
Name
Type
Reset
Description
7-0
JESD BANK PAGE SEL
R/W
0h
Program these bits to access the desired page in the JESD bank.
6100h = Interleaving engine page selected
6141h = Decimation filter page selected
6800h = Main digital page selected
6900h = JESD digital page selected
6A00h = JESD analog page selected
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7.6.3.1.3 Register 5h (offset = 5h) [reset = 0h]
Figure 88. Register 5h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
DIS BROADCAST
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 18. Register 5h Field Description
Bit
Name
Type
Reset
Description
7-1
0
W
0h
Must write 0.
DIS BROADCAST
R/W
0h
0 = Normal operation. Channel A and B are programmed as a pair. Channel
C and D are programmed as a pair.
1 = channel A and B can be individually programmed based on the CH bit.
Similarly channel C and D can be individually programmed based on the CH
bit.
0
7.6.3.1.4 Register 11h (offset = 11h) [reset = 0h]
Figure 89. Register 11h
7
6
5
4
3
ANALOG PAGE SELECTION [7:0]
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 19. Register 11h Field Descriptions
Bit
Name
Type
Reset
Description
7-0
ANALOG PAGE SELECTION [7:0]
R/W
0h
Register page (only one page at a time can be addressed).
Master page = 80h
ADC page = 0Fh
The five digital pages (main digital, interleaving engine, analog
JESD, digital JESD, and decimation filter) are selected via the
M bit. See Table 11 in the Details of the Serial Interface
section for more details.
7.6.3.2 Master Page (80h)
7.6.3.2.1 Register 20h (address = 20h) [reset = 0h], Master Page (080h)
Figure 90. Register 20h
7
6
5
PDN ADC CHAB
R/W-0h
4
3
2
1
PDN ADC CHCD
R/W-0h
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 20. Registers 20h Field Descriptions
46
Bit
Field
Type
Reset
Description
7-4
PDN ADC CHAB
R/W
0h
3-0
PDN ADC CHCD
R/W
0h
There are two power-down masks that are controlled via the
PDN mask register bit in address 55h. The power-down mask 1
or mask 2 are selected via register bit 5 in address 26h.
Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
See the Power-Down Mode section for details.
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7.6.3.2.2 Register 21h (address = 21h) [reset = 0h], Master Page (080h)
Figure 91. Register 21h
7
6
PDN BUFFER CHCD
R/W-0h
5
4
PDN BUFFER CHAB
R/W-0h
3
0
W-0h
2
0
R/W-0h
1
0
R/W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 21. Register 21h Field Descriptions
Bit
Field
Type
Reset
Description
7-6
PDN BUFFER CHCD
R/W
0h
5-4
PDN BUFFER CHAB
R/W
0h
There are two power-down masks that are controlled via the
PDN mask register bit in address 55h. The power-down mask 1
or mask 2 are selected via register address 26h, bit 5.
Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
See the Power-Down Mode section for details.
3-0
0
W
0h
Must write 0.
7.6.3.2.3 Register 23h (address = 23h), Master Page (080h)
Figure 92. Register 23h
7
6
5
PDN ADC CHAB
R/W-0h
4
3
W-0h
2
1
PDN ADC CHCD
R/W-0h
R/W-0h
0
W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 22. Register 23h Field Descriptions
Bit
Field
Type
Reset
Description
7-4
PDN ADC CHAB
R/W
0h
3-0
PDN ADC CHCD
R/W
0h
There are two power-down masks that are controlled via the
PDN mask register bit in address 55h. The power-down mask 1
or mask 2 are selected via register bit 5 in address 26h.
Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
See the Power-Down Mode section for details.
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7.6.3.2.4 Register 24h (address = 24h) [reset = 0h], Master Page (080h)
Figure 93. Register 24h
7
6
PDN BUFFER CHCD
R/W-0h
5
4
PDN BUFFER CHAB
R/W-0h
3
0
W-0h
2
0
R/W-0h
1
0
R/W-0h
0
0
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 23. Register 24h Field Descriptions
Bit
Field
Type
Reset
Description
7-6
PDN BUFFER CHCD
R/W
0h
5-4
PDN BUFFER CHAB
R/W
0h
There are two power-down masks that are controlled via the
PDN mask register bit in address 55h. The power-down mask 1
or mask 2 are selected via register address 26h, bit 5.
Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
See the Power-Down Mode section for details.
3-0
0
W
0h
Must write 0.
7.6.3.2.5 Register 26h (address = 26h), Master Page (080h)
Figure 94. Register 26h
7
GLOBAL PDN
R/W-0h
6
OVERRIDE PDN PIN
R/W-0h
5
PDN MASK SEL
R/W-0h
4
0
R/W-0h
3
0
R/W-0h
2
0
R/W-0h
1
0
R/W-0h
0
0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 24. Register 26h Field Descriptions
Bit
Field
Type
Reset
Description
7
GLOBAL PDN
R/W
0h
Bit 6 (OVERRIDE PDN PIN) must be set before this bit can be
programmed.
0 = Normal operation
1 = Global power-down via the SPI
6
OVERRIDE PDN PIN
R/W
0h
This bit ignores the power-down pin control.
0 = Normal operation
1 = Ignores inputs on the power-down pin
5
PDN MASK SEL
R/W
0h
This bit selects power-down mask 1 or mask 2.
0 = Power-down mask 1
1 = Power-down mask 2
0
R/W
0h
Must write 0
4-0
48
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7.6.3.2.6 Register 3Ah (address = 3Ah) [reset = 0h], Master Page (80h)
Figure 95. Register 3Ah
7
0
W-0h
6
BUFFER CURR INCREASE
R/W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 25. Register 3Ah Field Descriptions
Bit
Name
Type
Reset
Description
7
0
W
0h
Must write 0.
6
BUFFER CURR INCREASE
R/W
0h
0 = Normal operation
1 = Increases AVDD3V current by 30 mA., improves HD3, helpful for
second Nyquist application. Ensure that the INPUT BUF CUR EN
regiser bit is also set to 1.
0
W
0h
Must write 0.
5-0
7.6.3.2.7 Register 39h (address = 39h) [reset = 0h], Master Page (80h)
Figure 96. Register 39h
7
6
ALWAYS WRITE 1
R/W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 26. Register 39h Field Descriptions
Bit
Name
Type
Reset
Description
7-6
ALWAYS WRITE 1
R/W
0h
Always set these bits to 11.
5-0
0
W
0h
Must write 0.
7.6.3.2.8 Register 53h (address = 53h) [reset = 0h], Master Page (80h)
Figure 97. Register 53h Register
7
CLK DIV
R/W-0h
6
MASK SYSREF
R/W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 27. Register 53h Field Descriptions
Bit
Name
Type
Reset
Description
7
CLK DIV
R/W
0h
This bit configures the input clock divider.
0 = Divide-by-4
1= Divide-by-2 (must be enabled for proper operation of the ADS54J66)
6
MASK SYSREF
R/W
0h
0 = Normal operation
1 = Ignores the SYSREF input
0
W
0h
Must write 0.
5-0
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7.6.3.2.9 Register 55h (address = 55h) [reset = 0h], Master Page (80h)
Figure 98. Register 55h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
PDN MASK
R/W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 28. Register 55h Field Descriptions
Bit
Name
Type
Reset
Description
7-5
0
W
0h
Must write 0.
PDN MASK
R/W
0h
Power-down via register bit.
0 = Normal operation
1 = Power down enabled powering down internal blocks specified in the
selected power-down mask
0
W
0h
Must write 0.
4
3-0
7.6.3.2.10 Register 56h (address = 56h) [reset = 0h], Master Page (80h)
Figure 99. Register 56h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
INPUT BUFF CURR EN
R/W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 29. Register 56h Field Descriptions
Bit
Name
Type
Reset
Description
7-4
0
W
0h
Must write 0.
INPUT BUFF CURR EN
R/W
0h
0 = Normal operation
1 = Increases AVDD3V current by 30 mA., improves HD3, helpful for
second Nyquist application. Ensure that the BUFFER CURR INCREASE
register bit is also set to 1.
0
W
0h
Must write 0.
3
2-0
7.6.3.2.11 Register 59h (address = 59h) [reset = 0h], Master Page (80h)
Figure 100. Register 59h
7
0
W-0h
6
0
W-0h
5
ALWAYS WRITE 1
R/W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 30. Register 59h Field Descriptions
Bit
Name
Type
Reset
Description
7-6
0
W
0h
Must write 0.
ALWAYS WRITE 1
R/W
0h
Always set this bit to 1.
0
W
0h
Must write 0.
5
4-0
50
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7.6.3.3 ADC Page (0Fh)
7.6.3.3.1 Register 5Fh (address = 5Fh) [reset = 0h], ADC Page (0Fh)
Figure 101. Register 5Fh
7
6
5
4
3
2
1
0
FOVR THRESH
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 31. Register 5Fh Field Descriptions
Bit
Name
Type
Reset
Description
7-0
FOVR THRESH
R/W
0h
These bits control the location of FAST OVR threshold for all four channels
together; see the Overrange Indication section.
7.6.3.3.2 Register 60h (address = 60h) [reset = 0h], ADC Page (0Fh)
Figure 102. Register 60h
7
PULSE BIT CHC
R/W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 32. Register 60h Field Descriptions
Bit
7
6-0
(1)
Name
Type
Reset
Description
PULSE BIT CHC
R/W
0h
Pulse this bit to improve HD3 for 2nd Nyquist frequencies (fIN > 250 MHz) for
channel C. (1)
Before pulsing this bit, the HD3 NYQ2 CHCD register bit must be set to 1.
0
W
0h
Must write 0.
Pulsing = set the bit to 1 and then reset to 0.
7.6.3.3.3 Register 61h (address = 61h) [reset = 0h], ADC Page (0Fh)
Figure 103. Register 61h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
HD3 NYQ2 CHCD
R/W-0h
2
0
W-0h
1
0
W-0h
0
PULSE BIT CHD
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 33. Register 61h Field Descriptions
Bit
Name
Type
Reset
Description
7-4
0
W
0h
Must write 0.
HD3 NYQ2 CHCD
R/W
0h
Set this bit to improve HD3 for 2nd Nyquist frequencies (fIN > 250 MHz) for
channel C and D. When this bit is set, the PULSE BIT CHx register bits must
be pulsed to obtain the improvement in corresponding channels.
0
W
0h
Must write 0.
PULSE BIT CHD
R/W
0h
Pulse this bit to improve HD3 for 2nd Nyquist frequencies (fIN > 250 MHz) for
channel D. (1)
Before pulsing this bit, the HD3 NYQ2 CHCD register bit must be set to 1.
3
2-1
0
(1)
Pulsing = set the bit to 1 and then reset to 0.
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7.6.3.3.4 Register 6Ch (address = 6Ch) [reset = 0h], ADC Page (0Fh)
Figure 104. Register 6Ch
7
PULSE BIT CHA
R/W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 34. Register 6Ch Field Descriptions
Bit
7
6-0
(1)
Name
Type
Reset
Description
PULSE BIT CHA
R/W
0h
Pulse this bit to improve HD3 for 2nd Nyquist frequencies (fIN > 250 MHz) for
channel A. (1)
Before pulsing this bit, the HD3 NYQ2 CHCAB register bit must be set to 1.
0
W
0h
Must write 0.
Pulsing = set the bit to 1 and then reset to 0.
7.6.3.3.5 Register 6Dh (address = 6Dh) [reset = 0h], ADC Page (0Fh)
Figure 105. Register 6Dh
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
HD3 NYQ2 CHAB
R/W-0h
2
0
W-0h
1
0
W-0h
0
PULSE BIT CHB
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 35. Register 6Dh Field Descriptions
Bit
Name
Type
Reset
Description
7-4
0
W
0h
Must write 0.
HD3 NYQ2 CHAB
R/W
0h
Set this bit to improve HD3 for 2nd Nyquist frequencies (fIN > 250 MHz) for
channel A and B. When this bit is set, the PULSE BIT CHx register bits must
be pulsed to obtain the improvement in corresponding channels.
0
W
0h
Must write 0.
PULSE BIT CHB
R/W
0h
Pulse this bit to improve HD3 for 2nd Nyquist frequencies (fIN > 250 MHz) for
channel B. (1)
Before pulsing this bit, the HD3 NYQ2 CHAB register bit must be set to 1.
3
2-1
0
(1)
52
Pulsing = set the bit to 1 and then reset to 0.
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7.6.3.3.6 Register 74h (address = 74h) [reset = 0h], ADC Page (0Fh)
Figure 106. Register 74h
7
6
5
TEST PATTERN ON CHANNEL
R/W-0h
4
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 36. Register 74h Field Descriptions
Bit
Field
Type
Reset
Description
7-4
TEST PATTERN ON CHANNEL
R/W
0h
Test pattern output on channel A and B
0000 = Normal operation using ADC output data
0001 = Outputs all 0s
0010 = Outputs all 1s
0011 = Outputs toggle pattern: Output data are an alternating
sequence of 101010101010 and 010101010101
0100 = Output digital ramp: output data increment by one LSB
every clock cycle from code 0 to 16384
0110 = Single pattern: output data are custom pattern 1 (75h
and 76h)
0111 = Double pattern: output data alternate between custom
pattern 1 and custom pattern 2
1000 = Deskew pattern: output data are 2AAAh
1001 = SYNC pattern: output data are 3FFFh
See the ADC Test Pattern section for more details.
3-0
0
W
0h
Must write 0.
7.6.3.3.7 Register 75h (address = 75h) [reset = 0h], ADC Page (0Fh)
Figure 107. Register 75h
7
6
5
4
3
CUSTOM PATTERN 1[13:6]
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 37. Register 75h Field Descriptions
Bit
Name
Type
Reset
Description
7-0
CUSTOM PATTERN
R/W
0h
These bits set the custom pattern (13-6) for all channels; see the ADC Test
Pattern section for more details.
7.6.3.3.8 Register 76h (address = 76h) [reset = 0h], ADC Page (0Fh)
Figure 108. Register 76h
7
6
5
4
CUSTOM PATTERN 1[ 5:0]
R/W-0h
3
2
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 38. Register 76h Field Descriptions
Bit
Name
Type
Reset
Description
7-2
CUSTOM PATTERN
R/W
0h
These bits set the custom pattern (5-0) for all channels; see the ADC Test
Pattern section for more details.
1-0
0
W
0h
Must write 0.
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7.6.3.3.9 Register 77h (address = 77h) [reset = 0h], ADC Page (0Fh)
Figure 109. Register 77h
7
6
5
4
3
CUSTOM PATTERN 2[13:6]
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 39. Register 77h Field Descriptions
Bit
Name
Type
Reset
Description
7-0
CUSTOM PATTERN
R/W
0h
These bits set the custom pattern (13-6) for all channels; see the ADC Test
Pattern section for more details.
7.6.3.3.10 Register 78h (address = 78h) [reset = 0h], ADC Page (0Fh)
Figure 110. Register 78h
7
6
5
4
CUSTOM PATTERN 2[ 5:0]
R/W-0h
3
2
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 40. Register 78h Field Descriptions
54
Bit
Name
Type
Reset
Description
7-2
CUSTOM PATTERN
R/W
0h
These bits set the custom pattern (5-0) for all channels; see the ADC Test
Pattern section for more details.
1-0
0
W
0h
Must write 0.
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7.6.3.4 Interleaving Engine Page (6100h)
7.6.3.4.1 Register 18h (address = 18h) [reset = 0h], Interleaving Engine Page (6100h)
Figure 111. Register 18h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
IL BYPASS
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 41. Register 18h Field Descriptions
Bit
Name
Type
Reset
Description
7-2
0
W
0h
Must write 0.
1-0
IL BYPASS
R/W
0h
These bits allow bypassing of the interleaving correction, which is to be
used when ADC test patterns are enabled.
00 = Interleaving correction enabled
11 = Interleaving correction bypassed
7.6.3.4.2 Register 68h (address = 68h) [reset = 0h], Interleaving Engine Page (6100h)
Figure 112. Register 68h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
1
DC CORR DIS
R/W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 42. Register 68h Field Descriptions
Bit
Name
Type
Reset
Description
7-3
0
W
0h
Must write 0.
2-1
DC CORR DIS
R/W
0h
These bits enable the dc offset correction loop.
00 = DC offset correction enabled
11 = DC offset correction disabled
Others = Do not use
0
W
0h
Must write 0.
0
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7.6.3.5 Decimation Filter Page (6141h) Registers
7.6.3.5.1 Register 0h (address = 0h) [reset = 0h], Decimation Filter Page (6141h)
Figure 113. Register 0h
7
6
5
CHB/C FINE MIX
R/W-0h
4
3
2
1
0
DDC MODE
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 43. 0h Field Descriptions
Bit
Field
Type
Reset
Description
7-4
CHB/C FINE MIX
R/W
0h
These bits select fine mixing frequency for the N × fS / 16 mixer, where N is a twos
complement number varying from –8 to 7.
0000 = N is 0
0001 = N is 1
0010 = N is 2
...
0111 = N is 7
1000 = N is –8
...
1111 = N is –1
3-0
DDC MODE
R/W
0h
These bits select DDC mode for all channels; see Table 44 for bit settings.
Table 44. DDC MODE Bit Settings
SETTING
MODE
000
0
fS / 4 mixing with decimation-by-2, complex output
001
–
N/A
010
2
Decimation-by-2, high or low pass filter, real output
011
–
N/A
100
4
Decimation-by-2, N × fS / 16 mixer, real output
101
5
Decimation-by-2, N × fS / 16 mixer, complex output
6
Decimation-by-4, N × fS / 16 mixer, complex output. Ensure that the
DDC MODE 6 EN[3:1] register bits are also set to 111.
111
7
Decimation-by-2, N × fS / 16 mixer, insert 0, real output
1000
8
No decimation, no mixing, straight 500-MSPS data output
Others
–
Do not use
110
56
DESCRIPTION
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7.6.3.5.2 Register 1h (address = 1h) [reset = 0h], Decimation Filter Page (6141h)
Figure 114. Register 1h
7
6
5
4
0
0
0
0
W-0h
W-0h
W-0h
W-0h
3
DDC MODE6
EN1
R/W-0h
2
ALWAYS
WRITE 1
R/W-0h
1
CHB/C HPF EN
R/W-0h
0
CHB/C
COARSE MIX
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 45. Register 1h Field Descriptions
Bit
Name
Type
Reset
Description
7-4
0
W
0h
Must write 0.
3
DDC MODE6 EN1
R/W
0h
Set this bit along with the DDC MODE6 EN2 and DDC MODE6
EN3 register bits for proper operation of mode 6.
0 = Default
1 = Use for proper operation of DDC mode 6
2
ALWAYS WRITE 1
R/W
0h
Always write this bit to 1.
1
CHB/C HPF EN
R/W
0h
This bit enables the high-pass filter for DDC mode 2 for channel
B and C.
0 = Low-pass filter enabled
1 = High-pass filter enabled
0
CHB/C COARSE MIX
R/W
0h
This bit selects the fS / 4 mixer phase for DDC mode 0 for
channel B and C.
0 = Mix with fS / 4
1 = Mix with –fS / 4
7.6.3.5.3 Register 2h (address = 2h) [reset = 0h], Decimation Filter Page (6141h)
Figure 115. Register 2h
7
6
5
0
0
CHA/D HPF EN
W-0h
W-0h
R/W-0h
4
CHA/D
COARSE MIX
R/W-0h
3
2
1
0
CHA/D FINE MIX
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 46. 2h Field Descriptions
Bit
Name
Type
Reset
Description
7-6
0
W
0h
Must write 0.
5
CHA/D HPF EN
R/W
0h
This bit enables the high-pass filter for DDC mode 2 for channel
A and D.
0 = Low-pass filter enabled
1 = High-pass filter enabled
4
CHA/D COARSE MIX
R/W
0h
This bit selects the fS / 4 mixer phase for DDC mode 0 for
channel A and D.
0 = Mix with fS / 4
1 = Mix with –fS / 4
CHA/D FINE MIX
R/W
0h
These bits select the fine mixing frequency for the N × fS / 16
mixer, where N is a twos complement number varying from –8 to
7.
0000 = N is 0
0001 = N is 1
0010 = N is 2
...
0111 = N is 7
1000 = N is –8
...
1111 = N is –1
3-0
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7.6.3.6 Main Digital Page (6800h) Registers
7.6.3.6.1 Register 0h (address = 0h) [reset = 0h], Main Digital Page (6800h)
Figure 116. Register 0h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
IL RESET
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 47. Register 0h Field Descriptions
Bit
Name
Type
Reset
Description
7-1
0
W
0h
Must write 0.
IL RESET
R/W
0h
This bit resets the interleaving engine. This bit is not a selfclearing bit and must be pulsed (1).
Any register bit in the main digital page (6800h) takes effect only
after this bit is pulsed. Also, note that pulsing this bit clears
registers in the interleaving page (6100h).
0 = Normal operation
0 → 1 → 0 = Interleaving engine reset
0
(1)
Pulsing = set the bit to 1 and then reset to 0.
7.6.3.6.2 Register 42h (address = 42h) [reset = 0h], Main Digital Page (6800h)
Figure 117. Register 42h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
1
NYQUIST ZONE
R/W-0h
0
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 48. Register 42h Field Descriptions
Bit
Name
Type
Reset
Description
7-3
0
W
0h
Must write 0.
2-0
NYQUIST ZONE
R/W
0h
These bits provide Nyquist zone information to the interleaving engine. Ensure
that the CTRL NYQUIST register bit is set to 1.
000 = 1st Nyquist zone (input frequencies between 0 to fS / 2)
001 = 2nd Nyquist zone (input frequencies between fS / 2 to fS)
010 = 3rd Nyquist zone (input frequencies between fS to 3 fS / 2)
...
111 = 8th Nyquist zone (input frequencies between 7 fS / 2 to 4 fS)
7.6.3.6.3 Register 4Eh (address = 4Eh) [reset = 0h], Main Digital Page (6800h)
Figure 118. Register 4Eh
7
CTRL NYQUIST
R/W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 49. Register 4Eh Field Descriptions
Bit
7
6-0
58
Name
Reset
Description
CTRL NYQUIST R/W
Type
0h
Enables Nyquist zone control using register bits NYQUIST ZONE.
0 = Selection disabled
1 = Selection enabled
0
0h
Must write 0.
W
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7.6.3.6.4 Register ABh (address = ABh) [reset = 0h], Main Digital Page (6800h)
Figure 119. Register ABh
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
OVR EN
R/W-0h
1
0
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 50. Register ABh Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0.
OVR EN
R/W
0h
Set this bit to enable the OVR ON LSB register bit.
0 = Normal operation
1 = OVR ON LSB enabled
0
7.6.3.6.5 Register ADh (address = ADh) [reset = 0h], Main Digital Page (6800h)
Figure 120. Register ADh
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
2
OVR ON LSB
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 51. Register ADh Field Descriptions
Bit
Field
Type
Reset
Description
7-4
0
W
0h
Must write 0.
3-0
OVR EN
R/W
0h
Set this bit to bring OVR on two LSBs of the 16-bit output. Ensure that the OVR EN
register bit is set to 1.
0000 = Bits 0 and 1 of the 16-bit data are noise bits
0011 = OVR comes on bit 0 of the 16-bit data
1100 = OVR comes on bit 1 of the 16-bit data
1111 = OVR comes on both bits 0 and 1 of the 16-bit data
7.6.3.6.6 Register F7h (address = F7h) [reset = 0h], Main Digital Page (68h)
Figure 121. Register F7h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
DIG RESET
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 52. Register F7h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0.
DIG RESET
R/W
0h
Self-clearing reset for the digital block. Does not include the interleaving correction.
0 = Normal operation
1 = Digital reset
0
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7.6.3.7 JESD Digital Page (6900h) Registers
7.6.3.7.1 Register 0h (address = 0h) [reset = 0h], JESD Digital Page (6900h)
Figure 122. Register 0h
7
6
JESD MODE
EN
R/W-0h
CTRL K
R/W-0h
5
DDC MODE6
EN2
R/W-0h
4
TESTMODE
EN
R/W-0h
3
2
1
0
0
LANE ALIGN
FRAME ALIGN
TX LINK DIS
W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 53. Register 0h Field Descriptions
Bit
60
Name
Type
Reset
Description
7
CTRL K
R/W
0h
Enable bit for a number of frames per multi frame.
0 = Default is five frames per multi frame
1 = Frames per multi frame can be set in register 06h
6
JESD MODE EN
R/W
0h
Allows changing the JESD MODE setting in register 01h (bits 1-0)
0 = Disabled
1 = Enables changing the JESD MODE setting
5
DDC MODE6 EN2
R/W
0h
Set this bit along with the DDC MODE6 EN1 and DDC MODE6 EN3 register
bits for proper operation of mode 6.
0 = Default
1 = Use for proper operation of DDC mode 6
4
TESTMODE EN
R/W
0h
This bit generates the long transport layer test pattern mode, as per section
5.1.6.3 of the JESD204B specification.
0 = Test mode disabled
1 = Test mode enabled
3
0
W
0h
Must write 0.
2
LANE ALIGN
R/W
0h
This bit inserts the lane alignment character (K28.3) for the receiver to align to
lane boundary, as per section 5.3.3.5 of the JESD204B specification.
0 = Normal operation
1 = Inserts lane alignment characters
1
FRAME ALIGN
R/W
0h
This bit inserts the lane alignment character (K28.7) for the receiver to align to
lane boundary, as per section 5.3.3.5 of the JESD204B specification.
0 = Normal operation
1 = Inserts frame alignment characters
0
TX LINK DIS
R/W
0h
This bit disables sending the initial link alignment (ILA) sequence when SYNC is
de-asserted.
0 = Normal operation
1 = ILA disabled
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7.6.3.7.2 Register 1h (address = 1h) [reset = 0h], JESD Digital Page (6900h)
Figure 123. Register 1h
7
6
SYNC REG
SYNC REG EN
R/W-0h
R/W-0h
5
SYNCB SEL
AB/CD
R/W-0h
4
0
W-0h
3
DDC MODE6
EN3
R/W-0h
2
1
0
0
JESD MODE
W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 54. Register 1h Field Descriptions
Bit
Name
Type
Reset
Description
7
SYNC REG
R/W
0h
SYNC register (bit 6 must be enabled).
0 = Normal operation
1 = ADC output data are replaced with K28.5 characters
6
SYNC REG EN
R/W
0h
Enables bit for SYNC operation.
0 = Normal operation
1 = ADC output data overwrite enabled
5
SYNCB SEL AB/CD
R/W
0h
This bit selects which SYNCb input controls the JESD interface; must be
configured for ch AB and ch CD.
0 = SYNCbAB
1 = SYNCbCD
4
0
W
0h
Must write 0.
3
DDC MODE6 EN3
R/W
0h
Set this bit along with the DDC MODE6 EN1 and DDC MODE6 EN2 register
bits for proper operation of mode 6.
0 = Default
1 = Use for proper operation of DDC mode 6
2
0
W
0h
Must write 0.
JESD MODE
R/W
0h
These bits select the number of serial JESD output lanes per ADC. The JESD
MODE EN (00h) and JESD PLL MODE register (JESD ANALOG page, register
16h) must also be set accordingly.
01 = 20x mode
10 = 40x mode
11 = 80x mode
All others = Not used
1-0
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7.6.3.7.3 Register 2h (address = 2h) [reset = 0h], JESD Digital Page (6900h)
Figure 124. Register 2h
7
6
5
4
LINK LAYER
RPAT
R/W-0h
LINK LAYER TESTMODE
R/W-0h
3
LMFC MASK
RESET
R/W-0h
2
1
0
0
W-0h
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 55. Register 2h Field Descriptions
Bit
Name
Type
Reset
Description
7-5
LINK LAYER TESTMODE
R/W
0h
These bits generate a pattern according to clause 5.3.3.8.2 of
the JESD204B document.
000 = Normal ADC data
001 = D21.5 (high-frequency jitter pattern)
010 = K28.5 (mixed-frequency jitter pattern)
011 = Repeat initial lane alignment (generates a K28.5 character
and continuously repeats lane alignment sequences)
100 = 12-octet RPAT jitter pattern
4
LINK LAYER RPAT
R/W
0h
This bit changes the running disparity in the modified RPAT
pattern test mode (only when the link layer test mode = 100).
0 = Normal operation
1 = Changes disparity
3
LMFC MASK RESET
R/W
0h
0 = Default
1 = Resets the LMFC mask
0
W
0h
Must write 0.
2-0
7.6.3.7.4 Register 3h (address = 3h) [reset = 0h], JESD Digital Page (6900h)
Figure 125. Register 3h
7
FORCE LMFC COUNT
R/W-0h
6
5
4
LMFC COUNT INIT
R/W-0h
3
2
1
0
RELEASE ILANE SEQ
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 56. Register 3h Field Descriptions
Bit
Name
Type
Reset
Description
FORCE LMFC COUNT
R/W
0h
This bit forces the LMFC count.
0 = Normal operation
1 = Enables using a different starting value for the LMFC
counter
6-2
LMFC COUNT INIT
R/W
0h
SYSREF coming to the digital block resets the LMFC count to 0
and K28.5 stops coming when the LMFC count reaches 31. The
initial value that the LMFC count resets to can be set using
LMFC COUNT INIT. In this manner, Rx can be synchronized
early because it receives the LANE ALIGNMENT SEQUENCE
early. The FORCE LMFC COUNT register bit must be enabled.
1-0
RELEASE ILANE SEQ
R/W
0h
These bits delay the generation of lane alignment sequence by
0, 1, 2, or 3 multi frames after code group synchronization.
00 = 0
01 = 1
10 = 2
11 = 3
7
62
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7.6.3.7.5 Register 5h (address = 5h) [reset = 0h], JESD Digital Page (6900h)
Figure 126. Register 5h
7
SCRAMBLE EN
R/W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 57. Register 5h Field Descriptions
Bit
7
6-0
Name
Type
Reset
Description
SCRAMBLE EN
R/W
0h
Scramble enable bit in the JESD204B interface.
0 = Scrambling disabled
1 = Scrambling enabled
0
W
0h
Must write 0.
7.6.3.7.6 Register 6h (address = 6h) [reset = 0h], JESD Digital Page (6900h)
Figure 127. Register 6h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
3
2
1
FRAMES PER MULTI FRAME (K)
R/W-0h
0
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 58. Register 6h Field Descriptions
Bit
Name
Type
Reset
Description
7-5
0
W
0h
Must write 0.
4-0
FRAMES PER MULTI FRAME (K)
R/W
0h
These bits set the number of multi frames.
Actual K is the value in hex + 1 (that is, 0Fh is K = 16).
7.6.3.7.7 Register 19h (address = 19h) [reset = 0h], JESD Digital Page (6900h)
Figure 128. Register 19h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
2
1
0
LC[27:24]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 59. Register 19h Field Descriptions
Bit
Name
Type
Reset
Description
7-4
0
W
0h
Must write 0.
3-0
LC[27:24]
R/W
0h
These bits set the low resolution counter value. When programming
LC[27:0], first program LC[7:0], then LC[15:8], then LC[23:16], and then
LC[27:24] in the same order.
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7.6.3.7.8 Register 1Ah (address = 1Ah) [reset = 0h], JESD Digital Page (6900h)
Figure 129. Register 1Ah
7
6
5
4
3
2
1
0
LC[23:16]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 60. 1Ah Field Descriptions
Bit
Name
Type
Reset
Description
7-0
LC[23:16]
R/W
0h
These bits set the low resolution counter value. When programming
LC[27:0], first program LC[7:0], then LC[15:8], then LC[23:16], and then
LC[27:24] in the same order.
7.6.3.7.9 Register 1Bh (address = 1Bh) [reset = 0h], JESD Digital Page (6900h)
Figure 130. Register 1Bh
7
6
5
4
3
2
1
0
LC[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 61. Register 1Bh Field Descriptions
Bit
Name
Type
Reset
Description
7-0
LC[15:8]
R/W
0h
These bits set the low resolution counter value. When programming
LC[27:0], first program LC[7:0], then LC[15:8], then LC[23:16], and then
LC[27:24] in the same order.
7.6.3.7.10 Register 1Ch (address = 1Ch) [reset = 0h], JESD Digital Page (6900h)
Figure 131. Register 1Ch
7
6
5
4
3
2
1
0
LC[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 62. Register 1Ch Field Descriptions
64
Bit
Name
Type
Reset
Description
7-0
LC[7:0]
R/W
0h
These bits set the low resolution counter value. When programming
LC[27:0], first program LC[7:0], then LC[15:8], then LC[23:16], and then
LC[27:24] in the same order.
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7.6.3.7.11 Register 1Dh (address = 1Dh) [reset = 0h], JESD Digital Page (6900h)
Figure 132. Register 1Dh
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
2
1
0
HC[27:24]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 63. Register 1Dh Field Descriptions
Bit
Name
Type
Reset
Description
7-4
0
W
0h
Must write 0.
3-0
HC [xx:xx]
R/W
0h
These bits set the high resolution counter value. When programming
HC[27:0], first program HC[7:0], then HC[15:8], then HC[23:16], and then
HC[27:24] in the same order.
7.6.3.7.12 Register 1Eh (address = 1Eh) [reset = 0h], JESD Digital Page (6900h)
Figure 133. Register 1Eh
7
6
5
4
3
2
1
0
HC[23:16]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 64. Register 1Eh Field Descriptions
Bit
Name
Type
Reset
Description
7-0
HC[23:16]
R/W
0h
These bits set the high resolution counter value. When programming
HC[27:0], first program HC[7:0], then HC[15:8], then HC[23:16], and then
HC[27:24] in the same order.
7.6.3.7.13 Register 1Fh (address = 1Fh) [reset = 0h], JESD Digital Page (6900h)
Figure 134. Register 1Fh
7
6
5
4
3
2
1
0
HC[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 65. Register 1Fh Field Descriptions
Bit
Name
Type
Reset
Description
7-0
HC[15:8]
R/W
0h
These bits set the high resolution counter value. When programming
HC[27:0], first program HC[7:0], then HC[15:8], then HC[23:16], and then
HC[27:24] in the same order.
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7.6.3.7.14 Register 20h (address = 20h) [reset = 0h], JESD Digital Page (6900h)
Figure 135. Register 20h
7
6
5
4
3
2
1
0
HC[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 66. Register 20h Field Descriptions
Bit
Name
Type
Reset
Description
7-0
HC[7:0]
R/W
0h
These bits set the high resolution counter value. When programming
HC[27:0], first program HC[7:0], then HC[15:8], then HC[23:16], and then
HC[27:24] in the same order.
7.6.3.7.15 Register 21h (address = 21h) [reset = 0h], JESD Digital Page (6900h)
Figure 136. Register 21h
7
6
OUTPUT CHA MUX SEL
R/W-0h
5
4
OUTPUT CHB MUX SEL
R/W-0h
3
2
OUTPUT CHC MUX SEL
R/W-0h
1
0
OUTPUT CHD MUX SEL
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 67. 21h Field Descriptions
66
Bit
Name
Type
Reset
Description
7-6
OUTPUT CHA MUX SEL
R/W
0h
SERDES lane swap with ch B.
00 = Ch A is output on lane DA
10 = Ch A is output on lane DB
01, 11 = Do not use
5-4
OUTPUT CHB MUX SEL
R/W
0h
SERDES lane swap with ch A.
00 = Ch B is output on lane DB
10 = Ch B is output on lane DA
01, 11 = Do not use
3-2
OUTPUT CHC MUX SEL
R/W
0h
SERDES lane swap with ch D.
00 = Ch C is output on lane DC
10 = Ch C is output on lane DD
01, 11 = Do not use
1-0
OUTPUT CHD MUX SEL
R/W
0h
SERDES lane swap with ch C.
00 = Ch D is output on lane DD
10 = Ch D is output on lane DC
01, 11 = Do not use
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7.6.3.7.16 Register 22h (address = 22h) [reset = 0h], JESD Digital Page (6900h)
Figure 137. Register 22h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
OUT CHA INV
R/W-0h
2
OUT CHB INV
R/W-0h
1
OUT CHC INV
R/W-0h
0
OUT CHD INV
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 68. 22h Field Descriptions
Bit
Name
Type
Reset
Description
7-4
0
W
0h
Must write 0.
3
OUT CHA INV
R/W
0h
Polarity inversion of JESD output of ch A.
0 = Normal operation
1 = Output polarity inverted
2
OUT CHB INV
R/W
0h
Polarity inversion of JESD output of ch B.
0 = Normal operation
1 = Output polarity inverted
1
OUT CHC INV
R/W
0h
Polarity inversion of JESD output of ch C.
0 = Normal operation
1 = Output polarity inverted
0
OUT CHD INV
R/W
0h
Polarity inversion of JESD output of ch D.
0 = Normal operation
1 = Output polarity inverted
7.6.3.8 JESD Analog Page (6A00h) Register
7.6.3.8.1 Register 12h, 13h (address 12h, 13h) [reset = 0h], JESD Analog Page (6Ah)
Figure 138. Register 12h
7
6
5
4
SEL EMP LANE DA/DD
R/W-0h
3
2
1
0
W-0h
0
0
W-0h
2
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 139. Register 13h
7
6
5
4
SEL EMP LANE DB/DC
R/W-0h
3
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 69. 12h, 13h Field Descriptions
Bit
Name
Type
Reset
Description
7-2
SEL EMP LANE DA/DD
SEL EMP LANE DB/DC
R/W
0h
Selects the amount of de-emphasis for the JESD output transmitter. The
de-emphasis value in dB is measured as the ratio between the peak
value after the signal transition to the settled value of the voltage in one
bit period.
0 = 0 dB
1 = –1 dB
3 = –2 dB
7 = –4.1 dB
15 = –6.2 dB
31 = –8.2 dB
63 = –11.5 dB
1-0
0
W
0h
Must write 0.
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7.6.3.8.2 16h (address = 16h) [reset = 0h], JESD Analog Page (6A00h)
Figure 140. Register 16h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
JESD PLL MODE
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 70. 16h Field Descriptions
Bit
Name
Type
Reset
Description
7-1
0
W
0h
Must write 0.
JESD PLL MODE
R/W
0h
This bit selects the JESD PLL multiplication factor.
0 = 20x mode
1 = 40x mode
0
7.6.3.8.3 Register 1Bh (address = 1Bh) [reset = 0h], JESD Analog Page (6Ah)
Figure 141. Register 1Bh
7
6
JESD SWING
R/W-0h
5
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 71. 1Bh Field Descriptions
68
Bit
Name
Type
Reset
Description
7-5
JESD SWING
R/W
0h
This bit programs the SERDES output swing.
0 = 860 mVPP
1 = 810 mVPP
2 = 770 mVPP
3 = 745 mVPP
4 = 960 mVPP
5 = 930 mVPP
6 = 905 mVPP
7 = 880 mVPP
4-3
0
W
0h
Must write 0.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Start-Up Sequence
The following steps are recommended as the power-up sequence with the ADS54J66 in DDC mode 8 (no
decimation) with LMFS = 4421 (shown in Table 72).
Table 72. Recommended Power-Up Sequence
STEP
DESCRIPTION
REGISTER
ADDRESS
REGISTER
DATA
COMMENT
1
Supply all supply voltages. There is no required
power supply sequence for the 1.15-V supply,
1.9-V supply, and 3-V supply, and they can be
supplied in any order.
—
—
—
2
Pulse a hardware reset (low to high to low) on pin
48.
—
—
—
Alternatively, the device can be reset with an
analog reset and a digital reset.
0000h
4004h
4003h
4002h
4001h
60F7h
60F7h
70F7h
70F7h
81h
68h
00h
00h
00h
01h
00h
01h
00h
—
3
Set the input clock divider.
0011h
0053h
0039h
0059h
80h
80h
C0h
20h
Select the master page in the analog bank.
Set the clock divider to divide-by-2.
Set the ALWAYS WRITE 1 bit for all channels.
Set the ALWAYS WRITE 1 bit for all channels.
4
Reset the interleaving correction engine in
register 6800h of the main digital page of the
JESD bank. (Register access is already set to
page 6800h in step 2.)
6000h
6000h
7000h
7000h
01h
00h
01h
00h
Resets the interleaving engine for channel A, B
(because the device is in broadcast mode).
Resets the interleaving engine for channel C, D
(because the device is in broadcast mode).
5
Set DDC mode 8 for all channels (no decimation,
14-bit, 500-MSPS data output).
4004h
4003h
61h
41h
Select the decimation filter page of the JESD bank.
6000h
7000h
08h
08h
Select DDC mode 8 for channel A, B.
Select DDC mode 8 for channel C, D.
6001h
7001h
04h
04h
Set the ALWAYS WRITE 1 bit for channel A, B.
Set the ALWAYS WRITE 1 bit for channel C, D.
4003h
4004h
00h
6Ah
Select the analog page in the JESD bank.
6016h
7016h
02h
02h
PLL mode 40x for channel A, B.
PLL mode 40x for channel C, D.
6
Default registers for the analog page of the JESD
bank.
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Application Information (continued)
Table 72. Recommended Power-Up Sequence (continued)
STEP
7
DESCRIPTION
REGISTER
ADDRESS
REGISTER
DATA
4003h
4004h
00h
69h
Select the digital page in the JESD bank.
6000h
6001h
7000h
7001h
20h
01h
20h
01h
Enable JESD MODE control for channel A, B.
Set JESD MODE to 20x mode for LMFS = 4421.
Enable JESD MODE control for channel C, D.
Set JESD MODE to 20x mode for LMFS = 4421.
6000h
6006h
7000h
7006h
80h
0Fh
80h
0Fh
Set CTRL K for channel A, B.
Set K to 16.
Set CTRL K for channel C, D.
Set K to 16.
4005h
7001h
01h
20h
Disable broadcast mode.
Use SYNCbABP, SYNCbABM to issue a SYNC
request for all four channels.
Default registers for the digital page of the JESD
bank.
COMMENT
8
Enable a single SYNCb input (on the SYNCbAB
pin).
9
Pulse SYNCbAB (pins 55 and 56) from high to
low.
—
—
K28.5 characters are transmitted by all four
channels (CGS phase).
10
Pulse SYNCbAB (pins 55 and 56) from low to
high.
—
—
The ILA sequence begins and lasts for four
multiframes. The device transmits ADC data after
the ILA sequence ends.
8.1.2 Hardware Reset
8.1.2.1 Register Initialization
After power-up, the internal registers can be initialized to their default values through a hardware reset by
applying a high pulse on the RESET pin (of durations greater than 10 ns), as shown in Figure 142. Alternatively,
the serial interface registers can be cleared a set of register writes as described in the Start-Up Sequence
section. Table 73 lists the timing requirements for the pulse signal on the RESET pin.
Power Supplies
t1
RESET
t2
t3
SEN
Figure 142. Hardware Reset Timing Diagram
Table 73. Timing Requirements for Hardware Reset
MIN
TYP MAX
UNIT
t1
Power-on delay from power-up to active high RESET pulse
1
ms
t2
Reset pulse duration : active high RESET pulse duration
10
ns
t3
Register write delay from RESET disable to SEN active
100
ns
70
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8.1.3 SNR and Clock Jitter
The signal-to-noise ratio of the ADC is limited by three different factors (as shown in Equation 2): the
quantization noise is typically not noticeable in pipeline converters and is 84 dB for a 14-bit ADC. The thermal
noise limits the SNR at low input frequencies and the clock jitter sets the SNR for higher input frequencies.
(2)
The SNR limitation resulting from sample clock jitter can be calculated by Equation 3:
(3)
The total clock jitter (TJitter) has two components: the internal aperture jitter (120 fs for the ADS54J66) that is set
by the noise of the clock input buffer and the external clock jitter. TJitter can be calculated by Equation 4:
(4)
External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass
filters at the clock input; a faster clock slew rate also improves the ADC aperture jitter.
The ADS54J66 has a thermal noise of approximately 72 dBFS and an internal aperture jitter of 120 fs.
8.1.4 ADC Test Pattern
The ADS54J66 provides several different options to output test patterns instead of the actual output data of the
ADC in order to simplify bring up of the JESD204B digital interface link. The output data path is shown in
Figure 143.
ADC Section
Transport Layer
Link Layer
PHY Layer
DDC
ADC
Interleaving
Correction
DDC
Block
ADC Test
Pattern
Data Mapping
Frame Construction
Scrambler
1+x14+x15
JESD204B Long
Transport Layer
Test Pattern
8b/10b
Encoding
Serializer
JESD204B
Link Layer
Test Pattern
Figure 143. ADC Test Pattern
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8.1.4.1 ADC Section
The ADC test pattern replaces the actual output data of the ADC. The following test patterns are available in
register 74h. In order to properly obtain the test pattern output, the interleaving correction must be disabled
(6100h, address 18h) and DDC mode-8 must be selected (un-decimated output).
In un-decimated output (DDC mode-8), the device supports LMFS = 4421 only. Available ADC test patterns are
summarized in Table 74.
Table 74. ADC Test Pattern Settings
BIT
7-4
NAME
DEFAULT
TEST PATTERN
0000
DESCRIPTION
These bits provide the test pattern output on channels A and B.
0000 = Normal operation using ADC output data
0001 = Outputs all 0s
0010 = Outputs all 1s
0011 = Outputs toggle pattern: output data are an alternating
sequence of 101010101010 and 010101010101
0100 = Output digital ramp: output data increment by one LSB
every clock cycle from code 0 to 16384
0110 = Single pattern: output data are custom pattern 1 (75h and
76h)
0111 = Double pattern: output data alternate between custom
pattern 1 and custom pattern 2
1000 = Deskew pattern: output data are 2AAAh
1001 = SYNC pattern: output data are 3FFFh
8.1.4.2 Transport Layer Pattern
The transport layer maps the ADC output data into 8-bit octets and constructs the JESD204B frames using the
LMFS parameters. Tail bits or 0s are added when needed. Alternatively, the JESD204B long transport layer test
pattern can be substituted as shown in Table 75.
Table 75. Transport Layer Test Mode
BIT
4
NAME
TESTMODE EN
DEFAULT
0
DESCRIPTION
This bit generates the long transport layer test pattern mode
according to clause 5.1.6.3 of the JESD204B specification.
0 = Test mode disabled
1 = Test mode enabled
8.1.4.3 Link Layer Pattern
The link layer contains the scrambler and the 8b/10b encoding of any data passed on from the transport layer.
Additionally, the link layer also handles the initial lane alignment sequence that can be manually restarted. The
link layer test patterns are intended for testing the quality of the link (jitter testing and so forth). The test patterns
do not pass through the 8b/10b encoder and contain the options shown in Table 76.
Table 76. Link Layer Test Mode
BIT
7-5
NAME
LINK LAYER TESTMODE
DEFAULT
DESCRIPTION
000
These bits generate the pattern according to clause 5.3.3.8.2 of the
JESD204B document.
000 = Normal ADC data
001 = D21.5 (high-frequency jitter pattern)
010 = K28.5 (mixed-frequency jitter pattern)
011 = Repeat initial lane alignment (generates a K28.5 character
and repeats lane alignment sequences continuously)
100 = 12-octet RPAT jitter pattern
Furthermore, a 215 PRBS can be enabled by setting up a custom test pattern (AAAA) in the ADC section and
running that through the 8b/10b encoder with scrambling enabled.
72
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8.2 Typical Application
The ADS54J66 is designed for wideband receiver applications demanding excellent dynamic range over a large
input frequency range. A typical schematic for an ac-coupled dual receiver (dual FPGA with dual SYNC) is
shown in Figure 144.
DVDD
5
25
10 k
25
0.1 uF
Driver
0.1 uF
3.3 pF
GND
25
SPI Master
25
5
GND
0.1 uF
25
5
GND
INCP
AVDD
AVDD
0.1 uF
GND
AGND
NC
NC
GND
0.1 uF
AVDD3V
AVDD3V
AVDD
AVDD
0.1 uF
GND
10 nF
AGND
CLKINP
100
CLKINM
AGND
GND
0.1 uF
AVDD
Low Jitter
Clock
Generator
AVDD
AVDD3V
AVDD3V
0.1 uF
GND
AGND
SYSREFP
100
SYSREFM
AVDD
AVDD
5
INBP
10
8
7
6
5
3
2
4
NC
IOVDD
SDIN
SCLK
SEN
DVDD
9
NC
11
AVDD
SDOUT
12
DGND
13
AVDD
INDP
AVDD
INDM
14
100
20
71
21
70
22
69
23
68
24
67
25
66
26
65
27
64
ADS54J66
28
29
Differential
1
63
62
GND PAD (backside)
30
61
31
60
32
59
33
58
34
57
35
56
36
55
SYNCbCDP
50
Vterm=1.2 V
SYNCbCDM 50
FPGA
IOVDD
IOVDD
10 nF
GND
DDP
10 nF
DDM
DGND
10 nF
GND
DCP
DCM
IOVDD
IOVDD
0.1 uF
GND
DGND
DBM
DBP
DGND
10 nF
GND
DAM
DAP
IOVDD
IOVDD
10 nF
10 nF
GND
SYNCbABM
50
SYNCbABP 50
FPGA
Vterm=1.2 V
25
AVDD3V
AVDD
GND
53
54
100
Differential
NC
52
NC
51
DGND
50
IOVDD
49
PDN
48
SCAN_EN
47
RESET
46
DVDD
45
AVDD
44
AVDD
43
AVDD
42
INAP
41
INAM
40
AVDD
3.3 pF
25
5
39
AVDD3V
GND
38
AVDD3V
37
0.1 uF
25
15
DVDD
72
INBM
Driver
0.1 uF
16
0.1 uF
AVDD
19
AVDD
25
17
AVDD3V
3.3 pF
18
25
AVDD
25
0.1 uF
INCM
25
0.1 uF
IOVDD GND
0.1 uF
AVDD3V
AVDD
AVDD3V
5
Driver
0.1 uF
AVDD3V
GND
DVDD
AVDD
AVDD3V
0.1 uF
GND
0.1 uF
GND
0.1 uF
IOVDD GND
5
25
Driver
25
0.1 uF
0.1 uF
GND
25
3.3 pF
5
25
GND = AGND + DGND connected in Layout
NOTE: GND = AGND and DGND are connected in the PCB layout.
Figure 144. Application Diagram for the ADS54J66
8.2.1 Design Requirements
By using the simple drive circuit of Figure 144 (when the amplifier drives the ADC) or Figure 51 (when
transformers drive the ADC), uniform performance can be obtained over a wide frequency range. The buffers
present at the analog inputs of the device help isolate the external drive source from the switching currents of the
sampling circuit.
8.2.2 Detailed Design Procedure
For optimum performance, the analog inputs must be driven differentially. This architecture improves the
common-mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with
each input pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 144.
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Typical Application (continued)
8.2.3 Application Curves
0
0
-20
-20
Amplitude (dBFS)
Amplitude (dBFS)
Figure 145 and Figure 146 show the typical performance at 190 MHz and 230 MHz, respectively.
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
0
50
100
150
Input Frequency (MHz)
200
250
0
D003
fIN = 190 MHz, AIN = –1 dBFS,
SNR = 69.4 dBFS, SFDR = 88 dBc, SFDR = 96 dBc (non 23)
50
100
150
Input Frequency (MHz)
200
250
D004
fIN = 230 MHz, AIN = –1 dBFS,
SNR = 69.4 dBFS, SFDR = 85 dBc, SFDR = 96 dBc (non 23)
Figure 145. FFT for 190-MHz Input Signal
Figure 146. FFT for 230-MHz Input Signal
9 Power Supply Recommendations
The device requires a 1.9-V nominal supply for DVDD, a 1.9-V nominal supply for AVDD, and a 3-V nominal
supply for AVDD3V. There is no specific sequence for power-supply requirements during device power-up.
AVDD, DVDD, and AVDD3V can power-up in any order.
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10 Layout
10.1 Layout Guidelines
The device evaluation module (EVM) layout can be used as a reference layout to obtain the best performance. A
layout diagram of the EVM top layer is provided in Figure 147. A complete layout of the EVM is available at the
ADS54J66 EVM folder. Some important points to remember during board layout are:
• Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package
level. To minimize crosstalk onboard, the analog inputs must exit the pinout in opposite directions, as shown
in the reference layout of Figure 147 as much as possible.
• In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to
minimize coupling between them. This configuration is also maintained on the reference layout of Figure 147
as much as possible.
• Keep digital outputs away from the analog inputs. When these digital outputs exit the pinout, the digital output
traces must not be kept parallel to the analog input traces because this configuration can result in coupling
from the digital outputs to the analog inputs and degrade performance. All digital output traces to the receiver
[such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)] must be
matched in length to avoid skew among outputs.
• At each power-supply pin (AVDD, DVDD, or AVDDD3V), keep a 0.1-µF decoupling capacitor close to the
device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF
capacitors can be kept close to the supply source.
10.2 Layout Example
Figure 147. ADS54J66EVM Layout
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS54J66IRMP
ACTIVE
VQFN
RMP
72
168
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ54J66
ADS54J66IRMPT
ACTIVE
VQFN
RMP
72
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ54J66
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
RMP0072A
VQFN - 0.9 mm max height
SCALE 1.700
VQFN
10.1
9.9
B
A
PIN 1 ID
10.1
9.9
0.9 MAX
0.05
0.00
C
0.08 C
(0.2)
SEATING PLANE
4X (45 X0.42)
19
36
18
4X
8.5
37
SYMM
8.5 0.1
PIN 1 ID
(R0.2)
1
68X 0.5
54
55
72
SYMM
72X
0.5
0.3
72X
0.30
0.18
0.1
0.05
C B
C
A
4221047/B 02/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RMP0072A
VQFN - 0.9 mm max height
VQFN
(
8.5)
SYMM
72X (0.6)
SEE DETAILS
55
72
1
54
72X (0.24)
(0.25) TYP
(9.8)
SYMM
(1.315) TYP
68X (0.5)
( 0.2) TYP
VIA
37
18
19
36
(1.315) TYP
(9.8)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221047/B 02/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB application report
in literature No. SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
RMP0072A
VQFN - 0.9 mm max height
VQFN
(9.8)
72X (0.6)
(1.315) TYP
72
55
1
54
72X (0.24)
(1.315)
TYP
(0.25) TYP
SYMM
(1.315)
TYP
(9.8)
68X (0.5)
METAL
TYP
37
18
( 0.2) TYP
VIA
19
36
36X ( 1.115)
(1.315) TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
62% PRINTED SOLDER COVERAGE BY AREA
SCALE:8X
4221047/B 02/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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