AN76405
®
EZ-USB FX3™/FX3S™ Boot Options
Author: Rama Sai Krishna V
Associated Project: No
Associated Part Family: CYUSB30xx
Related Application Notes: For a complete list, click here
To get the latest version of this application note, or the associated project file, please
visit http://www.cypress.com/go/AN76405
AN76405 describes the boot options—over USB, I2C, SPI, and synchronous Address Data Multiplexed (ADMux)
interfaces—available for the Cypress EZ-USB® FX3™ peripheral controller. This application note is also applicable to FX3S
and CX3 peripheral controllers. For a complete list of USB SuperSpeed Code Examples, visit
http://www.cypress.com/?rID=101781.
Contents
1
2
3
4
5
6
7
Introduction................................................................. 2
Related Resources ..................................................... 2
2.1
EZ-USB FX3 Software Development Kit .......... 2
2.2
GPIF™ II Designer .......................................... 3
FX3 Boot Options ....................................................... 3
USB Boot.................................................................... 4
4.1
PMODE Pins.................................................... 4
4.2
Features........................................................... 5
4.3
Checksum Calculation ..................................... 9
4.4
Boot Image Format ........................................ 12
I2C EEPROM Boot.................................................... 13
5.1
Features......................................................... 14
5.2
Storing Firmware Image on EEPROM ........... 14
5.3
Boot Image Format ........................................ 16
5.4
Checksum Calculation ................................... 18
I2C EEPROM Boot With USB Fallback ..................... 19
6.1
Features......................................................... 20
6.2
Example Image for Boot with VID and PID .... 20
SPI Boot ................................................................... 20
7.1
Features......................................................... 21
7.2
Selection of SPI Flash ................................... 22
7.3
Storing Firmware Image on SPI
Flash/EEPROM ........................................................ 22
7.4
Boot Image Format ........................................ 22
7.5
Checksum Calculation ................................... 24
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8
SPI Boot With USB Fallback .................................... 25
8.1
Example Image for Boot with VID and PID .... 25
9 Synchronous ADMux Boot ....................................... 25
9.2
Boot Image Format ........................................ 37
10 eMMC Boot ............................................................ 40
11 Default State of I/Os During Boot ........................... 40
A Appendix: Steps for Booting Using FX3 DVK Board 43
A.1 USB Boot ....................................................... 43
A.2 I2C Boot ......................................................... 47
A.3 SPI Boot ........................................................ 52
Document History............................................................ 57
Worldwide Sales and Design Support ............................. 58
Products .......................................................................... 58
PSoC® Solutions ............................................................. 58
Cypress Developer Community....................................... 58
Technical Support ........................................................... 58
Document No. 001-76405 Rev.*E
1
EZ-USB® FX3™/FX3S™ Boot Options
1
Introduction
EZ-USB FX3 is the next-generation USB 3.0 peripheral controller, providing highly integrated and flexible features that
enable developers to add USB 3.0 functionality to a wide range of applications.
FX3 supports several boot options, including booting over USB, I2C, SPI, synchronous and asynchronous ADMux, and
asynchronous SRAM interfaces.
Note: This application note describes the details of only the USB, I 2C, SPI, and synchronous ADMux boot options.
The default state of the FX3 I/Os during boot is also documented. The appendix covers the stepwise sequence for
testing the different boot modes using the FX3 DVK.
2
Related Resources
Cypress provides a wealth of data at www.cypress.com to help you to select the right device for your design, and to
help you to integrate the device into your design quickly and effectively. For a comprehensive list of resources, see the
knowledge base article KBA87889, How to design with FX3/FX3S.
2.1
Overview: USB Portfolio, USB Roadmap
USB 3.0 Product Selectors: FX3, FX3S, CX3, HX3, West Bridge Benicia
Application notes: Cypress offers a large number of USB application notes covering a broad range of topics, from
basic to advanced level. Recommended application notes for getting started with FX3 are:
AN75705 – Getting Started with EZ-USB FX3
AN86947 – Optimizing USB 3.0 Throughput with EZ-USB FX3
AN76405 – EZ-USB FX3 Boot Options
AN70707 – EZ-USB FX3/FX3S Hardware Design Guidelines and Schematic Checklist
AN65974 – Designing with the EZ-USB FX3 Slave FIFO Interface
AN75779 – How to Implement an Image Sensor Interface with EZ-USB FX3 in a USB Video Class (UVC)
Framework
AN84868 – Configuring an FPGA over USB Using Cypress EZ-USB FX3
AN68829 – Slave FIFO Interface for EZ-USB FX3: 5-Bit Address Mode
AN73609 – EZ-USB FX2LP/ FX3 Developing Bulk-Loop Example on Linux
AN77960 – Introduction to EZ-USB FX3 High-Speed USB Host Controller
AN76348 – Differences in Implementation of EZ-USB FX2LP and EZ-USB FX3 Applications
AN89661 – USB RAID 1 Disk Design Using EZ-USB FX3S
Code Examples:
USB Hi-Speed
USB Full-Speed
USB SuperSpeed
Technical Reference Manual (TRM):
EZ-USB FX3 Technical Reference Manual
Development Kits:
CYUSB3KIT-003, EZ-USB FX3 SuperSpeed Explorer Kit
CYUSB3KIT-001, EZ-USB FX3 Development Kit
Models: IBIS
EZ-USB FX3 Software Development Kit
Cypress delivers the complete software and firmware stack for FX3 to easily integrate SuperSpeed USB into any
embedded application. The Software Development Kit (SDK) comes with tools, drivers, and application examples,
which help accelerate application development.
www.cypress.com
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EZ-USB® FX3™/FX3S™ Boot Options
2.2
GPIF™ II Designer
The GPIF II Designer is a graphical software that allows designers to configure the GPIF II interface of the EZ-USB
FX3 USB 3.0 Device Controller.
The tool allows users the ability to select from one of five Cypress-supplied interfaces, or choose to create their own
GPIF II interface from scratch. Cypress has supplied industry-standard interfaces such as asynchronous and
synchronous Slave FIFO, and asynchronous and synchronous SRAM. Designers who already have one of these predefined interfaces in their system can simply select the interface of choice, choose from a set of standard parameters
such as bus width (x8, 16, x32) endianness, clock settings, and compile the interface. The tool has a streamlined threestep GPIF interface development process for users who need a customized interface. Users can first select their pin
configuration and standard parameters. Secondly, they can design a virtual state machine using configurable actions.
Finally, users can view output timing to verify that it matches the expected timing. After this three-step process is
complete, the interface can be compiled and integrated with FX3.
3
FX3 Boot Options
FX3 integrates a bootloader that resides in the masked ROM. The function of the bootloader is to download the FX3
firmware image from various interfaces such as USB, I2C, SPI, or GPIF II (for example, synchronous ADMux,
asynchronous SRAM, or asynchronous ADMux).
The FX3 bootloader uses the three PMODE input pins of FX3 to determine the boot option to be used. Figure 1 shows
the boot options discussed in this application note. Table 1 lists these boot options along with the required PMODE pin
settings.
Figure 1. FX3 Boot Options
I2C EEPROM
Boot from an
I2C EEPROM
External FPGA/
Processor
I2C
Boot over
Sync ADMux
EZ-USB FX3
Sync
ADMux
Sync
ADMux
Bootloader
ROM
Boot over
USB2.0
USB Host
PMODE2
PMODE1
SPI
PMODE0
Boot from
SPI Flash
SPI Flash
Table 1. Boot Options for FX3*
PMODE[2:0] Pins
Boot Option
USB Fallback
0
Sync ADMux (16-bit)
No
1
USB Boot
Yes
PMODE[2]
PMODE[1]
PMODE[0]
Z
0
Z
1
1
Z
2
Z
IC
No
Z
1
Z
I C USB
Yes
0
Z
1
SPI USB
Yes
1
0
0
eMMC**
No
0
0
0
eMMC** USB
Yes
2
Other combinations are reserved.
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EZ-USB® FX3™/FX3S™ Boot Options
Notes:
* Z = Float. The PMODE pin can be made to float either by leaving it unconnected or by connecting it to an
FPGA I/O and then configuring that I/O as an input to the FPGA.
**: eMMC boot is only supported by FX3S.
In addition to the boot options listed in Table 1, FX3 supports booting from asynchronous SRAM and asynchronous
ADMux interfaces. Contact Cypress Applications Support for details. The following sections describe the boot options
supported by FX3:
4
USB Boot: The FX3 firmware image is downloaded into the FX3 system RAM from the USB Host.
SPI Boot: The FX3 firmware image is programmed into an external SPI flash or SPI EEPROM, and on reset, the
FX3 bootloader downloads the firmware over SPI.
Synchronous ADMux Boot: The FX3 firmware image is downloaded from an external processor or an FPGA
connected to the FX3 GPIF II interface.
I2C EEPROM Boot: The FX3 firmware image is programmed into an external I2C EEPROM, and on reset, the
FX3 bootloader downloads the firmware over I2C.
USB Boot
Figure 2 shows the system diagram for FX3 when booting over USB.
Figure 2. FX3 System Diagram
EZ-USB FX3
Boot over
USB2.0
External FPGA/
Processor
Bootloader
ROM
PMODE2=Z
PMODE1=1
USB Host
PMODE0=1
4.1
PMODE Pins
For USB boot, the state of the PMODE[2:0] pins should be Z11, as shown in Table 2.
Table 2. PMODE Pins for USB Boot
PMODE[2]
Z
PMODE[1]
1
PMODE[0]
1
Note: Z = Float
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EZ-USB® FX3™/FX3S™ Boot Options
4.2
Features
The external USB Host can download the firmware image to FX3 in USB 2.0 mode. FX3 enumerates as a USB Vendor
class device with bus-powered support.
The state of FX3 in USB boot mode follows:
USB 3.0 (SuperSpeed) signaling is disabled.
USB 2.0 (High Speed/Full Speed) is enabled.
The FX3 uses the vendor command A0h for firmware download/upload. This vendor command is implemented in
the bootloader. (Unlike FX2LP™, the A0h vendor command is implemented in firmware; that is, in the bootloader
code.)
4.2.1
Default Silicon ID
By default, FX3 has the default Cypress Semiconductor VID=04B4h and PID=00F3h stored in the ROM space. This
VID/PID is used for default USB enumeration unless the eFUSE1 VID/PID is programmed. The default Cypress ID
values should be used only for development purposes. Users must use their own VID/PID for final products. A VID is
obtained through registration with the USB-IF.
4.2.2
B o o t l o a d e r R e vi s i o n
The bootloader revision is stored in the ROM area at the address FFFF_0020h, as shown in Table 3.
Table 3. Bootloader Revision
4.2.3
Minor revision
FFFF_0020h
Major revision
FFFF_0021h
Reserved bytes
FFFF_0022h, FFFF_0023h
ReNumeration™
Cypress’s ReNumeration feature is supported in FX3 and is controlled by firmware.
When first plugged into a USB Host, the FX3 enumerates automatically with its default USB descriptors. Once the
firmware is downloaded, the FX3 enumerates again, this time as a device defined by the downloaded USB descriptor
information. This two-step process is called “ReNumeration.”
4.2.4
B u s - P o w e r e d Ap p l i c a t i o n s
The bootloader enumerates in bus-powered mode. The FX3 can fully support bus-powered designs by enumerating
with less than 100 mA, as required by the USB 2.0 specification.
4.2.5
USB Fallback Options (--> USB)
When booting over other options with USB fallback enabled, FX3 will fall back to the same USB boot mode described
in this section. The operating current may be slightly higher than USB boot mode due to other clock sources being
turned on.
4.2.6
USB with VID/PID Options
The bootloader supports booting with a new VID/PID that may be stored in the following:
I2C EEPROM: See the I2C EEPROM Boot section of this application note.
SPI EEPROM: See the SPI Boot section of this application note.
eFUSE (VID/PID): Contact Cypress Sales for custom eFUSE VID/PID programming.
4.2.7
U S B D e f a u l t D e vi c e
The FX3 bootloader consists of a single USB configuration containing one interface (interface 0) and an alternative
setting of 0. In this mode, only endpoint 0 is enabled. All other endpoints are turned off.
4.2.8
USB Setup Packet
The FX3 bootloader decodes the SETUP packet that contains an 8-byte data structure defined in Table 4.
1
eFUSE is the technology that allows reprogramming of certain circuits in the chip. Contact your Cypress representative for details on eFUSE programming.
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EZ-USB® FX3™/FX3S™ Boot Options
Table 4. Setup Packet
Byte
0
Field
bmRequestType
Description
Request type: Bit7: Direction
Bit6–0: Recipient
1
bRequest
This byte will be A0h for
firmware download/upload
vendor command.
2-3
wValue
16-bit value (little-endian
format)
4-5
wIndex
16-bit value (little-endian
format)
6-7
wLength
Number of bytes
Note: Refer to the USB 2.0 Specification for the bitwise explanation.
4.2.9
USB Chapter 9 and Vendor Commands
The FX3 bootloader handles the commands in Table 5.
Table 5. USB Commands
bRequest
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Descriptions
00
GetStatus: Device, Endpoints, and Interface
01
ClearFeature: Device, Endpoints
02
Reserved: Returns STALL
03
SetFeature: Device, Endpoints
04
Reserved: Returns STALL
05
SetAddress: Handle in FX3 hardware
06
GetDescriptor: Devices’ descriptors in ROM
07
Reserved: Returns STALL
08h
GetConfiguration: Returns internal value
09h
SetConfiguration: Sets internal value
0Ah
GetInterface:Rreturns internal value
0Bh
SetInterface: Sets internal value
0Ch
Reserved: Returns STALL
20h-9Fh
Reserved: Returns STALL
A0h
Vendor Commands: Firmware upload/download
and so on
A1h-FFh
Reserved: Returns STALL
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EZ-USB® FX3™/FX3S™ Boot Options
4.2.10 USB Vendor Commands
The bootloader supports the A0h vendor command for firmware download and upload. The fields for the command are
shown in Table 6 and Table 7.
Table 6. Command Fields for Firmware Download
Byte
0
Field
BmRequest
Type
Value
40h
Description
Request type: Bit7:
Direction
Bit6-0: Recipient.
1
bRequest
A0h
This byte will be A0 for
firmware
download/upload vendor
command.
2-3
WValue
AddrL
(LSB)
16-bit value (little endian
format)
4-5
WIndex
AddrH
(MSB)
16-bit value (little endian
format)
6-7
wLength
Count
Number of bytes
Table 7. Command Fields for Firmware Upload
Byte
0
Field
BmRequest
Type
Value
C0h
Description
Request type: Bit7:
Direction
Bit6-0: Recipient.
1
bRequest
A0h
This byte will be A0 for
firmware
download/upload vendor
command.
2-3
WValue
AddrL
(LSB)
16-bit value (little endian
format)
4-5
WIndex
AddrH
(MSB)
16-bit value (little endian
format)
6-7
wLength
Count
Number of bytes
Table 8. Command Fields for Transfer of Execution to Program Entry
Byte
0
Field
bmRequest
Type
Value
40h
Description
Request type: Bit7:
Direction
Bit6-0: Recipient
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1
bRequest
A0h
This byte will be A0 for
firmware
download/upload vendor
command.
2-3
wValue
AddrL
(LSB)
32-bit Program Entry
4-5
wIndex
AddrH
(MSB)
32-bit Program Entry>>16
6-7
wLength
0
This field must be zero.
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EZ-USB® FX3™/FX3S™ Boot Options
In the transfer execution entry command, the bootloader will turn off all the interrupts and disconnect the USB. Three
examples of vendor command subroutines follow.
Example 1. Vendor Command Write Data Protocol With 8-Byte Setup Packet
bmRequestType=0x40
bRequest
=
wValue
=
wIndex
=
wLength
=
0xA0;
(WORD)address;
(WORD)(address>>16);
1 to 4K-byte max
This command will send DATA OUT packets with a length of transfer equal to wLength and a DATA IN Zero length
packet.
Example 2. Reading Bootloader Revision With Setup Packet
bmRequestType=
bRequest
wValue
wIndex
wLength
0xC0
=
=
=
=
0xA0;
(WORD)0x0020;
(WORD)0xFFFF;
4
This command will issue DATA IN packets with a length of transfer equal to wLength and a DATA OUT Zero length
packet.
Example 3. Jump to Program Entry With 8-Byte Setup Packet (refer to Table 8.)
bmRequestType= 0x40
bRequest
wValue
wIndex
wLength
=
=
=
=
0xA0;
Program Entry
(16-bit LSB)
Program Entry >>16
(16-bit MSB)
0
Note: The FX2LP uses only 16-bit addressing, but FX3 uses 32-bit addressing. Addresses should be written to the
wValue and wIndex fields of the command.
4.2.11 USB Download Sample Code
To download the code, the application should read the firmware image file and write 4K sections at a time using the
vendor write command. The size of the section is limited to the size of the buffer used in the bootloader.
Note The firmware image must be in the format specified in Table 14.
The following is an example of how the firmware download routine can be implemented.
DWORD dCheckSum, dExpectedCheckSum, dAddress, i, dLen;
WORD wSignature, wLen;
DWORD dImageBuf[512*1024];
BYTE *bBuf, rBuf[4096];
fread(&wSignature,1,2,input_file);/*fread(void *ptr, size_t size, size_t
count, FILE *stream)
read signature bytes. */
if (wSignature != 0x5943)
// check ‘CY’ signature byte
{
printf(“Invalid image”);
return fail;
}
fread(&i, 2, 1, input_file);
// skip 2 dummy bytes
dCheckSum = 0;
while (1)
{
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EZ-USB® FX3™/FX3S™ Boot Options
fread(&dLength,4,1,input_file); // read dLength
fread(&dAddress,4,1,input_file); // read dAddress
if (dLength==0) break;
// done
// read sections
fread(dImageBuf, 4, dLength, input_file);
for (i=0; i<dLength; i++) dCheckSum += dImageBuf[i];
dLength <<= 2; // convert to Byte length
bBuf = (BYTE*)dImageBuf;
while (dLength > 0)
{
dLen = 4096; // 4K max
if (dLen > dLength) dLen = dLength;
VendorCmd(0x40, 0xa0, dAddress, dLen, bBuf); // Write data
VendorCmd(0xc0, 0xa0, dAddress, dLen, rBuf); // Read data
// Verify data: rBuf with bBuf
for (i=0; i<dLen; i++)
{
if (rBuf[i] != bBuf) { printf(“Fail to verify image”); return
fail; }
}
dLength -= dLen;
bBuf += dLen;
dAddress += dLen;
}
}
// read pre-computed checksum data
fread(&dExpectedChecksum, 4, 1, input_file);
if (dCheckSum != dExpectedCheckSum)
{
printf(“Fail to boot due to checksum error\n”);
return fail;
}
// transfer execution to Program Entry
VendorCmd(0x40, 0xa0, dAddress, 0, NULL);
input_file is the FILE pointer that points to the firmware image file, which is in the format specified in Table 14.
4.3
Checksum Calculation
In the USB download, the download tool is expected to handle the checksum computation as shown in the USB
Download Sample Code section.
4.3.1
FX3 Bootloader Memory Allocation
The FX3 bootloader allocates 1280 bytes of data tightly-coupled memory (DTCM) from 0x1000_0000 to 0x1000_04FF
for its variables and stack. The firmware application can use it as long as this area remains uninitialized, that is,
uninitialized local variables, during the firmware download.
The bootloader allocates the first 16 bytes from 0x4000_0000 to 0x4000_000F for warm boot and standby boot. These
bytes should not be used by firmware applications.
The bootloader allocates about 10K bytes from 0x4000_23FF for its internal buffers. The firmware application can use
this area as the uninitialized local variables/buffers.
The bootloader does not use the instruction tightly-coupled memory (ITCM).
4.3.2
Registers/Memory Access
The FX3 bootloader allows read access from the ROM, MMIO, SYSMEM, ITCM, and DTCM memory spaces.
The bootloader allows write access to the MMIO, SYSMEM, ITCM, and DTCM memory spaces except for the first
1280-byte of DTCM and first 10K of system memory. When writing to the MMIO space, the expected transfer length
for Bootloader must be four (equal to LONG word), and the address should be aligned by 4 bytes.
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EZ-USB® FX3™/FX3S™ Boot Options
4.3.3
USB eFUSE VID/PID Boot Option
The FX3 bootloader can boot with your choice of VID and PID by scanning the eFUSE (eFUSE_USB_ID) to see whether
the USB_VID bits are programmed. If they are, the bootloader will use the eFUSE value for VID and PID.
4.3.4
USB OTG
The FX3 bootloader does not support OTG protocol. It always operates as a USB bus-powered device.
4.3.5
Bootloader Limitations
The FX3 bootloader handles limited checking of the address range. Accessing nonexisting addresses can lead to
unpredictable results.
The bootloader does not check the Program Entry. An invalid Program Entry can lead to unpredictable results.
The bootloader allows write access to the MMIO register spaces. Write accesses to invalid addresses can lead to
unpredictable results.
4.3.6
USB Watchdog Timer
FX3 USB hardware requires a 32-kHz clock input to the USB core hardware. The bootloader will configure the watchdog
timer to become the internal 32 kHz for the USB core if the external 32-kHz clock is not present.
4.3.7
USB Suspend/Resume
The FX3 bootloader will enter suspend mode if there is no activity on USB. It will resume when the PC resumes the
USB operation.
4.3.8
U S B Ad d i t i o n a l P I D
The bootloader may boot with VID=0x04B4/PID=0x00BC or VID=0x04B4/PID=0x0053 based on the setting of the
PMODE pins.
4.3.9
USB Wall-Charger Detection
When connecting FX3 to a wall charger, the bootloader will enter suspend mode and set the O[60] (charger detection
output) pin to logic ‘1’. When connecting FX3 to a USB Host, the bootloader will resume normal operation and set the
O[60] pin to logic ‘0’.
4 . 3 . 1 0 U S B D e vi c e D e s c r i p t o r s
The following tables are the FX3 bootloader descriptors for High Speed and Full Speed.
Note The Device Qualifier is not available in the Full-Speed mode.
Table 9. Device Descriptor
Offset
Field
Value
Description
0
bLength
12h
Length of this descriptor = 18 bytes
1
bDescType
01
Descriptor type = Device
2-3
wBCDUSB
0200h
USB Specification version 2.0
4
bDevClass
00
Device class (No class-specific protocol is
implemented.)
5
bDevSubClass
00
Device subclass (No class-specific protocol is
implemented.)
6
bDevProtocol
00
Device protocol (No class-specific protocol is
implemented.)
7
bMaxPktSize
40h
Endpoint0 packet size is 64.
8-9
wVID
04B4h
Cypress Semiconductor VID
10-11
wPID
00F3h
FX3 silicon
12-13
wBCDID
0100h
FX3 bcdID
14
iManufacture
01h
Manufacturer index string = 01
15
iProduct
02h
Serial number index string = 02
16
iSerialNum
03h
Serial number index string = 03
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Offset
17
Field
Value
bNumConfig
Description
01h
One configuration
Table 10. Device Qualifier
Offset
Field
Value
Description
0
bLength
0Ah
Length of this descriptor = 10 bytes
1
bDescType
06
Descriptor type = Device Qualifier
2-3
wBCDUSB
0200h
USB Specification version 2.00
4
bDevClass
00
Device class (No class-specific protocol is implemented.)
5
bDevSubClass
00
Device subclass (No class-specific protocol is
implemented.)
6
bDevProtocol
00
Device protocol (No class-specific protocol is
implemented.)
7
bMaxPktSize
40h
Endpoint0 packet size is 64.
8
bNumConfig
01h
One configuration
9
bReserved
00h
Must be zero
Table 11. Configuration Descriptor
Offset
Field
Value
Description
0
bLength
09h
Length of this descriptor = 10 bytes
1
bDescType
02h
Descriptor type = Configuration
2-3
wTotalLength
0012h
Total length
4
bNumInterfaces
01
Number of interfaces in this configuration
5
bConfigValue
01
Configuration value used by SetConfiguration
request to select this interface
6
bConfiguration
00
Index of string describing this configuration = 0
7
bAttribute
80h
Attributes: Bus Powered, No Wakeup
8
bMaxPower
64h
Maximum power: 200 mA
Table 12. Interface Descriptor (Alt. Setting 0)
Offset
Field
Value
Description
0
bLength
09h
Length of this descriptor = 10 bytes
1
bDescType
04h
Descriptor type = Interface
2
bInterfaceNum
00h
Zero-based index of this interface = 0
4
bAltSetting
00
Alternative Setting value = 0
5
bNumEndpoints
00
Only endpoint0
6
bInterfaceClass
FFh
Vendor Command Class
7
bInterfaceSubClass
00h
8
bInterfaceProtocol
00h
9
iInterface
00h
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EZ-USB® FX3™/FX3S™ Boot Options
Table 13. String Descriptors
Offset
4.4
Field
Value
Description
0
bLength
04h
Length of this descriptor = 04 bytes
1
bDescType
03h
Descriptor type = String
2-3
wLanguage
0409h
Language = English
4
bLength
10h
Length of this descriptor = 16 bytes
5
bDescType
03h
Descriptor type = String
6-21
wStringIdx1
–
“Cypress”
22
bLength
18h
Length of this descriptor = 24 bytes
23
bDescType
03h
Descriptor type = String
24-47
wStringIdx2
–
“WestBridge”
48
bLength
1Ah
Length of this descriptor = 26 bytes
49
bDescType
03h
Descriptor type = String
50-75
wStringIdx3
–
“0000000004BE”
Boot Image Format
For USB boot, the bootloader expects the firmware image file to be in the format shown in Table 14. The EZ-USB FX3
SDK provides a software utility that can be used to generate a firmware image in the format required for USB boot.
Please refer to the elf2img utility located in the C:\Program Files\Cypress\EZ-USB FX3 SDK\1.3\util\elf2img directory
after installing the SDK. For 64-bit systems, the first folder in the path is Program Files(x86). The number 1.3 in the
directory path is the version number of the SDK, and it can vary based on the latest release of the FX3 SDK.
Table 14. Boot Image Format
Binary Image
Header
Length (16-bit)
Description
wSignature
1
Signature 2 bytes initialize with “CY” ASCII text.
bImageCTL;
½
Bit0 = 0: Execution binary file; 1: data file type
Bit3:1 No use when booting in SPI EEPROM
Bit5:4(SPI speed):
00: 10 MHz
01: 20 MHz
10: 30 MHz
11: Reserved
Bit7:6: Reserved, should be set to zero
bImageType;
½
bImageType = 0xB0: Normal FW binary image with checksum
bImageType = 0xB2: I2C/SPI boot with new VID and PID
dLength 0
2
First section length, in long words (32-bit)
When bImageType = 0xB2, the dLength 0 will contain PID and VID. Bootloader
ignores the rest of the following data.
dAddress 0
2
First section address of Program Code.
Note: Internal ARM address is byte addressable, so the address for each section
should be 32-bit aligned.
dData[dLength 0]
dLength 0*2
…
dLength N
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Image Code/Data must be 32-bit aligned.
More sections
2
0x00000000 (Last record: termination section)
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Binary Image
Header
dAddress N
Length (16-bit)
2
Description
Should contain valid Program Entry (Normally, it should be the Startup code, that is,
the RESET vector.)
Note If bImageCTL.bit0 = 1, the bootloader will not transfer the execution to this
Program Entry.
If bImageCTL.bit0 = 0, the bootloader will transfer the execution to this Program
Entry. This address should be in the ITCM area or SYSTEM RAM area.
The bootloader does not validate the Program Entry.
dCheckSum
4.4.1
2
32-bit unsigned little endian checksum data will start from the first section to the
termination section. The checksum will not include the dLength, dAddress, and
Image Header.
Example of boot image format organized in long -word format:
Location1: 0xB0 0x10 ’Y’ ’C’
//CY Signature, 20 MHz, 0xB0 Image
Location2: 0x00000004
//Image length of section 1 = 4
Location3: 0x40008000
//1st section stored in SYSMEM RAM at
0x40008000
Location4: 0x12345678
//Image starts (Section1)
Location5: 0x9ABCDEF1
Location6: 0x23456789
Location7: 0xABCDEF12
//Section 1 ends
Location8: 0x00000002
//Image length of section 2 = 2
Location9: 0x40009000
//2nd section stored in SYSMEM RAM at
0x40009000
Location10: 0xDDCCBBAA
//Section 2 starts
Location11: 0x11223344
Location12: 0x00000000
//Termination of Image
Location13: 0x40008000
//Jump to 0x40008000 on FX3 System RAM
Location 14: 0x6AF37AF2
//Checksum (0x12345678 + 0x9ABCDEF1 +
0x23456789 +
0xABCDEF12+ 0xDDCCBBAA +0x11223344)
The stepwise sequence for testing the USB boot mode using the FX3 DVK is shown in the USB Boot section of the
appendix.
5
I2C EEPROM Boot
Figure 3 shows the system diagram for FX3 when booting over I 2C.
Figure 3. FX3 System Diagram for I2C Boot
I2C EEPROM
On Reset, FX3 bootloader
downloads firmware over I2C
I2C
EZ-USB FX3
External FPGA/
Processor
PMODE2=1
PMODE1=Z
PMODE0=Z
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USB3.0/
USB2.0
USB Host
Bootloader
ROM
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For I2C EEPROM boot, the state of the PMODE[2:0] pins should be 1ZZ, as shown in Table 15.
Table 15. PMODE Pins for I2C Boot
PMODE[2]
PMODE[1]
PMODE[0]
1
Z
Z
The pin mapping of the FX3 I2C interface is shown in Table 16.
Table 16. Pin Mapping of I2C interface
5.1
I2C Interface
I2C_GPIO[58]
I2C_SCL
I2C_GPIO[59]
I2C_SDA
Features
5.2
EZ-USB FX3 Pin
FX3 boots from I2C EEPROM devices through a two-wire I2C interface.
EEPROM2 device sizes supported are:
32 kilobit (Kb) or 4 kilobyte (KB)
64 Kb or 8 KB
128 Kb or 16 KB
256 Kb or 32 KB
512 Kb or 64 KB
1024 Kb or 128 KB
2048 Kb or 256 KB
Note: It is recommended to use the firmware image built in Release mode, as the size of the generated image
file in the Release version is smaller than that in the Debug version.
ATMEL,Microchip and ST Electronics devices have been tested.
Boot from multiple I2C EEPROM devices of the same size is supported. When the I2C EEPROM is smaller than
the firmware image, multiple I2C EEPROM devices must be used. The bootloader supports loading the image
across multiple I2C EEPROM devices. SuperSpeed Explorer CYUSB3KIT-003 uses 256 KB EEPROM (M24M02)
from ST Electronics. The bootloader can support up to eight I2C EEPROM devices smaller than 128 KB. The
bootloader can support up to four I2C EEPROM devices of 128 KB.
Only one firmware image can be stored on I2C EEPROM. No redundant images are allowed.
100 kHz, 400 kHz, and 1 MHz I2C frequencies are supported during boot. Note that when VIO5 is 1.2 V, the
maximum operating frequency supported is 100 kHz. When VIO5 is 1.8 V, 2.5 V, or 3.3 V, the operating
frequencies supported are 400 kHz and 1 MHz. (VIO5 is the I/O voltage for I2C interface).
The bootloader does not support the multimaster I2C feature of FX3. Therefore, during the FX3 I2C booting
process, other I2C masters should not perform any activity on the I2C bus.
Storing Firmware Image on EEPROM
The FX3 bootloader supports a master I2C interface for external serial I2C EEPROM devices. The serial I2C EEPROM
can be used to store application-specific code and data. Figure 4 shows the pin connections of a typical I2C EEPROM.
The I2C EEPROM interface consists of two active wires: serial clock line (SCL) and serial data line (SDA).
The Write Protect (WP) pin should be pulled low while writing the firmware image to EEPROM.
2
Only 2-byte I2C addressees are supported. Single-byte address is not supported for any I2C EEPROM size less than 32 Kb.
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The A0, A1, and A2 pins are the address lines. They set the slave device address from 000 to 111. This makes it
possible to address eight I2C EEPROMs of the same size. These lines should be pulled HIGH or LOW based on the
address required.
Figure 4. Pin Connections of a Typical I2C EEPROM
VIO5
10 KΩ
10 KΩ
VIO5
VIO5
10 KΩ
2.2 KΩ
VCC
A0
SCL
A1
SDA
2.2 KΩ
A2
I2C EEPROM
WP
GND
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EZ-USB® FX3™/FX3S™ Boot Options
5.2.1
I m p o r t a n t P o i n t s o n 1 2 8 - K B E E P R O M Ad d r e s s i n g
In the case of a 128-KB I2C EEPROM, the addressing style is not standard across EEPROMs. For example, Microchip
EEPROMs use pins A1 and A0 for chip select, and pin A2 is unused. However, Atmel EEPROMs use A2 and A1 for
chip select, and A0 is unused. Both these cases are handled by the bootloader. The addressing style can be indicated
in the firmware image header.
Table 17 shows how four Microchip 24LC1025 EEPROM devices can be connected.
Table 17. Microchip 24LC1025 EEPROM Device Connections
Device
No.
Address Range
A2 A1 A0
Size
1
0x00000-0x1FFFF
Vcc
0
0
128 KB
2
0x20000-0x3FFFF
Vcc
0
1
128 KB
3
0x40000-0x5FFFF
Vcc
1
0
128 KB
4
0x60000-0x7FFFF
Vcc
1
1
128 Kbytes
Table 18 shows how four Atmel 24C1024 EEPROM devices can be connected.
Table 18. ATMEL 24C1024 EEPROM Device Connections
Device
No.
Address Range
A2 A1 A0
Size
1
0x00000-0x1FFFF
0
0
NC
128 KB
2
0x20000-0x3FFFF
0
1
NC
128 KB
3
0x40000-0x5FFFF
1
0
NC
128 KB
4
0x60000-0x7FFFF
1
1
NC
128 KB
Note: NC indicates no connection.
For example, if the firmware code size is greater than 128 KB, then you must use two I2C EEPROMs, with the
addressing schemes corresponding to that EEPROM, as shown in the previous two tables. The firmware image should
be stored across the EEPROMs as a contiguous image as in a single I2C EEPROM.
5.3
Boot Image Format
The bootloader expects the firmware image file to be in the format shown in Table 19. The EZ-USB FX3 SDK provides
a software utility that can be used to generate a firmware image in the format required for I2C EEPROM boot. Refer to
the elf2img utility located in the C:\Program Files\Cypress\EZ-USB FX3 SDK\1.3\util\elf2img directory after installing
the SDK. For 64-bit systems, the first folder in the path is Program Files(x86). The number 1.3 in the directory path is
the version number of the SDK, and it can vary based on the latest release of the FX3 SDK.
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Table 19. Firmware Image Storage Format
Binary Image Header
Length (16-bit)
Description
WSignature
1
Signature 2 bytes initialize with “CY” ASCII text
bImageCTL;
½
Bit0 = 0: execution binary file; 1: data file type
Bit3:1 (I2C size)
7: 128 KB (microchip)
6: 64 KB (128K ATMEL and 256K ST Electronics)
5: 32 KB
4: 16 KB
3: 8 KB
2: 4 KB
Note
Options 1 and 0 are reserved for future usage. Unpredicted results will occur
when booting in these modes.
Bit5:4 (I2C speed):
00: 100 KHz
01: 400 kHz
10: 1 MHz
11: Reserved
Note
The bootloader power-up default will be set at 100 kHz, and it will adjust the I2C
speed if needed.
Bit7:6: Reserved; should be set to zero
bImageType;
½
bImageType = 0xB0: Normal FW binary image with checksum
bImageType = 0xB2: I2C boot with new VID and PID
dLength 0
2
First section length, in long words (32-bit)
When bImageType = 0xB2, the dLength 0 will contain PID and VID. The
bootloader will ignore the rest of the following data.
dAddress 0
2
First section address of Program Code, not the I2C address.
Note
The internal ARM address is byte addressable, so the address for each section
should be 32-bit aligned.
dData[dLength 0]
dLength 0*2
…
All image code/data also must be 32-bit aligned.
More sections
dLength N
2
0x00000000 (Last record: termination section)
dAddress N
2
Should contain valid Program Entry (Normally, it should be the startup code,
that is, the RESET vector.)
Note
If bImageCTL.bit0 = 1, the bootloader will not transfer the execution to this
Program Entry.
If bImageCTL.bit0 = 0, the bootloader will transfer the execution to this Program
Entry. This address should be in the ITCM area or SYSTEM RAM area.
The bootloader does not validate the Program Entry
dCheckSum
2
The 32-bit unsigned little-endian checksum data will start from the First sections
to the termination section. The checksum will not include the dLength,
dAddress, and Image Header.
Example: The binary image file is stored in the I2C EEPROM in the following order:
Byte0: “C”
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Byte1: “Y”
Byte2: bImageCTL
Byte3: bImageType
…..
Byte N: Checksum of Image
Important Notes:
Bootloader default boot speed = 100 kHz; to change the speed from 100 kHz to 1 MHz, bImageCTL<5:4> should
be set to 10.
To select the I2C EEPROM size, bImageCTL[3:1]should be used.
The addressing for the Microchip EEPROM 24LC1026 is different from the addressing of other 128-KB Microchip
EEPROMs. If using Microchip EEPROM 24LC1026, the I2C EEPROM size field, for example, bImageCTL[3:1],
should be set to 6.
5.4
Checksum Calculation
The bootloader computes the checksum when loading the binary image I2C EEPROM. If the checksum does not match
the one in the image, the bootloader does not transfer execution to the Program Entry.
The bootloader operates in little endian mode; for this reason, the checksum must also be computed in little endian
mode.
The 32-bit unsigned little endian checksum data starts from the first sections to the termination section. The checksum
does not include the dLength, dAddress, and Image Header.
5.4.1
First Example Boot Image
The following image is stored only at one section in the system RAM of FX3 at the location 0x40008000:
Location1: 0xB0 0x1A ’Y’ ’C’
//CY Signature, 32KB EEPROM,400Khz,0xB0 Image
Location2:
0x00000004
//Image length =4
Location3:
0x40008000
// 1st section stored in FX3 System RAM at 0x40008000
Location4: 0x12345678
//Image starts
Location5: 0x9ABCDEF1
Location6: 0x23456789
Location7: 0xABCDEF12
5.4.2
Location8: 0x00000000
//Termination of Image
Location9: 0x40008000
//Jump to 0x40008000 in FX3 System RAM
Location 10: 0x7C048C04
//Check sum (0x12345678 + 0x9ABCDEF1 + 0x23456789 + 0xABCDEF12)
Second Example Boot Image
The following image is stored at two sections in the system RAM of FX3 at the locations 0x40008000 and 0x40009000:
Location1: 0xB0 0x1A ’Y’ ’C’
//CY Signature, 32KB EEPROM,400Khz,0xB0 Image
Location2:
0x00000004
//Image length of section 1 =4
Location3:
0x40008000
// 1st section stored in FX3 System RAM at 0x40008000
Location4: 0x12345678
//Image starts (Section1)
Location5: 0x9ABCDEF1
Location6: 0x23456789
Location7: 0xABCDEF12
//Section 1 ends
Location8:
//Image length of section 2 =2
0x00000002
Location9: 0x40009000
www.cypress.com
// 2nd section stored in FX3 System RAM at 0x40009000
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Location10: 0xDDCCBBAA
//Section 2 starts
Location11: 0x11223344
Location12: 0x00000000
//Termination of Image
Location13 0x40008000
//Jump to 0x40008000 in FX3 System RAM
Location 14: 0x6AF37AF2
//Check sum (0x12345678 + 0x9ABCDEF1 + 0x23456789 + 0xABCDEF12+
0xDDCCBBAA +0x11223344)
Similarly, you can have N sections of an image stored using one boot image.
The stepwise sequence for testing the USB boot mode using the FX3 DVK is shown in the I2C Boot section of the
appendix.
5.4.3
Checksum Calculation Sample Code
Following is the checksum sample code:
// Checksum sample code
DWORD dCheckSum, dExpectedCheckSum;
WORD wSignature, wLen;
DWORD dAddress, i;
DWORD dImageBuf[512*1024];
fread(&wSignature,1,2,input_file); // read signature bytes
if (wSignature != 0x5943)
// check ‘CY’ signature byte
{
printf(“Invalid image”);
return fail;
}
fread(&i, 2, 1, input_file);
// skip 2 dummy bytes
dCheckSum = 0;
while (1)
{
fread(&dLength,4,1,imput_file); // read dLength
fread(&dAddress,4,1,input_file); // read dAddress
if (dLength==0) break;
// done
// read sections
fread(dImageBuf, 4, dLength, input_file);
for (i=0; i<dLength; i++) dCheckSum += dImageBuf[i];
}
// read pre-computed checksum data
fread(&dExpectedChecksum, 4, 1, input_file);
if (dCheckSum != dExpectedCheckSum)
{
printf(“Fail to boot due to checksum error\n”);
return fail;
}
This section described the details of the I2C boot option. The next section describes the I2C boot option with the USB
fallback enabled.
6
I2C EEPROM Boot With USB Fallback
For the I2C EEPROM boot with USB fallback, the state of the PMODE[2:0] pins should be Z1Z, as shown in Table 20.
Table 20. PMODE Pins for I2C Boot with USB Fallback
PMODE[2]
Z
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PMODE[1]
1
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PMODE[0]
Z
19
EZ-USB® FX3™/FX3S™ Boot Options
In all USB fallback modes (denoted as “--> USB”), USB enumeration occurs if 0xB2 boot is selected or an error occurs.
After USB enumeration, the external USB Host can boot FX3 using USB boot. I2C EEPROM boot with USB allback
(I2C --> USB) may also be used to store only Vendor Identification (VID) and Product Identification (PID) for USB boot.
The I2C EEPROM boot fails under the following conditions:
I2C address cycle or data cycle error
Invalid signature in FX3 firmware image
Invalid image type
A special image type is used to denote that instead of the FX3 firmware image, data on EEPROM is the VID and PID
for USB boot. This helps in having a new VID and PID for USB boot.
6.1
6.2
7
Features
In case of USB boot, the bootloader supports only USB 2.0. USB 3.0 is not supported.
On USB fallback, when any error occurs during I2C boot, the USB descriptor uses the VID=0x04B4 and
PID=0x00F3.
The USB device descriptor is reported as bus-powered, which will consume about 200 mA. However, the FX3
chip is typically observed to consume about 100 mA.
If the 0xB2 boot option is specified, the USB descriptor uses the customer-defined VID and PID stored as part of
the 0xB2 image in the I2C EEPROM.
Example Image for Boot with VID and PID
Location1: 0xB2 0x1A ’Y’ ’C’
//CY Signature,32k EEPROM,400Khz,0xB2 Image
Location2: 0x04B40008
// VID = 0x04B4 | PID=0x0008
SPI Boot
Figure 5 shows the system diagram for FX3 when booting over SPI.
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EZ-USB® FX3™/FX3S™ Boot Options
Figure 5. System Diagram for SPI Boot
SPI Flash/
EEPROM
SPI
External FPGA/
Processor
USB3.0/
USB2.0
EZ-USB FX3
PMODE2=0
PMODE1=Z
USB Host
Bootloader
ROM
PMODE0=1
For SPI boot, the state of the PMODE[2:0] pins should be 0Z1, as shown in Table 21.
Table 21. MODE Pins for SPI Boot
PMODE[2]
PMODE[1]
0
Z
PMODE[0]
1
The pin mapping of the FX3 SPI interface is shown in Table 22.
Table 22. Pin Mapping of SPI interface
EZ-USB FX3 Pin
7.1
SPI Interface
GPIO[53]
SPI_SCK
GPIO[54]
SPI_SSN
GPIO[55]
SPI_MISO
GPIO[56]
SPI_MOSI
Features
FX3 boots from SPI flash/EEPROM devices through a 4-wire SPI interface.
SPI flash/EEPROM devices from 1 Kb to 32 Mb in size are supported for boot.
SPI frequencies supported during boot are ~10 MHz, ~20 MHz, and ~30 MHz.
Please note that the SPI frequency may vary due to a rounding off on the SPI clock divider and clock input.
When the crystal or clock input to FX3 is 26 MHz or 52 MHz, the internal PLL runs at 416 MHz. SPI
frequencies with PLL_CLK = 416 MHz can be 10.4 MHz, 20.8 MHz, or 34.66 MHz.
Please note that SPI boot has been tested with the part numbers M25P16 (16 Mb), M25P80 (8 Mb), M25P40 (4
Mb), W25916 and MX25L1606L, but the equivalents of these parts may also be used.
When the crystal or clock input to FX3 is 19.2 MHz or 38.4 MHz, the internal PLL runs at 384 MHz. SPI
frequencies with PLL_CLK = 384 MHz can be 9.6 MHz, 19.2 MHz, and 32 MHz.
Operating voltages supported are 1.8 V, 2.5 V, and 3.3 V.
USB fallback is supported and used for storing new VID/PID information for USB boot. See the SPI Boot With
USB Fallback section in this application note for more information.
Only one firmware image is stored on an SPI flash/EEPROM. No redundant image is allowed.
For SPI boot, the bootloader sets CPOL=0 and CPHA=0. (For the timing diagram of this SPI mode, please refer
to the SPI timing in the FX3 datasheet.)
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EZ-USB® FX3™/FX3S™ Boot Options
7.2
Selection of SPI Flash
SPI flash should support the following commands to support FX3 boot.
Read data: 03h with 3-byte addressing
Read Status register: 05h
Write Enable: 06h
Write data (Page Program): 02h
Sector Erase: D8h
An SPI flash can be used for FX3 boot as long as the read commands match. If there are any differences in the write
commands, then programming of that SPI flash will not be successful with the provided CyBootProgrammer.img
(located at C:\Program Files (x86)\Cypress\Cypress USBSuite\application\c_sharp\ controlcenter); it requires changing
the SPI write commands used in the USBFlashProg example project of the FX3 SDK. The image file created after
building the modified USBFlashProg project should replace the provided CyBootProgrammer.img (with the same name)
for successful programming of the SPI flash.
7.3
Storing Firmware Image on SPI Flash/EEPROM
The FX3 bootloader supports a master SPI controller for interfacing with external serial SPI flash/EEPROM devices.
The SPI flash/EEPROM can be used to store application-specific code and data. Figure 6 shows the pinout of a typical
SPI flash/EEPROM.
The SPI EEPROM interface consists of four active wires:
CS#: Chip Select
SO: Serial Data Output (master in, slave out (MISO))
SI: Serial Data Input (master out, slave in (MOSI))
SCK: Serial Clock input
The HOLD# signal should tied to VCC while booting or reading from the SPI device
The Write Protect (WP#) and HOLD# signals should be tied to VCC while writing the image onto EEPROM.
Please note that external pull-ups should not be connected on the MOSI and MISO signals, as shown in Figure 6.
Figure 6. Pin Connections of a Typical SPI Flash
SPI_MOSI
SPI_MISO
100 KΩ
SPI_CLK
SI
VCC
SO
CK
SPI Flash
VIO4
4.7 KΩ
4.7 KΩ
4.7 KΩ
7.4
SPI_HOLD#
SPI_SSN#
SPI_WP#
HOLD#
CS#
VSS
WP#
Boot Image Format
For SPI boot, the bootloader expects the firmware image file to be in the format shown in Table 23. The EZ-USB FX3
SDK provides a software utility that can be used to generate a firmware image in the format required for SPI boot.
Please refer to the elf2img utility located in the C:\Program Files\Cypress\EZ-USB FX3 SDK\1.3\util\elf2img directory
after installing the SDK. For 64-bit systems, the first folder in the path is Program Files(x86). The number 1.3 in the
directory path is the version number of the SDK, and it can vary based on the latest release of the FX3 SDK.
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Table 23. Boot Image Format for SPI Boot Option
Binary Image Header
Length (16-bit)
Description
wSignature
1
Signature 2 bytes initialize with “CY” ASCII text
bImageCTL
½
Bit0 = 0: execution binary file; 1: data file type
Bit3:1 Not use when booting from SPI
Bit5:4(SPI speed):
00: 10 MHz
01: 20 MHz
10: 30 MHz
11: Reserved
Note: Bootloader power-up default is set to 10 MHz, and it will adjust the SPI
speed if needed. The FX3 SPI hardware can run only up to 33 MHz.
Bit7:6: Reserved. Should be set to zero.
bImageType
½
bImageType = 0xB0: Normal firmware binary image with checksum
bImageType = 0xB2: SPI boot with new VID and PID
dLength 0
2
First section length, in long words (32-bit)
When bImageType = 0xB2, the dLength 0 will contain PID and VID. Bootloader
ignores the rest of any following data.
dAddress 0
2
First section address of program code
Note: The internal ARM address is byte addressable, so the address for each
section should be 32-bit aligned.
dData[dLength 0]
dLength 0*2
…
Image Code/Data must be 32-bit aligned.
More sections
dLength N
2
0x00000000 (Last record: termination section)
dAddress N
2
Should contain valid Program Entry (Normally, it should be the Startup code, that
is, the RESET vector.)
Note:
If bImageCTL.bit0 = 1, the bootloader will not transfer the execution to this
Program Entry.
If bImageCTL.bit0 = 0, the bootloader will transfer the execution to this Program
Entry: This address should be in the ITCM area or SYSTEM RAM area.
Bootloader does not validate the Program Entry.
dCheckSum
2
32-bit unsigned little endian checksum data will start from the first section to the
termination section. The checksum will not include the dLength, dAddress, and
Image Header.
Example: The binary image file is stored in the SPI EEPROM in the following order:
Byte0: “C”
Byte1: “Y”
Byte2: bImageCTL
Byte3: bImageType
…..
Byte N: Checksum of Image
Important Point to Note:
Bootloader default boot speed = 10 MHz; to change the speed from 10 MHz to 20 MHz, the bImageCTL[5:4] should be
set to 01.
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7.5
Checksum Calculation
The bootloader computes the checksum when loading the binary image over SPI. If the checksum does not match the
one in the image, the bootloader will not transfer execution to the Program Entry.
The bootloader operates in little endian mode; for this reason, the checksum must also be computed in little endian
mode.
The 32-bit unsigned little endian checksum data starts from the first section to the termination section. The checksum
will not include the dLength, dAddress, and Image Header. Refer to the Checksum Calculation Sample Code section
for the sample code to calculate the checksum.
Example 1. Following is an example of a firmware image stored only at one section in the system RAM of FX3 at
location 0x40008000.
Location1: 0xB0 0x10 ’Y’ ’C’
//CY Signature, 20 MHz, 0xB0 Image
Location2: 0x00000004
//Image length = 4
Location3: 0x40008000
//1st section stored in FX3 System RAM at 0x40008000
Location4: 0x12345678
//Image starts
Location5: 0x9ABCDEF1
Location6: 0x23456789
Location7: 0xABCDEF12
Location8: 0x00000000
//Termination of Image
Location9: 0x40008000
//Jump to 0x40008000 in FX3 System RAM
Location 10: 0x7C048C04
//Checksum (0x12345678 + 0x9ABCDEF1 + 0x23456789 + 0xABCDEF12)
Example 2. Following is an example of a firmware image stored at two sections in the system RAM of FX3 at location
0x40008000 and 0x40009000.
Location1: 0xB0 0x10 ’Y’ ’C’
//CY Signature, 20MHz, 0xB0 Image
Location2: 0x00000004
//Image length of section 1 = 4
Location3: 0x40008000
//1st section stored in FX3 System RAM at 0x40008000
Location4: 0x12345678
//Image starts (Section1)
Location5: 0x9ABCDEF1
Location6: 0x23456789
Location7: 0xABCDEF12
//Section 1 ends
Location8: 0x00000002
//Image length of section 2 = 2
Location9: 0x40009000
//2nd section stored in FX3 System RAM at 0x40009000
Location10: 0xDDCCBBAA
//Section 2 starts
Location11: 0x11223344
Location12: 0x00000000
//Termination of Image
Location13: 0x40008000
//Jump to 0x40008000 in FX3 System RAM
Location 14: 0x6AF37AF2
//Checksum (0x12345678 + 0x9ABCDEF1 + 0x23456789 + 0xABCDEF12+
0xDDCCBBAA +0x11223344)
Similarly, you can have N sections of an image stored using one boot image.
The stepwise sequence for testing the USB boot mode using the FX3 DVK is shown in the SPI Boot section of the
appendix.
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8
SPI Boot With USB Fallback
In all USB fallback (“-->USB”) modes, USB enumeration occurs if 0xB2 boot is selected or an error occurs. After USB
enumeration occurs, the external USB Host can boot FX3 using USB boot. SPI boot with USB fallback (SPI --> USB)
is also used to store VID and PID for USB boot.
SPI boot fails under the following conditions:
SPI address cycle or data cycle error
Invalid signature on FX3 firmware. Invalid image type.
A special image type is used to denote that instead of the FX3 firmware image, data on SPI flash/EEPROM is the VID
and PID for USB boot. This helps in having a new VID and PID for USB boot.
8.1
In the case of USB boot, the bootloader supports only USB 2.0. USB 3.0 is not supported.
If the 0xB2 boot option is specified, the USB descriptor uses the customer-defined VID and PID stored as part of
the 0xB2 image in the SPI flash/ EEPROM.
On USB fallback, when any error occurs during I2C boot, the USB descriptor uses the VID=0x04B4 and
PID=0x00F3.
The USB Device descriptor is reported as bus-powered, which will consume about 200 mA. However, the FX3
chip is typically observed to consume about 100 mA.
Example Image for Boot with VID and PID
Location1: 0xB2 0x10 ’Y’ ’C’
//CY Signature, 20 MHz, 0xB2 Image
Location2: 0x04B40008
//VID = 0x04B4 | PID = 0x0008
The next section describes the details of the synchronous ADMux interface and booting over the synchronous ADMux
interface.
9
Synchronous ADMux Boot
Figure 7 shows the FX3 system diagram when booting over the synchronous ADMux interface.
Figure 7. System Diagram for Synchronous ADMux Boot
External FPGA/
Processor
EZ-USB FX3
Sync
ADMux
Sync
ADMux
PMODE2=Z
PMODE1=0
USB3.0/
USB2.0
USB Host
Bootloader
ROM
PMODE0=0
For booting over the synchronous ADMux interface, the state of the PMODE[2:0] pins should be Z00, as shown in
Table 24.
Table 24. PMODE Pins for Sync ADMux Boot
PMODE[2]
Z
PMODE[1]
0
PMODE[0]
0
The FX3 GPIF II interface supports a synchronous ADMux interface, which may be used for downloading a firmware
image from an external processor or FPGA. The synchronous ADMux interface configured by the bootloader consists
of the following signals:
PCLK: This must be a clock input to FX3. The maximum frequency supported for the clock input is 100 MHz.
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9.1.1
DQ[15:0]: 16-bit data bus
A[7:0]: 8-bit address bus
CE#: Active low chip enable
ADV#: Active low address valid
WE#: Active low write enable
OE#: Active low output enable
RDY: Active high ready signal
Interface Signals
Figure 8 shows the typical interconnect diagram for the sync ADMux interface configured by the bootloader and
connected with an external processor.
Figure 8. Sync ADMUX Interface
CLK
CE#
ADV#
External
Processor
A[7:0]/DQ[15:0]
EZ-USB FX3
WE#
OE#
RDY
For read operations, both CE# and OE# must be asserted.
For write operations, both CE# and WE# are asserted.
ADV# must be low during the address phase of a read/write operation. ADV# must be high during the data phase of a
read/write operation.
The RDY output signal from the FX3 device indicates that data is valid for read transfers.
The pin mapping of the FX3 sync ADMux interface is shown in Table 25.
Table 25. Pin Mapping of Sync ADMux Interface
9.1.2
EZ-USB FX3 Pin
Sync ADMux Interface
GPIO[7:0]/GPIO[15:0]
A[7:0]/DQ[15:0]
GPIO[16]
CLK
GPIO[17]
CE#
GPIO[18]
WE#
GPIO[19]
OE#
GPIO[25]
RDY
GPIO[27]
ADV#
S yn c h r o n o u s A D M u x T i m i n g
For details on the sync ADMux timing diagrams (synchronous ADMux interface—read cycle timing and write cycle
timing) and timing parameters, please refer to the Figure 9, Figure 10 and Table 26.
Sync ADMUX Mode Power-Up Delay
On power-up or a hard reset on the RESET# line, the bootloader will take some time to configure GPIF II for the sync
ADMux interface. This process can take a few hundred microseconds. Read/write access to FX3 should be performed
only after the the bootloader has completed the configuration. Otherwise, data corruption can result. To avoid it, use
one of the following schemes:
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Wait for 1 ms after RESET# deassertion.
Keep polling the PP_IDENTIFY register until the value 0x81 is read back.
Wait for the INT# signal to assert, and then read the RD_MAILBOX registers and verify that the value readback
equals 0x42575943 (that is, ‘CYWB’).
9.1.3
USB Fallback (-->USB)
The USB fallback will not be active during sync ADMUX boot even if an error occurs on the commands.
9.1.4
Warm Boot
When warm boot is detected, the bootloader will transfer execution to the previously stored “Program Entry,” which
could be the user’s RESET vector. In this case, the GPIF II configuration is preserved.
9.1.5
Wakeup/Standby
After wakeup from standby, the application firmware is responsible for configuring and restoring the hardware registers,
GPIF II configuration, ITCM, or DTCM.
After wakeup from standby, the bootloader checks that both ITCM and DTCM are enabled.
Note When the bootloader wakes up from standby mode or the warm boot process, the bootloader jumps to the reset
interrupt service subroutine and does the following:
Invalidates both DCACHE and ICACHE
Turns on ICACHE
Disables MMU
Turns on DTCM and ITCM
Sets up the stack using the DTC
The bootloader allocates 0x500 bytes from 0x1000_0000 – 0x1000_04FF, so 0x1000_0500 – 0x1000_1FFF is
available for downloading firmware. When the download application takes over, the memory from 0x1000_0000 –
0x1000_04FF can be used for other purposes.
Figure 9. Synchronous ADMux Interface – Read Cycle Timing
Notes:
1)
External P-Port processor and FX3S operate on the same clock edge
2)
External processor sees RDY assert 2 cycles after OE# asserts and sees RDY deassert a cyle after the data
appears on the output.
3)
Valid output data appears 2 cycles after OE# is asserted. The data is held until OE# dewasserts.
4)
Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than
50 MHz. (This 1 cycle latency is not supported by the bootloader)
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Figure 10. Synchronous ADMux Interface – Write Cycle Timing
Notes:
1)
External P-Port processor and FX3S operate on the same clock edge
2)
External processor sees RDY assert 2 cycles after WE# asserts and deasserts 3 cyles after the edge sampling the
data.
3)
Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than
50 MHz. (This 1 cycle latency is not supported by the bootloader)
Table 26 . Synchronous ADMux Timing Parameters
Parameter
9.1.6
Description
Min
Max
Unit
FREQ
Interface Clock frequency
-
100
MHz
tCLK
Clock period
10
-
ns
tCLKH
Clock HIGH time
4
-
ns
tCLKL
Clock LOW time
4
-
ns
tS
CE#/WE#/DQ setup time
2
-
ns
tH
CE#/WE#/DQ hold time
0.5
-
ns
tCH
Clock to data output hold time
0
-
ns
tDS
Data input setup time
2
-
ns
tDH
Clock to data input hold time
0.5
-
ns
tAVDOE
ADV# HIGH to OE# LOW
0
-
ns
tAVDWE
ADV# HIGH to WE# LOW
0
-
ns
tHZ
CE# HIGH to Data HIGH-Z
-
8
ns
tOHZ
OE# HIGH to Data HIGH-Z
-
8
ns
tOLZ
OE# LOW to Data HIGH-Z
0
-
ns
tKW
Clock to RDY valid
-
8
ns
GPIF II API Protocol
This protocol is used only in GPIF II boot mode. After reset, the external application processor (AP) communicates with
the bootloader using the command protocol defined in Table 27.
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Table 27. GPIF II API Protocol
Field
bSignature[2]
Description
2-byte
Sender initialize with “CY”
The bootloader responses with “WB”
bCommand
Sender: 1-byte Command
0x00: NOP
0x01: WRITE_DATA_CMD: Write Data Command
0x02: Enter Boot mode
0x03: READ_DATA_CMD: Read Data Command
The bootloader treats all others as no operation and return error code in bLenStatus
bLenStatus
Input: (1-byte)
00: bLenStatus = 0 (the bootloader will jump to addr in dAddr if bCommand is WRITE_DATA_CMD
and ignore value for all other commands; )
01: Length in Long Word (Max = (512-8)/4)
02: Number of 512 byte blocks (Max = 16)
03: Length in Long Word (Max = (512-8)/4)
Bootloader responses with the following data in the PIB_RD_MAILBOX1 register:
0x00: Success
0x30: Fail on Command process encounter error
0x31: Fail on Read process encounter error
0x32: Abort detection
0x33: PP_CONFIG.BURSTSIZE mailbox notification from the bootloader to application. The
PIB_RD_MAILBOX0 will contain the GPIF_DATA_COUNT_LIMIT register.
0x34: The bootloader detects DLL _LOST_LOCK. The PIB_RD_MAILBOX0 will contain the
PIB_DLL_CTRL register.
0x35: The bootloader detects PIB_PIB_ERR bit. The PIB_RD_MAILBOX0 will contain the
PIB_PIB_ERROR register.
0x36: The bootloader detects PIB_GPIF_ERR bit. The PIB_RD_MAILBOX0 will contain the
PIB_PIB_ERROR register.
dAddr
4-byte
Sender: Address used by command 1 and 3
dData[bLenStatus]
Data length determine by bLenStatus
Sender: Data to be filled by the Sender
Note The error code bLenStatus will be reported on the mailbox of the GPIF II.
When downloading firmware to FX3 using sync ADMUX, the external AP should do the following:
Command block length should be exactly 512 bytes.
Response block length should be exactly 512 bytes.
The bootloader binary image should be converted to a data stream that is segmented in multiples of 512 bytes.
The data chunk of the bootloader image should not be larger than 8K. For instance, on the command 0x02, the
bLenStatus should not be larger than 16 blocks (8K bytes).
The host should not send more than the total image size.
The bootloader does not support queuing commands. Therefore, every time a command is sent, the host must read
the response.
You should prevent the corruption of this API structure during the downloading process.
The host should not download firmware to the reserved bootloader SYSTEM address (0x4000_0000 to 0x4000_23FF).
An error will be returned if the firmware application attempts to use this space.
The first 1280 bytes of DTCM should not be used (0x1000_0000 – 0x1000_04FF).
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On the WRITE_DATA_CMD: When bLenStatus = 0, the bootloader jumps to the Program Entry of the dAddr.
9.1.7
Firmware Download Example
This section describes a simple way to implement firmware download from a host processor to FX3 via the 16-bit
synchronous ADMux interface.
The host processor communicates with the FX3 bootloader to perform the firmware download. The communication
requires the host processor to read and write FX3 registers and data sockets.
Note Refer to the “FX3 Terminology” section in the Getting Started with EZ-USB FX3 application note to learn about
the concept of sockets in FX3.
The host processor uses available GPIF II sockets to transfer blocks of data into and out of FX3. The FX3 bootloader
maintains three data sockets to handle the firmware download protocol: one each for command, response, and firmware
data.
#define CY_WB_DOWNLOAD_CMD_SOCKET
socket
#define CY_WB_DOWNLOAD_DATA_SOCKET
#define CY_WB_DOWNLOAD_RESP_SOCKET
(0x00)
// command block write only
(0x01)
(0x02)
// data block read/write socket
// response read only socket
The host processor communicates with the FX3 bootloader via these data sockets to carry out the firmware download.
The command and response are data structures used for the firmware download protocol. Both are 512 bytes in size.
The bit fields are defined in these data structures to perform various functions by the FX3 bootloader. In the simple
example implementation given in this document, only the first 4 bytes of both command and response are actually
used. The rest of the data bytes in the command and response are don't cares.
From the high-level FX3 firmware, the download requires the host processor to perform the following sequence of
socket accesses:
1.
One command socket write with command block initialized as:
command[0] = 'C';
command[1] = 'Y';
command[2] = 0x02;
command[3] = 0x01;
2.
One response socket read that expects response block data as:
response[0] = 'W';
response[1] = 'B';
//response[2] = 0x0;
response[3] = 0x0;
3.
/* first two bytes are signature bytes with
constant value of "CY" */
/* 0x2 is value for boot mode command. */
/* 1 data block */
/* first two bytes are signature bytes with
constant value of "WB" */
/* this byte is don't care. */
/* indicate command is accepted */
One data socket write that transfers the entire firmware image in terms of byte array into FX3.
Note that once the firmware image has been completely transferred, the FX3 bootloader automatically jumps to the
entry point of the newly downloaded firmware and starts executing. Before the host process can communicate with the
downloaded firmware, it is recommended to wait for a certain amount of time (depending on the firmware
implementation) to allow the firmware to be fully initialized. An even better option is to implement in the firmware a
status update via mailbox registers after the initialization. In this case, the host processor is notified whenever the
firmware is ready.
9.1.8
Processor Port (P-Port) Register Map
The register list shown in Table 28 indicates how the PP_xxx registers are mapped on the external P-Port address
space. Addresses in this space indicate a word, not a byte address. The sync ADMux interface provides eight address
lines to access these registers.
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Table 28. Processor Port Register Map
Register Name
Address
Width (bits)
Description
PP_ID
0x80
16
P-Port Device ID Register. Provides device ID information.
PP_INIT
0x81
16
P-Port reset and power control. This register is used for reset and power
control and determines endian orientation of the P-Port.
PP_CONFIG
0x82
16
P-Port configuration register.
PP_IDENTIFY
0x83
16
P-Port identification register. The lower 8 bits of this register are readonly and defaulted to 0x81.
PP_INTR_MASK
0x88
16
P-Port Interrupt Mask Register. This register has the same layout as
PP_EVENT and masks which events lead to assertion of interrupt.
PP_DRQR5_MASK
0x89
16
P-Port DRQ/R5 Mask Register. This register has the same layout as
PP_EVENT and masks which events lead to assertion of interrupt or
DRQ/R5 respectively.
PP_ERROR
0x8C
16
P-Port error indicator register.
PP_DMA_XFER
0x8E
16
P-Port DMA transfer register. This register is used to set up and control a
DMA transfer.
PP_DMA_SIZE
0x8F
16
P-Port DMA Transfer Size Register. This register indicates the
(remaining) size of the transfer.
PP_WR_MAILBOX
0x90
64
P-Port Write Mailbox Registers. These registers contain a message of up
to 8 bytes from the AP to FX3 firmware.
PP_MMIO_ADDR
0x94
32
P-Port MMIO Address Registers. These registers together form a 32-bit
address for accessing the FX3 internal MMIO space.
PP_MMIO_DATA
0x96
32
P-Port MMIO Data Registers These registers together form a 32-bit data
for accessing the FX3 internal MMIO space.
PP_MMIO
0x98
16
P-Port MMIO Control Register. This register controls the access to the
FX3 MMIO space.
PP_EVENT
0x99
16
P-Port Event Register. This register indicates all types of events that can
cause interrupt or DRQ to assert.
PP_RD_MAILBOX
0x9A
64
P-Port Read Mailbox Registers. These registers contain a message of
up to 8 bytes from FX3 firmware to the AP.
PP_SOCK_STAT
0x9E
32
P-Port Socket Status Register. These registers contain 1 bit for each of
the 32 sockets in the P-port, indicating the buffer availability of each
socket.
Refer to the “Registers” chapter in the EZ-USB FX3 TRM for the bit field definitions of these registers.
Before delving into the details of the FX3 firmware download, note that the following functions are frequently used in
the example implementation in this document and are platform dependent. Please contact Cypress Support for more
information on how these can be implemented on a specific platform.
IORD_REG16(); // 16-bit read from GPIF II
IOWR_REG16(); // 16-bit write to GPIF II
IORD_SCK16(); // 16-bit read from active socket set in PP_DMA_XFER. The address driven
on
//
on the Sync ADMux bus during the address phase is treated as a
//
don’t-care
IOWR_SCK16(); // 16-bit write to active socket set in PP_DMA_XFER. The address driven
on
//
on the Sync ADMux bus during the address phase is treated as a
//
don’t-care
Note: While performing register access, the most significant bit of the 8-bit address should be 1 notifying FX3 that it is
register access operation. Similarly, for performing socket access, the most significant bit should be set to 0.
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mdelay();
udelay();
// millisecond delay
// microsecond delay
Following is the example implementation of the fx3_firmware_download() function that takes a pointer to the firmware
data array and the size of the firmware as parameters.
/* Register addresses and the constants used in the code shown below. */
#define CY_WB_DOWNLOAD_CMD_SOCKET
#define CY_WB_DOWNLOAD_DATA_SOCKET
#define CY_WB_DOWNLOAD_RESP_SOCKET
0x00
0x01
0x02
// command block write only socket
// data block read/write socket
// response read only socket
// All register addresses defined with bit 7 set to indicate Register access (not
Socket)
#define PP_CONFIG
#define CFGMODE
0x82
0x0040
int fx3_firmware_download(const u8 *fw, u16 sz)
{
u8 *command=0, *response=0;
u16 val;
u32 blkcnt;
u16 *p = (u16 *)fw;
int i=0;
printf("FX3 Firmware Download with size = 0x%x\n", sz);
/* Check PP_CONFIG register and make sure FX3 device is configured */
/*
When FX3 bootloader is up with correct PMODE, bootloader configures */
/*
the GPIF II into proper interface and sets the CFGMODE bit on PP_CONFIG
*/
val = IORD_REG16(PP_CONFIG);
if ((val & CFGMODE)== 0) {
printf("ERROR: WB Device CFGMODE not set !!! PP_CONFIG=0x%x\n", val);
return FAIL;
}
/* A good practice to check for size of image */
if (sz > (512*1024)) {
printf("ERROR: FW size larger than 512kB !!!\n");
return FAIL;
}
/* Allocate memory for command and response */
/* Host processor may use DMA sequence to transfer the command and response */
/* In that case make sure system is allocating contiguous physical memory area
*/
command = (u8 *) malloc(512);
response = (u8 *) malloc(512);
memset(command, 0, 512);
memset(response, 0, 512);
if (command==0 || response==0) {
printf("ERROR: Out of memory !!!\n");
return FAIL;
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}
/* Initialize the command block */
command[0] = 'C';
command[1] = 'Y';
command[2] = 0x02;
/* Enter boot mode command. */
command[3] = 0x01;
/* 1 data block */
/* Print the command block if you like to see it */
for (i=0; i<512; i++) {
if (!(i%16))
printf("\n%.3x: ", i);
printf("%.2x ",command[i]);
}
printf("\n");
/* write boot command into command socket */
sck_bootloader_write(CY_WB_DOWNLOAD_CMD_SOCKET, 512, (u16 *)command);
/* read the response from response socket */
sck_bootloader_read(CY_WB_DOWNLOAD_RESP_SOCKET, 512, (u16 *)response);
/* Check if correct response */
if ( response[3]!=0 || response[0]!='W' || response[1]!='B' ) {
printf("ERROR: Incorrect bootloader response = 0x%x
!!!\n",response[3]);
for (i=0; i<512; i++) {
if (!(i%16))
printf("\n%.3x: ", i);
printf("%.2x ",response[i]);
}
printf("\n");
kfree(command);
kfree(response);
return FAIL;
}
/* Firmware image transfer must be multiple of 512 byte */
/* Here it rounds up the firmware image size */
/* and write the array to data socket */
blkcnt = (sz+511)/512;
sck_bootloader_write(CY_WB_DOWNLOAD_DATA_SOCKET, blkcnt*512, p);
/* Once the transfer is completed, bootloader automatically jumps to */
/* entry point of the new firmware image and start executing */
kfree(command);
kfree(response);
mdelay(2);
return PASS;
/* let the new image come up */
}
Following is an example implementation of the socket write and socket read functions. Besides the data direction,
function implementations for both socket write and read are based on the following command, configuration, and status
bits on the PP_* register interface:
PP_SOCK_STAT.SOCK_STAT[N]. For each socket, this status bit indicates that a socket has a buffer available
to exchange data (it has either data or space available).
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PP_DMA_XFER.DMA_READY. This status bit indicates whether the GPIF II is ready to service reads from or
writes to the active socket (the active socket is selected through the PP_DMA_XFER register).
PP_EVENT.DMA_READY_EV mirrors PP_DMA_XFER.DMA_READY with a short delay of a few cycles.
PP_EVENT.DMA_WMARK_EV. This status bit is similar to DMA_READY, but it deasserts a programmable
number of words before the current buffer is completely exchanged. It can be used to create flow control signals
with offset latencies in the signaling interface.
PP_DMA_XFER.LONG_TRANSFER. This config bit indicates if long (multibuffer) transfers are enabled. This bit
is set by the application processor as part of transfer initiation.
PP_CONFIG.BURSTSIZE and PP_CONFIG.DRQMODE. These config bits define and enable the size of the
DMA burst. Whenever the PP_CONFIG register is updated successfully, the FX3 bootloader responds with a
value 0x33 in the PP_RD_MAILBOX register.
PP_DMA_XFER.DMA_ENABLE. This command and status indicates that DMA transfers are enabled. This bit is
set by the host processor as part of transfer initiation and cleared by FX3 hardware upon transfer completion for
short transfers and by the application processor for long transfers.
/* Register addresses and the constants used in the code shown below. */
#define PP_CONFIG
#define CFGMODE
0x82
0x0040
#define PP_DRQR5_MASK
#define DMA_WMARK_EV
0x89
0x0800
#define PP_DMA_XFER
#define LONG_TRANSFER
#define DMA_DIRECTION
#define DMA_ENABLE
#define PP_EVENT
#define DMA_READY_EV
0x8E
0x0400
0x0200
0x0100
0x99
0x1000
#define PP_RD_MAILBOX0
registers
#define PP_RD_MAILBOX1
#define PP_RD_MAILBOX2
#define PP_RD_MAILBOX3
0x9A
0x9B
0x9C
0x9D
#define PP_SOCK_STAT_L
#define PP_SOCK_STAT_H
0x9E
0x9F
// 64 Bit register accessed as 4 x 16 bit
// LSB 16 bits of 32 bit register
// MSB 16 bits of 32 bit register
static u32 sck_bootloader_write(u8 sck, u32 sz, u16 *p)
{
u32 count;
u16 val, buf_sz;
int i;
buf_sz = 512;
/* Poll for PP_SOCK_STAT_L and make sure socket status is ready */
do {
val = IORD_REG16(PP_SOCK_STAT_L);
udelay(10);
} while(!(val&(0x1<<sck)));
/* write to pp_dma_xfer to configure transfer
socket number, rd/wr operation, and long/short xfer modes */
val = (DMA_ENABLE | DMA_DIRECTION | LONG_TRANSFER | sck);
IOWR_REG16(PP_DMA_XFER, val);
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/* Poll for DMA_READY_EV */
count = 10000;
do {
val = IORD_REG16(PP_EVENT);
udelay(10);
count--;
} while ((!(val & DMA_READY_EV)) && (count != 0));
if (count == 0) {
printf("%s: Fail timeout; Count = 0\n", __func__);
return FAIL;
}
/* enable DRQ WMARK_EV for DRQ assert */
IOWR_REG16(PP_DRQR5_MASK, DMA_WMARK_EV);
/* Change FX3 FW to single cycle mode */
val = IORD_REG16(PP_CONFIG);
val = (val&0xFFF0)|CFGMODE;
IOWR_REG16(PP_CONFIG, val);
/* Poll for FX3 FW config init ready */
count = 10000;
do {
val = IORD_REG16 (PP_RD_MAILBOX2);
udelay(10);
count --;
} while ((!(val & 0x33)) || count==0); /* CFGMODE bit is cleared by FW */
if (count == 0) {
printk("%s: Fail timeout; Count = 0\n", __func__);
return FAIL;
}
count=0;
do {
for (i = 0; i < (buf_sz / 2); i++)
IOWR_SCK16(*p++); /* Write 512 bytes of data continuously to data socket 16
bits at a time ( Sync ADMux has 16 data lines) */
count += (buf_sz / 2);
if (count < (sz/2))
do {
udelay(10);
val = IORD_REG16 (PP_SOCK_STAT_L); /* After writing 512 bytes to data
socket of the device, P-Port Socket Status Register is read to check if the Socket is
available for reading or writing next set of 512 bytes data */
} while(!(val&(0x1<<sck)));/* You remain in this Do-while loop till
PP_SOCK_STAT_L register makes the bit corresponding to the socket as 1 indicating
socket is now available for next read/write */
} while (count < (sz/2)); /* sz is the total size of data to be written. In case of
firmware_download, sz will be total size of the firmware */
/* disable dma */
val = IORD_REG16(PP_DMA_XFER);
val &= (~DMA_ENABLE);
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IOWR_REG16(PP_DMA_XFER, val);
printf("DMA write completed .....\n");
return PASS;
}
static u32 sck_bootloader_read(u8 sck, u32 sz, u16 *p)
{
u32 count;
u16 val, buf_sz;
int i;
buf_sz = 512;
/* Poll for PP_SOCK_STAT_L and make sure socket status is ready */
do {
val = IORD_REG16(PP_SOCK_STAT_L);
udelay(10);
} while(!(val&(0x1<<sck)));
/* write to PP_DMA_XFER to configure transfer
socket number, rd/wr operation, and long/short xfer modes */
val = (DMA_ENABLE | LONG_TRANSFER | sck);
IOWR_REG16(PP_DMA_XFER, val);
/* Poll for DMA_READY_EV */
count = 10000;
do {
val = IORD_REG16 (PP_EVENT);
udelay(10);
count--;
} while ((!(val & DMA_READY_EV)) && (count != 0));
if (count == 0) {
printk("%s: Fail timeout; Count = 0\n", __func__);
return FAIL;
}
/* enable DRQ WMARK_EV for DRQ assert */
IOWR_REG16(PP_DRQR5_MASK, DMA_WMARK_EV);
/* Change FX3 FW to single cycle mode */
val = IORD_REG16(PP_CONFIG);
val = (val&0xFFF0)|CFGMODE;
IOWR_REG16(PP_CONFIG, val);
/* Poll for FX3 FW config init ready */
count = 10000;
do {
val = IORD_REG16 (PP_RD_MAILBOX2);
udelay(10);
count --;
} while ((!(val & 0x33)) || count==0); /* CFGMODE bit is cleared by FW */
if (count == 0) {
printk("%s: Fail timeout; Count = 0\n", __func__);
return -1;
}
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count=0;
do {
for (i = 0; i < (buf_sz / 2); i++) {
p[count+i] = IORD_SCK16();
}
count += (buf_sz / 2); /* count in words */
if (count < (sz/2))
do {
udelay(10);
val = IORD_REG16 (PP_SOCK_STAT_L);
} while(!(val&(0x1<<sck)));
} while (count < (sz/2));
/* disable dma */
val = IORD_REG16(PP_DMA_XFER);
val &= (~DMA_ENABLE);
IOWR_REG16(PP_DMA_XFER, val);
printf("DMA read completed .....\n");
return PASS;
}
9.2
Boot Image Format
For sync ADMux boot, the booloader expects the firmware image to be in the format shown in Table 29. The EZ-USB
FX3 SDK provides a software utility that can be used to generate a firmware image in the format required for sync
ADMux boot. Please refer to the elf2img utility located in the C:\Program Files\Cypress\EZ-USB FX3
SDK\1.3\util\elf2img directory after installing the SDK. For 64-bit systems, the first folder in the path is Program
Files(x86). The number 1.3 in the directory path is the version number of the SDK, and it can vary based on the latest
release of the FX3 SDK.
Note that the elf2img post-build command generates an .img fie. This then needs to be converted into an array that can
be used for the download example shown previously. Figure 11 shows how the elf2img post-build command is issued,
followed by an example for printing the contents of the .img file into an array in ASCII format.
Table 29. Boot Image Format for Sync ADMux Boot Option
Binary Image Header
Length (16-bit)
Description
wSignature
1
Signature 2 bytes initialize with “CY” ASCII text
bImageCTL;
½
Bit0 = 0: execution binary file; 1: data file type
Bit3:1 Do not use when booting in SPI EEPROM
Bit5:4(SPI speed):
00: 10 MHz
01: 20 MHz
10: 30 MHz
11: Reserved
Bit7:6: Reserved, should be set to zero
bImageType;
½
bImageType = 0xB0:Normal FW binary image with checksum
bImageType = 0xB2: SPI boot with new VID and PID
dLength 0
2
First section length, in long words (32-bit)
When bImageType = 0xB2, the dLength 0 will contain PID and VID. The
bootloader ignores the rest of the following data.
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Binary Image Header
dAddress 0
Length (16-bit)
2
Description
First section address of Program Code.
Note The internal ARM address is byte addressable, so the address for each
section should be 32-bit aligned.
dData[dLength 0]
dLength 0*2
…
Image Code/Data must be 32-bit aligned.
More sections
dLength N
2
0x00000000 (Last record: termination section)
dAddress N
2
Should contain valid Program Entry (Normally, it should be the startup code, for
example, the RESET vector.)
Note: If bImageCTL.bit0 = 1, the bootloader will not
transfer the execution to this Program Entry.
If bImageCTL.bit0 = 0, the bootloader will transfer the execution to this Program
Entry. This address should be in the ITCM area or SYSTEM RAM area. The
bootloader does not validate the Program Entry.
dCheckSum
2
32-bit unsigned little endian checksum data will start from the first section to the
the termination section. The checksum will not include the dLength, dAddress,
and Image Header
Example of boot image format organized in long-word format:
Location1: 0xB0 0x10 ’Y’ ’C’
Location2: 0x00000004
Location3: 0x40008000
Location4: 0x12345678
Location5: 0x9ABCDEF1
Location6: 0x23456789
Location7: 0xABCDEF12
Location8: 0x00000002
Location9: 0x40009000
Location10: 0xDDCCBBAA
Location11: 0x11223344
Location12: 0x00000000
Location13: 0x40008000
Location 14: 0x6AF37AF2
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//CY Signature, 20 MHz, 0xB0 Image
//Image length of section 1 = 4
//1st section stored in SYSMEM RAM at 0x40008000
//Image starts (Section1)
//Section 1 ends
//Image length of section 2 = 2
//2nd section stored in SYSMEM RAM at 0x40009000
//Section 2 starts
//Termination of Image
//Jump to 0x40008000 on FX3 System RAM
//Checksum (0x12345678 + 0x9ABCDEF1 + 0x23456789 +
0xABCDEF12+ 0xDDCCBBAA +0x11223344)
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Figure 11. Post-Build Command in Eclipse IDE
The following is an example of code for printing the contents of the .img file into an array in ASCII format:
#include <stdio.h>
#include <stdint.h>
int main (int argc, char *argv[])
{
char *filename = "firmware.img";
FILE *fp;
int i = 0;
uint32_t k;
if (argc > 1)
filename = argv[1];
fprintf (stderr, "Opening file %s\n", filename);
fp = fopen (filename, "r");
printf ("const uint8_t fw_data[] = {\n\t");
while (!feof(fp))
{
fread (&k, sizeof (uint32_t), 1, fp);
printf ("0x%02x, 0x%02x, 0x%02x, 0x%02x,",
((uint8_t *)&k)[0], ((uint8_t *)&k)[1],
((uint8_t *)&k)[2], ((uint8_t *)&k)[3]);
i++;
if (i == 4)
{
i = 0;
printf ("\n\t");
}
else
printf (" ");
}
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printf ("\n};\n");
fclose (fp);
return 0;
}
10
eMMC Boot
The FX3S peripheral controller supports booting from the eMMC device. Connect the eMMC device to the S0 storage
port of FX3S from which the firmware can be booted. FX3S also supports eMMC boot with USB fall back. If no valid
firmware is found in the eMMC, FX3S will fall back to the USB boot mode. For the PMODE pin settings that are required
to enable eMMC boot, refer to Table 30.
Table 30. PMODE Settings for eMMC Boot
PMODE[2]
PMODE[1]
PMODE[0]
Boot option
1
0
0
eMMC
0
0
0
eMMC -> USB
After downloading the FX3 SDK, refer to cyfwstorprog_usage.txt for detailed instructions on how to implement eMMC
boot . This file is located at:
<FX3 SDK installation path>\Cypress\EZ-USB FX3 SDK\1.x\util\cyfwstorprog\
Note: eMMC boot is only supported by the FX3S peripheral.
11
Default State of I/Os During Boot
Table 31 shows the default state of the FX3 I/Os for the different boot modes, while the bootloader is executing before
application firmware download).
Note: The default state of the GPIOs need not be same when FX3 is in reset and after the boot-loader finishes the
configuration.
Table 31. Default State of I/Os During Boot
GPIO
SPI Boot Default State
USB Boot
Default State
I2C Boot
Default State
Sync ADMux Boot
Default State
GPIO[0]
Tristate
Tristate
Tristate
Tristate
GPIO[1]
Tristate
Tristate
Tristate
Tristate
GPIO[2]
Tristate
Tristate
Tristate
Tristate
GPIO[3]
Tristate
Tristate
Tristate
Tristate
GPIO[4]
Tristate
Tristate
Tristate
Tristate
GPIO[5]
Tristate
Tristate
Tristate
Tristate
GPIO[6]
Tristate
Tristate
Tristate
Tristate
GPIO[7]
Tristate
Tristate
Tristate
Tristate
GPIO[8]
Tristate
Tristate
Tristate
Tristate
GPIO[9]
Tristate
Tristate
Tristate
Tristate
GPIO[10]
Tristate
Tristate
Tristate
Tristate
GPIO[11]
Tristate
Tristate
Tristate
Tristate
GPIO[12]
Tristate
Tristate
Tristate
Tristate
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GPIO
SPI Boot Default State
USB Boot
Default State
I2C Boot
Default State
Sync ADMux Boot
Default State
GPIO[13]
Tristate
Tristate
Tristate
Tristate
GPIO[14]
Tristate
Tristate
Tristate
Tristate
GPIO[1(5]
Tristate
Tristate
Tristate
Tristate
GPIO[16]
Tristate
Tristate
Tristate
CLK Input
GPIO[17]
Tristate
Tristate
Tristate
Input
GPIO[18]
Tristate
Tristate
Tristate
Input
GPIO[19]
Tristate
Tristate
Tristate
Input
GPIO[20]
Tristate
Tristate
Tristate
Input
GPIO[21]
Tristate
Tristate
Tristate
Output
GPIO[22]
Tristate
Tristate
Tristate
Tristate
GPIO[23]
Tristate
Tristate
Tristate
Input
GPIO[24]
Tristate
Tristate
Tristate
Tristate
GPIO[25]
Tristate
Tristate
Tristate
Tristate
GPIO[26]
Tristate
Tristate
Tristate
Tristate
GPIO[27]
Tristate
Tristate
Tristate
Input
GPIO[28]
Tristate
Tristate
Tristate
Tristate
GPIO[29]
Tristate
Tristate
Tristate
Tristate
GPIO[30]
PMODE[0] I/P to FX3
PMODE[0] I/P to FX3
PMODE[0] I/P to FX3
PMODE[0] I/P to FX3
GPIO[31]
PMODE[1] I/P to FX3
PMODE[1] I/P to FX3
PMODE[1] I/P to FX3
PMODE[1] I/P to FX3
GPIO[32]
PMODE[2] I/P to FX3
PMODE[2] I/P to FX3
PMODE[2] I/P to FX3
PMODE[2] I/P to FX3
GPIO[33]
Tristate
Tristate
Tristate
Tristate
GPIO[34]
Tristate
Tristate
Tristate
Tristate
GPIO[35]
Tristate
Tristate
Tristate
Tristate
GPIO[36]
Tristate
Tristate
Tristate
Tristate
GPIO[37]
Tristate
Tristate
Tristate
Tristate
GPIO[38]
Tristate
Tristate
Tristate
Tristate
GPIO[39]
Tristate
Tristate
Tristate
Tristate
GPIO[40]
Tristate
Tristate
Tristate
Tristate
GPIO[41]
Tristate
Tristate
Tristate
Tristate
GPIO[42]
LOW
LOW
LOW
LOW
GPIO[43]
Tristate
Tristate
Tristate
Tristate
GPIO[44]
Tristate
Tristate
Tristate
Tristate
GPIO[45]
Tristate (HIGH if SPI boot fails)
HIGH
HIGH
HIGH
GPIO[46]
HIGH
Tristate
Tristate
Tristate
GPIO[47]
Tristate
Tristate
Tristate
Tristate
GPIO[48]
HIGH
Tristate
Tristate
Tristate
GPIO[49]
Tristate
Tristate
Tristate
Tristate
GPIO[50]
Tristate (LOW if SPI boot fails)
Tristate
Tristate
Tristate
GPIO[51]
LOW
LOW
LOW
LOW
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GPIO
SPI Boot Default State
USB Boot
Default State
I2C Boot
Default State
Sync ADMux Boot
Default State
GPIO[52]
HIGH
Tristate
Tristate
Tristate
GPIO[53]
LOW (toggles during SPI transactions)
HIGH
HIGH
HIGH
GPIO[54]
HIGH
Tristate
Tristate
Tristate
GPIO[55]
Tristate
HIGH
HIGH
HIGH
GPIO[56]
LOW
Tristate
Tristate
Tristate
GPIO[57]
LOW
Tristate
Tristate
Tristate
Tristate
Tristate
GPIO[58] I2C_SCL
Tristate
Tristate
Tristate (Toggles
during transaction.,
then Tristated)
GPIO[59] I2C_SDA
Tristate
Tristate
Tristate
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A
Appendix: Steps for Booting Using FX3 DVK Board
This appendix describes the stepwise sequence for exercising USB boot, I2C boot, and SPI boot using the FX3 DVK
board. Figure 12 shows a part of the FX3 DVK board that contains switches and jumpers, which need to be configured
appropriately for each boot option. The required settings for them are also described.
Figure 12. FX3 DVK board: Essential Switches and Jumpers To Be Configured for Boot
SW25 – Switch to
control PMODE
input pins
SW40 – Switch to
control EEPROM
address
U44 –
EEPROM
socket
J101,102,103,104 –
Jumpers to connect
with SPI Flash
J96,97,97 – Jumpers to
control PMODE input pins
A.1
USB Boot
1.
Build the firmware image in the Eclipse IDE as shown in Figure 13, Figure 14. , and Figure 15. .
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Figure 13. Right-Click on Project in Eclipse IDE
Figure 14. Select Settings
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Figure 15. elf2img Command Configuration in Post-Build Steps for USB Boot Image
2.
Enable USB boot by setting the PMODE[2:0] pins to Z11. On the DVK board, this is done by configuring the
jumpers and switches as shown in Table 32.
Table 32. Jumper Configurations for USB Boot
Jumper/Switch
3.
Position
State of Corresponding PMODE Pin
J96 (PMODE0)
2-3 Closed
PMODE0 controlled by SW25
J97 (PMODE1)
2-3 Closed
PMODE1 controlled by SW25
J98 (PMODE2)
Open
PMODE2 Floats
SW25.1-8 (PMODE0)
Open (OFF position)
PMODE0 = 1
SW25.2-7 (PMODE1)
Open (OFF position)
PMODE1 = 1
SW25.3-6 (PMODE2)
Don’t care
PMODE2 Floats
When connected to a USB Host, the FX3 device enumerates in the Control Center as “Cypress USB BootLoader,”
as shown in Figure 16.
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Figure 16. Cypress USB BootLoader Enumeration in Control Center
4.
In the Control Center, select the FX3 device by choosing Program > FX3 > RAM, as shown in Figure 17. .
Figure 17. Select the Device From the Control Center
5.
Next, browse to the .img file to be programmed into the FX3 RAM. Double-click on the .img file, as shown in Figure
18.
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Figure 18. Select .img File
6.
A.2
A “Programming Succeeded” message is displayed on the bottom left of the Control Center, and the FX3 device
re-enumerates with the programmed firmware.
I2C Boot
1.
Build the firmware image in the Eclipse IDE as shown in Figure 19, Figure 20, and Figure 21
Figure 19. Right-Click on Project in Eclipse IDE
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Figure 20. Properties of Fx3BootAppGcc
Figure 21. elf2img Command Configuration in Post-Build Steps for I2C Boot Image
2.
Enable USB boot, by setting the PMODE[2:0] pins to Z11. On the DVK board, this is done by configuring the
jumpers and switches as shown in Table 33
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Table 33 Jumper Configurations for USB Boot
Jumper/Switch
Position
State of Corresponding PMODE Pin
J96 (PMODE0)
2-3 Closed
PMODE0 controlled by SW25
J97 (PMODE1)
2-3 Closed
PMODE1 controlled by SW25
J98 (PMODE2)
Open
PMODE2 Floats
SW25.1-8 (PMODE0)
Open (OFF)
PMODE0 = 1
SW25.2-7 (PMODE1)
Open (OFF)
PMODE1 = 1
SW25.3-6 (PMODE2)
Don’t care
PMODE2 Floats
3.
When connected to a USB Host, the FX3 device enumerates in the Control Center as “Cypress USB BootLoader,”
as shown in Figure 22. .
Figure 22. Cypress USB BootLoader Enumeration in Control Center
4.
Before attempting to program the EEPROM, ensure that the address signals of the EEPROM are configured
correctly using switch SW40 (For Microchip part 24AA1025, 1-8 ON, 2-7 ON, 3-6 OFF). Also, the I2C Clock (SCL)
and data Line (SDA) jumpers J42 and J45 pins 1–2 should be shorted on the DVK board. In the Control Center,
select the FX3 device. Next, choose Program > FX3 > I2C E2PROM, as shown in Figure 23. . This causes a
special I2C boot firmware to be programmed into the FX3 device, which then enables programming of the I2C
device connected to FX3. Now the FX3 device re-enumerates as “Cypress USB BootProgrammer,” as shown in
Figure 24. .
Figure 23. Choose Program > FX3 > I2C E2PROM
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Figure 24. FX3 Re-Enumerates as “Cypress USB BootProgrammer”
5.
After the FX3 DVK board enumerates as “Cypress USB BootProgrammer,” the Control Center application prompts
you to select the firmware binary to download. Browse to the .img file that is to be programmed into the I2C
EEPROM, as shown in Figure 25. .
Figure 25. Select Firmware Image to Download
After programming is complete, the bottom left corner of the window displays “Programming of I2C EEPROM
Succeeded,” as shown in Figure 26. .
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Figure 26. I2C EEPROM Programming Update in Control Center
6.
Change the PMODE pins on the DVK board to Z1Z to enable I2C boot. On the DVK board, this is done by
configuring the jumpers and switches as shown in Table 34.
Table 34. Jumper Configurations for I2C Boot
Jumper/Switch
Position
State of Corresponding PMODE Pin
J96 (PMODE0)
Open
PMODE0 Floats
J97 (PMODE1)
2-3 Closed
PMODE1 controlled by SW25
J98 (PMODE2)
Open
PMODE2 Floats
SW25.1-8 (PMODE0)
Don’t care
PMODE0 Floats
SW25.2-7 (PMODE1)
Open (OFF position)
PMODE1 = 1
SW25.3-6 (PMODE2)
Don’t care
PMODE2 Floats
7.
Reset the DVK. Now the FX3 device boots from the I2C EEPROM.
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A.3
SPI Boot
1.
Build the firmware image in the Eclipse IDE as shown in Figure 27. , Figure 28, and Figure 29.
Figure 27. Right-Click on Project in Eclipse IDE
Figure 28. Select “Settings”
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Figure 29. elf2img Command Configuration in Post-Build Steps for SPI Boot Image
2.
Enable USB boot by setting the PMODE[2:0] pins to Z11. On the DVK board, this is done by configuring the
jumpers and switches as shown in Table 35.
Table 35. Jumper Configurations for USB Boot
Jumper/Switch
Position
State of Corresponding PMODE Pin
J96 (PMODE0)
2-3 Closed
PMODE0 controlled by SW25
J97 (PMODE1)
2-3 Closed
PMODE1 controlled by SW25
J98 (PMODE2)
Open
PMODE2 Floats
SW25.1-8 (PMODE0)
Open (OFF position)
PMODE0 = 1
SW25.2-7 (PMODE1)
Open (OFF position)
PMODE1 = 1
SW25.3-6 (PMODE2)
Don’t care
PMODE2 Floats
3.
When connected to a USB Host, the FX3 device enumerates in the Control Center as “Cypress USB BootLoader,
as shown in Figure 30.
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Figure 30. Cypress USB BootLoader Enumeration in Control Center
4.
In the Control Center, select the FX3 device and then choose Program > FX3 > SPI FLASH, as shown in Figure
31. . Browse to the .img file to be programmed into the SPI flash, as shown in Figure 32.
Figure 31. Choose Program > FX3 > SPI FLASH in Control Center
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Figure 32. Double-Click on the .img File to be Programmed into SPI Flash
5.
After programming is complete, the bottom left corner of the window displays “Programming of SPI FLASH
Succeeded,” as shown in Figure 33. .
Figure 33. Successful Programming of SPI Flash Indicated at Bottom Left of Control Center
6.
Change the PMODE[2:0] pins on the DVK board to 0Z1 to enable SPI boot. On the DVK board, this is done by
configuring the jumpers and switches as shown in Table 36.
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EZ-USB® FX3™/FX3S™ Boot Options
Table 36. Jumper Configurations for SPI Boot
Jumper/Switch
Position
State of Corresponding PMODE Pin
J96 (PMODE0)
2-3 Closed
PMODE0 controlled by SW25
J97 (PMODE1)
Open
PMODE1 Floats
J98 (PMODE2)
2-3 Closed
PMODE2 controlled by SW25
SW25.1-8 (PMODE0)
Open (OFF position)
PMODE0 = 1
SW25.2-7 (PMODE1)
Don’t care
PMODE1 Floats
SW25.3-6 (PMODE2)
Closed (ON position)
PMODE2 = 0
7.
Reset the DVK. Now the FX3 boots from the SPI flash.
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EZ-USB® FX3™/FX3S™ Boot Options
Document History
Document Title: AN76405 - EZ-USB® FX3™/FX3S™ Boot Options
Document Number: 001-76405
Revision
**
ECN
3616262
Orig. of
Change
VSO
Submission
Date
05/14/2012
Description of Change
New application note
Merged the following application notes into AN76405: AN73150,
AN70193, AN68914, and AN73304
Clarified the SPI Flash parts tested for boot
*A
3807283
OSG
11/19/2012
Added an example for Sync ADMux firmware download implementation
Added a step-by-step-sequence of instructions for testing boot options on
the DVK
Added a table with the default state of the GPIOs during boot
Template updates.
*B
3836755
OSG
Table 26 – Updated default state of GPIO[33] for all boot modes
12/10/12
Updated default states of GPIO[51], GPIO[55]-[57] for SPI boot mode.
*C
3964017
OSG
Updated GPIO[55] in Table 31.
04/12/13
Added Figure 1 to show all the boot options discussed in this application
note.
Added pin mapping for I2C, SPI, and sync ADMux interfaces.
*D
4422078
RSKV
06/27/2014
Added command set of supported SPI flashes.
Added the Processor Port register map.
Pointed to FX3S datasheet for sync ADMux timing diagrams.
Added SPI flash part numbers supported by FX3
Updated the I2C EEPROM part number that is in production
Added more information in Sync ADMux boot options
Added read and write waveforms for Sync ADMux boot
Updated GPIO[45] and GPIO[50] in Table 30.
*E
4827883
MDDD
07/28/2015
Corrected the RDY pin mapping for Sync ADMux.
Removed secure boot (0xB1) format
Added eMMC boot details
Added FX3S and CX3 parts
Changed the AN title by including FX3S
Updated template
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EZ-USB® FX3™/FX3S™ Boot Options
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