DATASHEET

DATASHEET
Digital DC/DC PMBus 33A Module
ISL8271M
Features
The ISL8271M is a 33A step-down DC/DC power supply module
with integrated digital PWM controller, synchronous power
switches, an inductor and passives. Only bulk input and output
capacitors are needed to finish the design. The 33A of
continuous output current can be delivered without a need of
airflow or a heatsink. The thermally enhanced HDA module is
capable of dissipating heat directly into the PCB.
• Complete digital switch mode power supply
- Wide VIN range: 4.5V to 14V
- Programmable VOUT range: 0.6V to 5V
The ISL8271M uses ChargeMode™ control architecture, which
responds to a transient load within a single switching cycle.
The ISL8271M comes with a preprogrammed configuration for
operating in a pin strap mode; output voltage, switching
frequency and device SMBus address can be programmed
with external resistors. More configuration such as soft-start
and fault limits can be easily programmed or changed via
PMBus compliant serial bus interface. PMBus can be used to
monitor voltages, current, temperatures and fault status. The
ISL8271M is supported by PowerNavigator™ software, a
graphical user interface (GUI) that can be used to configure
modules to a desired solution.
The ISL8271M is available in a 40-pin compact 17mmx19mm
HDA module with very low profile height of 3.55mm, suitable
for automated assembly by standard surface mount
equipment. The ISL8271M is RoHS compliant by exemption.
• PMBus compliant I2C communication interface
- Programmable VOUT, margining, UV/OV, IOUT limit,
soft-start/stop, sequencing and external synchronization
- Monitor: VIN, VOUT, IOUT, temperature, duty cycle,
switching frequency and faults
• ChargeMode control architecture
• ±1.0% VOUT accuracy over line, load and temperature
• Power-Good indicator
• Over-temperature protection
• Internal nonvolatile memory and fault logging
• Patented thermally enhanced HDA package
Applications
• Server, telecom, storage and datacom
• Industrial/ATE and networking equipment
• General purpose power for ASIC, FPGA, DSP and memory
Related Literature
• AN1925, “ISL8271MEVAL1Z Evaluation Board User Guide”
VIN
CIN
VIN
VOUT
VDD
VSEN+
VSEN-
2.2
m
19
COUT
m
17m
m
SCL
VDRVOUT
SDA
10µ
SALRT
SGND
PMBUS
INTERFACE
ISL8271M
VDRVIN
1µ
VOUT
3.55mm
PGND
NOTE:
1. Only bulk input and output capacitors are required to finish the design.
FIGURE 1. A COMPLETE DIGITAL SWITCH MODE POWER SUPPLY
June 17, 2016
FN8636.3
1
FIGURE 2. A SMALL PACKAGE FOR HIGH POWER DENSITY
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014, 2016. All Rights Reserved
Intersil (and design), ChargeMode, PowerNavigator and Digital-DC are trademarks owned by Intersil Corporation
or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
ISL8271M
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
ISL8271M Internal Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Efficiency Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transient Response Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Derating Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Derating Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
11
12
13
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMBus Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-start Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Undervoltage Lockout (UVLO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMBus Module Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output PreBias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Monitoring Using XTEMP Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitoring Via SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Snapshot Parameter Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NonVolatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
16
16
16
17
17
17
17
18
18
18
18
19
19
19
19
19
19
19
20
PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB Layout Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stencil Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reflow Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
21
21
21
21
PMBus Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PMBus™ Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PMBus Use Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PMBus Commands Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Firmware Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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FN8636.3
June 17, 2016
ISL8271M
Ordering Information
PART NUMBER
(Notes 2, 3, 4)
PART
MARKING
ISL8271MAIRZ
ISL8271M
ISL8271MEVAL1Z
Evaluation Board
TEMP RANGE
(°C)
-40 to +85
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
40 Ld 17x19 HDA
Y40.17x19
NOTES:
2. Add “-T” suffix for a 500 unit Tape and Reel option. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products are RoHS compliant by EU exemption 7C-I and 7A. They employ special Pb-free material sets; molding
compounds/die attach materials and NiPdAu plate-e4 termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see product information page for ISL8271M. For more information on MSL, please see tech brief TB363.
ISL
xxxxM
INTERSIL DEVICE DESIGNATOR
BASE PART NUMBER
FIRMWARE REVISION
A: FC01
OPERATING TEMPERATURE
I: INDUSTRIAL (‐ 40°C TO +85°C)
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3
F
T
R
Z
S
SHIPPING OPTION
BLANK: BULK
T: TAPE AND REEL
ROHS
Z: ROHS COMPLIANT
PACKAGE DESIGNATOR
R: HIGH DENSITY ARRAY (HDA)
FN8636.3
June 17, 2016
ISL8271M
Pin Configuration
SGND
NC
VSET
MGN
PGND
NC
SA
SALRT
SDA
SCL
EN
VDD
ISL8271M
(40 LD HDA)
TOP VIEW
27
26
25
24
23
22
21
20
19
18
17
16
XTEMP+
2
28 PG
XTEMP -
3
29 UVLO
NC
4
NC
5
VSEN+
6
VSEN -
7
VDRVOUT
8
PGND
9
38
37
40
SGND
15
VR5
36
VR6
35
SGND
30
34
PHASE
VDRVIN
SYNC 39
VDDC
1
V25
DDC
PGND
10
33
VIN
NC
11
31
32
NC
VOUT 14
PGND
PGND
VSWH
13
12
Pin Descriptions
PIN
LABEL
TYPE
DESCRIPTION
1
DDC
I/O
A Digital-DC™ bus. This dedicated bus provides the communication channel between devices for features such as
sequencing and fault spreading. The DDC pin on all Digital-DC devices should be connected together. A pull-up resistor
is required for this application.
2
XTEMP+
I
Differential external temperature sensor positive input pin.
3
XTEMP-
I
Differential external temperature sensor negative input pin.
6
VSEN+
I
Differential Output voltage sense feedback. Connect to positive output regulation point.
7
VSEN-
I
Differential Output voltage sense feedback. Connect to negative output regulation point.
8
VDRVOUT
PWR
Output of internal LDO for powering internal gate driver block. Place a 10µF ceramic capacitor at this pin. LDO output
is dedicated to powering internal gate driver stage only. Do not use this LDO for any other purpose.
9, 12, 23,
31, 34
PGND
PWR
Power ground. Refer to the “PCB Layout Guidelines” on page 20 for the PGND pad connections and decoupling
capacitors placement.
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4
FN8636.3
June 17, 2016
ISL8271M
Pin Descriptions
(Continued)
PIN
LABEL
TYPE
DESCRIPTION
10
VDRVIN
PWR
Input supply to internal LDO for powering internal gate driver block. A RC filter is required if VIN supply is shared. Refer
to the “PCB Layout Guidelines” on page 20.
11
VIN
PWR
Main input supply. Refer to the“PCB Layout Guidelines” on page 20 for the decoupling capacitors placement from VIN
to PGND.
13
VSWH
PWR
Switch node. Refer to the “PCB Layout Guidelines” on page 20 for connecting VSWH pads to electrically isolated PCB
copper island to dissipate internal heat.
14
VOUT
PWR
Power supply output. Range: 0.6V to 5V. Refer to “Derating Curves” on page 12 for maximum recommended output
current at various output voltages.
15, 27,
40
SGND
PWR
Controller Signal ground. Refer to the “PCB Layout Guidelines” on page 20 for the SGND pad connections.
16
VDD
PWR
Input supply to digital controller. Connect VDD pad to VIN supply. Refer to the “PCB Layout Guidelines” on page 20 for
the decoupling capacitors placement from VDD to SGND.
17
EN
I
External enable input. Logic high enables the module.
18
SCL
I
Serial clock input. A pull-up resistor is required for this application.
19
SDA
I/O
Serial data. A pull-up resistor is required for this application.
20
SALRT
O
Serial alert. A pull-up resistor is required for this application.
21
SA
I
Serial bus address select pin. Refer to Table 6 for list of resistor values to set various serial bus address.
24
MGN
I
External VOUT margin control pin. Active high (>2V) signal at this pin sets VOUT margin high, Active low (<0.8V) sets
VOUT margin low and high impedance (float) will bring VOUT back to nominal voltage. Factory default range for
margining is nominal VOUT ±5%. When using PMBus to control margin command, leave this pin as no connect.
25
VSET
I
Output voltage selection pin. Refer to Table 3 for list of resistor values to set various output voltages.
28
PG
O
Power-Good output. Power-Good output can be open drain that requires pull-up resistor or push-pull output that can
drive a logic input.
29
UVLO
I
VDD undervoltage lockout selection. Refer to Table 5 for list of resistors value to set various UVLO levels.
30
PHASE
PWR
Switch node pad for DCR sensing. Electrically shorted inside to VSWH but for higher current sensing accuracy connect
PHASE pad to VSWH pad externally. Refer to the “PCB Layout Guidelines” on page 20.
35
VR6
PWR
6V Internal reference supply voltage.
36
VR5
PWR
5V Internal reference supply voltage.
37
VDDC
PWR
VDD Clean. Noise at the VDD pin is filtered with ferrite bead and capacitor. For VDD > 6V, leave this pin as no connect.
For 5.5  VDD  6V, connect VDDC pin to VR6 pin. For 4.5  VDD < 5.5V, connect VDDC pin to VR6 and VR5 pin.
38
V25
PWR
2.5V Internal reference supply voltage.
39
SYNC
I/O
4, 5, 22,
26, 32,
33
NC
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SYNC pin can be input to external clock for frequency synchronization or output to supply clock signal to other
modules for synchronization. Refer to Table 4 for list of resistor values to program various switching frequencies.
These are test pins and are not electrically isolated. Leave these pins as no connect.
5
FN8636.3
June 17, 2016
ISL8271M
FB
VIN
VDRVIN
VDRVOUT
V25
VR5
VR6
VDDC
VDD
ISL8271M Internal Block Diagram
LDO
LDO
LDO
INTERLEAVE
OT/UT OC/UC
Power
Management
SNAPSHOT
FAULT SPREADING
MARGINING
SS
OV/UV
VIN
VSET
EN
PG
DDC
MGN
LDO
SEQUENCE
PLL
0.24µH
LOGIC
SYNC
SYNC
OUT
VOUT
PWM OUT
D-PWM
PGND
NVM
SUPERVISOR
ChargeModeTM
CONTROL
PROTECTION
DRIVER AND FETS
CSA
100
ADC-10
VSEN+
VSA
ADC-10
VSEN-
VDRV
SCL
SDA
SALRT
100
VDD
EXTERNAL
TEMP
PMBus/I2C
INTERFACE
SA
XTEMP+
INTERNAL TEMP
SENSOR
100pF
SGND
XTEMP-
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6
PGND
SGND
DIGITAL CONTROLLER
FN8636.3
June 17, 2016
ISL8271M
Absolute Maximum Ratings
Thermal Information
Input Supply Voltage, VIN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 17V
Input Supply Voltage for Controller, VDD Pin . . . . . . . . . . . . . . -0.3V to 17V
Input Gate Driver Supply Voltage, VDRVIN Pin . . . . . . . . . . . . . -0.3V to 17V
Output Gate Driver Supply Voltage, VDRVOUT Pin . . . . . . . . . . . -0.3V to 6V
6V Internal Reference Supply Voltage, VR6 Pin . . . . . . . . . . . -0.3V to 6.6V
5V Internal Reference Supply Voltage, VR5 Pin . . . . . . . . . . . -0.3V to 6.5V
2.5V Internal Reference Supply Voltage, V25 Pin. . . . . . . . . . . . -0.3V to 3V
Logic I/O Voltage for DDC, EN, MGN, PG, DISB#
SA, SCL, SDA, SALRT, SYNC, UVLO, VMON, VSET . . . . . . . . . -0.3V to 6.0V
Analog Input Voltages for
VSEN+, XTEMP+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
VSEN-, XTEMP- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . 2000V
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . . 750V
Latch Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
40 LD HDA Package (Notes 5, 6) . . . . . . . .
7.5
2.2
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to Figure 31
Recommended Operating Conditions
Input Supply Voltage Range, VIN . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 14V
Input Supply Voltage Range for Controller, VDD . . . . . . . . . . . 4.5V to 14V
Output Voltage Range, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.6V to 5V
Output Current Range, IOUT(DC) (Note 9) . . . . . . . . . . . . . . . . . . . . 0A to 33A
Operating Junction Temperature Range, TJ. . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. JA is measured in free air with the module mounted on an evaluation board 3x4.5inch in size with 2oz surface and 2oz buried planes and multiple
via interconnects as specified on AN1925, “ISL8271MEVAL1Z Evaluation Board User Guide”.
6. For JC, the “case temp” location is the center of the package underside.
Electrical Specifications
VIN = VDD = 12V, fSW = 533kHz, COUT = 1340µF, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
40
50
mA
5.5
6.1
6.6
V
4.5
5.2
5.5
V
2.25
2.5
2.75
V
INPUT AND SUPPLY CHARACTERISTICS
IDD
Input Supply Current for Controller
VR6
6V Internal Reference Supply Voltage
VR5
5V Internal Reference Supply Voltage
V25
2.5V Internal Reference Supply Voltage
VDD_READ_RES
Input Supply Voltage for Controller
Read Back Resolution
VDD_READ_ERR
Input Supply Voltage for Controller
Read Back Total Error (Note 10)
VIN = VDD = 12V, VOUT = 0V, Module not
Enabled
IVR5 < 5mA
PMBus Read
10
Bits
±2
%FS
OUTPUT CHARACTERISTICS
VOUT_RANGE
Output Voltage Adjustment Range
VIN > VOUT + 1.8V
VOUT_RES
Output Voltage Set-Point Range
Configured using PMbus
VOUT_ACCY
Output Voltage Set-Point Accuracy
(Notes 8, 10)
Includes Line, Load and Temperature
(-20°C ≤ TA ≤ +85°C)
VOUT_READ_RES
Output Voltage Read Back Resolution
VOUT_READ_ERR
Output Voltage Read Back Total Error
(Note 10)
IOUT_READ_RES
Output Current Read Back Resolution
IOUT_RANGE
IOUT_READ_ERR
0.54
5.5
±0.025
-1
+1
-2
10
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7
±2
%VOUT
Bits
33
PMBus Read at Max Load
%VOUT
Bits
+2
Output Current Range (Note 9)
Output Current Read back Total Error
%
10
PMBus Read
V
A
A
FN8636.3
June 17, 2016
ISL8271M
Electrical Specifications
VIN = VDD = 12V, fSW = 533kHz, COUT = 1340µF, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
5000
ms
SOFT-START AND SEQUENCING
tON_DELAY
tON_DELAY_ACCY
Delay Time From Enable to VOUT Rise
Output Voltage Ramp-up Time
tON_RISE_ACCY
Output Voltage Ramp-up Time
Accuracy
tOFF_DELAY_ACCY
tOFF_FALL
tON_FALL_ACCY
2
tON_DELAY Accuracy
tON_RISE
tOFF_DELAY
Configured using PMBus
Delay Time From disable to VOUT Fall
±2
Configured using PMBus
0.5
100
ms
±250
Configured using PMBus
2
tOFF_DELAY Accuracy
Output Voltage Fall Time
ms
µs
5000
ms
±2
Configured using PMBus
0.5
Output Voltage Fall Time Accuracy
ms
100
ms
±250
µs
POWER-GOOD
VPG_DELAY
Power-good Delay
Configured using PMBus
0
5000
ms
Configurable VIA PMBus
-50
150
C
-5
+5
C
TEMPERATURE SENSE
TSENSE_RANGE
Temperature Sense Range
INT_TEMPACCY
Internal Temperature Sensor Accuracy Tested at +100°C
XTEMPACCY
External Temperature Sensor Accuracy Using 2N3904 NPN transistor
C
±5
FAULT PROTECTION
VDD_UVLO_RANGE
VDD Undervoltage Threshold Range
Measured internally
4.18
16
V
VDD_UVLO_ACCY
VDD Undervoltage Threshold Accuracy
(Note 10)
±2
%FS
VDD_UVLO_DELAY
VDD Undervoltage Response Time
10
µs
VOUT+15
%
VOUT_OV_RANGE
VOUT_UV_RANGE
VOUT Overvoltage Threshold Range
VOUT Undervoltage Threshold Range
VOUT_OV/UV_ACCY
VOUT OV/UV Threshold Accuracy
(Note 8)
VOUT_OV/UV_DELAY
VOUT OV/UV Response Time
Factory default
Configured using PMBus
Configured using PMBus
ILIMIT_ACCY
Output Current Limit Set-Point
Accuracy (Note 10)
Tested at IOUT_OC_FAULT_LIMIT = 40A
ILIMIT_DELAY
Output Current Fault Response Time
(Note 11)
Factory default
TJUNCTION
TJUNCTION_HYS
VOUT +5
Over-temperature Protection Threshold Factory Default
(Controller Junction Temperature)
Configured using PMBus
VOUT_MAX
VOUT-15
Factory default
%
%
0
VOUT -5
%
-2
+2
%
10
µs
±10
%FS
3
tSW
125
C
-40
Thermal Protection Hysteresis
125
C
C
15
OSCILLATOR AND SWITCHING CHARACTERISTICS
fSW_RANGE
fSW_ACCY
EXT_SYNCPW
Switching Frequency Range
Switching Frequency Set-Point
Accuracy
Minimum Pulse Width Required from
External SYNC Clock
Submit Document Feedback
8
Measured at 50% Amplitude
296
1067
kHz
-5
+5
%
150
ns
FN8636.3
June 17, 2016
ISL8271M
Electrical Specifications
VIN = VDD = 12V, fSW = 533kHz, COUT = 1340µF, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
EXT_SYNCDRIFT
PARAMETER
TEST CONDITIONS
Drift Tolerance for External SYNC Clock External SYNC clock equal to 500kHz is
not supported
MIN
(Note 7)
MAX
(Note 7)
UNITS
-10
+10
%
-100
+100
nA
0.8
V
TYP
LOGIC INPUT/OUTPUT CHARACTERISTICS
ILOGIC_BIAS
Bias Current at the Logic Input Pins
VLOGIC_IN_LOW
Logic Input Low Threshold Voltage
VLOGIC_IN_HIGH
Logic Input High Threshold Voltage
VLOGIC_OUT_LOW
Logic Output Low Threshold Voltage
2mA sinking
VLOGIC_OUT_HIGH
Logic Output High Threshold Voltage
2mA sourcing
DDC, EN, MGN, PG, SA, SCL, SDA,
SALRT, SYNC, UVLO, VMON, VSET
2.0
V
0.5
2.25
V
V
PMBus INTERFACE TIMING CHARACTERISTIC
FSMB
PMBus Operating Frequency
100
400
kHz
NOTES:
7. Compliance to datasheet limits is assured by one or more methods: Production test, characterization and/or design.
8. VOUT measured at the termination of the VSEN+ and VSEN- sense points.
9. The MAX load current is determined by the thermal “Derating Curves” on page 12, provided with this document.
10. “FS” stand for full scale of recommended maximum operation range.
11. “tSW” stands for time period of operation switching frequency.
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FN8636.3
June 17, 2016
ISL8271M
Typical Performance Curves
Efficiency Performance
100
Operating condition: TA= +25°C, No air flow. COUT = 1340µF. Typical values are used unless otherwise noted.
3.3V
2.5V
95
3.3V
92
90
EFFICIENCY (%)
EFFICIENCY (%)
94
1.8V
85
1.2V
1V
80
0.8V
75
70
1.8V
88
1.2V
86
1V
84
0.8V
82
65
60
2.5V
90
1
3
5
7
80
300
9 11 13 15 17 19 21 23 25 27 29 31 33
400
IOUT (A)
FIGURE 3. EFFICIENCY vs OUTPUT CURRENT AT VIN = 5V AND
fSW = 533kHz FOR VARIOUS OUTPUT VOLTAGES
100
5V
(700kHz)
95
3.3V
2.5V
EFFICIENCY (%)
EFFICIENCY (%)
2.5V
1.2V
1V
0.8V
75
900
3.3V
92
80
800
5V
94
70
90
1.8V
88
86
1.2V
84
1V
82
65
0.8V
80
1
3
5
7
78
300
9 11 13 15 17 19 21 23 25 27 29 31 33
400
IOUT (A)
500
600
700
800
FIGURE 6. EFFICIENCY vs SWITCHING FREQUENCY AT VIN = 9V AND
IOUT = 33A FOR VARIOUS OUTPUT VOLTAGES
100
95
5V
(700kHz)
95
2.5V
3.3V
1.8V
5V
93
2.5V
3.3V
91
85
1V
75
1.2V
0.8V
70
EFFICIENCY (%)
90
80
900
SWITCHING FREQUENCY (kHz)
FIGURE 5. EFFICIENCY vs OUTPUT CURRENT AT VIN = 9V AND
fSW = 533kHz FOR VARIOUS OUTPUT VOLTAGES
EFFICIENCY (%)
700
96
1.8V
85
89
1.8V
87
85
1.2V
83
1V
81
65
60
600
FIGURE 4. EFFICIENCY vs SWITCHING FREQUENCY AT VIN = 5V AND
IOUT = 33A FOR VARIOUS OUTPUT VOLTAGES
90
60
500
SWITCHING FREQUENCY (kHz)
0.8V
79
1
3
5
7
9 11 13 15 17 19 21 23 25 27 29 31 33
IOUT (A)
FIGURE 7. EFFICIENCY vs OUTPUT CURRENT AT VIN = 12V AND
fSW = 533kHz FOR VARIOUS OUTPUT VOLTAGES
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10
77
300
400
500
600
700
800
900
SWITCHING FREQUENCY (kHz)
FIGURE 8. EFFICIENCY vs SWITCHING FREQUENCY AT VIN = 12V AND
IOUT = 33A FOR VARIOUS OUTPUT VOLTAGES
FN8636.3
June 17, 2016
ISL8271M
Typical Performance Curves
Transient Response Performance
used unless otherwise noted.
(Continued)
COUT = 4x100µF Ceramic and 2x470µF POSCAP, IOUT = 0/16A, TA = +25°C, Typical values are
VOUT (50mV/DIV)
VOUT (50mV/DIV)
fSW = 550kHz
ASCR GAIN = 256
RESIDUAL = 90
fSW = 550kHz
ASCR GAIN = 600
RESIDUAL = 60
IOUT (10A/DIV)
IOUT (10A/DIV)
20µs/DIV
50µs/DIV
FIGURE 9. LOAD TRANSIENT RESPONSE AT VIN = 12V, VOUT = 1V
WITH HIGH BANDWIDTH ASCR PARAMETER
FIGURE 10. LOAD TRANSIENT RESPONSE AT VIN = 12V, VOUT = 1V
WITH DEFAULT ASCR PARAMETERS
VOUT (50mV/DIV)
VOUT (50mV/DIV)
f SW = 700kHz
ASCR GAIN = 256
RESIDUAL = 90
fSW = 700kHz
ASCR GAIN = 500
RESIDUAL = 70
IOUT (10A/DIV)
IOUT (10A/DIV)
20µs /DIV
50µs/DIV
FIGURE 11. LOAD TRANSIENT RESPONSE AT VIN = 12V, VOUT = 2.5V
WITH HIGH BANDWIDTH ASCR PARAMETERS
VOUT(50mV/DIV)
FIGURE 12. LOAD TRANSIENT RESPONSE AT VIN = 12V, VOUT = 2.5V
WITH DEFAULT ASCR PARAMETERS
VOUT(50mV/DIV)
fSW = 700kHz
ASCR GAIN = 400
RESIDUAL = 75
IOUT(10A/DIV)
IOUT(10A/DIV)
20µs /DIV
FIGURE 13. LOAD TRANSIENT RESPONSE AT VIN = 12V, VOUT = 3.3V
WITH HIGH BANDWIDTH ASCR PARAMETERS
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fSW = 700kHz
ASCR GAIN = 256
RESIDUAL = 90
11
50µs /DIV
FIGURE 14. LOAD TRANSIENT RESPONSE AT VIN = 12V, VOUT = 3.3V
WITH DEFAULT ASCR PARAMETERS
FN8636.3
June 17, 2016
ISL8271M
Typical Performance Curves
All of the following curves were plotted at TJ = +115°C, fSW = 533kHz.
33
33
30
30
27
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
Derating Curves
(Continued)
400 LFM
24
21
200 LFM
18
15
0 LFM
12
9
6
3
0
40
50
60
70
80
90
100
110
27
21
200 LFM
18
15
0 LFM
12
9
6
3
0
120
400 LFM
24
30
40
50
TEMPERATURE (°C)
33
33
30
30
27
400 LFM
21
18
200 LFM
15
12
0 LFM
9
6
3
0
40
50
60
70
80
90
100
110
24
18
12
30
40
50
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
200 LFM
0 LFM
6
60
70
80
90
TEMPERATURE (°C)
FIGURE 19. 5VIN TO 1.8VOUT
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12
70
80
110
90
100
110
FIGURE 18. 12VIN TO 1.2VOUT
400 LFM
50
60
TEMPERATURE (°C)
30
3
0
40
100
3
0
120
27
9
90
6
33
12
110
0 LFM
9
30
15
100
200 LFM
15
33
18
90
400 LFM
21
FIGURE 17. 5VIN TO 1.2VOUT
21
80
27
TEMPERATURE (°C)
24
70
FIGURE 16. 12VIN TO 1VOUT
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
FIGURE 15. 5VIN TO 1VOUT
24
60
TEMPERATURE (°C)
100
110
120
27
24
400 LFM
21
18
200 LFM
15
12
0 LFM
9
6
3
0
30
40
50
60
70
80
TEMPERATURE (°C)
FIGURE 20. 12VIN TO 1.8VOUT
FN8636.3
June 17, 2016
ISL8271M
Typical Performance Curves
All of the following curves were plotted at TJ = +115°C, fSW = 533kHz (Continued)
33
33
30
30
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
Derating Curves
(Continued)
27
24
400 LFM
21
18
200 LFM
15
12
0 LFM
9
6
3
0
40
50
60
70
80
90
100
110
27
24
400 LFM
21
18
200 LFM
15
12
0 LFM
9
6
3
0
120
30
40
50
TEMPERATURE (°C)
33
33
30
30
27
400 LFM
21
18
200 LFM
15
12
0 LFM
9
6
3
0
40
50
60
70
80
70
80
90
100
110
90
100
110
FIGURE 22. 12VIN TO 2.5VOUT
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
FIGURE 21. 5VIN TO 2.5VOUT
24
60
TEMPERATURE (°C)
90
100
110
27
24
21
400 LFM
18
15
200 LFM
12
9
0 LFM
6
3
0
120
30
40
50
TEMPERATURE (°C)
60
70
80
TEMPERATURE (°C)
FIGURE 23. 5VIN TO 3.3VOUT
FIGURE 24. 12VIN TO 3.3VOUT
MAXIMUM LOAD CURRENT (A)
33
30
27
24
21
400 LFM
18
15
200 LFM
12
9
0 LFM
6
3
0
30
40
50
60
70
80
90
100
110
TEMPERATURE (°C)
FIGURE 25. 12VIN TO 5VOUT, 700kHz
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FN8636.3
June 17, 2016
ISL8271M
Typical Application Circuit
(Note 15)
MGN
R3
V25
PMBus
Interface
DDC
SCL
SDA
SALRT
VOUT_COMMAND = 1.2V
PMBus Address = 0x28
C5
10µ
C4
1µ
UVLO
R4
XTEMP-
R5
XTEMP+
R6
EN
R3, R4, R5, R6 = 4.7k
VAUX
3.3V TO 5V
SYNC
(Notes 12, 13)
(Note 16)
VDDC
VR5
VR6
VSET
ISL8271M
SA
VSWH
PHASE
VDRVOUT
C6
C3
VIN
4.5V TO 13.2V
VIN
C2
C1
+
220µ
C7
+
(Note 14)
R7
VSEN+
VSEN-
10µ
SGND
VDD
PGND
R1
2.2
VOUT
1.2V 33A
VOUT
VDRVIN
2x22µ
4x100µ
200
2x470µ
(POSCAP)
NOTES:
12. R4 and R5 are not required if the PMBus host already has I2C pull-up resistors.
13. Only one R3 per DDC bus is required when DDC bus is shared with other modules.
14. R7 is optional but recommended to sink possible ~100µA back-flow current from the VSEN+ pin. Back-flow current is present only when the
module is in a disabled state with power still available at the VDD pin.
15. Unused pins (SYNC, XTEMP, MGN, UVLO) can be no connect.
16. Internal reference supply pins (V25, VDDC, VR5, VR6) do not need external capacitors and can be no connect. Refer to “PCB Layout Guidelines”
on page 20 for more information.
FIGURE 26. TYPICAL SINGLE PHASE APPLICATION CIRCUIT FOR 1.2V/33A OUTPUT
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FN8636.3
June 17, 2016
ISL8271M
TABLE 1. ISL8271M DESIGN GUIDE MATRIX AND OUTPUT VOLTAGE RESPONSE
VIN
(V)
VOUT
(V)
CIN (BULK)
(Note 17)
CIN
(CERAMIC)
COUT
(BULK)
COUT
(CERAMIC)
ASCR GAIN
(Note 18)
ASCR
RESIDUAL
(Note 18)
P-P
DEVIATION
(mV)
RECOVERY
TIME
(µs)
LOAD STEP
(Note 19)
(A)
FREQ.
(kHz)
5
1
2x150µF
4x47µF
2x470µF
6x100µF
350
90
50
20
16.5
516
12
1
2x150µF
3x22µF
4x470µF
4x100µF
200
80
45
20
16.5
348
12
1
2x150µF
2x22µF
2x470µF
6x100µF
350
90
50
22
16.5
516
5
1.8
2x150µF
5x47µF
2x470µF
3x100µF
220
90
80
16
16.5
516
12
1.8
2x150µF
3x22µF
2x470µF
3x100µF
190
80
80
14
16.5
516
5
2.5
2x150µF
5x47µF
1x470µF
3x100µF
140
90
120
25
16.5
516
12
2.5
2x150µF
2x22µF
1x470µF
3x100µF
220
100
110
16
16.5
696
5
3.3
2x150µF
4x47µF
1x470µF
3x100µF
120
80
130
25
16.5
516
12
3.3
2x150µF
3x22µF
1x470µF
3x100µF
220
100
130
25
16.5
696
12
5
2x150µF
3x22µF
1x470µF
1x100µF
200
70
180
6
16.5
1066
NOTES:
17. CIN bulk capacitor is optional only for energy buffer from the long input power supply cable.
18. ASCR gain and residual are selected to guarantee that the phase margin is higher than 60° and gain margin is higher than 6dB at room temperature
and full load (33A).
19. Output voltage response is tested with load step slew rate higher than 20A/µs.
TABLE 2. RECOMMENDED I/O CAPACITOR IN TABLE 1
VENDORS
VALUE
PART NUMBER
MURATA, Input Ceramic
47µF, 16V, 1210
GRM32ER61C476ME15L
MURATA, Input Ceramic
22µF, 16V, 1210
GRM32ER61E226KE15L
TAIYO YUDEN, Input Ceramic
47µF, 16V, 1210
EMK325BJ476MM-T
TAIYO YUDEN, Input Ceramic
22µF, 25V, 1210
TMK325BJ226MM-T
MURATA, Output Ceramic
100µF, 6.3V, 1210
GRM32ER60J107M
TDK, Output Ceramic
100µF, 6.3V, 1210
C3225X5R0J107M
AVX, Output Ceramic
100µF, 6.3V, 1210
12106D107MAT2A
SANYO POSCAP, Input Bulk
150µF, 16V
16TQC150MYF
SANYO POSCAP, Output Bulk
470µF, 4V
4TPE470MCL
SANYO POSCAP, Output Bulk
470µF, 6.3V
6TPF470MAH
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15
FN8636.3
June 17, 2016
ISL8271M
Functional Description
TABLE 3. OUTPUT VOLTAGE RESISTOR SETTINGS (Continued)
VOUT
(V)
RSET
(kΩ)
The ISL8271M provides an SMBus digital interface that enables
the user to configure all aspects of the module operation as well
as monitor the input and output parameters. The ISL8271M can
be used with any SMBus host device. In addition, the module is
compatible with PMBus™ Power System Management Protocol
Specification Parts I & II version 1.2. The ISL8271M accepts
most standard PMBus commands. When controlling the device
with PMBus commands, it is recommended that the enable pin is
tied to SGND.
2.20
90.9
2.30
100
2.50
110, or Connect to V25
The SMBus device address is the only parameters that must be
set by external pins. All other device parameters can be set with
PMBus commands.
SMBus Communications
Output Voltage Selection
The output voltage may be set to a voltage between 0.6V and 5V
provided that the input voltage is higher than the desired output
voltage by an amount sufficient to maintain regulation.
The VSET pin is used to set the output voltage to levels as shown
in Table 3. The RSET resistor is placed between the VSET pin and
SGND. A standard 1% resistor is recommend.
TABLE 3. OUTPUT VOLTAGE RESISTOR SETTINGS
VOUT
(V)
RSET
(kΩ)
0.60
10
0.65
11
0.70
12.1
0.75
13.3
0.80
14.7
0.85
16.2
0.90
17.8
0.95
19.6
1.00
21.5, or Connect to SGND
1.05
23.7
1.10
26.1
1.15
28.7
1.20
31.6, or OPEN
1.25
34.8
1.30
38.3
1.40
42.2
1.50
46.4
1.60
51.1
1.70
56.2
1.80
61.9
1.90
68.1
2.00
75
2.10
82.5
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2.80
121
3.00
133
3.30
147
4.00
162
5.00
178
The output voltage may also be set to any value between 0.6V
and 5V using a PMBus command VOUT_COMMAND.
By Default, VOUT_MAX is set 110% higher than VOUT set by the pin
strap resistor, which can be changed to any value up to 5.5V with
PMBus Command VOUT_MAX.
Soft-start Delay and Ramp Times
It may be necessary to set a delay from when an enable signal is
received until the output voltage starts to ramp to its target
value. In addition, the designer may wish to precisely set the time
required for VOUT to ramp to its target value after the delay
period has expired. These features may be used as part of an
overall in-rush current management strategy or to precisely
control how fast a load IC is turned on. The ISL8271M gives the
system designer several options for precisely and independently
controlling both the delay and ramp time periods. The soft-start
delay period begins when the EN pin is asserted and ends when
the delay time expires.
The soft-start delay and ramp times can be programmed to
custom values with PMBus commands; TON_DELAY and
TON_RISE. When the delay time is set to 0ms, the device begins
its ramp-up after the internal circuitry has initialized
(approximately 2ms). When the soft-start ramp period is set to
0ms, the output ramps up as quickly as the output load
capacitance and loop settings allow. It is generally
recommended to set the soft-start ramp to a value greater than
500µs to prevent inadvertent fault conditions due to excessive
in-rush current.
Power-Good
The ISL8271M provides a Power-Good (PG) signal that indicates
the output voltage is within a specified tolerance of its target
level and no fault condition exists. By default, the PG pin asserts
if the output is within 10% of the target voltage. These limits and
the polarity of the pin may be changed with PMBus command
POWER_GOOD_ON.
A PG delay period is defined as the time from when all conditions
within the ISL8271M for asserting PG are met to when the PG pin
is actually asserted. This feature is commonly used instead of
using an external reset controller to control external digital logic.
A PG delay can be programmed with PMBus command
POWER_GOOD_DELAY.
FN8636.3
June 17, 2016
ISL8271M
Switching Frequency and PLL
TABLE 5. UVLO RESISTOR SETTINGS (Continued)
The device’s switching frequency is set from 296kHz to 1067kHz
using the pin-strap method as shown in Table 1, or by using a
PMBus command FREQUENCY_SWITCH. The ISL8271M
incorporates an internal phase-locked loop (PLL) to clock the
internal circuitry. The PLL can be driven by an external clock source
connected to the SYNC pin. When using the internal oscillator, the
SYNC pin can be configured as a clock source as a external sync to
other modules. Refer to SYNC_CONFIG command on page 45 for
more information.
UVLO
(V)
RUVLO
(kΩ)
5.57
34.8
6.13
38.3
6.75
42.2
TABLE 4. SWITCHING FREQUENCY RESISTOR SETTINGS
7.42
46.4
8.18
51.1
8.99
56.2
9.90
61.9
10.90
68.1
fSW
(V)
RSET
(kΩ)
12.00
75
296
14.7, or Connect to SGND
13.20
82.5
320
16.2
14.54
90.9
364
17.8
16.00
100
400
19.6
421
21.5
471
23.7
533
26.1, or OPEN
571
28.7
615
31.6
727
34.8
800
38.3
842
42.2
889
46.4
1067
51.1, or Connect to V25
Loop Compensation
The module is internally compensated via the PMBus command
ASCR_CONFIG. The ISL8271M uses the ChargeMode control
algorithm that responds to output current changes within a
single PWM switching cycle, achieving a smaller total output
voltage variation with less output capacitance than traditional
PWM controllers.
Input Undervoltage Lockout (UVLO)
The input undervoltage lockout (UVLO) prevents the ISL8271M
from operating when the input falls below a preset threshold,
indicating the input supply is out of its specified range. The UVLO
threshold (VUVLO) can be set between 4.18V and 16V using the
pin-strap method as shown in Table 2, or by using a PMBus
command VIN_UV_FAULT_LIMIT.
SMBus Module Address Selection
Each module must have its own unique serial address to
distinguish between other devices on the bus. The module
address is set by connecting a resistor between the SA pin and
SGND. Table 6 lists the available module addresses.
TABLE 6. SMBus ADDRESS RESISTOR SELECTION
RSA
(kΩ)
SMBus
ADDRESS
10
19h
11
1Ah
12.1
1Bh
13.3
1Ch
14.7
1Dh
16.2
1Eh
17.8
1Fh
19.6
20h
21.5
21h
23.7
22h
26.1
23h
28.7
24h
31.6
25h
34.8, or connect to SGND
26h
38.3
27h
42.2, or Open
28h
Fault response to an input undervoltage fault can be programmed
with PMBus command VIN_UV_FAULT_RESPONSE.
46.4
29h
51.1
2Ah
TABLE 5. UVLO RESISTOR SETTINGS
56.2
2Bh
61.9
2Ch
68.1
2Dh
75
2Eh
UVLO
(V)
RUVLO
(kΩ)
4.5
OPEN
10.8
Connect to V25
4.18
26.1
4.59
28.7
5.06
31.6
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17
82.5
2Fh
90.9
30h
100
31h
FN8636.3
June 17, 2016
ISL8271M
Output Overvoltage Protection
The ISL8271M offers an internal output overvoltage protection
circuit that can be used to protect sensitive load circuitry from
being subjected to a voltage higher than its prescribed limits. A
hardware comparator is used to compare the actual output
voltage (seen at the VSEN+, VSEN- pins) to a threshold set to 15%
higher than the target output voltage (the default setting). Fault
threshold can be programmed to a desired level with PMBus
command VOUT_OV_FAULT_LIMIT. If the VSEN+ voltage exceeds,
this threshold module will initiate an immediate shutdown
without retry. Retry settings can be programmed with PMBus
command VOUT_OV_FAULT_RESPONSE.
Internal to module, two 100Ω resistors are populated from VOUT
to VSEN+ and SGND to VSEN- to protect from overvoltage
conditions in case of open at VSENSE pins and differential
remote sense traces due to assembly error. As long as
differential remote sense traces have low resistance, VOUT
regulation accuracy is not sacrificed.
Output PreBias Protection
An output prebias condition exists when an externally applied
voltage is present on a power supply’s output before the power
supply’s control IC is enabled. Certain applications require that
the converter not be allowed to sink current during start-up if a
prebias condition exists at the output. The ISL8271M provides
prebias protection by sampling the output voltage prior to
initiating an output ramp.
If a prebias voltage lower than the target voltage exists after the
preconfigured delay period has expired, the target voltage is set
to match the existing prebias voltage and both drivers are
enabled. The output voltage is then ramped to the final
regulation value at the preconfigured ramp rate.
The actual time the output takes to ramp from the prebias
voltage to the target voltage varies, depending on the prebias
voltage, however, the total time elapsed from when the delay
period expires and when the output reaches its target value will
match the preconfigured ramp time (see Figure 27).
If a prebias voltage is higher than the target voltage after the
preconfigured delay period has expired, the target voltage is set
to match the existing prebias voltage and both drivers are
enabled with a PWM duty cycle that would ideally create the
pre-bias voltage.
Once the preconfigured soft-start ramp period has expired, the
PG pin is asserted (assuming the prebias voltage is not higher
than the overvoltage limit). The PWM then adjusts its duty cycle
to match the original target voltage and the output ramps down
to the preconfigured output voltage.
If a prebias voltage is higher than the overvoltage limit, the
device does not initiate a turn-on sequence and declares an
overvoltage fault condition. The device then responds based on
the output overvoltage fault response setting programmed with
PMBus command VOUT_OV_FAULT_RESPONSE.
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VOUT
DESIRED OUTPUT
VOLTAGE
PREBIAS VOLTAGE
TIME
TONDELAY
TONRISE
VPREBIAS < VTARGET
VOUT
PREBIAS VOLTAGE
DESIRED OUTPUT
VOLTAGE
TIME
TONDELAY
TONRISE
VPREBIAS > VTARGET
FIGURE 27. OUTPUT RESPONSES TO PREBIAS VOLTAGES
Output Overcurrent Protection
The ISL8271M can protect the power supply from damage if the
output is shorted to ground or if an overload condition is imposed
on the output. Average output overcurrent fault threshold can be
programmed with PMBus command IOUT_OC_FAULT_LIMIT.
Module automatically programs peak inductor current fault
threshold, by calculating inductor ripple current by reading
real-time input voltage, switching frequency and
VOUT_COMMAND. When peak inductor current crosses peak
inductor current fault threshold for five successive cycle modules
it will initiate an immediate shutdown.
The default response from an overcurrent fault is an immediate
shutdown without retry. Retry settings can be programmed with
PMBus command MFR_IOUT_OC_FAULT_RESPONSE.
Thermal Overload Protection
The ISL8271M includes a thermal sensor that continuously
measures the internal temperature of the module and shuts
down the controller when the temperature exceeds the preset
limit. The default temperature limit is set to +125°C in the
factory, but can be changed with PMBus command
OT_FAULT_LIMIT.
The default response from an over-temperature fault is an
immediate shutdown without retry. Retry settings can be
programmed with PMBus command OT_FAULT_RESPONSE.
If the user has configured the module to retry, the controller
waits the preset delay period (if configured to do so) and then
checks the module temperature. If the temperature has dropped
below a threshold that is approximately +15°C lower than the
selected temperature fault limit, the controller attempts to
restart. If the temperature still exceeds the fault limit, the
controller waits the preset delay period and retries again.
FN8636.3
June 17, 2016
ISL8271M
Digital-DC Bus
The Digital-DC Communications (DDC) bus is used to
communicate between Intersil digital power modules and digital
controllers. This dedicated bus provides the communication
channel between devices for features such as sequencing and
fault spreading. The DDC pin on all Digital-DC devices in an
application should be connected together. A pull-up resistor is
required on the DDC bus in order to guarantee the rise time as
shown in Equation 1:
Rise Time = R PU C LOAD  1s
(EQ. 1)
Where RPU is the DDC bus pull-up resistance and CLOAD is the
bus loading. The pull-up resistor may be tied to an external 3.3V
or 5V supply as long as this voltage is present prior to or during
device power-up. In principle, each device connected to the DDC
bus presents approximately 10pF of capacitive loading and each
inch of FR4 PCB trace introduces approximately 2pF. The ideal
design uses a central pull-up resistor that is well matched to the
total load capacitance.
DDC bus. The other devices on the DDC bus shutdown
simultaneously, if configured to do so and attempt to restart in
their prescribed order.
Temperature Monitoring Using XTEMP Pin
The ISL8271M supports measurement of an external device
temperature using either a thermal diode integrated in a
processor, FPGA or ASIC, or using a discrete diode-connected
2N3904 NPN transistor. Figure 28 illustrates the typical
connections required. The external temperature sensors can be
used to provide the temperature reading for over-temperature
and under-temperature faults. These options for the external
temperature sensors are enabled using the USER_CONFIG
PMBus™ command.
XTEMP+
ISL8271M
2N3904
XTEMP-
Phase Spreading
DISCRETE NPN
When multiple point-of-load converters share a common DC
input supply, it is desirable to adjust the clock phase offset of
each device, such that not all devices start to switch
simultaneously. Setting each converter to start its switching cycle
at a different point in time, can dramatically reduce input
capacitance requirements and efficiency losses. Since the peak
current drawn from the input supply is effectively spread out over
a period of time, the peak current drawn at any given moment is
reduced and the power losses proportional to the IRMS2 are
reduced dramatically.
To enable phase spreading, all converters must be synchronized
to the same switching clock. The phase offset of each device
may also be set to any value between 0° and 360° in 22.5°
increments with PMBus command INTERLEAVE.
XTEMP+
ISL8271M
XTEMP-
EMBEDDED THERMAL DIODE
FIGURE 28. EXTERNAL TEMPERATURE MONITORING
Monitoring Via SMBus
A system controller can monitor a wide variety of different
ISL8271M system parameters with PMBus commands:
Output Sequencing
• READ_VIN
A group of Digital-DC modules or devices may be configured to
power-up in a predetermined sequence. This feature is especially
useful when powering advanced processors, (FPGAs and ASICs
that require one supply to reach its operating voltage) prior to
another supply reaching its operating voltage in order to avoid
latch-up. Multi-device sequencing can be achieved by configuring
each device with PMBus command SEQUENCE. Multiple device
sequencing is configured by issuing PMBus commands to assign
the preceding device in the sequencing chain as well as the
device that follows in the sequencing chain.
• READ_VOUT
The Enable pins of all devices in a sequencing group must be tied
together and driven high to initiate a sequenced turn-on of the
group. Enable must be driven low to initiate a sequenced turnoff
of the group.
Snapshot Parameter Capture
Fault Spreading
µP
FPGA
DSP
ASIC
• READ_IOUT
• READ_INTERNAL_TEMP
• READ_EXTERNAL_TEMP
• READ_DUTY_CYCLE
• READ_FREQEUNCY
• READ_VDRV
The ISL8271M offers a special feature to capture parametric data
and some fault status following a fault. A detailed description is
provided in “SNAPSHOT_CONTROL (F3h)” on page 46 under
PMBus command SNAPSHOT and SNAPSHOT_CONTROL.
Digital DC modules and devices can be configured to broadcast a
fault event over the DDC bus to the other devices in the group
with PMBus command DDC_GROUP. When a non-destructive
fault occurs and the device is configured to shutdown on a fault,
the device shuts down and broadcasts the fault event over the
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FN8636.3
June 17, 2016
ISL8271M
PHASE
PGND
VDRVIN
NC
VSWH
VOUT
NC
PGND
PGND
CVOUT
FIGURE 29. RECOMMENDED LAYOUT - TOP PCB LAYER
SGND
CONNECT SGND TO
PGND IN THE MIDDLE
LAYER
SGND
SGND
SGND
PGND
PGND
PGND
• Use large copper areas for power path (VIN, PGND, VOUT) to
minimize conduction loss and thermal stress. Also, use
multiple vias to connect the power planes in different layers.
Extra ceramic capacitors at VIN and VOUT can be placed on the
bottom layer under VIN and VOUT pads when multiple vias are
used for connecting copper pads on top and bottom layers.
SGND
VR6
PGND
C
VIN
• Establish separate SGND plane and PGND plane, then connect
SGND to PGND plane as shown in Figure 30 in the middle
layer. For making connections between SGND/PGND on the
top layer and other layers use multiple vias for each pin to
connect to inner SGND/PGND layer. Do not connect SGND
directly to PGND on a top layer. Connecting SGND directly to
PGND without establishing SGND plane will bypass the
decoupling capacitor at internal reference supplies, making
controller susceptible to noise.
• Place enough ceramic capacitors between VIN and PGND,
VOUT and PGND and bypass capacitors between VDD and the
ground plane, as close to the module as possible to minimize
high frequency noise.
VR5
VDRVOUT
CVIN
• For 5.5V  VDD  6V, connect VDDC pin to VR6 pin. For
4.5  VDD < 5.5V, connect VDDC pin to VR6 and VR5 pin. An
RC filter is required at the input of VDRVIN pin if input supply is
shared with VIN pin.
NC
VSET
MGN
DGND
NC
SA
SALRT
SDA
SCL
EN
SGND
PCB Layout Guidelines
• For VDD > 6V recommended PCB layout is shown in Figure 29.
Leave V25, VDDC, VR5 and VR6 as no connect.
CVDD
UVLO
C
R
To achieve stable operation, low losses and good thermal
performance some layout considerations are necessary.
A
B
C
VDD
SYNC
PG
VDDC
Modules are shipped with factory defaults configuration and
most settings can be overwritten with PMBus Commands and
can be stored in nonvolatile memory with PMBus command
STORE_USER_ALL.
DDC
XTEMP+
XTEMP VTRK+
VTRK VSEN+
VSEN -
PGND
SGND
VR25
The ISL8271M has internal nonvolatile memory where user
configurations are stored. Integrated security measures ensure
that the user can only restore the module to a level that has been
made available to them. During the initialization process, the
ISL8271M checks for stored values contained in its internal
non-volatile memory.
SGND
NonVolatile Memory
• Connect differential remote sensing traces to the regulation point
to achieve a tight output voltage regulation. Route a trace from
VSEN- and VSEN+ to the point-of-load where the tight output
voltage is desired. Avoid routing any sensitive signal traces,
such as the VSENSE signal near VSWH pads.
• For noise sensitive applications, it is recommended to connect
VSWH pads only on the top layer but thermal performance gets
sacrificed. External airflow might be required to keep module
heat at desired level. For applications where switching noise is
less critical, an excellent thermal performance can be
achieved in the ISL8271M module by increasing copper mass
attached to VSWH pad. To increase copper mass on the VSWH
node create copper islands in the middle and bottom layers
under VSWH pad and connect them to the top layer with
multiple vias. Make sure to shield those copper islands with a
PGND layer to avoid any interference to noise sensitive signals.
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20
FIGURE 30. RECOMMENDED LAYOUT - CONNECT SGND TO PGND IN
THE MIDDLE PCB LAYER AFTER ESTABLISHING
SEPARATE SGND AND PGND
FN8636.3
June 17, 2016
ISL8271M
Experimental power loss curves along with θJA from thermal
modeling analysis can be used to evaluate the thermal
consideration for the module. The derating curves are derived
from the maximum power allowed while maintaining the
temperature below the maximum junction temperature of
+125°C. In actual application, other heat sources and design
margin should be considered.
Package Description
The structure of the ISL8271M belongs to the High Density Array
(HDA) no-lead package. This kind of package has advantages,
such as good thermal and electrical conductivity, low weight and
small size. The HDA package is applicable for surface mounting
technology and is being more readily used in the industry. The
ISL8271M contains several types of devices, including resistors,
capacitors, inductors and control ICs. The ISL8271M is a copper
lead-frame based package with exposed copper thermal pads,
which have good electrical and thermal conductivity. The copper
lead frame and multi component assembly is over-molded with
polymer mold compound to protect these devices.
The package outline, a typical PCB land pattern design and a
typical stencil opening edge position are shown on pages 49, 51
and 52 respectively. The module has a small size of
17mmx19mmx3.55mm. Figure 31 shows typical reflow profile
parameters. These guidelines are general design rules. Users
could modify parameters according to their application.
PCB Layout Pattern Design
The bottom of ISL8271M is a lead-frame footprint, which is
attached to the PCB by surface mounting process. The PCB land
pattern is shown on page 51. The PCB layout pattern is
essentially 1:1 with the HDA exposed pad and I/O termination
dimensions. The thermal lands on the PCB layout should match
1:1 with the package exposed die pads.
Thermal Vias
A grid of 1.0mm to 1.2mm pitch thermal vias, which drops down
and connects to buried copper plane(s), should be placed under the
thermal land. The vias should be about 0.3mm to 0.33mm in
diameter with the barrel plated to about 1.0 ounce copper.
Although adding more vias (by decreasing via pitch) will improve
the thermal performance, diminishing returns will be seen as more
and more vias are added. Simply use as many vias as practical for
the thermal land size and your board design rules allow.
Stencil Pattern Design
Reflowed solder joints on the perimeter I/O lands should have
about a 50µm to 75µm (2mil to 3mil) standoff height. The solder
paste stencil design is the first step in developing optimized,
reliable solder joins. Stencil aperture size to land size ratio should
typically be 1:1. The aperture width may be reduced slightly to help
prevent solder bridging between adjacent I/O lands. To reduce
solder paste volume on the larger thermal lands, it is
recommended that an array of smaller apertures be used instead
of one large aperture. It is recommended that the stencil printing
area cover 50% to 80% of the PCB layout pattern. A typical solder
stencil pattern is shown on page 52. The gap width between pad to
pad is 0.6mm. The user should consider the symmetry of the
whole stencil pattern when designing its pads. A laser cut,
stainless steel stencil with electropolished trapezoidal walls is
recommended. Electropolishing “smooths” the aperture walls
resulting in reduced surface friction and better paste release,
which reduces voids. Using a Trapezoidal Section Aperture (TSA)
also promotes paste release and forms a “brick like” paste deposit
that assists in firm component placement. A 0.1mm to 0.15mm
stencil thickness is recommended for this large pitch (1.3mm) HDA.
Reflow Parameters
Due to the low mount height of the HDA, “No Clean” Type 3 solder
paste per ANSI/J-STD-005 is recommended. Nitrogen purge is
also recommended during reflow. A system board reflow profile
depends on the thermal mass of the entire populated board, thus
it is not practical to define a specific soldering profile just for the
HDA. The profile given in Figure 31 is provided as a guideline, to
be customized for varying manufacturing practices and
applications.
300
PEAK TEMPERATURE ~+245°C;
TYPICALLY 60s-150s ABOVE +217°C
KEEP LESS THAN 30s WITHIN 5°C OF PEAK TEMP.
250
TEMPERATURE (°C)
Thermal Considerations
200
SLOW RAMP (3°C/s MAX)
AND SOAK FROM +150°C
TO +200°C FOR 60s~180s
150
100
RAMP RATE 1.5°C FROM +70°C TO +90°C
50
0
0
100
150
200
250
300
350
DURATION (s)
FIGURE 31. TYPICAL REFLOW PROFILE
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FN8636.3
June 17, 2016
ISL8271M
PMBus Command Summary
COMMAND
CODE
COMMAND
NAME
DESCRIPTION
TYPE
DATA
FORMAT
DEFAULT
VALUE
DEFAULT
SETTING
PAGE
01h
OPERATION
Sets Enable, Disable and VOUT
Margin modes.
R/W BYTE
BIT
02h
ON_OFF_CONFIG
Configures the EN pin and PMBus
commands to turn the unit
ON/OFF
R/W BYTE
BIT
03h
CLEAR_FAULTS
Clears fault indications.
SEND BYTE
27
15h
STORE_USER_ALL
Stores all PMBus values written
since last restore at user level.
SEND BYTE
27
16h
RESTORE_USER_ALL
Restores PMBus settings that
were stored using
STORE_USER_ALL.
SEND BYTE
27
20h
VOUT_MODE
Preset to defined data format of
VOUT commands.
READ BYTE
BIT
21h
VOUT_COMMAND
Sets the nominal value of the
output voltage.
R/W WORD
L16u
23h
VOUT_CAL_OFFSET
Applies a fixed offset voltage to
the VOUT_COMMAND.
R/W WORD
L16s
24h
VOUT_MAX
Sets the maximum possible value
of VOUT. 110% of pin-strap VOUT.
R/W WORD
25h
VOUT_MARGIN_HIGH
Sets the value of the VOUT during a
margin high.
26h
VOUT_MARGIN_LOW
27h
26
17h
26
Linear Mode,
Exponent = -13
27
Pin Strap
27
0V
28
L16u
1.1*VOUT
Pin Strap
28
R/W WORD
L16u
1.05*VOUT
Pin Strap
29
Sets the value of the VOUT during a
margin low.
R/W WORD
L16u
0.95*VOUT
Pin Strap
29
VOUT_TRANSITION_RATE
Sets the transition rate during
margin or other change of VOUT.
R/W WORD
L11
BA00h
1V/ms
29
28h
VOUT_DROOP
Sets the loadline (V/I Slope)
resistance for the rail.
R/W WORD
L11
0000h
0mV/A
29
33h
FREQUENCY_SWITCH
Sets the switching frequency.
R/W WORD
L11
Pin Strap
29
37h
INTERLEAVE
Configures a phase offset
between devices sharing a SYNC
clock.
R/W WORD
BIT
0000h
Set based on
PMBus Address
30
38h
IOUT_CAL_GAIN
Sense resistance for inductor DCR
current sensing.
R/W WORD
L11
B2AEh
0.67mΩ
30
39h
IOUT_CAL_OFFSET
Sets the current-sense offset.
R/W WORD
L11
0000h
0A
30
40h
VOUT_OV_FAULT_LIMIT
Sets the VOUT overvoltage fault
threshold.
R/W WORD
L16u
1.15*VOUT
Pin Strap
30
41h
VOUT_OV_FAULT_RESPONSE
Configures the VOUT overvoltage
fault response.
R/W BYTE
BIT
Disable and
No Retry
30
42h
VOUT_OV_WARN_LIMIT
Sets the VOUT overvoltage warn
threshold.
R/W WORD
L16u
1.10*VOUT
Pin Strap
31
43h
VOUT_UV_WARN_LIMIT
Sets the VOUT undervoltage warn
threshold.
R/W WORD
L16u
0.9*VOUT
Pin Strap
31
44h
VOUT_UV_FAULT_LIMIT
Sets the VOUT undervoltage fault
threshold.
R/W WORD
L16u
0.85*VOUT
Pin Strap
31
45h
VOUT_UV_FAULT_RESPONSE
Configures the VOUT undervoltage
fault response.
R/W BYTE
BIT
80h
Disable and
No Retry
31
46h
IOUT_OC_FAULT_LIMIT
Sets the IOUT average overcurrent
fault threshold.
R/W WORD
L11
E280h
40A
31
4Bh
IOUT_UC_FAULT_LIMIT
Sets the IOUT average
undercurrent fault threshold.
R/W WORD
L11
E57Fh
-40A
32
4Fh
OT_FAULT_LIMIT
Sets the over-temperature fault
threshold.
R/W WORD
L11
EBE8h
+125°C
32
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13h
Hardware Enable,
Immediate Off
0000h
80h
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ISL8271M
PMBus Command Summary (Continued)
COMMAND
CODE
COMMAND
NAME
DESCRIPTION
TYPE
DATA
FORMAT
DEFAULT
VALUE
R/W BYTE
BIT
80h
50h
OT_FAULT_RESPONSE
Configures the over-temperature
fault response.
51h
OT_WARN_LIMIT
Sets the over-temperature
warning limit.
R/W WORD
L11
52h
UT_WARN_LIMIT
Sets the under-temperature
warning limit.
R/W WORD
53h
UT_FAULT_LIMIT
Sets the under-temperature fault
threshold.
54h
UT_FAULT_RESPONSE
Configures the under-temperature
fault response.
55h
VIN_OV_FAULT_LIMIT
56h
DEFAULT
SETTING
PAGE
Disable and
No Retry
32
Eb70h
+110°C
32
L11
DC40h
-30°C
32
R/W WORD
L11
E530h
-45°C
33
R/W BYTE
BIT
80h
Disable and
No Retry
33
Sets the VIN overvoltage fault
threshold.
R/W WORD
L11
D380h
14V
33
VIN_OV_FAULT_RESPONSE
Configures the VIN overvoltage
fault response.
R/W BYTE
BIT
80h
Disable and
No Retry
33
57h
VIN_OV_WARN_LIMIT
Sets the input overvoltage warning
limit.
R/W WORD
L11
D327h
12.6V
34
58h
VIN_UV_WARN_LIMIT
Sets the input undervoltage
warning limit.
R/W WORD
L11
1.10*VIN
UV Fault Limit
34
59h
VIN_UV_FAULT_LIMIT
Sets the VIN undervoltage fault
threshold.
R/W WORD
L11
Pin Strap
34
5Ah
VIN_UV_FAULT_RESPONSE
Configures the VIN undervoltage
fault response.
R/W BYTE
BIT
Disable and
No Retry
34
5Eh
POWER_GOOD_ON
Sets the voltage threshold for
Power-Good indication.
R/W WORD
L16u
0.9*VOUT
Pin Strap
34
60h
TON_DELAY
Sets the delay time from ENABLE
to start of VOUT rise.
R/W WORD
L11
CA80h
5ms
35
61h
TON_RISE
Sets the rise time of VOUT after
ENABLE and TON_DELAY.
R/W WORD
L11
CA80h
5ms
35
64h
TOFF_DELAY
Sets the delay time from DISABLE
to start of VOUT fall.
R/W WORD
L11
CA80h
5ms
35
65h
TOFF_FALL
Sets the fall time for VOUT after
DISABLE and TOFF_DELAY.
R/W WORD
L11
CA80h
5ms
35
78h
STATUS_BYTE
Returns an abbreviated status for
fast reads.
READ BYTE
BIT
00h
No Faults
35
79h
STATUS_WORD
Returns information with a
summary of the units's fault
condition.
READ WORD
BIT
0000h
No Faults
36
7Ah
STATUS_VOUT
Returns the VOUT specific status.
READ BYTE
BIT
00h
No Faults
36
7Bh
STATUS_IOUT
Returns the IOUT specific status.
READ BYTE
BIT
00h
No Faults
37
7Ch
STATUS_INPUT
Returns specific status specific to
the input.
READ BYTE
BIT
00h
No Faults
37
7Dh
STATUS_TEMPERATURE
Returns the temperature specific
status.
READ BYTE
BIT
00h
No Faults
37
7Eh
STATUS_CML
Returns the Communication,
Logic and Memory specific status.
READ BYTE
BIT
00h
No Faults
38
80h
STATUS_MFR_SPECIFIC
Returns the VDRV and External
Sync clock specific status.
READ BYTE
BIT
00h
No Faults
38
88h
READ_VIN
Returns the input voltage reading. READ WORD
L11
38
8Bh
READ_VOUT
Returns the output voltage
reading.
READ WORD
L16u
38
8Ch
READ_IOUT
Returns the output current
reading.
READ WORD
L11
39
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80h
FN8636.3
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ISL8271M
PMBus Command Summary (Continued)
COMMAND
CODE
COMMAND
NAME
DESCRIPTION
TYPE
DATA
FORMAT
DEFAULT
VALUE
DEFAULT
SETTING
PAGE
8Dh
READ_INTERNAL_TEMP
Returns the temperature reading
internal to the device.
READ WORD
L11
39
8Eh
READ_EXTERNAL_TEMP
Returns the temperature reading
from external monitor source.
READ WORD
L11
39
94h
READ_DUTY_CYCLE
Returns the duty cycle reading
during the ENABLE state.
READ WORD
L11
39
95h
READ_FREQUENCY
Returns the measured operating
switch frequency.
READ WORD
L11
39
99h
MFR_ID
Sets a user defined identification.
R/W BLOCK
ASC
Null
39
9Ah
MFR_MODEL
Sets a user defined model.
R/W BLOCK
ASC
Null
40
9Bh
MFR_REVISION
Sets a user defined revision.
R/W BLOCK
ASC
Null
40
9Ch
MFR_LOCATION
Sets a user defined location
identifier.
R/W BLOCK
ASC
Null
40
9Dh
MFR_DATE
Sets a user defined date.
R/W BLOCK
ASC
Null
40
9Eh
MFR_SERIAL
Sets a user defined serialized
identifier.
R/W BLOCK
ASC
Null
40
A8h
LEGACY_FAULT_GROUP
Broadcast faults when mixed with
old generation modules
R/W BLOCK
BIT
00000000h
41
B0h
USER_DATA_00
Sets a user defined data.
R/W BLOCK
ASC
Null
41
D0h
ISENSE_CONFIG
Configures ISENSE related
features.
R/W BYTE
BIT
05h
256ns Blanking
Time, Mid Range
42
D1h
USER_CONFIG
Configures several user-level
features.
R/W BYTE
BIT
00h
Open Drain PG,
XTEMP Disabled
42
D3h
DDC_CONFIG
Configures the DDC bus.
R/W BYTE
BIT
00h
Set based on
PMBus Address
42
D4h
POWER_GOOD_DELAY
Sets the delay between VOUT > PG
threshold and asserting the PG
pin.
R/W WORD
L11
CA00h
4ms
43
DFh
ASCCR_CONFIG
Configures ASCCR control loop.
R/W BLOCK
CUS
E0h
SEQUENCE
Identifies the Rail DDC ID to
perform multi-rail sequencing.
R/W WORD
BIT
0000h
E2h
DDC_GROUP
Sets rail DDC IDs to obey faults
and margining spreading
information.
R/W BLOCK
BIT
000000h
E4h
DEVICE_ID
Returns the 16-byte (character)
device identifier string.
READ
BLOCK
ASC
E5h
MFR_IOUT_OC_FAULT_RESPONSE Configures the IOUT overcurrent
fault response.
R/W BYTE
BIT
E6h
MFR_IOUT_UC_FAULT_RESPONSE Configures the IOUT undercurrent
fault response.
R/W BYTE
E9h
SYNC_CONFIG
Configures the Sync pin.
EAh
SNAPSHOT
EBh
015A0100h Residual = 90
Gain = 256
43
Prequel and
Sequel Disabled
43
Broadcast
Disabled
44
Reads Device
Version
44
80h
Disable and
No Retry
44
BIT
80h
Disable and
No Retry
45
R/W BYTE
BIT
00h
Pin Strap
45
Returns 32-byte read-back of
parametric and status values.
READ
BLOCK
BIT
45
BLANK_PARAMS
Returns recently changed
parameter values.
READ
BLOCK
BIT
46
F3h
SNAPSHOT_CONTROL
Snapshot feature control
command.
R/W BYTE
BIT
46
F4h
RESTORE_FACTORY
Restores device to the factory
default values.
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R/W BLOCK
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PMBus Command Summary (Continued)
COMMAND
CODE
COMMAND
NAME
DESCRIPTION
TYPE
DATA
FORMAT
DEFAULT
VALUE
DEFAULT
SETTING
PAGE
F5h
VDRV_OV_FAULT_LIMIT
Returns the VDRV overvoltage
threshold.
READ WORD
L11
CB00h
6V
46
F6h
VDRV_UV_FAULT_LIMIT
Returns the VDRV undervoltage
threshold.
READ WORD
L11
CA00h
4V
46
F7h
READ_VDRV
Returns the VDRV voltage reading. READ WORD
L11
F8h
VDRV_OV_FAULT_RESPONSE
Returns the VDRV overvoltage
response.
READ BYTE
BIT
80h
Disable and
No Retry
47
F9h
VDRV_UV_FAULT_RESPONSE
Returns the VDRV undervoltage
response.
READ BYTE
BIT
80h
Disable and
No Retry
47
46
PMBus™ Data Formats
Linear-11 (L11)
L11 data format uses 5-bit two’s compliment exponent (N) and 11-bit two’s compliment mantissa (Y) to represent real world decimal
value (X).
Data Byte High
Data Byte Low
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Exponent (N)
Mantissa (Y)
Relation between real world decimal value (X), N and Y is: X = Y·2N
Linear-16 Unsigned (L16u)
L16u data format uses a fixed exponent (hard-coded to N = -13h) and a 16-bit unsigned integer mantissa (Y) to represent real world
decimal value (X). Relation between real world decimal value (X), N and Y is: X = Y·2-13
Linear-16 Signed (L16s)
L16s data format uses a fixed exponent (hard-coded to N = -13h) and a 16-bit two’s compliment mantissa (Y) to represent real world
decimal value (X).
Relation between real world decimal value (X), N and Y is: X = Y·2-13
Bit Field (BIT)
Break down of Bit Field is provided in PMBus™ on “PMBus Commands Description” on page 26.
Custom (CUS)
Break down of Custom data format is provided in PMBus™ “PMBus Commands Description” on page 26. A combination of Bit Field and
integer are common type of Custom data format.
ASCII (ASC)
A variable length string of text characters uses ASCII data format.
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PMBus Use Guidelines
The PMBus is a powerful tool that allows the user to optimize circuit performance by configuring devices for their application. When
configuring a device in a circuit, the device should be disabled whenever most settings are changed with PMBus commands. Some
exceptions to this recommendation are OPERATION, ON_OFF_CONFIG, CLEAR_FAULTS, VOUT_COMMAND, VOUT_MARGIN_HIGH,
VOUT_MARGIN_LOW, and ASCCR_CONFIG. While the device is enabled any command can be read. Many commands do not take effect
until after the device has been re-enabled, hence the recommendation that commands that change device settings are written while
the device is disabled.
When sending the STORE_DEFAULT_ALL, STORE_USER_ALL, RESTORE_DEFAULT_ALL, and RESTORE_USER_ALL commands, it is
recommended that no other commands are sent to the device for 100ms after sending STORE or RESTORE commands.
In addition, there should be a 2ms delay between repeated READ commands sent to the same device. When sending any other
command, a 5ms delay is recommended between repeated commands sent to the same device.
Summary
All commands can be read at any time.
Always disable the device when writing commands that change device settings. Exceptions to this rule are commands intended to be
written while the device is enabled, for example, VOUT_MARGIN_HIGH.
To be sure a change to a device setting has taken effect, write the STORE_USER_ALL command, then cycle input power and re-enable.
PMBus Commands Description
OPERATION (01h)
Definition: Sets Enable, Disable and VOUT Margin settings. Data values of OPERATION that force margin high or low only take effect
when the MGN pin is left open (i.e., in the NOMINAL margin state).
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value:
Units: N/A
SETTINGS
ACTIONS
04h
Immediate off (no sequencing).
44h
Soft off (with sequencing).
84h
On - Nominal.
94h
On - Margin low.
A4h
On - Margin high.
ON_OFF_CONFIG (02h)
Definition: Configures the interpretation and coordination of the OPERATION command and the ENABLE pin (EN).
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 17h (Device starts from ENABLE pin with immediate off)
Units: N/A
SETTINGS
ACTIONS
00h
Device starts any time power is present regardless of ENABLE pin or OPERATION command states.
16h
Device starts from ENABLE pin with soft off.
17h
Device starts from ENABLE pin with immediate off.
1Ah
Device starts from OPERATION command.
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CLEAR_FAULTS (03h)
Definition: Clears all fault bits in all registers and releases the SALRT pin (if asserted) simultaneously. If a fault condition still exists, the
bit will reassert immediately. This command will not restart a device if it has shut down, it will only clear the faults.
Data Length in Bytes: 0 Byte
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/vA
Reference: N/A
STORE_USER_ALL (15h)
Definition: Stores all PMBus settings from the operating memory to the nonvolatile USER store memory. To clear the USER store,
perform a RESTORE_FACTORY then STORE_USER_ALL. To add to the USER store, perform a RESTORE_USER_ALL, write commands to
be added, then STORE_USER_ALL. This command can be used during device operation, but the device will be unresponsive for 20ms
while storing values.
Data Length in Bytes: 0
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/A
RESTORE_USER_ALL (16h)
Definition: Restores all PMBus settings from the USER store memory to the operating memory. Command performed at power-up.
Security level is changed to Level 1 following this command. This command can be used during device operation, but the device will be
unresponsive for 20ms while storing values.
Data Length in Bytes: 0
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/A
VOUT_MODE (20h)
Definition: Reports the VOUT mode and provides the exponent used in calculating several VOUT settings. Fixed with linear mode with
default exponent (N) = -13.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 13h (Linear Mode, N = -13)
Units: N/A
VOUT_COMMAND (21h)
Definition: This command sets or reports the target output voltage. This command cannot set a value higher than either VOUT_MAX or
110% of the pin strap VOUT setting.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: Pin strap setting
Units: Volts
Range: 0V to VOUT_MAX
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VOUT_CAL_OFFSET (23h)
Definition: The VOUT_CAL_OFFSET command is used to apply a fixed offset voltage to the output voltage command value. This
command is typically used by the user to calibrate a device in the application circuit.
Data Length in Bytes: 2
Data Format: L16s
Type: R/W
Default Value: 0000h
Units: Volts
VOUT_MAX (24h)
Definition: The VOUT_ MAX command sets an upper limit on the output voltage the unit can command regardless of any other
commands or combinations. The intent of this command is to provide a safeguard against a user accidentally setting the output
voltage to a possibly destructive level rather than to be the primary output overprotection. Default value can be changed via PMBus.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 1.10xVOUT_COMMAND pin strap setting
Units: Volts
Range: 0V to 5.5V
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VOUT_MARGIN_HIGH (25h)
Definition: Sets the value of the VOUT during a margin high. This VOUT_MARGIN_HIGH command loads the unit with the voltage to
which the output is to be changed when the OPERATION command is set to “Margin High”.
Data Length in Bytes: 2
Data Format: L11
Type: R/W word
Default value: 1.05 x VOUT_COMMAND pin strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_MARGIN_LOW (26h)
Definition: Sets the value of the VOUT during a margin low. This VOUT_MARGIN_LOW command loads the unit with the voltage to which
the output is to be changed when the OPERATION command is set to “Margin Low”.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default value: 0.95 x VOUT_COMMAND pin strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_TRANSITION_RATE (27h)
Definition: This command sets the rate at which the output should change voltage when the device receives an OPERATION command
(Margin High, Margin Low) that causes the output voltage to change. The maximum possible positive value of the two data bytes
indicates that the device should make the transition as quickly as possible.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default value: BA00h (1.0 V/ms)
Units: V/ms
Range: 0.1 to 4V/ms
VOUT_DROOP (28h)
Definition: The VOUT_DROOP sets the effective load line (V/I slope) for the rail in which the device is used. It is the rate, in mV/A at
which the output voltage decreases (or increases) with increasing (or decreasing) output current for use with Adaptive Voltage
Positioning schemes.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default value: 0000h (0mV/A)
Units: mV/A
Range: 0 to 40 mV/A
FREQUENCY_SWITCH (33h)
Definition: Sets the switching frequency of the device. Initial default value is defined by a pin strap and this value can be overridden by
writing this command via PMBus. If an external SYNC is utilized, this value should be set as close as possible to the external clock value.
The output must be disabled when writing this command.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: Pin strap setting
Units: kHz
Range: 300kHz to 1066MHz
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INTERLEAVE (37h)
Definition: Configures the phase offset of a device that is sharing a common SYNC clock with other devices. A value of 0 for the Number
in Group field is interpreted as 16, to allow for phase spreading groups of up to 16 devices.
Data Length in Bytes: 2
Data Format: BIT
Type: R/W
Default Value: Pin strap setting
Units: kHz
BITS
15:2
11:8
PURPOSE
VALUE
Reserved
0
DESCRIPTION
Reserved
Group Number
0 to 15
Sets a number to a group of interleaved rails
7:4
Number in Group
0 to 15
Sets the number of rails in the group A value of 0 is interpreted as 16
3:0
Position in Group
0 to 15
Sets position of the device's rail within the group
IOUT_CAL_GAIN (38h)
Definition: Sets the effective impedance across the current sense circuit for use in calculating output current at +25°C.
Data Length in Bytes: 2
Data Format: L11.
Type: R/W
Default Value: B2AEh (0.67mΩ)
Units: mΩ
IOUT_CAL_OFFSET (39h)
Definition: Used to null out any offsets in the output current sensing circuit and to compensate for delayed measurements of current
ramp due to Isense blanking time.
Data Length in Bytes: 2
Data Format: 11.
Type: R/W
Default Value: 0000h (0A)
Units: A
VOUT_OV_FAULT_LIMIT (40h)
Definition: Sets the VOUT overvoltage fault threshold.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 1.15xVOUT_COMMAND pin strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_OV_FAULT_RESPONSE (41h)
Definition: Configures the VOUT overvoltage fault response. Note that the device cannot be set to ignore this fault mode.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable and no retry)
Units:
SETTINGS
ACTIONS
80h
Disable with no retry
BFh
Disable and continuous retry with 70ms delay
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VOUT_OV_WARNING_LIMIT (42h)
Definition: Sets the VOUT overvoltage wring threshold. Power-good signal is pulled low when output voltage goes higher than this
threshold.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 0.85xVOUT_COMMAND pin strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_UV_WARNING_LIMIT (43h)
Definition: Sets the VOUT undervoltage warning threshold. Power-Good signal is pulled low when output voltage goes lower than this
threshold.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 0.85xVOUT_COMMAND pin strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_UV_FAULT_LIMIT (44h)
Definition: Sets the VOUT undervoltage fault threshold. This fault is masked during ramp or when disabled.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 0.85xVOUT_COMMAND pin strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_UV_FAULT_RESPONSE (45h)
Definition: Configures the VOUT undervoltage fault response.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable, no retry)
Units:
SETTINGS
ACTIONS
80h
Disable with no retry
BFh
Disable and continuous retry with 70ms delay
IOUT_OC_FAULT_LIMIT (46h)
Definition: Sets the IOUT average overcurrent fault threshold. Device will automatically calculate peak inductor overcurrent fault limit.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: E280h (40A)
Units: A
Range: -100 to 100A
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IOUT_UC_FAULT_LIMIT (4Bh)
Definition: Sets the IOUT average undercurrent fault threshold. Device will automatically calculate valley inductor undercurrent fault limit.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: -1xIOUT_OC_FAULT_LIMIT
Units: A
Range: -100 to 100A
OT_FAULT_LIMIT (4Fh)
Definition: The OT_FAULT_LIMIT command sets the temperature at which the device should indicate an over-temperature fault. Note
that the temperature must drop below OT_WARN_LIMIT to clear this fault.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: EBE8h (+125˚C)
Units: Celsius
Range: 0˚C to +175˚C
OT_FAULT_RESPONSE (50h)
Definition: The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an over-temperature fault.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
fault Value: 80h (Disable and no retry)
Units:
SETTINGS
ACTIONS
80h
Disable with no retry
BFh
Disable and continuous retry with 70ms delay
OT_WARN_LIMIT (51h)
Definition: The OT_WARN_LIMIT command sets the temperature at which the device should indicate an over-temperature warning
alarm. In response to the OT_WARN_LIMIT being exceeded, the device: Sets the TEMPERATURE bit in STATUS_WORD, Sets the
OT_WARNING bit in STATUS_TEMPERATURE and notifies the host.
Data Length in Bytes: 2
Data Format: Linear-11.
Type: R/W
Default Value: EB70h (+110°C)
Units: Celsius
Range: 0˚C to +175˚C
UT_WARN_LIMIT (52h)
Definition: The UT_WARN_LIMIT command set the temperature at which the device should indicate an under-temperature Warning
alarm. In response to the UT_WARN_LIMIT being exceeded, the device: Sets the TEMPERATURE bit in STATUS_WORD, Sets the
UT_WARNING bit in STATUS_TEMPERATURE and notifies the host.
Data Length in Bytes: 2
Data Format: L11.
Type: R/W
Default Value: DC40h (-30°C)
Units: Celsius
Range: -55˚C to +25˚C
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ISL8271M
UT_FAULT_LIMIT (53h)
Definition: The UT_FAULT_LIMIT command sets the temperature, in degrees Celsius, of the unit where it should indicate an
under-temperature fault. Note that the temperature must rise above UT_WARN_LIMIT to clear this fault.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: E530h (-45°C)
Units: Celsius
Range: -55˚C to +25˚C
UT_FAULT_RESPONSE (54h)
Definition: Configures the under-temperature fault response as defined by the following table. The delay time is the time between
restart attempts.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable, no retry)
Units:
SETTINGS
ACTIONS
80h
Disable with no retry
BFh
Disable and continuous retry with 70ms delay
VIN_OV_FAULT_LIMIT (55h)
Definition: Sets the VIN overvoltage fault threshold.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: D380h (14V)
Units: V
Range: 0V to 16V
VIN_OV_FAULT_RESPONSE (56h)
Definition: Configures the VIN overvoltage fault response as defined by the following table. The delay time is the time between restart
attempts.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable and no retry)
Units:
SETTINGS
ACTIONS
80h
Disable with no retry
BFh
Disable and continuous retry with 70ms delay
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FN8636.3
June 17, 2016
ISL8271M
VIN_OV_WARN_LIMIT (57h)
Definition: Sets the VIN overvoltage warning threshold as defined by the table below. In response to the OV_WARN_LIMIT being
exceeded, the device: Sets the NONE OF THE ABOVE and INPUT bits in STATUS_WORD, Sets the VIN_OV_WARNING bit in STATUS_INPUT
and notifies the host.
Data Length in Bytes: 2
Data Format: L11.
Type: R/W
Protectable: Yes
Default Value: D327h (12.6V)
Units: V
Range: 0V to 16V
VIN_UV_WARN_LIMIT (58h)
Definition: Sets the VIN undervoltage warning threshold. If a VIN_UV_FAULT occurs, the input voltage must rise above
VIN_UV_WARN_LIMIT to clear the fault, which provides hysteresis to the fault threshold. In response to the UV_WARN_LIMIT being
exceeded, the device: Sets the NONE OF THE ABOVE and INPUT bits in STATUS_WORD, Sets the VIN_UV_WARNING bit in STATUS_INPUT
and notifies the host.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Default Value: 1.1 x VIN_UV_FAULT_LIMIT pin strap setting
Units: V
Range: 0V to 12V
VIN_UV_FAULT_LIMIT (59h)
Definition: Sets the VIN undervoltage fault threshold.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: Pin strap setting
Units: V
Range: 0V to 12V
VIN_UV_FAULT_RESPONSE (5Ah)
Definition: Configures the VIN undervoltage fault response as defined by the following table. The delay time is the time between restart
attempts.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable and no retry)
Units:
SETTINGS
ACTIONS
80h
Disable with no retry
BFh
Disable and continuous retry with 70ms delay
POWER_GOOD_ON (5Eh)
Definition: Sets the voltage threshold for Power-Good indication. Power-Good asserts when the output voltage exceeds
POWER_GOOD_ON and de-asserts when the output voltage is less than VOUT_UV_FAULT_LIMIT.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 0.9xVOUT_COMMAND pin strap setting
Units: V
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FN8636.3
June 17, 2016
ISL8271M
TON_DELAY (60h)
Definition: Sets the delay time from when the device is enabled to the start of VOUT rise.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: 5
Units: ms
Range: 0 to 500ms
TON_RISE (61h)
Definition: Sets the rise time of VOUT after ENABLE and TON_DELAY.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: 5
Units: ms
Range: 0 to 200ms
TOFF_DELAY (64h)
Definition: Sets the delay time from DISABLE to start of VOUT fall.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: 5
Units: ms
Range: 0 to 500 seconds
TOFF_FALL (65h)
Definition: Sets the fall time for VOUT after DISABLE and TOFF_DELAY.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: 5
Units: ms
Range: 0 to 200ms
STATUS_BYTE (78h)
Definition: The STATUS_BYTE command returns one byte of information with a summary of the most critical faults.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 00h
Units: N/A
BIT NUMBER
STATUS BIT NAME
MEANING
7
BUSY
A fault was declared because the device was busy and unable to respond.
6
OFF
This bit is asserted if the unit is not providing power to the output, regardless of
the reason, including simply not being enabled.
5
VOUT_OV_FAULT
An output overvoltage fault has occurred.
4
IOUT_OC_FAULT
An output overcurrent fault has occurred.
3
VIN_UV_FAULT
An input undervoltage fault has occurred.
2
TEMPERATURE
A temperature fault or warning has occurred.
1
CML
A communications, memory or logic fault has occurred.
0
NONE OF THE ABOVE
A fault or warning not listed in bits 7:1 has occurred.
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FN8636.3
June 17, 2016
ISL8271M
STATUS_WORD (79h)
Definition: The STATUS_WORD command returns two bytes of information with a summary of the unit's fault condition. Based on the
information in these bytes, the host can get more information by reading the appropriate status registers. The low byte of the
STATUS_WORD is the same register as the STATUS_BYTE (78h) command.
Data Length in Bytes: 2
Data Format: BIT
Type: Read-only
Default Value: 0000h
Units: N/A
BIT NUMBER
STATUS BIT NAME
MEANING
15
VOUT
An output voltage fault or warning has occurred.
14
IOUT/POUT
An output current or output power fault or warning has occurred.
13
INPUT
An input voltage, input current, or input power fault or warning has occurred.
12
MFG_SPECIFIC
A manufacturer specific fault or warning has occurred.
11
POWER_GOOD#
The POWER_GOOD signal, if present, is negated.
10
FANS
A fan or airflow fault or warning has occurred.
9
OTHER
A bit in STATUS_OTHER is set.
8
UNKNOWN
A fault type not given in bits 15:1 of the STATUS_WORD has been detected.
7
BUSY
A fault was declared because the device was busy and unable to respond.
6
OFF
This bit is asserted if the unit is not providing power to the output, regardless of
the reason, including simply not being enabled.
5
VOUT_OV_FAULT
An output overvoltage fault has occurred.
4
IOUT_OC_FAULT
An output overcurrent fault has occurred.
3
VIN_UV_FAULT
An input undervoltage fault has occurred.
2
TEMPERATURE
A temperature fault or warning has occurred.
1
CML
A communications, memory or logic fault has occurred.
0
NONE OF THE ABOVE
A fault or warning not listed in bits 7:1 has occurred.
STATUS_VOUT (7Ah)
Definition: The STATUS_VOUT command returns one data byte with the status of the output voltage.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 00h
Units: N/A
BIT NUMBER
STATUS BIT NAME
MEANING
7
VOUT_OV_FAULT
6
VOUT_OV_WARNING
Indicates an output overvoltage warning.
5
VOUT_UV_WARNING
Indicates an output undervoltage warning.
4
VOUT_UV_FAULT
Indicates an output undervoltage fault.
N/A
These bits are not used.
3:0
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Indicates an output overvoltage fault.
FN8636.3
June 17, 2016
ISL8271M
STATUS_IOUT (7Bh)
Definition: The STATUS_IOUT command returns one data byte with the status of the output current.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 00h
Units: N/A
BIT NUMBER
STATUS BIT NAME
MEANING
7
IOUT_OC_FAULT
An output overcurrent fault has occurred.
6
IOUT_OC_LV_FAULT
An output overcurrent and low voltage fault has occurred.
5
IOUT_OC_WARNING
An output overcurrent warning has occurred.
4
IOUT_UC_FAULT
An output undercurrent fault has occurred.
N/A
These bits are not used.
3:0
STATUS_INPUT (7Ch)
Definition: The STATUS_INPUT command returns input voltage and input current status information.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 00h
Units: N/A
BIT NUMBER
STATUS BIT NAME
MEANING
7
VIN_OV_FAULT
An input overvoltage fault has occurred.
6
VIN_OV_WARNING
An input overvoltage warning has occurred.
5
VIN_UV_WARNING
An input undervoltage warning has occurred.
4
VIN_UV_FAULT
An input undervoltage fault has occurred.
N/A
These bits are not used.
3:0
STATUS_TEMP (7Dh)
Definition: The STATUS_TEMP command returns one byte of information with a summary of any temperature related faults or warnings.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 00h
Units: N/A
BIT NUMBER
STATUS BIT NAME
MEANING
7
OT_FAULT
An over-temperature fault has occurred.
6
OT_WARNING
An over-temperature warning has occurred.
5
UT_WARNING
An under-temperature warning has occurred.
4
UT_FAULT
An under-temperature fault has occurred.
N/A
These bits are not used.
3:0
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FN8636.3
June 17, 2016
ISL8271M
STATUS_CML (7Eh)
Definition: The STATUS_CML command returns one byte of information with a summary of any Communications, Logic and/or Memory
errors.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 00h
Units: N/A
BIT NUMBER
MEANING
7
Invalid or unsupported PMBus command was received.
6
The PMBus command was sent with invalid or unsupported data.
5
packet error was detected in the PMBus command.
4:2
Not Used.
1
A PMBus command tried to write to a read-only or protected command, or a communication fault other than the ones listed in
this table has occurred.
0
Not Used.
STATUS_MFR_SPECIFIC (80h)
Definition: The STATUS_MFR_SPECIFIC command returns one byte of information providing the status of the device's voltage
monitoring and clock synchronization faults. VDRV OV/UV warnings are set at ±10% of the VMON_FAULT commands.
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default value: 00h
Units: N/A
BIT NUMBER
7:6
FIELD NAME
MEANING
Reserved
5
VDRV UV Warning
The voltage on the VMON pin has dropped 10% below the level set by
VDRV_UV_FAULT.
4
VDRV OV Warning
The voltage on the VMON pin has risen 10% above the level set by
VDRV_OV_FAULT.
3
External Switching Period Fault
Loss of external clock synchronization has occurred.
2
Reserved
1
VDRV UV Fault
The voltage on the VMON pin has dropped below the level set by
VDRV_UV_FAULT.
0
VDRV OV Fault
The voltage on the VMON pin has risen above the level set by VDRV_OV_FAULT.
READ_VIN (88h)
Definition: Returns the input voltage reading.
Data Length in Bytes: 2
Data Format: L11
Type: Read-only
Units: V
READ_VOUT (8Bh)
Definition: Returns the output voltage reading.
Data Length in Bytes: 2
Data Format: L16u
Type: Read-only
Units: V
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FN8636.3
June 17, 2016
ISL8271M
READ_IOUT (8Ch)
Definition: Returns the output current reading.
Data Length in Bytes: 2
Data Format: L11
Type: Read-only
Default Value: N/A
Units: A
READ_INTERNAL_TEMP (8Dh)
Definition: Returns the controller junction temperature reading from internal temperature sensor.
Data Length in Bytes: 2
Data Format: L11
Type: Read-only
Units: °C
READ_EXTERNAL_TEMP (8Eh)
Definition: Returns the temperature reading from the external temperature device connected to XTEMP pins.
Data Length in Bytes: 2
Data Format: L11
Type: Read-only
Units: °C
READ_DUTY_CYCLE (94h)
Definition: Reports the actual duty cycle of the converter during the enable state.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Units: %
READ_FREQUENCY (95h)
Definition: Reports the actual switching frequency of the converter during the enable state.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Units: kHz
MFR_ID (99h)
Definition: MFR_ID sets user defined identification. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,
MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command then perform a STORE/RESTORE.
Data Length in Bytes: User defined
Data Format: ASCII
Type: Block R/W
Default Value: null
Units: N/A
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June 17, 2016
ISL8271M
MFR_MODEL (9Ah)
Definition: MFR_MODEL sets a user defined model. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,
MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command then perform a STORE/RESTORE.
Data Length in Bytes: User defined
Data Format: ASC
Type: Block R/W
Default Value: null
Units: N/A
MFR_REVISION (9Bh)
Definition: MFR_REVISION sets a user defined revision. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,
MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command then perform a STORE/RESTORE.
Data Length in Bytes: User defined
Data Format: ASC
Type: Block R/W
Default Value: null
Units: N/A
MFR_LOCATION (9Ch)
Definition: MFR_LOCATION sets a user defined location identifier. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,
MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command then perform a STORE/RESTORE.
Data Length in Bytes: User defined
Data Format: ASC
Type: Block R/W
Default Value: null
Units: N/A
MFR_DATE (9Dh)
Definition: MFR_DATE sets a user defined date. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION, MFR_LOCATION,
MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This limitation includes
multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this command then
perform a STORE/RESTORE.
Data Length in Bytes: User defined
Data Format: ASC
Type: Block R/W
Default Value: null
Units: N/A
Reference: N/A
MFR_SERIAL (9Eh)
Definition: MFR_SERIAL sets a user defined serialized identifier. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,
MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command then perform a STORE/RESTORE.
Data Length in Bytes: User defined
Data Format: ASC
Type: Block R/W
Default Value: null
Units: N/A
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FN8636.3
June 17, 2016
ISL8271M
LEGACY_FAULT_GROUP (A8h)
Definition: This command is used only when the power system is created by mixing the ISL8271M module with old generation digital
modules (ZL9101M, ZL9117M, ZL9006M, ZL9010M) to power various rails. This command provides an ability to powering down the
system by broadcast faults between old and new generation digital modules.
New generation module uses group ID to broadcast faults between each other. Refer to DDC_GROUP(E2h) command. Old generation
module uses rail ID to broadcast fault. When new and old modules are mixed, ISL8271M can use GROUP-ID (new generation module)
and/or RAIL-ID (old generation module) to execute shutdown as response to fault to selected GROUP_ID or RAIL-ID. A module can listen
to multiple RAIL-IDs by writing 1 to a bit location representing RAIL-ID of old generation modules.
NOTE; Bit-5 in DDC_GROUP command should be programmed 1 to activate fault broadcast.
Data Length in Bytes: 4
Data Format: BIT
Type: R/W Block
Default Value: 00000000h
Units: N/A
TABLE 7.
BIT
DESCRIPTION
BIT
DESCRIPTION
BIT
31
Listen to Rail-31
23
Listen to Rail-23
15
Listen to Rail-15
DESCRIPTION
BIT
7
Listen to Rail-7
DESCRIPTION
30
Listen to Rail-30
22
Listen to Rail-22
14
Listen to Rail-14
6
Listen to Rail-6
29
Listen to Rail-29
21
Listen to Rail-21
13
Listen to Rail-13
5
Listen to Rail-5
28
Listen to Rail-28
20
Listen to Rail-20
12
Listen to Rail-12
4
Listen to Rail-4
27
Listen to Rail-27
19
Listen to Rail-19
11
Listen to Rail-11
3
Listen to Rail-3
26
Listen to Rail-26
18
Listen to Rail-18
10
Listen to Rail-10
2
Listen to Rail-2
25
Listen to Rail-25
17
Listen to Rail-17
9
Listen to Rail-9
1
Listen to Rail-1
24
Listen to Rail-24
16
Listen to Rail-16
8
Listen to Rail-8
0
Listen to Rail-0
USER_DATA_00 (B0h)
Definition: USER_DATA_00 sets a user defined data. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,
MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command then perform a STORE/RESTORE.
Data Length in Bytes: User defined
Data Format: ASCII
Type: Block R/W
Default Value: null
Units: N/A
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FN8636.3
June 17, 2016
ISL8271M
ISENSE_CONFIG (D0h)
Definition: Configures current sense circuitry.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W Byte
Default Value: 05h
Units: N/A
BIT
FIELD NAME
VALUE
7:4
Reserved
000
3:2
1:0
Current Sense
Blanking Time
Current Sense Range
SETTING
00
192ns
01
256ns
10
412ns
11
640ns
00
Low Range
DESCRIPTION
Sets the blanking time current sense blanking time.
±25mV
01
Mid Range
±35mV
10
High Range
±50mV
11
Not Used
USER_CONFIG (D1h)
Definition: Configures several user-level features. This command overrides the CONFIG pin settings.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W Byte
Default Value: 00h
Units: N/A
BIT
7:5
FIELD NAME
VALUE
Reserved
0.39%
01
0.78%
10
1.17%
11
1.56%
Minimum Duty Cycle
Control
0
Disable
1
Enable
Power-Good Pin
Configuration
0
Open Drain
1
Push-Pull
0
Disable
1
Enable
Ramp-Up and
Ramp-Down Minimum
Duty Cycle
1
0
XTEMP Enable
DESCRIPTION
Reserved.
00
4:3
2
SETTING
0
Sets the minimum duty-cycle during start-up and shutdown ramp.
Must be enabled with Bit 10.
Control for minimum duty cycle.
0 = PG is open drain output.
1 = PG is push-pull output.
Enable external temperature monitoring.
DDC_CONFIG (D3h)
Definition: Configures DDC addressing.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 00h
Units: N/A
BIT
FIELD NAME
VALUE
SETTING
7:5
4:0
Reserved
00
Reserved
Rail ID
0 to 31 (00 to 1Fh)
0
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DESCRIPTION
Reserved.
Configures DDC address
FN8636.3
June 17, 2016
ISL8271M
POWER_GOOD_DELAY (D4h)
Definition: Sets the delay applied between the output exceeding the PG threshold (POWER_GOOD_ON) and asserting the PG pin. The
delay time can range from 0ms up to 500s, in steps of 125ns. A 1ms minimum configured value is recommended to apply proper
de-bounce to this signal.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: 1ms
Units: ms
Range: 0 to 5s
ASCR_CONFIG (DFh)
Definition: Allows user configuration of ASCR settings.
Data Length in Bytes: 4
Data Format: CUS
Type: R/W
Default Value: 015A0100h
BIT
PURPOSE
31:25
Unused
24
DATA Format
ASCCR Enable
BIT
23:16
ASCR Residual Setting
Integer
15:0
ASCR Gain Setting
Integer
VALUE
DESCRIPTION
0000000h
Unused
1
Enable
0
Disable
SEQUENCE (E0h)
Definition: Identifies the Rail DDC ID of the prequel and sequel rails when performing multi-rail sequencing. The device will enable its
output when its EN or OPERATION enable states, as defined by ON_OFF_CONFIG, is set and the prequel device has issued a Power-Good
event on the DDC bus. The device will disable its output (using the programmed delay values) when the sequel device has issued a
Power-Down event on the DDC bus.
The data field is a two-byte value. The most-significant byte contains the 5-bit Rail DDC ID of the prequel device. The least-significant
byte contains the 5-bit Rail DDC ID of the sequel device. The most significant bit of each byte contains the enable of the prequel or
sequel mode. This command overrides the corresponding sequence configuration set by the CONFIG pin settings.
Data Length in Bytes: 2
Data Format: BIT
Type: R/W
Default Value: 00h (Prequel and Sequel disabled)
BIT
15
FIELD NAME
Prequel Enable
14:13
Reserved
12:8
Prequel Rail DDC ID
7
Sequel Enable
6:5
Reserved
4:0
Sequel Rail DDC ID
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VALUE
SETTING
DESCRIPTION
0
Disable
Disable, no prequel preceding this rail.
1
Enable
Enable, prequel to this rail is defined by bits 12:8.
0
Reserved
0-31
DDC ID
Set to the DDC ID of the prequel rail.
Reserved.
0
Disable
Disable, no sequel following this rail.
1
Enable
Enable, sequel to this rail is defined by bits 4:0.
0
Reserved
0-31
DDC ID
Reserved.
Set to the DDC ID of the sequel rail.
FN8636.3
June 17, 2016
ISL8271M
DDC_GROUP (E2h)
Definition: This command configures fault spreading group ID and enable, broadcast OPERATION group ID and enable and broadcast
VOUT_COMMAND group ID and enable.
Data Length in Bytes: 3
Data Format: BIT
Type: R/W
Default Value: 0000h (Ignore BROADCAST VOUT_COMMAND and OPERATION, Sequence shutdown on POWER_FAIL event)
BITS
23:22
PURPOSE
VALUE
Reserved
21
BROADCAST_VOUT_COMMAND Response
20:16
BROADCAST_VOUT_COMMAND Group ID
15:14
Reserved
13
12:8
7:6
BROADCAST_OPERATION Group ID
POWER_FAIL Response
4:0
POWER_FAIL group ID
1
Responds to BROADCAST_VOUT_COMMAND with same Group ID.
0
Ignores BROADCAST_VOUT_COMMAND.
Group ID sent as data for broadcast BROADCAST_VOUT_COMMAND events.
0
Reserved.
1
Responds to BROADCAST_OPERATION with same Group ID.
0
Ignores BROADCAST_OPERATION.
0-31d
Reserved
5
Reserved
0-31d
BROADCAST_OPERATION Response
DESCRIPTION
0
Group ID sent as data for broadcast BROADCAST_OPERATION events.
0
Reserved.
1
Responds to POWER_FAIL events with same Group ID by shutting down
immediately.
0
Responds to POWER_FAIL events with same Group ID with sequenced shutdown.
0-31d
Group ID sent as data for broadcast POWER_FAIL events.
DEVICE_ID (E4h)
Definition: Returns the 16-byte (character) device identifier string.
Data Length in Bytes: 16
Data Format: ASCII
Type: Block Read
Default Value: Part number/Die revision/Firmware revision
MFR_IOUT_OC_FAULT_RESPONSE (E5h)
Definition: Configures the IOUT overcurrent fault response as defined by the following table. The command format is the same as the
PMBus standard fault responses except that it sets the overcurrent status bit in STATUS_IOUT.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable and no retry)
Units:
SETTINGS
ACTIONS
80h
Disable with no retry.
BFh
Disable and continuous retry with 70ms delay.
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June 17, 2016
ISL8271M
MFR_IOUT_UC_FAULT_RESPONSE (E6h)
Definition: Configures the IOUT undercurrent fault response as defined by the following table. The command format is the same as the
PMBus standard fault responses except that it sets the undercurrent status bit in STATUS_IOUT.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable and no retry)
Units:
SETTINGS
ACTIONS
80h
Disable with no retry.
BFh
Disable and continuous retry with 70ms delay.
SYNC_CONFIG (E9h)
Definition: This command is used to set options for SYNC output configurations.
Data Length in Bytes: 2
Data Format: BIT
Type: R/W
Default Value: 0000h
SETTINGS
ACTIONS
00h
Use Internal clock. Clock frequency is set by pin strap or PMBus command.
02h
Use internal clock and output internal clock.
04h
Use external clock.
SNAPSHOT (EAh)
Definition: The SNAPSHOT command is a 32-byte read-back of parametric and status values. It allows monitoring and status data to be
stored to flash following a fault condition. In case of a fault, last updated values are stored to the flash memory. When SNAPSHOT
STATUS byte (22) is set stored, device will no longer automatically capture parametric and status values following fault till stored data
are erased. Use SNAPSHOT_CONTROL command to erase store data and clear the status bit before next ramp up. Data erased is not
allowed when module is enabled.
Data Length in Bytes: 32
Data Format: Bit field
Type: Block Read
BYTE NUMBER
31:23
VALUE
PMBUS COMMAND
FORMAT
Reserved
Reserved
00h
22
Flash Memory Status Byte
FF - Not Stored
00 - Stored
N/A
BIT
21
Manufacturer Specific Status Byte
STATUS_MFR_SPECIFIC (80h)
Byte
20
CML Status Byte
STATUS_CML (7Eh)
Byte
19
Temperature Status Byte
STATUS_TEMPERATURE (7Dh)
Byte
18
Input Status Byte
STATUS_INPUT (7Ch)
Byte
17
IOUT Status Byte
STATUS_IOUT (7Bh)
Byte
16
VOUT Status Byte
STATUS_VOUT (7Ah)
Byte
15:14
Switching Frequency
READ_FREQUENCY (95h)
L11
13:12
External Temperature
READ_EXTERNAL_TEMP (8Eh)
L11
11:10
Internal Temperature
READ_INTERNAL_TEMP (8Dh)
L11
9:8
Duty Cycle
READ_DUTY_CYCLE (94h)
L11
7:6
Highest Measured Output Current
N/A
L11
5:4
Output Current
READ_IOUT (8Ch)
L11
3:2
Output Voltage
READ_VOUT (8Bh)
L16u
1:0
Input Voltage
READ_VIN (88h)
L11
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ISL8271M
BLANK_PARAMS (EBh)
Definition: Returns a 16-byte string indicating which parameter values were either retrieved by the last RESTORE operation or have
been written since that time. Reading BLANK_PARAMS immediately after a restore operation allows the user to determine which
parameters are stored in that store. A one indicates the parameter is not present in the store and has not been written since the
RESTORE operation.
Data Length in Bytes: 16
Data Format: BIT
Type: Block Read
Default Value: FF…FFh
SNAPSHOT_CONTROL (F3h)
Definition: SNAPSHOT_CONTROL command can be used to erase parametric and status values stored at SNAPSHOT flash memory
location.
Data Length in Bytes: 1
Data Format: Bit field
Type: R/W byte
VALUE
DESCRIPTION
03h
Erase parametric and status values stored in SNAPSHOT.
RESTORE_FACTORY (F4h)
Definition: Restores the device to the hard-coded Factory default values and pin strap definitions. The device retains the DEFAULT and
USER stores for restoring. Security level is changed to Level 1 following this command.
Data Length in Bytes: 0
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/A
VDRV_OV_FAULT_LIMIT (F5h)
Definition: Reads the VDRV OV fault threshold.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Default Value: CB00h (6V)
Units:
Range: 4V to 6V
VDRV_UV_FAULT_LIMIT (F6h)
Definition: Reads the VDRV UV fault threshold
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Default Value: CA00h (4V)
Units: V
Range: 4V to 6V
READ_VDRV (F7h)
Definition: Reads the VDRV voltage.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Default Value: N/A
Units: V
Range: 4V to 6V
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ISL8271M
VDRV_OV_FAULT_RESPONSE (F8h)
Definition: Reads the VDRV OV fault response
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default Value: 80h (Disable and no retry)
Units:
VDRV_UV_FAULT_RESPONSE (F9h)
Definition: Reads the VDRV UV fault response
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default Value: 80h (Disable and no retry)
Units: V
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FN8636.3
June 17, 2016
ISL8271M
Firmware Revision History
TABLE 8. ISL8271M NOMENCLATURE GUIDE
FIRMWARE REVISION CODE
CHANGE DESCRIPTION
ISL8271-000-FC01
NOTE
Initial Release
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
June 17, 2016
FN8636.3
“Ordering Information” on page 3
Updated Note 2 by adding Tape and Reel option.
Updated Note 3 by adding exemption 7A.
Changed “VOUT_MAX (24h)” on page 28 - 0V to 4V to 0V to 5.5V
March 16, 2016
FN8636.2
Added “PMBus Use Guidelines” on page 26.
Updated POD Y40.17x19 to the latest revision changes are as follows:
-Detail A on page 1: Added corner radius on individual I/O pads.
December 18, 2014
FN8636.1
“Electrical Specifications” on page 7 under VOUT_ACCY and VOUT_READ_ERR: Updated unit value from “% FS”
to “%VOUT”.
August 11, 2014
FN8636.0
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN8636.3
June 17, 2016
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Package Outline Drawing
Y40.17x19
40 I/O 17.0mm x 19.0mm x 3.55mm HDA MODULE
Rev 2, 10/15
PIN 1 INDICATOR
C = 0.35
DATUM A
D
A
SEE
DETAIL A
B
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
49
TERMINAL #A1
INDEX AREA
(D/2 x E/2)
(nE-1) x eR
j fff m C A B
E1
eR1
E
f1
d aaa C 2X
f1
d aaa C 2X
TOP VIEW
DATUM B
(nD-1) x eT
D1
j fff m C A B
BOTTOM VIEW
f
ccc C
d eee C
eT
A
f
SEATING PLANE
A1
SIDE VIEW
C
f
0.075 R REF
NOTES:
FN8636.3
June 17, 2016
1.
All dimensions are in millimeters.
2.
‘eT’ and ‘eR’ represent the basic land grid pitch.
3.
“n” is the total number of I/O (excluding dummy pads).
4.
Dimensioning and tolerancing per ASME Y14.5M-2009.
5.
Tolerance for exposed DAP edge location dimension on
page 3 is ±0.1mm.
6.
Mold cap thickness: 3.40mm
3
3
nxL
nxb
j bbbm C A B
j bbbm C
eR
TERMINAL TIP
DETAIL A
DIMENSIONS
MIN
NOM
3.50
3.55
0.55
0.60
0.55
0.60
1.00 BSC
1.35 BSC
1.00 BSC
17.00 BSC
16.35
16.50
2.50
2.40
1.40
1.50
0.70
0.80
5.00
5.10
0.90
1.00
1.50
1.60
0.90
1.00
0.50
0.60
3.40
3.50
9.90
10.00
2.90
3.00
5.70
5.80
1.70
1.80
2.90
3.00
1.90
2.00
4.70
4.80
0.60
0.70
0.50
0.60
1.50
1.60
19.00 BSC
18.35
18.50
0.50
0.60
7.50
7.60
1.50
1.60
5.00
5.10
1.30
1.40
0.50
0.60
0.50
0.60
0.70
0.80
8.10
8.20
8.10
8.20
4.80
4.90
1.90
2.00
1.40
1.50
2.60
2.70
1.40
1.50
2.95
3.05
0.60
0.70
1.90
2.00
0.50
0.60
0.50
0.60
1.50
1.60
0.50
0.60
0.20 REF
0.30 REF
20
13
8
MAX
3.60
0.025
0.65
0.65
6
16.65
2.60
1.60
0.90
5.20
1.10
1.70
1.10
0.70
3.60
10.10
3.10
5.90
1.90
3.10
2.10
4.90
0.80
0.70
1.70
ISL8271M
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
SYMBOL
A
A1
b
L
eR
eR1
eT
D
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D22
D23
E
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
f
f1
n
nD
nE
18.65
0.70
7.70
1.70
5.20
1.50
0.70
0.70
0.90
8.30
8.30
5.00
2.10
1.60
2.80
1.60
3.15
0.80
2.10
0.70
0.70
1.70
0.70
3
ISL8271M
D22
E2
D5
D2
D23 (2X)
E23 (2X)
E22
D3
D4(4X)
E5
E3
E21
D6
E4(4X)
D8
E9
E6
E7
D7
E19
D9
D16
E8
E20
E12
E15
E14
E10
E11
D15
E16
D14
E13
E18
E17
D10
D12
D18
D17
D13
D11
SIZE DETAILS FOR THE 16 EXPOSED DAPS
BOTTOM VIEW
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TYPICAL PCB LAND PATTERN (For Reference)
8.20
6.70
5.70
6.00
5.20
5.30
3.70
4.70
4.30
2.70
3.30
1.70
2.20
2.30
0.70
1.30
0.00
0.30
1.70
1.30
1.10
0.70
0.30
2.70
2.30
3.30
2.90
3.70
4.70
4.40
4.30
5.40
5.70
5.30
6.30
7.30
6.70
7.70
8.30
ISL8271M
9.30
9.30
8.70
8.70
8.30
8.30
7.70
7.70
7.30
7.30
6.70
7.10
6.30
5.70
5.70
5.30
5.30
4.70
4.30
3.70
3.70
3.30
3.30
2.70
2.00
2.30
1.70
1.10
0.04
0.90
1.70
1.30
0.90
0.30
0.00
0.56
1.00
0.30
0.40
1.40
2.00
2.50
2.68
3.28
3.70
4.02
4.63
5.20
5.90
6.15
7.90
8.50
9.20
8.20
4.70
3.00
0.00
1.00
1.60
2.80
2.90
3.50
4.70
5.30
7.00
8.30
7.60
9.20
TYPICAL PCB LAND PATTERN (For Reference)
TOP VIEW
NOTE: All dimensions are in millimeters.
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TYPICAL STENCIL OPENING
9.20
8.20
8.05
7.02
6.90
6.87
5.86
5.90
5.20
5.30
4.29
4.80
3.28
3.72
1.95
2.29
2.71
0.35
1.71
0.55
0.71
1.28
0.72
0.29
0.28
1.05
2.29
1.72
1.29
1.25
2.72
2.65
2.60
3.72
3.29
4.50
4.29
5.72
5.30
6.29
6.45
6.95
7.30
7.15
6.80
7.80
7.65
8.20
ISL8271M
9.29
8.80
9.20
8.80
7.72
8.29
7.80
6.85
7.20
7.80
7.28
6.72
7.15
6.28
6.10
5.72
5.29
5.25
4.29
3.72
3.65
3.28
2.72
2.20
2.15
1.80
5.45
5.80
4.85
4.72
3.80
3.85
2.35
1.80
1.10
1.05
4.61
3.60
2.15
1.20
0.90
0.00
0.06
0.20
0.50
1.20
2.30
2.70
0.15
2.50
2.69
3.26
3.90
4.65
3.20
2.25
0.30
0.46
0.75
0.90
1.50
1.90
5.20
3.40
1.00
0.15
5.90
3.70
4.10
4.04
4.30
5.00
6.10
7.45
8.45
5.90
6.30
6.10
7.30
7.70
7.70
7.90
8.60
9.00
8.00
8.00
6.90
6.35
6.55
4.90
2.80
1.60
0.00
0.20
1.40
1.01
5.35
5.60
6.50
6.45
6.40
6.30
5.50
5.40
4.55
4.50
4.40
4.20
4.00
3.60
3.10
2.80
2.60
1.58
1.40
1.20
6.80
7.40
7.25
7.70
8.10
8.20
7.20
9.10
TYPICAL STENCIL OPENING EDGE POSITION (For Reference)
TOP VIEW
NOTE: All dimensions are in millimeters.
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FN8636.3
June 17, 2016
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