DATASHEET

[ /Title
(HIP65
02B)
/Subject
(Multiple
Linear
Power
Controller
with
ACPI
Control
Interface)
/Autho
r ()
/Keywords
(Intersil
Corporation,
semiconduCtor,
acpi,
power
management,
instantl
y
available,
HIP6502B
TM
Data Sheet
May 2000
Multiple Linear Power Controller with
ACPI Control Interface
The HIP6502B complements either an HIP6020 or an
HIP6021 in ACPI-compliant designs for microprocessor and
computer applications. The IC integrates four linear
controllers/regulators, switching, monitoring and control
functions into a 20-pin SOIC package. One linear controller
generates the 3.3VDUAL/3.3VSB voltage plane from the ATX
supply’s 5VSB output, powering the south bridge and the
PCI slots through an external pass transistor during sleep
states (S3, S4/S5). A second transistor is used to switch in
the ATX 3.3V output for operation during S0 and S1/S2
(active) operating states. Two linear controllers/regulators
supply at choice either or both of the computer system’s
2.5V or 3.3V memory power through external pass
transistors in active states. During sleep states, integrated
pass transistors supply the sleep power. Another controller
powers up the 5VDUAL plane by switching in the ATX 5V
output in active states, and the ATX 5VSB in sleep states.
One internal regulator outputs a dedicated, noise-free 2.5V
clock chip supply. The HIP6502B’s operating mode (active
outputs or sleep outputs) is selectable through two digital
control pins, S3 and S5. Enabling sleep state support on the
5VDUAL output is offered through the EN5VDL pin. In active
state, the 3.3VDUAL and 3.3VMEM linear regulators use
external N-channel pass MOSFETs to connect the outputs
directly to the 3.3V input supplied by an ATX (or equivalent)
power supply, for minimal losses. In sleep state, power
delivery on both outputs is transferred to NPN transistors external to the controller on the 3.3VDUAL, internal on the
3.3VMEM . Active state regulation on the 2.5VMEM output is
performed through an external NPN transistor. In sleep
state, conduction on this output is transferred to an internal
pass transistor. The 5VDUAL output is powered through two
external MOS transistors. In sleep states, a PMOS (or PNP)
transistor conducts the current from the ATX 5VSB output;
while in active state, current flow is transferred to an NMOS
transistor connected to the ATX 5V output. The operation of
the 5VDUAL output is dictated not only by the status of the
S3 and S5 pins, but that of the EN5VDL pin as well. The
3.3VDUAL/3.3VSB output is active for as long as the ATX
5VSB voltage is applied to the chip. The 2.5VCLK output is
only active during S0 and S1/S2, and uses the 3V3 pin as
input source for its internal pass element.
PART NUMBER
HIP6502BCB
HIP6502BEVAL1
TEMP.
RANGE (oC)
0 to 70
PACKAGE
20 Ld SOIC
4871
Features
• Provides 5 ACPI-Controlled Voltages
- 5VDUAL USB/Keyboard/Mouse (Active/Sleep)
- 3.3VDUAL/3.3VSB PCI/Auxiliary/LAN (Active/Sleep)
- 2.5VMEM RDRAM (Active/Sleep)
- 3.3VMEM SDRAM (Active/Sleep)
- 2.5VCLK Clock/Processor Terminations (Active Only)
• Excellent Output Voltage Regulation
- 3.3VDUAL/3.3VSB Output: ±2.0% Over Temperature;
Sleep State Only
- 2.5VMEM and 3.3VMEM Output: ±2.0% Over
Temperature; Both Operational States (3.3VMEM in
Sleep Only)
- 2.5VCLK Output: ±2.0% Over Temperature
• Small Size
- Very Low External Component Count
• Dual Memory Voltage Support Via MSEL Pin
- 2.5V for RDRAM Memory
- 3.3V for SDRAM Memory
- Both 2.5V and 3.3V for Flexible Systems
• Under-Voltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
Applications
• Motherboard Power Regulation for ACPI-Compliant
Computers
Pinout
HIP6502B
(SOIC)
TOP VIEW
1
20 MSEL
5VSB 2
19 DRV2
VSEN2
VSEN1 3
3V3DLSB 4
3V3DL 5
VCLK 6
3V3 7
18 5V
17 12V
16 SS
15 5VDL
14 5VDLSB
EN5VDL
8
13 DLA
S3
9
12 FAULT
S5 10
Ordering Information
File Number
11 GND
PKG.
NO.
M20.3
Evaluation Board
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
Block Diagram
12V
3V3 5VSB
5V MONITOR
4.5V/4.25V
-
EA4
5V
3V3DL
3V3DLSB
5VDLSB
DLA
5VSB POR
4.4V/3.2V
TEMPERATURE
MONITOR
(TMON)
+
2
12V MONITOR
10.8V/9.8V
3V3 MONITOR
2.97V/2.8V
TO 5VSB
EA3
+
TO UV
DETECTOR
VSEN1
TO 3V3
+
TO
UV DETECTOR
EA3
VCLK
FAULT
UV DETECTOR
+
-
TO 5V
1.265V
DRV2
TO UV
DETECTOR
10μA
EA2
+
-
+
+
3.75V
UV COMPARATOR
-
VSEN2
5VDL
GND
SS
S3
S5
EN5VDL
FIGURE 1.
MSEL
HIP6502B
MONITOR AND CONTROL
HIP6502B
Simplified Power System Diagram
+5VIN
+12VIN
+5VSB
+3.3VIN
Q6
3.3V
Q1
LINEAR
LINEAR
REGULATOR
3.3VMEM
CONTROLLER
2.5VMEM
2.5V
Q2
LINEAR
CONTROLLER
Q3
3.3VDUAL/3.3VSB
LINEAR
VCLK
REGULATOR
2.5V
Q4
3.3V
FAULT
HIP6502B
MSEL
Q5
CONTROL
LOGIC
5VDUAL
5V
SHUTDOWN
SX
2
EN5VDL
FIGURE 2.
Typical Application
+5VIN
+12VIN
+5VSB
+3.3VIN
Q6
12V
VOUT1
3V3
5VSB
VSEN1
3.3VMEM
COUT1
DRV2
5V
VSEN2
3V3DLSB
Q2
VOUT2
2.5VMEM
COUT2
Q3
VOUT3
Q1
3V3DL
3.3VDUAL/3.3VSB
COUT3
VOUT4
HIP6502B
VCLK
FAULT
FAULT
2.5VCLK
COUT4
Q4
S3
SLP_S3
5VDLSB
S5
SLP_S5
DLA
EN5VDL
EN5VDL
Q5
MSEL
MSEL
VOUT5
5VDL
SS
COUT5
CSS
SHUTDOWN
FIGURE 3.
3
GND
5VDUAL
HIP6502B
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
12V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V
DLA, DRV2 . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V12V +0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 5VSB + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V
Digital Inputs, VSX, VEN5VDL, VMSEL . . . . . . . . . . . . . . . .0 to +5.5V
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
30
-
mA
-
14
-
mA
Rising 5VSB POR Threshold
-
-
4.5
V
5VSB POR Hysteresis
-
1.0
-
V
Rising 12V Threshold
-
-
10.8
V
12V Hysteresis
-
1.0
-
V
Rising 3V3 and 5V Thresholds
-
90
-
%
3V3 and 5V Hysteresis
-
5
-
%
VCC SUPPLY CURRENT
Nominal Supply Current
I5VSB
Shutdown Supply Current
I5VSB(OFF)
VSS = 0.8V
POWER-ON RESET, SOFT-START, AND VOLTAGE MONITORS
Soft-Start Current
ISS
-
10
-
μA
Shutdown Voltage Threshold
VSD
-
-
0.8
V
-
-
2.0
%
-
3.3
-
V
VSEN1 Undervoltage Rising Threshold
-
2.739
-
V
VSEN1 Undervoltage Hysteresis
-
99
-
mV
250
300
-
mA
-
-
2.0
%
-
2.5
-
V
-
2.075
-
V
250
300
-
mA
3.3VMEM LINEAR REGULATOR (VOUT1)
Sleep State Regulation
VSEN1 Nominal Voltage Level
VVSEN1
VSEN1 Output Current
IVSEN1
MSEL > 1.8V
5VSB = 5V
2.5VMEM LINEAR REGULATOR (VOUT2)
Regulation
VSEN2 Nominal Voltage Level
VVSEN2
MSEL < 2.0V
VSEN2 Undervoltage Rising Threshold
VSEN2 Output Current
IVSEN2
4
5VSB = 5V
HIP6502B
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
220
-
-
mA
-
-
2.0
%
-
3.3
-
V
3V3DL Undervoltage Rising Threshold
-
2.739
-
V
3V3DL Undervoltage Hysteresis
-
99
-
mV
5
10
-
mA
-
90
-
Ω
-
-
2.0
%
-
2.5
-
V
VCLK Undervoltage Rising Threshold
-
2.075
-
V
VCLK Undervoltage Hysteresis
-
75
-
mV
500
800
-
mA
5VDL Undervoltage Rising Threshold
-
4.150
-
V
5VDL Undervoltage Hysteresis
-
150
-
mV
-20
-
-40
mA
-
350
-
Ω
20
25
30
ms
-
200
-
μs
High Level Input Threshold
-
-
2.2
V
Low Level Input Threshold
0.8
-
-
V
-
50
-
kΩ
-
100
-
Ω
125
-
-
oC
-
155
-
oC
DRV2 Output Drive Current
IDRV2
TEST CONDITIONS
5VSB = 5V
3.3VDUAL/3.3VSB LINEAR REGULATOR (VOUT3)
Sleep State Regulation
3V3DL Nominal Voltage Level
V3V3DL
3V3DLSB Output Drive Current
I3V3DLSB
5VSB = 5V
DLA Output Impedance
2.5VCLK LINEAR REGULATOR (VOUT4)
Regulation
VCLK Nominal Voltage Level
VVCLK
VCLK Output Current (Note 2)
IVCLK
V3V3 = 3.3V
5VDUAL SWITCH CONTROLLER (VOUT5)
5VDLSB Output Drive Current
I5VDLSB
5VDLSB = 4V, 5VSB = 5V
5VDLSB Pull-Up Impedance to 5VSB
TIMING INTERVALS
Active State Assessment Past Input UV
Thresholds (Note 3)
Active-to-Sleep Control Input Delay
CONTROL I/O (S3, S5, EN5VDL, MSEL, FAULT)
S3, S5 Internal Pull-up Impedance to 5VSB
FAULT Output Impedance
FAULT = high
TEMPERATURE MONITOR
Fault-Level Threshold (Note 4)
Shutdown-Level Threshold (Note 4)
NOTES:
2. At Ambient Temperatures Less Than 50oC.
3. Guaranteed by Correlation.
4. Guaranteed by Design.
5
HIP6502B
Functional Pin Descriptions
3V3 (Pin 7)
Connect this pin to the ATX 3.3V output. This pin provides
the output current for the 2V5CLK pin, and is monitored for
power quality.
event, this pin is used to report the fault condition by being
pulled to 5VSB.
SS (Pin 16)
Provide a very well de-coupled 5V bias supply for the IC to
this pin by connecting it to the ATX 5VSB output. This pin
provides the output current for the VSEN1 and VSEN2 pins,
as well as the base current for Q2. The voltage at this pin is
monitored for power-on reset (POR) purposes.
Connect this pin to a small ceramic capacitor (no less than
5nF; 0.1μF recommended). The internal soft-start (SS)
current source along with the external capacitor creates a
voltage ramp used to control the ramp-up of the output
voltages. Pulling this pin low with an open-drain device shuts
down all the outputs as well as force the FAULT pin low. The
CSS capacitor is also used to provide a controlled voltage
slew rate during active-to-sleep transitions on the 3.3VDUAL,
and VMEM outputs.
5V (Pin 18)
VSEN2 (Pin 1)
Connect this pin to the ATX 5V output. This pin provides the
base bias current for Q1, and is monitored for power quality.
Connect this pin to the ATX 12V output. This pin provides
the gate bias voltage for Q3, Q5 and Q6, and is monitored
for power quality.
Connect this pin to the 2.5V memory output (VOUT2). In
sleep states, this pin is regulated to 2.5V through an internal
pass transistor capable of delivering 300mA (typically). The
active-state voltage at this pin is regulated through an
external NPN transistor connected at the DRV2 pin. During
all operating states, the voltage at this pin is monitored for
under-voltage events.
GND (Pin 11)
DRV2 (Pin 19)
5VSB (Pin 2)
12V (Pin 17)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
S3 and S5 (Pins 9 and 10)
These pins switch the IC’s operating state from active (S0,
S1/S2) to S3 and S4/S5 sleep states. These are digital
inputs featuring internal 50kΩ (typical) resistor pull-ups to
5VSB. Internal circuitry de-glitches these pins for
disturbances lasting as long as 2μs (typically). Additional
circuitry blocks any illegal state transitions (such as S3 to
S4/S5 or vice versa). Respectively, connect S3 and S5 to
the computer system’s SLP_S3 and SLP_S5 signals.
MSEL (Pin 20)
Unconnected, this pin is held at approximately 1.9V by an
internal resistor divider. Pulling this pin below 0.9V enables
the 2.5VMEM output, while pulling it above 2.9V enables the
3.3VMEM output (typical voltage levels). Leaving the pin
open enables both memory regulators.
EN5VDL (Pin 8)
This pin enables or disables sleep state support on the
5VDUAL output in response to S3 and S4/S5 requests. This
is a digital input pin whose status can only be changed
during active state operation or during chip shutdown (SS
pin grounded by external open-drain device or chip bias
below POR level). The input information is latched-in when
entering a sleep state, as well as following 5VSB POR
release or exit from shutdown. EN5VDL is internally pulled
high through a 40μA current source.
FAULT (Pin 12)
In case of an undervoltage on any of the outputs or on any of
the monitored ATX outputs, or in case of an overtemperature
6
Connect this pin to the base of a suitable NPN transistor.
This pass transistor regulates the 2.5V output from the ATX
3.3V during active states operation.
3V3DL (Pin 5)
Connect this pin to the 3.3V dual/stand-by output (VOUT3).
In sleep states, the voltage at this pin is regulated to 3.3V; in
active states, ATX 3.3V output is delivered to this node
through a fully on N-MOS transistor. During all operating
states, this pin is monitored for under-voltage events.
3V3DLSB (Pin 4)
Connect this pin to the base of a suitable NPN transistor. In
sleep state, this transistor is used to regulate the voltage at
the 3V3DL pin to 3.3V.
DLA (Pin 13)
Connect this pin to the gates of suitable N-MOSFETs, which
in active state, switch in the ATX 3.3V and 5V outputs into
the 3.3VMEM , 3.3VDUAL/3.3VSB and 5VDUAL outputs,
respectively.
5VDL (Pin 15)
Connect this pin to the 5VDUAL output (VOUT5). In either
operating state, the voltage at this pin is provided through a
fully on MOS transistor. This pin is also monitored for undervoltage events.
5VDLSB (Pin 14)
Connect this pin to the gate of a suitable P-MOSFET or
bipolar PNP. In sleep state, this transistor is switched on,
connecting the ATX 5VSB output to the 5VDUAL regulator
output.
HIP6502B
VSEN1 (Pin 3)
TABLE 1. 5VDUAL OUTPUT (VOUT5) TRUTH TABLE
Connect this pin to the 3.3V memory output (VOUT1). In
sleep states, this pin is regulated to 3.3V through an internal
pass transistor capable of delivering 300mA (typically). The
active-state voltage at this pin is provided from the ATX 3.3V
through a fully on N-MOS transistor. During all operating
states, the voltage at this pin is monitored for under-voltage
events.
VCLK (Pin 6)
This pin is the output of the internal 2.5V clock chip regulator
(VOUT4). This internal regulator operates only in active
states (S0, S1/S2) and is shut off during any sleep state,
regardless of the configuration of the chip. This pin is
monitored for under-voltage events.
Description
Operation
The HIP6502B controls 5 output voltages (Refer to Figures
1, 2, and 3). It is designed for microprocessor computer
applications with 3.3V, 5V, 5VSB, and 12V bias input from
an ATX power supply. The IC is composed of three linear
controllers/regulators supplying the computer system’s
3.3VSB and PCI slots’ 3.3VAUX power (VOUT3), the 2.5V
RDRAM and 3.3V SDRAM memory power (VOUT2, VOUT1),
an integrated regulator dedicated to 2.5V clock chip
(VOUT4), a dual switch controller supplying the 5VDUAL
voltage (VOUT5), as well as all the control and monitoring
functions necessary for complete ACPI implementation.
Initialization
The HIP6502B automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continually
monitors the 5VSB input supply voltage, initiating 3.3VSB
soft-start operation after exceeding POR threshold. At 3ms
(typically) after 3.3VSB finishes its ramp-up, the EN5VDL
status is latched in and the chip proceeds to ramp up the
remainder of the voltages, as required.
Operational Truth Table
EN5VDL
S5
S3
5VDL
COMMENTS
0
1
1
5V
S0, S1 States (Active)
0
1
0
0V
S3
0
0
1
Note
0
0
0
0V
S4/S5
1
1
1
5V
S0, S1 States (Active)
1
1
0
5V
S3
1
0
1
Note
1
0
0
5V
Maintains Previous State
Maintains Previous State
S4/S5
NOTE: Combination Not Allowed.
The internal circuitry does not allow the transition from an S3
(suspend to RAM) state to an S4/S5 (suspend to disk/soft
off) state or vice versa. The only ‘legal’ transitions are from
an active state (S0, S1) to a sleep state (S3, S5) and vice
versa.
Functional Timing Diagrams
Figures 4 through 6 are timing diagrams, detailing the power
up/down sequences of all three outputs in response to the
status of the enable (EN5VDL) and sleep-state pins (S3,
S5), as well as the status of the ATX supply.
5VSB
S3
S5
3.3V,
5V, 12V
3V3DLSB
DLA
3V3DL
5VDLSB
The EN5VDL pin offers the choice of supporting or disabling
5VDUAL output in S3 and S4/S5 sleep states. Table 1
describes the truth combinations pertaining to this output.
5VDL
FIGURE 4. 5VDUAL TIMING DIAGRAM FOR EN5VDL = 1;
3.3VDUAL/3.3VSB
The status of the EN5VDL pin can only be changed while in
active (S0, S1) states, when the bias supply (5VSB pin) is
below POR level, or during chip shutdown (SS pin shorted to
GND or within 3ms of 5VSB POR); a status change of this
pin while in a sleep state is ignored.
7
HIP6502B
proportional to the SS (soft-start) pin voltage. As the SS pin
voltage slews from about 1.25V to 2.5V, the input clamp
allows a rapid and controlled output voltage rise.
5VSB
S3
S5
3.3V,
5V, 12V
5VSB
(1V/DIV)
SOFT-START
(1V/DIV)
3V3DLSB
DLA
3V3DL
0V
5VDLSB
5VDL
VOUT5 (5VDUAL)
FIGURE 5. 5VDUAL TIMING DIAGRAM FOR EN5VDL = 0;
3VDUAL/3VSB
Not shown in these diagrams is the deglitching feature used
to protect against false sleep state tripping. Both S3 and S5
pins are protected against noise by a 2μs filter (typically 1 4μs). This feature is useful in noisy computer environments if
the control signals have to travel over significant distances.
Additionally, the S3 pin features a 200μs delay in
transitioning to sleep states. Once the S3 pin goes low, an
internal timer is activated. At the end of the 200μs interval, if
the S5 pin is low, the HIP6502B switches into S5 sleep state;
if the S5 pin is high, the HIP6502B goes into S3 sleep state.
5VSB
S3
S5
3.3V,
5V, 12V
INTERNAL
VSEN1, 2
DEVICES
DRV2
VSEN2
DLA
VSEN1
VCLK
FIGURE 6. 2.5VMEM, 3.3VMEM, AND 2.5VCLK TIMING
DIAGRAM; MSEL FLOATING (NOT CONNECTED)
Soft-Start Circuit
SOFT-START INTO SLEEP STATES (S3, S4/S5)
The 5VSB POR function initiates the soft-start sequence. An
internal 10μA current source charges an external capacitor.
The error amplifiers reference inputs are clamped to a level
8
VOUT3 (3.3VDUAL/3.3VSB)
OUTPUT
VOLTAGES
(1V/DIV)
VOUT1 (3.3VMEM)
VOUT2
(2.5VMEM)
VOUT4
(2.5VCLK)
0V
T0 T1 T2
T3
T4
TIME
T5
FIGURE 7. SOFT-START INTERVAL IN A SLEEP STATE
(ALL OUTPUTS ENABLED)
Figure 7 shows the soft-start sequence for the typical
application start-up in sleep state with all output voltages
enabled. At time T0 5VSB (bias) is applied to the circuit. At
time T1 the 5VSB surpasses POR level. An internal fast
charge circuit quickly raises the SS capacitor voltage to
approximately 1V, then the 10μA current source continues
the charging. The soft-start capacitor voltage reaches
approximately 1.25V at time T2, at which point the
3.3VDUAL/3.3VSB error amplifier’s reference input starts its
transition, causing the output voltage to ramp up
proportionally. The ramp-up continues until time T3 when the
3.3VDUAL/3.3VSB voltage reaches the set value. After this
output reached its set value, as the soft-start capacitor
voltage reaches approximately 2.75V, the under-voltage
monitoring circuit of this output is activated and the soft-start
capacitor is quickly discharged to approximately 1.25V.
Following the 3ms (typical) time-out between T3 and T4, the
MSEL and EN5VDL selections are latched in, and the softstart capacitor commences a second ramp-up designed to
smoothly bring up the remainder of the voltages required by
the system. At time T5 all voltages are within regulation
limits, and as the SS voltage reaches 2.75V, all the
remaining UV monitors are activated and the SS capacitor is
quickly discharged to 1.25V, where it remains until the next
transition.
HIP6502B
SOFT-START INTO ACTIVE STATES (S0, S1)
If both S3 and S5 are logic high at the time the 5VSB is
applied, the HIP6502B will assume active state wake-up and
keep off the controlled external transistors and the VCLK
output until some time (typically 25ms) after the ATX’s main
outputs used by the application (3.3V, 5V, and 12V) exceed
the set thresholds. This time-out feature is necessary in
order to insure the main ATX outputs are stabilized. The
time-out also assures smooth transitions from sleep into
active when sleep states are being supported.
3.3VDUAL/3.3VSB output, whose operation is only
dependent on 5VSB presence, will come up right as bias
voltage reaches POR level.
+12VIN
DLA PIN
(2V/DIV)
INPUT VOLTAGES
(2V/DIV)
+5VIN
+5VSB
+3.3VIN
SOFT-START
(1V/DIV)
0V
OUTPUT
VOLTAGES
(1V/DIV)
VOUT5 (5VDUAL)
VOUT1 (3.3VDUAL/3.3VSB)
VOUT2, 4
(2.5VMEM, 2.5VCLK)
VOUT3 (3.3VMEM)
0V
T0
T1
T2
T3
TIME
FIGURE 8. SOFT-START INTERVAL IN ACTIVE STATE
(2.5/3.3VMEM OUTPUT SHOWN IN 2.5V SETTING)
During sleep to active state transitions from conditions
where the outputs are initially 0V (such as S5 to S0 transition
on the 5VDUAL output with EN5VDL = 0, or simple power-up
sequence directly into active state), the 3.3VMEM and
5VDUAL outputs go through a quasi soft-start by being pulled
high through the body diodes of the N-Channel MOSFETs
connected between these outputs and the 3.3V and 5V ATX
outputs. Figure 8 shows this start-up.
5VSB is already present when the main ATX outputs are
turned on at time T0. As a result of +3.3VIN and +5VIN
ramping up, the 3.3VMEM and 5VDUAL output capacitors
charge up through the body diodes of Q6 and Q5,
respectively (see Figure 3). At time T1, all main ATX outputs
exceed the HIP6502B’s undervoltage thresholds, and the
internal 25ms (typical) timer is initiated. At T2 the time-out
9
initiates a soft-start, and the 2.5V memory and clock outputs
are ramped-up, reaching regulation limits at time T3.
Simultaneous with the beginning of the memory and clock
voltage ramp-up, at time T2, the DLA pin is pulled high,
turning on Q3, Q5, and Q6 in the process, and bringing the
3.3VMEM and 5VDUAL outputs in regulation. Shortly after
time T3, as the SS voltage reaches 2.75V, the soft-start
capacitor is quickly discharged down to approximately
2.45V, where it remains until a valid sleep state request is
received from the system.
It is important to note that in the typical application (as
pictured in Figure 3) the 3.3V memory output is powered up
during active state operation, regardless of the MSEL pin
status. Sleep state support on this output is, however,
dependent on the MSEL status.
Fault Protection
All the outputs are monitored against undervoltage events. A
severe overcurrent caused by a failed load on any of the
outputs, would, in turn, cause that specific output to
suddenly drop. If any of the output voltages drop below 80%
(typical) of their set value, such event is reported by having
the FAULT pin pulled to 5V. Additionally, exceeding the
maximum current rating of an integrated regulator (output
with pass regulator on chip) can lead to output voltage
drooping; if excessive, this droop can ultimately trip the
under-voltage detector and send a FAULT signal to the
computer system.
A FAULT condition occurring on an output when controlled
through an external pass transistor will only set off the
FAULT flag, and it will not shut off or latch off any part of the
circuit. A FAULT condition occurring on an output when
controlled through an internal pass transistor, will set off the
FAULT flag, and it will shut off the faulting regulator only. If
shutdown or latch off of the entire circuit is desired in case of
a fault, regardless of the cause, this can be achieved by
externally pulling or latching the SS pin low. Pulling the SS
pin low will also force the FAULT pin to go low and reset an
internally latched-off output.
Special consideration is given to the initial start-up
sequence. If, following a 5VSB POR event, the
3.3VDUAL/3.3VSB output is ramped up and is subject to an
undervoltage event before the remainder of the controlled
voltages have been brought up, then the FAULT output goes
high and the entire IC latches off. Latch-off condition can be
reset by cycling the bias power (5VSB). Undervoltage events
on the 3.3VDUAL/3.3VSB output at any other times are
handled according to the description found in the second
paragraph under the current heading.
Another condition that could set off the FAULT flag is chip
over-temperature. If the HIP6502B reaches an internal
temperature of 140oC (typical), the FAULT flag is set off, but
the chip continues to operate until the temperature reaches
155oC (typical), when unconditional shutdown of all outputs
HIP6502B
takes place. Operation resumes at 140oC and the
temperature cycling occurs until the fault-causing condition
is removed.
In HIP6502B applications, loss of any one active ATX output
(3.3VIN , 5VIN , or 12VIN; as detected by the on-board
voltage monitors) during active state operation causes the
chip to switch to S5 sleep state, in addition to reporting the
input UV condition on the FAULT/MSEL pin. Exiting from this
forced-S5 state can only be achieved by returning the
faulting input voltage above its UV threshold, by resetting the
chip through removal of 5VSB bias voltage, or by bringing
the SS pin at a potential lower than 0.8V.
Output Voltages
The output voltages are internally set and do not require any
external components. Selection of the memory voltages is
done by means the MSEL pin. Leaving the MSEL pin floating
enables support of both memory outputs. Pulling the MSEL
pin below 0.9V enables support only for the 2.5VMEM output.
It is important to notice that in a typical application (such as
that presented in Figure 3), setting the MSEL low will not
prevent the 3.3VMEM from being operational in active state.
Pulling the MSEL pin above 2.9V enables 3.3VMEM output
support, only. Following every 3.3VSB ramp-up, chip reset
(see Soft-Start Circuit), or at the exit from an S4/S5 sleep
state, the MSEL setting is latched in. During active state
(S0/S1/S2) and S3 sleep state, any changes in MSEL status
are ignored.
Application Guidelines
Soft-Start Interval
The 5VSB output of a typical ATX supply is capable of
725mA. During power-up in a sleep state, it needs to provide
sufficient current to charge up all the output capacitors and
simultaneously provide some amount of current to the output
loads. Drawing excessive amounts of current from the 5VSB
output of the ATX can lead to voltage collapse and induce a
pattern of consecutive restarts with unknown effects on the
system’s behavior or health.
The built-in soft-start circuitry allows tight control of the slewup speed of the output voltages controlled by the HIP6502B,
thus enabling power-ups free of supply drop-off events.
Since the outputs are ramped up in a linear fashion, the
current dedicated to charging the output capacitors can be
calculated with the following formula:
I SS
I COUT = ------------------------------ × Σ ( C OUT × V OUT ) , where
C SS × V BG
ISS - soft-start current (typically 10μA)
CSS - soft-start capacitor
VBG - bandgap voltage (typically 1.26V)
Σ(COUT x VOUT) - sum of the products between the
capacitance and the voltage of an output (total charge
delivered to all outputs)
10
Due to the various system timing events, it is recommended
that the soft-start interval not be set to exceed 30ms.
Shutdown
In case of a FAULT condition that might endanger the
computer system, or at any other time, all the HIP6502B
outputs can be shut down by pulling the SS pin below the
specified shutdown level (typically 0.8V) with an open drain
or open collector device capable of sinking a minimum of
2mA. Pulling the SS pin low effectively shuts down all the
pass elements. Upon release of the SS pin, the HIP6502B
undergoes a new soft-start cycle and resumes normal
operation in accordance to the ATX supply and control pins
status.
Layout Considerations
The typical application employing a HIP6502B is a fairly
straight forward implementation. Like with any other linear
regulator, attention has to be paid to the few potentially
sensitive small signal components, such as those connected
to sensitive nodes or those supplying critical by-pass
current.
The power components (pass transistors) and the controller
IC should be placed first. The controller should be placed in
a central position on the motherboard, closer to the memory
load if possible, but not excessively far from the clock chip or
the processor. Insure the VSEN1 and VSEN2 connections
are properly sized to carry 250mA without significant
resistive losses; similar guideline applies to the VCLK
output, which can deliver as much as 800mA (typical). As
the current for the VCLK output is provided from the ATX
3.3V, the connection from the 3V3 pin to the 3.3V plane
should be sized to carry the maximum clock output current
while exhibiting negligible voltage losses. Similarly, the
5VSB pin and the 5V pin are carrying significant levels of
current - for best results, insure these pins are connected to
their respective sources through adequate traces. The pass
transistors should be placed on pads capable of heatsinking
matching the device’s power dissipation. Where applicable,
multiple via connections to a large internal plane can
significantly lower localized device temperature rise.
Placement of the decoupling and bulk capacitors should
follow a placement reflecting their purpose. As such, the
high-frequency decoupling capacitors should be placed as
close as possible to the load they are decoupling; the ones
decoupling the controller close to the controller pins, the
ones decoupling the load close to the load connector or the
load itself (if embedded). Even though bulk capacitance
(aluminum electrolytics or tantalum capacitors) placement is
not as critical as the high-frequency capacitor placement,
having these capacitors close to the load they serve is
preferable.
The only critical small signal component is the soft-start
capacitor, CSS. Locate this component close to SS pin of the
control IC and connect to ground through a via placed close
HIP6502B
to the capacitor’s ground pad. Minimize any leakage current
paths from SS node, since the internal current source is only
10μA.
+12VIN
+5VSB
5VSB
12V
SS
VOUT5
VSEN1
Q2
CHF5
CBULK5
VOUT1
3V3DLSB
VOUT3
3V3DL
VOUT2
VCLK
3V3
VSEN2
GND DRV2
Q1
CBULK4
CBULK2
CHF4
LOAD
CHF2
LOAD
Q6
ΔVOUT - output voltage drop
COUT - output capacitor bank capacitance
+5VIN
5V
Q3
tt ⎞
⎛
ΔV OUT = I OUT × ⎜ ESR OUT + ----------------⎟ , where
C
⎝
OUT⎠
IOUT - output current during transition
Q5
DLA
CBULK3
Also, during the transition between active and sleep states,
there is a short interval of time during which none of the
power pass elements are conducting - during this time the
output capacitors have to supply all the output current. The
output voltage drop during this brief period of time can be
easily approximated with the following formula:
ESROUT - output capacitor bank ESR
HIP6502B
CHF3
LOAD
LOAD
5VDL
CBULK1
LOAD
Q4
5VDLSB
CSS
CHF1
CIN
C5VSB
C12V
the high slew rate (di/dt) current demands. Thus, it is
recommended that the output capacitors be selected for
transient load regulation, paying attention to their parasitic
components (ESR, ESL).
+3.3VIN
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT/POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
tt - active-to-sleep or sleep-to-active transition time (10μs typ.)
The output voltage drop is heavily dependent on the ESR
(equivalent series resistance) of the output capacitor bank,
the choice of capacitors should be such as to maintain the
output voltage above the lowest allowable regulation level.
VCLK (VOUT4) Output Capacitors Selection
The output capacitor for the VCLK linear regulator provides
loop stability. Figure 10 outlines a capacitance vs. equivalent
series resistance envelope. For stable operation and
optimized performance, select a COUT4 capacitor or
combination of capacitors with characteristics within the
shown envelope.
FIGURE 9. PRINTED CIRCUIT BOARD ISLANDS
Component Selection Guidelines
Output Capacitors Selection
The output capacitors for all outputs should be selected to
allow the output voltage to meet the dynamic regulation
requirements of active state operation (S0, S1). The load
transient for the various microprocessor system’s
components may require high quality capacitors to supply
11
10
1
ESR (Ω)
A multi-layer printed circuit board is recommended. Figure 9
shows the connections of most of the components in the
converter. Note that the individual capacitors shown each
could represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
component ground connections through vias placed as close
to the component terminal as possible. Dedicate another
solid layer as a power plane and break this plane into
smaller islands of common voltage levels. Ideally, the power
plane should support both the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers to create power islands connecting the filtering
components (output capacitors) and the loads. Use the
remaining printed circuit layers for small signal wiring.
0.1
0.01
10
100
CAPACITANCE (μF)
1000
FIGURE 10. COUT4 OUTPUT CAPACITOR
Input Capacitors Selection
The input capacitors for an HIP6502B application have to
have a sufficiently low ESR as to not allow the input voltage
to dip excessively when energy is transferred to the output
capacitors. If the ATX supply does not meet the
HIP6502B
specifications, certain imbalances between the ATX’s
outputs and the HIP6502B’s regulation levels could have as
a result a brisk transfer of energy from the input capacitors to
the supplied outputs. At the transition between active and
sleep states, this phenomena could result in the 5VSB
voltage dropping below the POR level (typically 4.1V) and
temporarily disabling the HIP6502B. The solution to a
potential problem such as this is using larger input
capacitors with a lower total combined ESR.
Transistor Selection/Considerations
The HIP6502B usually requires one P-Channel (or bipolar
PNP), three N-Channel MOSFETs and two bipolar NPN
transistors.
One important criteria for selection of transistors for all the
linear regulators/switching elements is package selection for
efficient removal of heat. The power dissipated in a linear
regulator/switching element is:
P LINEAR = I O × ( V IN – V OUT )
Select a package and heatsink that maintains the junction
temperature below the rating with the maximum expected
ambient temperature.
Q1
The active element on the 2.5VMEM output has to be a
bipolar NPN capable of conducting the maximum active
memory current and exhibit a current gain (hfe) of minimum
40 at this current and 0.7V VCE .
Q2
The NPN transistor used as sleep state pass element (Q2)
on the 3.3VDUAL output has to have a minimum current gain
of 100 at 1.5V VCE and 500mA ICE throughout the in-circuit
operating temperature range.
12
Q3, Q4, Q6
The three N-Channel MOSFETs are used to switch the 3.3V
and 5V inputs provided by the ATX supply into the 3.3VMEM ,
3.3VDUAL/3.3VSB , and 5VDUAL outputs, while in active (S0,
S1) state. The main criteria for the selection of these
transistors is output voltage budgeting. The maximum
rDS(ON) allowed at highest junction temperature can be
expressed with the following equation:
V INmin – V OUTmin
r DS ( ON )max = --------------------------------------------------- , where
I OUTmax
VINmin - minimum input voltage
VOUTmin - minimum output voltage allowed
IOUTmax - maximum output current
The gate bias available for these MOSFETs is of the order of
8V.
Q5
If a P-Channel MOSFET is used to switch the 5VSB output
of the ATX supply into the 5VDUAL output during S3 and S5
states (as dictated by EN5VDL status), then the selection
criteria of this device is proper voltage budgeting. The
maximum rDS(ON) , however, has to be achieved with only
4.5V of VGS , so a logic level MOSFET needs to be selected.
If a PNP device is chosen to perform this function, it has to
have a low saturation voltage while providing the maximum
sleep current and have a current gain sufficiently high to be
saturated using the minimum drive current (typically 20mA).
HIP6502B
HIP6502B Application Circuit
Figure 11 shows an application circuit of an ACPIsanctioned power management system for a microprocessor
computer system. The power supply provides the
3.3VDUAL/3.3VSB voltage (VOUT3), the SDRAM 3.3VMEM
voltage (VOUT1), the RDRAM 2.5VMEM memory voltage
(VOUT2), the 2.5VCLK clock voltage (VOUT4), and the
5VDUAL voltage (VOUT5) from +3.3V, +5VSB, +5V, and
+12VDC ATX supply outputs. Q4 can also be a PNP, such
as an MMBT2907AL. For detailed information on the circuit,
including a Bill-of-Materials and circuit board description, see
Application Note AN9862.
Also see Intersil Corporation’s web page (www.intersil.com).
+5VIN
+12VIN
+3.3VIN
+5VSB
+
C1
1μF
VOUT1
C3
1μF
Q6
HUF76113SK8
3.3VMEM
3.3VDUAL/3.3VSB
3V3
+
C17
1μF
C4
1μF
5VSB
DRV2
5V
VSEN1
U1
3V3DL
+
C9
1μF
VOUT2
C6,7 +
2X150μF
3V3DLSB
Q3
1/2 HUF76113DK8
Q1
2SD1802
VSEN2
C5,16
2X150μF
Q2
2SD1802
VOUT3
12V
C2
220μF
2.5VMEM
C8
1μF
VOUT4
VCLK
HIP6502B
2.5VCLK
C11 +
150μF
C12
1μF
C10
220μF
Q4
FDV304P
5VDLSB
FAULT
EN5VDL
CONFIGURATION
HARDWARE
DLA
Q5
1/2 HUF76113DK8
MSEL
S3
SLP_S3
SLP_S5
VOUT5
5VDL
S5
+
SS
C13
0.1μF
GND
SHUTDOWN
(FROM OPEN-DRAIN N-MOS)
FIGURE 11. TYPICAL HIP6502B APPLICATION DIAGRAM
13
C14
150μF
C15
1μF
5VDUAL
HIP6502B
Small Outline Plastic Packages (SOIC)
M20.3 (JEDEC MS-013-AC ISSUE C)
N
INDEX
AREA
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
0.25(0.010) M
H
B M
INCHES
E
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.4961
0.5118
12.60
13.00
3
E
0.2914
0.2992
7.40
7.60
4
e
µα
B S
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
20
0o
20
8o
0o
7
8o
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
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14
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