DATASHEET

HIP6019
TM
Data Sheet
April 1998
Advanced Dual PWM and Dual Linear
Power Control
Features
The HIP6019 provides the power control and protection for four
output voltages in high-performance microprocessor and
computer applications. The IC integrates two PWM controllers,
a linear regulator and a linear controller as well as the
monitoring and protection functions into a single 28 lead SOIC
package. One PWM controller regulates the microprocessor
core voltage with a synchronous-rectified buck converter, while
the second PWM controller supplies the computer’s 3.3V
power with a standard buck converter. The linear controller
regulates power for the GTL bus and the linear regulator
provides power for the clock driver circuits.
The HIP6019 includes an Intel-compatible, TTL 5-input digitalto-analog converter (DAC) that adjusts the core PWM output
voltage from 2.1VDC to 3.5VDC in 0.1V increments and from
1.8VDC to 2.05VDC in 0.05V steps. The precision reference
and voltage-mode control provide ±1% static regulation. The
second PWM controller is user-adjustable for output levels
between 3.0V and 3.5V with ±2% accuracy. The adjustable
linear regulator uses an internal pass device to provide 2.5V
±2.5%. The adjustable linear controller drives an external NChannel MOSFET to provide 1.5V ±2.5%.
The HIP6019 monitors all the output voltages. A single Power
Good signal is issued when the core is within ±10% of the DAC
setting and the other levels are above their under- voltage
levels. Additional built-in over-voltage protection for the core
output uses the lower MOSFET to prevent output voltages
above 115% of the DAC setting. The PWM controller’s overcurrent functions monitor the output current by sensing the
voltage drop across the upper MOSFET’s rDS(ON), eliminating
the need for a current sensing resistor.
Pinout
HIP6019 (SOIC)
TOP VIEW
FN4490.2
• Provides 4 Regulated Voltages
- Microprocessor Core, I/O, Clock Chip and GTL Bus
• Drives N-Channel MOSFETs
• Operates from +5V and +12V Inputs
• Simple Single-Loop Control Designs
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifiers
- Full 0% to 100% Duty Ratios
• Excellent Output Voltage Regulation
- Core PWM Output: ±1% Over Temperature
- I/O PWM Output: ±2% Over Temperature
- Other Outputs: ±2.5% Over Temperature
• TTL-Compatible 5-Bit Digital-to-Analog Core Output
Voltage Selection
- Wide Range . . . . . . . . . . . . . . . . . . . 1.8VDC to 3.5VDC
- 0.1V Steps . . . . . . . . . . . . . . . . . . . . 2.1VDC to 3.5VDC
- 0.05V Steps . . . . . . . . . . . . . . . . . . 1.8VDC to 2.05VDC
• Power-Good Output Voltage Monitor
• Microprocessor Core Voltage Protection Against Shorted
MOSFET
• Over-Voltage and Over-Current Fault Monitors
- Does Not Require Extra Current Sensing Element,
Uses MOSFET’s rDS(ON)
• Small Converter Size
- Constant Frequency Operation
- 200kHz Free-Running Oscillator; Programmable from
50kHz to 1MHz
UGATE2 1
28 VCC
Applications
PHASE2 2
27 UGATE1
• Full Motherboard Power Regulation for Computers
VID4 3
26 PHASE1
• Low-Voltage Distributed Power Supplies
VID3 4
25 LGATE1
VID2 5
24 PGND
VID1 6
23 OCSET1
VID0 7
22 VSEN1
PGOOD 8
21 FB1
OCSET2 9
20 COMP1
Ordering Information
PART NUMBER
HIP6019CB
HIP6019EVAL1
TEMP. (oC)
0 to 70
PACKAGE
28 Ld SOIC
PKG. NO.
M28.3
Evaluation Board
19 FB3
FB2 10
18 GATE3
COMP2 11
SS 12
17 GND
FAULT/RT 13
16 VOUT4
FB4 14
15 VSEN2
252
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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VSEN2
FB2
COMP2
PHASE2
GATE2
FB4
VOUT4
GATE3
FB3
2.5V
VCC
0.25A
VSEN2
+
-
+
-
+
-
+
4.3V
+
-
-
+
0.3V
-
INHIBIT
+
+
-
PWM
COMP2
PWM2
1.26V
1.26V
GATE
CONTROL
DRIVE2
-
+
+
-
-
+
-
+
-
+
ERROR
AMP2
-
253
+
+
FAULT / RT
LUV
4V
11µA
FIGURE 1.
SS
VCC
OV
SOFTSTART
AND FAULT
LOGIC
OC
FAULT
200µA
OSCILLATOR
OC2
OC4
LINEAR
UNDERVOLTAGE
OCSET2
DACOUT
-
+
-
+
-
+
-
+
OC1
COMP1
ERROR
AMP1
FB1
115%
90%
110%
VSEN1
PWM1
DRIVE1
RESET (POR)
POWER-ON
VCC
VID4
VID0
VID2
VID1
VID3
LOWER
DRIVE
GATE
CONTROL
INHIBIT
TTL D/A
CONVERTER
(DAC)
PWM
COMP1
-
+
-
+
200µA
OCSET1
VCC
VCC
GND
PGND
LGATE1
PHASE1
UGATE1
PGOOD
HIP6019
Block Diagram
HIP6019
Simplified Power System Diagram
+5VIN
PWM2
CONTROLLER
VOUT2
VOUT1
PWM1
CONTROLLER
HIP6019
LINEAR
CONTROLLER
VOUT3
LINEAR
REGULATOR
VOUT4
FIGURE 2.
Typical Application
+12VIN
+5VIN
CIN
VCC
OCSET2
OCSET1
POWERGOOD
PGOOD
VOUT2
Q3
LOUT2
3.0V TO 3.5V
COUT2
UGATE2
UGATE1
PHASE2
PHASE1
Q1
LGATE1
CR2
Q2
CR1
PGND
VSEN2
FB2
VSEN1
HIP6019
COMP2
FB1
COMP1
FAULT / RT
VOUT3
1.5V
Q4
VID0
GATE3
VID1
FB3
VID2
VID3
COUT3
VID4
VOUT4
2.5V
SS
VOUT4
CSS
FB4
COUT4
GND
FIGURE 3.
254
LOUT1
COUT1
VOUT1
1.8V TO 3.5V
HIP6019
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V
PGOOD, RT/FAULT, and GATE Voltage . . GND - 0.3V to VCC + 0.3V
Input, Output or I/O Voltage . . . . . . . . . . . . . . . . . . GND -0.3V to 7V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Resistance (Typical, Note 1)
Operating Conditions
Supply Voltage, V CC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 125oC
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
50
SOIC Package (with 3 in2 of copper) . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted.
Refer to Figures 1, 2 and 3
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
10
-
mA
VCC SUPPLY CURRENT
Nominal Supply
ICC
UGATE1, GATE2, GATE3, LGATE1, and
VOUT4 Open
POWER-ON RESET
Rising VCC Threshold
VOCSET = 4.5V
8.6
-
10.4
V
Falling VCC Threshold
VOCSET = 4.5V
8.2
-
10.2
V
-
1.25
-
V
Rising VOCSET1 Threshold
OSCILLATOR
Free Running Frequency
RT = OPEN
185
200
215
kHz
Total Variation
6kΩ < RT to GND < 200kΩ
-15
-
+15
%
-
1.9
-
V P-P
DAC(VID0-VID4) Input Low Voltage
-
-
0.8
V
DAC(VID0-VID4) Input High Voltage
2.0
-
-
V
DACOUT Voltage Accuracy
-1.0
-
+1.0
%
1.240
1.265
1.290
V
-2.5
-
2.5
%
-
75
87
%
-
6
-
%
180
230
-
mA
CSS Voltage < 4V
560
700
-
mA
VSEN3 = GATE3
-2.5
-
2.5
%
-
75
87
%
-
6
-
%
∆VOSC
Ramp Amplitude
RT = Open
REFERENCE AND DAC
Reference Voltage
(Pin FB2, FB3, and FB4)
LINEAR REGULATOR
Regulation
10mA < IVOUT4 < 150mA
Under-Voltage Level
FB4UV
FB4 Rising
Under-Voltage Hysteresis
Over-Current Protection
Over-Current Protection During Start-Up
LINEAR CONTROLLER
Regulation
Under-Voltage Level
FB3UV
Under-Voltage Hysteresis
255
FB3 Rising
HIP6019
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted.
Refer to Figures 1, 2 and 3 (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
88
-
dB
-
15
-
MHz
COMP = 10pF
-
6
-
V/µs
PWM CONTROLLER ERROR AMPLIFIERS
DC Gain
Gain-Bandwidth Product
GBWP
Slew Rate
SR
PWM CONTROLLER GATE DRIVERS
Drive1 (and 2) Source
IUGATE
VCC = 12V, VUGATE1 (or VGATE2) = 6V
-
1
-
A
Drive1 (and 2) Sink
RUGATE
VGATE-PHASE = 1V
-
1.7
3.5
Ω
Lower Gate Source
ILGATE
VCC = 12V, VLGATE = 1V
-
1
-
A
Lower Gate Sink
RLGATE
VGATE = 1V
-
1.4
3.0
Ω
PROTECTION
V OUT1 Over-Voltage Trip
VSEN1 Rising
112
115
118
%
VOUT2 Over-Voltage Trip
VSEN2 Rising
4.1
4.3
4.5
V
-
70
-
kΩ
VSEN2 Input Resistance
FAULT Sourcing Current
OCSET1(and 2) Current Source
IOVP
VFAULT/RT = 10.0V
10
14
-
mA
IOCSET
VOCSET = 4.5VDC
170
200
230
µA
-
11
-
µA
-
-
1.0
V
Soft-Start Current
ISS
Chip Shutdown Soft-Start Threshold
POWER GOOD
VOUT1 Upper Threshold
VSEN1 Rising
108
-
110
%
VOUT1 Under-Voltage
VSEN1 Rising
92
-
94
%
VOUT1 Hysteresis
Upper/Lower Threshold
-
2
-
%
VOUT2 Under-Voltage
VSEN2 Rising
2.45
2.55
2.65
V
-
100
-
mV
-
-
0.5
V
VOUT2 Under-Voltage Hysteresis
PGOOD Voltage Low
V PGOOD
IPGOOD = -4mA
Typical Performance Curves
140
120
RT PULLUP
TO +12V
CGATE = 4800pF
100
ICC (mA)
RESISTANCE (kΩ)
1000
CUGATE1 = CUGATE2 = CLGATE1 = CGATE
VVCC = 12V,VIN = 5V
100
80
CGATE = 3600pF
60
CGATE = 1500pF
40
10
CGATE = 660pF
RT PULLDOWN TO VSS
10
100
SWITCHING FREQUENCY (kHz)
FIGURE 4. RT RESISTANCE vs FREQUENCY
256
20
1000
100
200
300
400
500
600
700
800
900
SWITCHING FREQUENCY (kHz)
FIGURE 5. BIAS SUPPLY CURRENT vs FREQUENCY
1000
HIP6019
Functional Pin Description
VSEN1, VSEN2 (Pins 22 and 15)
These pins are connected to the PWM converters’ output
voltages. The PGOOD and OVP comparator circuits use
these signals to report output voltage status and for overvoltage protection. VSEN2 provides the input power to the
integrated linear regulator.
The PGOOD output is open for VID codes that inhibit
operation. See Table 1.
PHASE1, PHASE2 (Pins 26 and 2)
Connect the PHASE pins to the respective PWM
converter’s upper MOSFET source. These pins are used to
monitor the voltage drop across the upper MOSFETs for
over-current protection.
OCSET1, OCSET2 (Pins 23 and 9)
UGATE1, UGATE2 (Pins 27 and 1)
Connect a resistor (ROCSET) from this pin to the drain of the
respective upper MOSFET. ROCSET, an internal 200µA
current source (IOCSET), and the upper MOSFET onresistance (rDS(ON)) set the converter over-current (OC) trip
point according to the following equation:
Connect UGATE pins to the respective PWM converter’s
upper MOSFET gate. These pins provide the gate drive for
the upper MOSFETs.
I OCSET × R OCSET
I PEAK = ---------------------------------------------------r D S ( ON )
PGND (Pin 24)
This is the power ground connection. Tie the synchronous
PWM converter’s lower MOSFET source to this pin.
LGATE1 (Pin 25)
An over-current trip cycles the soft-start function. Sustaining an
over-current for 2 soft-start intervals shuts down the controller.
Additionally, OCSET1 is an output for the inverted FAULT
signal (FAULT). If a fault condition causes FAULT to go high,
OCSET1 will be simultaneously pulled to ground though an
internal MOS device (typical rDS(ON) = 100Ω).
SS (Pin 12)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 11µA current source, sets the softstart interval of the converter.
Pulling this pin low (typically below 1.0V) with an open drain
signal will shutdown the IC.
VID0, VID1, VID2, VID3, VID4 (Pins 7, 6, 5, 4 and 3)
VID0-4 are the input pins to the 5-bit DAC. The states of these
five pins program the internal voltage reference (DACOUT).
The level of DACOUT sets the core converter output voltage
(VOUT1). It also sets the core PGOOD and OVP thresholds.
COMP1, COMP2, and FB1, FB2
(Pins 20, 11, 21, and 10)
Connect LGATE1 to the synchronous PWM converter’s lower
MOSFET gate. This pin provides the gate drive for the lower
MOSFET.
VCC (Pin 28)
Provide a 12V bias supply for the IC to this pin. This pin also
provides the gate bias charge for all the MOSFETs
controlled by the IC.
FAULT/RT (Pin 13)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (RT) from this pin to GND, the nominal
200kHz switching frequency is increased according to the
following equation:
6
5 × 10
Fs ≈ 200kHz + --------------------R T ( kΩ )
(RT to GND)
Conversely, connecting a pull-up resistor (RT) from this pin
to VCC reduces the switching frequency according to the
following equation:
7
4 × 10
Fs ≈ 200kHz – --------------------R T ( kΩ )
COMP1, 2 and FB1, 2 are the available external pins of the
PWM error amplifiers. Both the FB pins are the inverting
input of the error amplifiers. Similarly, the COMP pins are the
error amplifier outputs. These pins are used to compensate
the voltage-control feedback loops of the PWM converters.
Nominally, this pin voltage is 1.26V, but is pulled to VCC in
the event of an over-voltage or over-current condition.
GND (Pin 17)
GATE3 (Pin 18)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
Connect this pin to the gate of an external MOSFET. This
pin provides the drive for the linear controller’s pass
transistor.
PGOOD (Pin 8)
PGOOD is an open collector output used to indicate the
status of the PWM converter output voltages. This pin is
pulled low when the core output is not within ±10% of the
DACOUT reference voltage, or when any of the other
outputs are below their under-voltage thresholds.
257
(R T to 12V)
FB3 (Pin 19)
Connect this pin to a resistor divider to set the linear
controller output.
VOUT4 (Pin 16)
HIP6019
Output of the linear regulator. Supplies current up to 230mA.
FB4 (Pin 14)
Connect this pin to a resistor divider to set the linear
regulator output.
Description
Operation
The HIP6019 monitors and precisely controls 4 output
voltage levels (Refer to Figures 1, 2, and 3). It is designed
for microprocessor computer applications with 5V power and
12V bias input from a PS2 or ATX power supply. The IC has
2 PWM controllers, a linear controller, and a linear regulator.
The first PWM controller (PWM1) is designed to regulate the
microprocessor core voltage (VOUT1). PWM1 controller
drives 2 MOSFETs (Q1 and Q2) in a synchronous-rectified
buck converter configuration and regulates the core voltage
to a level programmed by the 5-bit digital-to-analog
converter (DAC). The second PWM controller (PWM2) is
designed to regulate the I/O voltage (VOUT2). PWM2
controller drives a MOSFET (Q3) in a standard buck
converter configuration and regulates the I/O voltage to a
resistor programmable level between 3.0 and 3.5VDC. An
integrated linear regulator supplies the 2.5V clock generator
power (VOUT4). The linear controller drives an external
MOSFET (Q4) to supply the GTL bus power (VOUT3).
Figure 6 shows the soft-start sequence for the typical
application. At T0 the SS voltage rapidly increases to
approximately 1V. At T1, the SS pin and error amplifier output
voltage reach the valley of the oscillator’s triangle wave. The
oscillator’s triangular waveform is compared to the clamped
error amplifier output voltage. As the SS pin voltage
increases, the pulse-width on the PHASE pin increases. The
interval of increasing pulse-width continues until each output
reaches sufficient voltage to transfer control to the input
reference clamp. If we consider the 3.3V output (VOUT2) in
Figure 6, this time occurs at T2. During the interval between
T2 and T3, the error amplifier reference ramps to the final
value and the converter regulates the output to a voltage
proportional to the SS pin voltage. At T3 the input clamp
voltage exceeds the reference voltage and the output voltage
is in regulation.
PGOOD
(2V/DIV)
0V
SOFT-START
(1V/DIV)
VOUT2 (= 3.3V)
0V
Initialization
The HIP6019 automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input supply voltages. The POR monitors the
bias voltage (+12VIN) at the VCC pin and the 5V input voltage
(+5VIN) at the OCSET1 pin. The normal level on OCSET1 is
equal to +5VIN less a fixed voltage drop (see over-current
protection). The POR function initiates soft-start operation
after both input supply voltages exceed their POR thresholds.
VOUT4 (= 2.5V)
VOUT1 (DAC = 2V)
OUTPUT
VOLTAGES
(0.5V/DIV)
VOUT3 ( = 1.5V)
0V
Soft-Start
The POR function initiates the soft-start sequence. Initially,
the voltage on the SS pin rapidly increases to approximately
1V (this minimizes the soft-start interval). Then an internal
11µA current source charges an external capacitor (CSS) on
the SS pin to 4V. The PWM error amplifier reference inputs
(+ terminal) and outputs (COMP1 and COMP2 pins) are
clamped to a level proportional to the SS pin voltage. As the
SS pin voltage ramps from 1V to 4V, the output clamp allows
generation of PHASE pulses of increasing width that charge
the output capacitor(s). After this initial stage, the reference
input clamp slows the output voltage rate-of-rise and
provides a smooth transition to the final set voltage.
Additionally, both linear regulator’s reference inputs are
clamped to a voltage proportional to the SS pin voltage. This
method provides a rapid and controlled output voltage rise.
258
T0 T1
T2
T3
TIME
FIGURE 6. SOFT-START INTERVAL
The remaining outputs are also programmed to follow the
SS pin voltage. Each linear output (VOUT3 and VOUT4)
initially follows the 3.3V output (VOUT2). When each output
reaches sufficient voltage the input reference clamp slows
the rate of output voltage rise. The PGOOD signal toggles
‘high’ when all output voltage levels have exceeded their
under-voltage levels. See the Soft-Start Interval section
under Applications Guidelines for a procedure to determine
the soft-start interval.
Fault Protection
All four outputs are monitored and protected against extreme
overload. A sustained overload on any linear regulator
HIP6019
output or an over-voltage on the PWM outputs disables all
converters and drives the FAULT/RT pin to VCC.
Figure 7 shows a simplified schematic of the fault logic. An
over-voltage detected on either VSEN1 or VSEN2
immediately sets the fault latch. A sequence of three overcurrent fault signals also sets the fault latch. A comparator
indicates when CSS is fully charged (UP signal), such that an
under-voltage event on either linear output (FB3 or FB4) is
ignored until after the soft-start interval (approximately T3 in
Figure 6). At start-up, this allows VOUT3 and VOUT4 to slew
up over increased time intervals, without generating a fault.
Cycling the bias input voltage (+12VIN on the VCC pin) off
then on resets the counter and the fault latch.
LUV
OVER
CURRENT
LATCH
OC1
INHIBIT
Figures 8 and 9 illustrate the over-current protection with an
overload on OUT2. The overload is applied at T0 and the
current increases through the output inductor (LOUT2). At time
T1, the OVER-CURRENT2 comparator trips when the voltage
across Q3 (ID • rDS(ON)) exceeds the level programmed by
ROCSET. This inhibits all outputs, discharges the soft-start
capacitor (CSS) with a 11µA current sink, and increments the
counter. CSS recharges at T2 and initiates a soft-start cycle
with the error amplifiers clamped by soft-start. With OUT2 still
overloaded, the inductor current increases to trip the overcurrent comparator. Again, this inhibits all outputs, but the
soft-start voltage continues increasing to 4V before
discharging. The counter increments to 2. The soft-start cycle
repeats at T3 and trips the over-current comparator. The SS
pin voltage increases to 4V at T4 and the counter increments to
3. This sets the fault latch to disable the converter. The fault is
reported on the FAULT/RT pin.
S
R
0.15V
SS
+
+
4V
COUNTER
-
-
R
FAULT
LATCH
VCC
S Q
UP
POR
R
FAULT
OV
FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC
Over-Voltage Protection
During operation, a short on the upper MOSFET (Q1)
causes VOUT1 to increase. When the output exceeds the
over-voltage threshold of 115% of DACOUT, the overvoltage comparator trips to set the fault latch and turns Q2
on as required in order to regulate VOUT1 to 1.15 x
DACOUT. This blows the input fuse and reduces VOUT1.
The fault latch raises the FAULT/RT pin close to VCC
potential.
A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), V OUT1 is
monitored for voltages exceeding 1.26V. Should VSEN1
exceed this level, the lower MOSFET (Q2) is driven on, as
needed to regulate V OUT1 to 1.26V.
Over-Current Protection
All outputs are protected against excessive over-currents.
Both PWM controllers use the upper MOSFET’s
on-resistance, rDS(ON) to monitor the current for protection
against shorted outputs. The linear regulator monitors the
current of the integrated power device and signals an overcurrent condition for currents in excess of 230mA.
Additionally, both the linear regulator and the linear
controller monitor FB3 and FB4 for under-voltage to protect
against excessive currents.
259
INDUCTOR CURRENT SOFT-START
OC2
FAULT/RT
S Q
FAULT
REPORTED
10V
0V
COUNT
=1
COUNT
=2
COUNT
=3
4V
2V
0V
OVERLOAD
APPLIED
0A
T0 T1
T2
T3
T4
TIME
FIGURE 8. OVER-CURRENT OPERATION
The PWM1 controller and the linear regulator operate in the
same way as PWM2 to over-current faults. Additionally, the
linear regulator and linear controller monitor the feedback
pins for an under-voltage. Should excessive currents cause
FB3 or FB4 to fall below the linear under-voltage threshold,
the LUV signal sets the over-current latch if CSS is fully
charged. Blanking the LUV signal during the CSS charge
interval allows the linear outputs to build above the undervoltage threshold during normal start-up. Cycling the bias
input power off then on resets the counter and the fault latch.
HIP6019
OVER-CURRENT TRIP: VDS > VSET
VIN = +5V
(I D • rDS(ON) > I OCSET • ROCSET )
OCSET
IOCSET
200µA
ROCSET
VSET +
ID
VCC
DRIVE
OC2
+
UGATE
+
VDS
PHASE
-
OVERCURRENT2
PWM
VPHASE = VIN - VDS
VOCSET = VIN - VSET
GATE
CONTROL
HIP6019
FIGURE 9. OVER-CURRENT DETECTION
Resistors (ROCSET1 and ROCSET2) program the overcurrent trip levels for each PWM converter. As shown in
Figure 9, the internal 200µA current sink develops a voltage
across ROCSET (VSET) that is referenced to VIN. The DRIVE
signal enables the over-current comparator (OVERCURRENT1 or OVER-CURRENT2). When the voltage
across the upper MOSFET (VDS) exceeds VSET, the overcurrent comparator trips to set the over-current latch. Both
VSET and VDS are referenced to VIN and a small capacitor
across ROCSET helps VOCSET track the variations of V IN due
to MOSFET switching. The over-current function will trip at a
peak inductor current (IPEAK) determined by:
sudden change in the resulting reference voltage could toggle
the PGOOD signal and exercise the over-voltage protection. All
VID pin combinations resulting in an INHIBIT disable the IC and
the open-collector at the PGOOD pin.
Application Guidelines
Soft-Start Interval
Initially, the soft-start function clamps the error amplifiers’
output of the PWM converters. After the output voltage
increases to approximately 80% of the set value, the
reference input of the error amplifier is clamped to a voltage
proportional to the SS pin voltage. The resulting output
voltage sequence is shown in Figure 6.
The soft-start function controls the output voltage rate of rise
to limit the current surge at start-up. The soft-start interval is
programmed by the soft-start capacitor, CSS. Programming
a faster soft-start interval increases the peak surge current.
The peak surge current occurs during the initial output
voltage rise to 80% of the set value.
Shutdown
Neither PWM output switches until the soft-start voltage
(VSS) exceeds the oscillator’s valley voltage. Additionally,
the reference on each linear’s amplifier is clamped to the
soft-start voltage. Holding the SS pin low (with an open drain
or collector signal) turns off all four regulators.
The VID codes resulting in an INHIBIT as shown in Table 1
also shut down the IC.
I OCSET × R OCSET
IPEAK = ---------------------------------------------------r DS ( ON )
TABLE 1. VOUT1 VOLTAGE PROGRAM
PIN NAME
The OC trip point varies with MOSFET’s temperature. To avoid
over-current tripping in the normal operating load range,
determine the ROCSET resistor from the equation above with:
1. The maximum rDS(ON) at the highest junction temperature.
2. The minimum IOCSET from the specification table.
3. Determine IPEAK for IPEAK > IOUT(MAX) + (∆I)/2,
where ∆I is the output inductor ripple current.
For an equation for the output inductor ripple current see
the section under component guidelines titled ‘Output
Inductor Selection’.
OUT1 Voltage Program
The output voltage of the PWM1 converter is programmed to
discrete levels between 1.8VDC and 3.5VDC . This output is
designed to supply the microprocessor core voltage. The
voltage identification (VID) pins program an internal voltage
reference (DACOUT) through a TTL-compatible 5-bit digital-toanalog converter. The level of DACOUT also sets the PGOOD
and OVP thresholds. Table 1 specifies the DACOUT voltage for
the different combinations of connections on the VID pins. The
VID pins can be left open for a logic 1 input, because they are
internally pulled up to +5V by a 10µA current source. Changing
the VID inputs during operation is not recommended. The
260
VID4
VID3
VID2
VID1
VID0
NOMINAL
OUT1
VOLTAGE
DACOUT
0
1
X
X
X
INHIBIT
0
0
1
1
X
INHIBIT
0
0
1
0
1
1.80
0
0
1
0
0
1.85
0
0
0
1
1
1.90
0
0
0
1
0
1.95
0
0
0
0
1
2.00
0
0
0
0
0
2.05
1
1
1
1
1
INHIBIT
1
1
1
1
0
2.1
1
1
1
0
1
2.2
1
1
1
0
0
2.3
1
1
0
1
1
2.4
1
1
0
1
0
2.5
1
1
0
0
1
2.6
HIP6019
TABLE 1. VOUT1 VOLTAGE PROGRAM (Continued)
PIN NAME
VID4
VID3
VID2
VID1
VID0
NOMINAL
OUT1
VOLTAGE
DACOUT
1
1
0
0
0
2.7
1
0
1
1
1
2.8
1
0
1
1
0
2.9
1
0
1
0
1
3.0
1
0
1
0
0
3.1
1
0
0
1
1
3.2
1
0
0
1
0
3.3
1
0
0
0
1
3.4
1
0
0
0
0
3.5
NOTE: 0 = connected to GND or V SS, 1 = open or connected to 5V
through pull-up resistors, X = don’t care.
these components close to their connecting pins on the
control IC. Minimize any leakage current paths from SS
node because the internal current source is only 11µA.
A multi-layer printed circuit board is recommended. Figure
10 shows the connections of the critical components in the
converter. Note that capacitors CIN and COUT could each
represent numerous physical capacitors. Dedicate one solid
layer for a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another
solid layer as a power plane and break this plane into
smaller islands of common voltage levels. The power plane
should support the input power and output power nodes.
Use copper filled polygons on the top and bottom circuit
layers for the phase nodes. Use the remaining printed circuit
layers for small signal wiring. The wiring traces from the
control IC to the MOSFET gate and source should be sized
to carry 1A currents. The traces for OUT4 need only be
sized for 0.2A. Locate C OUT4 close to the HIP6019 IC.
+5VIN
There are two sets of critical components in a DC-DC
converter using a HIP6019 controller. The power
components are the most critical because they switch large
amounts of energy. The critical small signal components
connect to sensitive nodes or supply critical bypassing
current.
The power components should be placed first. Locate the
input capacitors close to the power switches. Minimize the
length of the connections between the input capacitors and
the power switches. Locate the output inductor and output
capacitors between the MOSFETs and the load. Locate the
PWM controller close to the MOSFETs.
The critical small signal components include the bypass
capacitor for VCC and the soft-start capacitor, CSS. Locate
261
+12V
CIN
COCSET2
ROCSET2
Q3
LOUT2
VOUT2
CVCC
COCSET1
VCC GND
OCSET2
OCSET1
R
UGATE2
PHASE2
OCSET1
Q1
UGATE1
LOUT1
VOUT1
COUT2
Q4
VOUT3
HIP6019
LGATE1
GATE3
SS
Q2
COUT1
CR1
LOAD
PHASE1
PGND
CSS
LOAD
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device over-voltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turnoff
transition of the upper MOSFET. Prior to turnoff, the upper
MOSFET was carrying the full load current. During the
turnoff, current stops flowing in the upper MOSFET and is
picked up by the lower MOSFET or Schottky diode. Any
inductance in the switched current path generates a large
voltage spike during the switching interval. Careful
component selection, tight layout of the critical components,
and short, wide circuit traces minimize the magnitude of
voltage spikes. Contact Intersil for evaluation board
drawings of the component placement and printed circuit
board.
LOAD
Layout Considerations
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 10. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
PWM Controller Feedback Compensation
Both PWM controllers use voltage-mode control for output
regulation. This section highlights the design consideration
for a voltage-mode controller. Apply the methods and
considerations to both PWM controllers.
Figure 11 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage is
regulated to the reference voltage level. The reference
voltage level is the DAC output voltage for PWM1 and is
1.265V for PWM2. The error amplifier output (V E/A) is
compared with the oscillator (OSC) triangular wave to
provide a pulse-width modulated wave with an amplitude of
VIN at the PHASE node. The PWM wave is smoothed by the
output filter (LO and C O).
HIP6019
6. Check Gain against Error Amplifier’s Open-Loop Gain.
VIN
OSC
∆ VOSC
7. Estimate Phase Margin - repeat if necessary.
DRIVER
PWM
COMP
LO
-
DRIVER
+
PHASE
VOUT
CO
ESR
(PARASITIC)
ZFB
VE/A
-
ERROR
AMP
ZIN
+
REFERENCE
DETAILED FEEDBACK COMPENSATION
ZFB
C2
C1
VOUT
ZIN
C3
R2
R1
COMP
-
FB
+
HIP6019
R3
Compensation Break Frequency Equations
1
F P1 = ------------------------------------------------------C1 × C2
2π × R 2 ×  ----------------------
 C1 + C2
1
F P2 = ----------------------------------2π × R 3 × C3
1
F Z1 = ----------------------------------2π × R 2 × C1
1
F Z2 = ------------------------------------------------------2π × ( R1 + R3 ) × C3
Figure 12 shows an asymptotic plot of the DC-DC
converter’s gain vs frequency. The actual modulator gain
has a peak due to the high Q factor of the output filter at FLC,
which is not shown in Figure 12. Using the above guidelines
should yield a compensation gain similar to the curve
plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at FP2
with the capabilities of the error amplifier. The closed loop
gain is constructed on the log-log graph of Figure 12 by
adding the modulator gain (in dB) to the compensation gain
(in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.
REFERENCE
100
FZ1 FZ2
FP1
FP2
80
FIGURE 11. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN
Modulator Break Frequency Equations
1
F LC = ---------------------------------------2π × L O × C O
1
FESR = ----------------------------------------2π × ESR × CO
GAIN (dB)
The modulator transfer function is the small-signal transfer
function of VOUT/ VE/A. This function is dominated by a DC
gain and the output filter, with a double pole break frequency
at FLC and a zero at FESR. The DC gain of the modulator is
simply the input voltage, VIN , divided by the peak-to-peak
oscillator voltage, ∆VOSC .
OPEN LOOP
ERROR AMP GAIN
60
40
20
20LOG
(R2/R 1)
0
20LOG
(VIN/∆VOSC )
MODULATOR
GAIN
-20
-40
-60
COMPENSATION
GAIN
FLC
10
100
1K
CLOSED LOOP
GAIN
FESR
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 12. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation network consists of the error amplifier
internal to the HIP6019 and the impedance networks ZIN
and ZFB . The goal of the compensation network is to provide
a closed loop transfer function with an acceptable 0dB
crossing frequency (f0dB) and adequate phase margin.
Phase margin is the difference between the closed loop
phase at f0dB and 180 degrees. The equations below relate
the compensation network’s poles, zeros and gain to the
components (R1, R2, R3, C1, C2, and C3) in Figure 11.
Use these guidelines for locating the poles and zeros of the
compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth.
2. Place 1ST Zero below filter’s Double Pole (~75% FLC).
3. Place 2ND Zero at filter’s Double Pole.
4. Place 1ST Pole at the ESR Zero.
5. Place 2ND Pole at half the switching frequency.
262
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth loop. A
stable control loop has a 0dB gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Oscillator Synchronization
The PWM controllers use a triangle wave for comparison with
the error amplifier output to provide a pulse-width modulated
wave. Should the output voltages of the two PWM converters
be programmed close to each other, then cross-talk could
cause nonuniform PHASE pulse-widths and increased output
voltage ripple. The HIP6019 avoids this problem by
synchronizing the two converters 180° out-of-phase for DAC
HIP6019
settings above, and including 2.5V. This is accomplished by
inverting the triangle wave sent to PWM 2.
Capacitor, COUT3 should be selected for transient load
regulation.
Component Selection Guidelines
The output capacitor for the linear regulator provides loop
stability. The linear regulator (OUT4) requires an output
capacitor characteristic shown in Figure 13 The upper line
plots the 45 phase margin with 150mA load and the lower
line is the 45 phase margin limit with a 10mA load. Select a
COUT4 capacitor with characteristic between the two limits.
The output capacitors for each output have unique
requirements. In general the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converters require an output
capacitor to filter the current ripple. The linear regulator is
internally compensated and requires an output capacitor that
meets the stability requirements. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.
PWM Output Capacitors
Modern microprocessors produce transient load rates above
10A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and ESL (effective
series inductance) parameters rather than actual capacitance.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple voltage and
the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the equivalent series inductance of these capacitors
increases with case size and can reduce the usefulness of the
capacitor to high slew-rate transient loading. Unfortunately,
ESL is not a specified parameter. Work with your capacitor
supplier and measure the capacitor’s impedance with
frequency to select suitable components. In most cases,
multiple electrolytic capacitors of small case size perform
better than a single large case capacitor. For a given transient
load magnitude, the output voltage transient response due to
the output capacitor characteristics can be approximated by
the following equation:
dITRAN
V TRAN = ESL × --------------------- + ESR × ITR AN
dt
Linear Output Capacitors
The output capacitors for the linear regulator and the linear
controller provide dynamic load current. The linear controller
uses dominant pole compensation integrated in the error
amplifier and is insensitive to output capacitor selection.
263
0.7
0.6
0.5
ESR (Ω)
Output Capacitor Selection
0.4
LE N
AB IO
ST RAT
E
OP
0.3
0.2
0.1
10
100
CAPACITANCE (µF)
1000
FIGURE 13. COUT4 OUTPUT CAPACITOR
Output Inductor Selection
Each PWM converter requires an output inductor. The
output inductor is selected to meet the output voltage ripple
requirements and sets the converter’s response time to a
load transient. The inductor value determines the converter’s
ripple current and the ripple voltage is a function of the ripple
current. The ripple voltage and current are approximated by
the following equations:
V IN – VOUT V OUT
∆I = -------------------------------- × ---------------VIN
FS × LO
∆V OU T = ∆I × ESR
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6019 will provide either 0% or 100% duty cycle in response
to a load transient. The response time is the time interval
required to slew the inductor current from an initial current value
to the post-transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitors.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The following
HIP6019
equations give the approximate response time interval for
application and removal of a transient load:
L O × ITRAN
t RISE = -------------------------------V IN – V OUT
L O × I TRAN
t FALL = ------------------------------V OUT
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. With a +5V input source,
the worst case response time can be either at the application or
removal of load and dependent upon the output voltage setting.
Be sure to check both of these equations at the minimum and
maximum output levels for the worst case response time.
Input Capacitor Selection
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline.
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitance
for the high frequency decoupling and bulk capacitors to
supply the RMS current. Small ceramic capacitors should be
placed very close to the upper MOSFET to suppress the
voltage induced in the parasitic circuit impedances.
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MVGX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
MOSFET Selection/Considerations
The HIP6019 requires 4 N-Channel power MOSFETs. Two
MOSFETs are used in the synchronous-rectified buck
topology of PWM1 converter. PWM2 converter uses a
MOSFET as the buck switch and the linear controller drives
a MOSFET as a pass transistor. These should be selected
based upon rDS(ON) , gate supply requirements, and thermal
management requirements.
power dissipation for the lower MOSFETs. Only the upper
MOSFET has switching losses, since the lower device turns
on into near zero voltage.
The equations below assume linear voltage-current
transitions and do not model power loss due to the reverserecovery of the lower MOSFET’s body diode. The gatecharge losses are proportional to the switching frequency
(FS) and are dissipated by the HIP6019, thus not
contributing to the MOSFETs’ temperature rise. However,
large gate charge increases the switching interval, tSW
which increases the upper MOSFET switching losses.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
2
IO × r DS ( ON ) × V OU T I O × VIN × t SW × F S
P UPPER = ------------------------------------------------------------ + ---------------------------------------------------VIN
2
2
I O × r DS ( ON ) × ( V I N – V OU T )
P LOWER = --------------------------------------------------------------------------------VIN
The rDS(ON) is different for the two previous equations even
if the type device is used for both. This is because the gate
drive applied to the upper MOSFET is different than the
lower MOSFET. Figure 14 shows the gate drive where the
upper gate-to-source voltage is approximately VCC less the
input supply. For +5V main power and +12V DC for the bias,
the gate-to-source voltage of Q1 is 7V. The lower gate drive
voltage is +12VDC . A logic-level MOSFET is a good choice
for Q1 and a logic-level MOSFET can be used for Q2 if its
absolute gate-to-source voltage rating exceeds the
maximum voltage applied to V CC .
+5V OR LESS
+12V
VCC
HIP6019
UGATE
Q1
PHASE
-
+
LGATE
PGND
GND
NOTE:
VGS ≈ VCC -5V
Q2
CR1
NOTE:
VGS ≈ VCC
PWM1 MOSFET Selection and Considerations
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes two
loss components; conduction loss and switching loss. These
losses are distributed between the upper and lower
MOSFETs according to duty factor (see the equations
below). The conduction losses are the only component of
264
FIGURE 14. OUTPUT GATE DRIVERS
Rectifier CR1 is a clamp that catches the negative inductor
swing during the dead time between the turn off of the
lower MOSFET and the turn on of the upper MOSFET. The
diode must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
HIP6019
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, but efficiency might drop
one or two percent as a result. The diode's rated reverse
breakdown voltage must be greater than twice the maximum
input voltage.
As it can be observed, conduction losses in the Schottky
diode are proportional with the forward voltage drop (Vf).
PWM2 MOSFET and Schottky Selection
Linear Controller MOSFET Selection
The power dissipation in PWM2 converter power devices is
similar to PWM1 except that the power losses of the lower
device are representative of a Schottky diode instead of a
MOSFET. The transistor power losses follow the PWM1
upper MOSFET equation, so the selection process should
be somewhat similar. The equation below describes the
conduction power losses incurred by the Schottky diode.
The main criteria for selection of MOSFET for the linear
regulator is package selection for efficient removal of heat.
The power dissipated in a linear regulator is:
265
IO × Vf × ( VIN – VOUT )
P SC H = ------------------------------------------------------------VIN
PLINEAR = I O × ( VIN – VOUT )
Select a package and heatsink that maintains the junction
temperature below the maximum rating while operating at
the highest expected ambient temperature.
HIP6019
HIP6019 DC-DC Converter Application Circuit
Figure 15 shows an application circuit of a power supply for
a microprocessor computer system. The power supply
provides the microprocessor core voltage (V OUT1), the I/O
voltage (V OUT2), the GTL bus voltage (VOUT3) and clock
generator voltage (VOUT4) from +5VDC and +12VDC. For
+12VIN
L1
F1
+5VIN
detailed information on the circuit, including a Bill-ofMaterials and circuit board description, see Application Note
AN9800. Also see Intersil’s web page
(http://www.intersil.com).
1µH
30A
C1-4 +
4x1000µF
GND
C14-15
2x1µF
C16
1µF
C18
C17
VCC
1000pF
R1
28
1.21K OCSET2
Q3
HUF76137S3S
VOUT2
(3.3V)
UGATE2
L2
PHASE2
23
9
8
1
27
2
26
1000pF
R2
1.21K
OCSET1
POWERGOOD
PGOOD
Q1
HUF76139S3S
UGATE1
PHASE1
5.2µH
+
2.9µH
C19-23
5x1000µF
R3
4.99K
R5
FB2
3.32K
0.68µF
R21
C38
COMP2
LGATE1
25
CR2
MBR2535CTL
VSEN2
C37
15
22
10
21
HIP6019
R7
R6
Q4
HUF75307D3S
VOUT3
(GTL = 1.5V)
VSEN1
2.21K
C43-46
4x1000µF
VOUT4
(2.5V)
+
10K
C47
270µF
0.68µF
C41
10pF
FB3
7
18
6
5
19
4
R12
10K
VOUT4
R13
COMP1
20
GATE3
1.87K
C40
R8
FB1
0.1µF
R11
R4
4.99K
11
C39
220K
5.11K
C24-36 +
7x1000µF
Q2
HUF76139S3S
PGND
24
10pF
+
VOUT1
(1.8 TO 3.5V)
L3
FB4
R14
10K
3
16
12
VID0
VID1
VID2
VID3
VID4
FAULT/RT
R10
0.01µF
150K
R9
732K
VID0
VID1
VID2
VID3
VID4
SS
14
13
C42
17
C48
0.039µF
GND
FIGURE 15. APPLICATION CIRCUIT
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
266
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