DATASHEET

ISL8010
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Sheet
October 18, 2010
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Monolithic 600mA Step-Down Regulator
with Low Quiescent Current
The ISL8010 is a synchronous, integrated FET 600mA
step-down regulator with internal compensation. It operates
with an input voltage range from 2.5V to 5.5V, which
accommodates supplies of 3.3V, 5V, or a Li-Ion battery
source. The output can be externally set from 0.8V to VIN
with a resistive divider.
The ISL8010 features automatic PFM/PWM mode control, or
PWM mode only. The PWM frequency is typically 1.4MHz
and can be synchronized up to 12MHz. The typical no load
quiescent current is only 120µA. Additional features include
a Power-Good output, <1µA shutdown current, short-circuit
protection, and over-temperature protection.
FN6191.6
Features
• Less than 0.18in2 footprint for the complete 600mA
converter
• Components on one side of PCB
• Max height 1.1mm 10 Ld MSOP
• Power-Good (PG) output
• Internally-compensated voltage mode controller
• Up to 95% efficiency
• <1µA shutdown current
• 120µA quiescent current
• Hiccup mode overcurrent and over-temperature protection
The ISL8010 is available in the 10 Ld MSOP package,
making the entire converter occupy less than 0.18in2 of PCB
area with components on one side only. The 10 Ld MSOP
package is specified for operation over the full -40°C to
+85°C temperature range.
• Externally synchronizable up to 12MHz
Ordering Information
• Bar code readers
PART
NUMBER
(Notes 2, 3)
PART
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL8010IUZ
8010Z
10 Ld MSOP
MDP0043
ISL8010IUZ-T7 (Note 1)
8010Z
10 Ld MSOP
MDP0043
ISL8010IUZ-T13 (Note 1)
8010Z
10 Ld MSOP
MDP0043
• Pb-free available (RoHS compliant)
Applications
• PDA and pocket PC computers
• Cellular phones
• Portable test equipment
• Li-Ion battery powered devices
• Small form factor (SFP) modules
Typical Application Diagram
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish,
which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device
information page for ISL8010. For more information on MSL
please see techbrief TB363.
VS
(2.5V TO 5.5V)
R3 100
C2
10µF
ISL8010
(10 LD MSOP)
TOP VIEW
1 SGND
FB 10
2 PGND
VO 9
3 LX
PG 8
4 VIN
EN 7
5 VDD
ISL8010
R1*
124k
PG
EN
R6
100k
1.8µH
C1
10µF
R5 100k
R4 100k
Pinout
LX
VDD
C3
0.1µF
VO
L1
VIN
FB
SYNC
PGND
SGND
R2*
100k
VO
C4
470pF
(1.8V @ 600mA)
*VO = 0.8V*(1 + R1/R2)
SYNC 6
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006, 2007, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8010
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
VIN, VDD, PG to SGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V)
SYNC, EN, VO, FB to SGND . . . . . . . . . . . . . -0.3V to (VIN + +0.3V)
PGND to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mA
Thermal Resistance (Typical, Note 4)
JA (°C/W)
10 Ld MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VDD = VIN = VEN = 3.3V, C1 = C2 = 10µF, L = 1.8µH, VO = 1.8V (as shown in “Typical Application Diagram” on
page 1), TA = -40°C to +85°C unless otherwise specified. Boldface limits apply over the operating
temperature range, -40°C to +85°C.
DESCRIPTION
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
790
800
810
mV
100
nA
2.5
5.5
V
DC CHARACTERISTICS
VFB
Feedback Input Voltage
IFB
Feedback Input Current
VIN, VDD
Input Voltage
VIN,OFF
Minimum Voltage for Shutdown
VIN falling, TA = +25°C only
2
2.2
V
VIN,ON
Maximum Voltage for Start-up
VIN rising, TA = +25°C only
2.2
2.4
V
IS
Input Supply Quiescent Current
IDD
PWM Mode
Active - PFM Mode
VSYNC = 0V
120
145
µA
Active - PWM Mode
VSYNC = 3.3V
6.5
7.5
mA
Supply Current
PWM, VIN = VDD = 5V
400
500
µA
EN = 0, VIN = VDD = 5V
0.1
3
µA
rDS(ON)-PMOS
PMOS FET Resistance
VDD = 5V, TA = +25°C
70
100
m
rDS(ON)-NMOS
NMOS FET Resistance
VDD = 5V, TA = +25°C
45
75
m
ILMAX
Current Limit
1.2
A
TOT,OFF
Over-temperature Threshold
T rising
145
°C
TOT,ON
Over-temperature Hysteresis
T falling
130
°C
IEN, ISYNC
EN, SYNC Current
VEN, VRSI = 0V and 3.3V
VEN1, VSYNC1
EN, SYNC Rising Threshold
VDD = 3.3V
VEN2, VSYNC2
EN, SYNC Falling Threshold
VDD = 3.3V
VPG
Minimum VFB for PG, WRT Targeted VFB VFB rising
Value
VFB falling
VOLPG
PG Voltage Drop
-1
1
µA
2.4
V
0.8
V
95
86
ISINK = 3.3mA
%
%
35
70
mV
1.4
1.6
MHz
AC CHARACTERISTICS
FPWM
PWM Switching Frequency
tSS
Soft-start Time
1.25
650
µs
NOTE:
5. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
2
FN6191.6
October 18, 2010
ISL8010
Pin Descriptions
PIN NUMBER
PIN NAME
PIN FUNCTION
1
SGND
Negative supply for the controller stage
2
PGND
Negative supply for the power stage
3
LX
Inductor drive pin; high current digital output with average voltage equal to the regulator output voltage
4
VIN
Positive supply for the power stage
5
VDD
Power supply for the controller stage
6
SYNC
7
EN
Enable
8
PG
Power-Good open drain output
9
VO
Output voltage sense
10
FB
Voltage feedback input; connected to an external resistor divider between VO and SGND for variable
output
SYNC input pin; when connected to HI, regulator runs at forced PWM mode; when connected to Low, auto
PFM/PWM mode; when connected to external sync signal, at external PWM frequency up to 12MHz
Block Diagram
100
0.1µF
VDD
INDUCTOR SHORT
VO
C4
470pF
124k
+
CURRENT
SENSE
10pF
FB
5M
+
PWM
COMPENSATION
PWM
COMPARATOR
+
-
P-DRIVER
100k
SYNC
SYNC
RAMP
GENERATOR
SOFTSTART
10µF
5V +
–
CLOCK
EN
EN
VIN
BANDGAP
REFERENCE
PFM
ON-TIME
CONTROL
+
PWM
COMPARATOR
UNDERVOLTAGE
LOCKOUT
TEMPERATURE
SENSE
SGND
LX
CONTROL
LOGIC
1.8V
0mA TO 600mA
10µF
N-DRIVER
+
SYNCHRONOUS
RECTIFIER
1.8µH
PGND
100k
PG
PG
POWER
GOOD
3
FN6191.6
October 18, 2010
ISL8010
Typical Performance Curves
100
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on
page 1 at room ambient temperature, unless otherwise noted.
100
VO = 3.3V
95
90
VO = 2.5V
90
80
75
VO = 1.8V
VO = 1.5V
70
VO = 1.0V
65
VO = 0.8V
60
EFFICIENCY (%)
EFFICIENCY (%)
85
VO = 1.2V
55
45
VO = 1.8V
60
VO = 1.5V
50
VO = 1.2V
40
VO = 1.0V
30
VO = 0.8V
10
VIN = 5V
1
VO = 2.5V
70
20
50
40
VO = 3.3V
80
10
100
0
600
VIN = 5V
1
10
100
FIGURE 1. EFFICIENCY vs IO (PFM/PWM MODE)
100
FIGURE 2. EFFICIENCY vs IO (PWM MODE)
100
VO = 2.5V
VO = 1.8V
95
90
VO = 1.8V
80
80
EFFICIENCY (%)
EFFICIENCY (%)
VO = 2.5V
90
85
VO = 1.5V
VO = 1.2V
VO = 1.0V
75
70
65
VO = 0.8V
60
55
VO = 1.5V
70
VO = 1.2V
60
VO = 1.0V
50
40
30
20
50
45
40
1
10
100
VO = 0.8V
10
VIN = 3.3V
0
600
VIN = 3.3V
1
10
100
FIGURE 3. EFFICIENCY vs IO (PFM/FWM MODE)
1.44
VIN = 5V IO = 600mA
0.1
VIN = 5V IO = 0A
VO CHANGES (%)
0.0
1.40
FS (MHz)
FIGURE 4. EFFICIENCY vs IO (PWM MODE)
VIN = 3.3V IO = 600mA
1.42
600
IO (mA)
IO (mA)
VIN = 3.3V IO = 0A
1.38
1.36
1.34
1.32
-50
600
IO (mA)
IO (mA)
-0.1
VIN = 3.3V
-0.2
VIN = 5V
-0.3
-0.4
-0.5
0
50
TA (°C)
100
150
FIGURE 5. FS vs JUNCTION TEMPERATURE (PWM MODE)
4
0
0.2
0.4
0.6
0.8
1.0
IO (A)
FIGURE 6. LOAD REGULATIONS (PWM MODE)
FN6191.6
October 18, 2010
ISL8010
Typical Performance Curves
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on
page 1 at room ambient temperature, unless otherwise noted. (Continued)
0.1
12
VIN = 5V IO = 0A
10
VIN = 3.3V IO = 0A
-0.1
8
-0.2
IS (mA)
VO CHANGES (%)
0.0
VIN = 3.3V IO = 600mA
-0.3
-0.4
6
4
-0.5
-0.6
-0.7
2
VIN = 5V IO = 600mA
-50
0
50
100
0
2.5
150
3.0
3.5
TJ (°C)
4.0
4.5
5.0
VS (V)
FIGURE 7. PWM MODE LOAD/LINE REGULATIONS vs
JUNCTION TEMPERATURE
FIGURE 8. NO LOAD QUIESCENT CURRENT (PWM MODE)
140
130
VO = 1.8V
VO = 3.3V
120
IS (µA)
110
100 V = 1.5V
O
90
VO = 1.0V
VO = 1.2V
VO = 0.8V
80
70
60
50
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VS (V)
FIGURE 9. NO LOAD QUIESCENT CURRENT (PFM MODE)
2
1
VIN
(2V/DIV)
EN
IIN
(0.25A/DIV)
IIN
(0.25A/DIV)
VO
(2V/DIV)
VO
(2V/DIV)
PG
PG
200µs/DIV
FIGURE 10. START-UP AT IO = 600mA
5
500µs/DIV
FIGURE 11. ENABLE AND SHUTDOWN
FN6191.6
October 18, 2010
ISL8010
Typical Performance Curves
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on
page 1 at room ambient temperature, unless otherwise noted. (Continued)
LX
(2V/DIV)
LX
(2V/DIV)
IL
(0.5A/DIV)
IL
(0.5A/DIV)
VO
(10mV/DIV)
VO
(50mV/DIV)
0.5µs/DIV
2µs/DIV
FIGURE 12. PFM STEADY-STATE OPERATION WAVEFORM
(IO = 100mA)
FIGURE 13. PWM STEADY-STATE OPERATION (IO = 600mA)
SYNC
(2V/DIV)
SYNC
(2V/DIV)
LX
(2V/DIV)
IL
(0.5A/DIV)
LX
(2V/DIV)
IL
(0.5A/DIV)
20ns/DIV
0.2µs/DIV
FIGURE 14. EXTERNAL SYNCHRONIZATION TO 2MHz
FIGURE 15. EXTERNAL SYNCHRONIZATION TO 12MHz
IO
(200mA/DIV)
IO
(200mA/DIV)
VO
(100mV/DIV)
VO
(100mV/DIV)
50µs/DIV
FIGURE 16. LOAD TRANSIENT RESPONSE (22mA TO 600mA)
6
50µs/DIV
FIGURE 17. PWM LOAD TRANSIENT RESPONSE
(30mA TO 600mA)
FN6191.6
October 18, 2010
ISL8010
Typical Performance Curves
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on
page 1 at room ambient temperature, unless otherwise noted. (Continued)
100
1.4MHz
IO
(200mA/DIV)
EFFICIENCY (%)
80
VO
(50mV/DIV)
5MHz
12MHz
60
40
20
0
0
200
400
50µs/DIV
600
800
1k
1.2k
IO (mA)
FIGURE 18. PWM LOAD TRANSIENT RESPONSE
(100mA TO 500mA)
FIGURE 19. EFFICIENCY vs IO (PWM MODE)
0.5
1.0
12MHz
0.3
VO CHANGES (%)
VO CHANGES (%)
0.6
1.4MHz
0.2
5MHz
0
1.4MHz
-0.1
5MHz
-0.3
-0.2
-0.6
12MHz
0.1
0
200
400
600
800
1k
1.2k
-0.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
IO (mA)
FIGURE 20. LOAD REGULATION (PWM MODE)
FIGURE 21. LINE REGULATION @ 500mA (PWM MODE)
IO = 50mA
IO = 150mA
2µs/DIV
FIGURE 22. PFM-PWM TRANSITION TIME
7
SYNC
(2V/DIV)
SYNC
(2V/DIV)
LX
(2V/DIV)
LX
(2V/DIV)
2µs/DIV
FIGURE 23. PFM-PWM TRANSITION TIME
FN6191.6
October 18, 2010
ISL8010
Typical Performance Curves
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on
page 1 at room ambient temperature, unless otherwise noted. (Continued)
3
PG
VO CHANGES (%)
2
1
IO
0
-1
PFM
PWM
-2
-3
VO
0
200
400
600
800
1000
1200
IOUT (mA)
FIGURE 24. PFM-PWM TRANSITION
FIGURE 25. PFM-PWM LOAD TRANSIENT
PG
PG
IO
IO
VO
VO
FIGURE 26. PFM TO PWM TRANSITION
FIGURE 27. PWM TO PFM TRANSITION
PG
PG
IL
IL
VO
VO
FIGURE 28. OVERCURRENT SHUTDOWN
8
FIGURE 29. OVERCURRENT HICCUP MODE
FN6191.6
October 18, 2010
ISL8010
Applications Information
Product Description
The ISL8010 is a synchronous, integrated FET 600mA
step-down regulator, which operates from an input of 2.5V to
5.5V. The output voltage is user-adjustable with a pair of
external resistors.
When the load is very light, the regulator automatically
operates in the PFM mode, thus achieving high efficiency at
light load (>70% for 1mA load). When the load increases,
the regulator automatically switches over to a voltage-mode
PWM operating at nominal 1.4MHz switching frequency. The
efficiency is up to 95%.
It can also operate in a fixed PWM mode or be synchronized
to an external clock up to 12MHz for improved EMI
performance.
PFM Operation
The heart of the ISL8010 regulator is the automatic
PFM/PWM controller.
If the SYNC pin is connected to ground, the regulator
operates automatically in either the PFM or PWM mode,
depending on load. When the SYNC pin is connected to VIN,
the regulator operates in the fixed PWM mode. When the pin
is connected to an external clock ranging from 1.6MHz to
12MHz, the regulator is in the fixed PWM mode and
synchronized to the external clock frequency.
In the automatic PFM/PWM operation, when the load is light,
the regulator operates in the PFM mode to achieve high
efficiency. The top P-Channel MOSFET is turned on first.
The inductor current increases linearly to a preset value
before it is turned off. Then the bottom N-Channel MOSFET
turns on, and the inductor current linearly decreases to zero
current. The N-Channel MOSFET is then turned off, and an
anti-ringing MOSFET is turned on to clamp the LX pin to VO.
Both MOSFETs remain off until VFB drops below the internal
reference voltage of 0.8V. The inductor current looks like
triangular pulses. The frequency of the pulses is mainly a
function of output current. The higher the load, the higher the
frequency of the pulses until the inductor current becomes
continuous. At this point, the controller automatically
changes to PWM operation.
When the controller transitions to PWM mode, there can be
a perturbation to the output voltage. This perturbation is due
to the inherent behavior of switching converters when
transitioning between two control loops. To reduce this
effect, it is recommended to use the phase-lead capacitor
(C4) shown in the “Typical Application Diagram” on page 1.
This capacitor allows the PWM loop to respond more quickly
to this type of perturbation. To properly size C4, refer to
“Component Selection” on page 10.
9
PWM Operation
The regulator operates the same way in the forced PWM or
synchronized PWM mode. In this mode, the inductor current
is always continuous and does not stay at zero.
In this mode, the P-Channel MOSFET and N-Channel
MOSFET always operate complementary. When the
P-Channel MOSFET is on and the N-Channel MOSFET off,
the inductor current increases linearly. The input energy is
transferred to the output and also stored in the inductor.
When the P-Channel MOSFET is off and the N-Channel
MOSFET on, the inductor current decreases linearly, and
energy is transferred from the inductor to the output. Hence,
the average current through the inductor is the output
current. Since the inductor and the output capacitor act as a
low pass filter, the duty cycle ratio is approximately equal to
VO divided by VIN.
The output LC filter has a second order effect. To maintain
the stability of the converter, the overall controller must be
compensated. This is done with the fixed internally
compensated error amplifier and the PWM compensator.
Because the compensations are fixed, the values of input
and output capacitors are 10µF to 22µF ceramic and
inductor is 1.5µH to 2.2µH.
Forced PWM Mode/SYNC Input
Pulling the SYNC pin HI (>2.5V) forces the converter into
PWM mode in the next switching cycle regardless of output
current. The duration of the transition varies depending on the
output current. Figures 22 and 23 (under two different loading
conditions) show the device goes from PFM to PWM mode.
Note: In forced PWM mode, the IC will continue to start-up in
PFM mode to support pre-biased load applications.
Start-Up and Shutdown
When the EN pin is tied to VIN and VIN reaches
approximately 2.4V, the regulator begins to switch. The
inductor current limit is gradually increased to ensure proper
soft-start operation.
When the EN pin is connected to a logic low, the ISL8010 is
in the shutdown mode. All the control circuitry and both
MOSFETs are off, and VOUT falls to zero. In this mode, the
total input current is less than 1µA.
When the EN reaches logic HI, the regulator repeats the
start-up procedure, including the soft-start function.
Current Limit and Short-Circuit Protection
The current limit is set at about 1.2A for the PMOS. When a
short-circuit occurs in the load, the preset current limit restricts
the amount of current available to the output, which causes
the output voltage to drop as load demand increases. When
the output voltage drops 30mV below the reference voltage,
the converter will shutdown for a period of time (approximated
by Equation 1) and then restart. If the overcurrent condition
still exists, it will repeat the shutdown-wait-restart event. This
FN6191.6
October 18, 2010
ISL8010
is called a “hiccup” event. The average power dissipation is
reduced, thereby reducing the likelihood of damaged current
and thermal conditions in the IC.
700  V IN
tHICCUP   ---------------------------- + 216


3
(EQ. 1)
The inductor peak-to-peak ripple current is given as
Equation 4:
 V IN – V O   V O
I IL = -------------------------------------------L  V IN  f S
(EQ. 4)
L is the inductance
Thermal Shutdown
Once the junction reaches about +145°C, the regulator shuts
down. Both the P-Channel and the N-Channel MOSFETs
turn off. The output voltage will drop to zero. With the output
MOSFETs turned off, the regulator will cool down. Once the
junction temperature drops to about +130°C, the regulator
will perform a normal restart.
Thermal Performance
The ISL8010 is available in a fused-lead 10 Ld MSOP
package. Compared with regular 10 Ld MSOP package, the
fused-lead package provides lower thermal resistance. The
JA is +100°C/W on a 4-layer board and +125°C/W on
2-layer board. Maximizing the copper area around the pins
will further improve the thermal performance.
Power Good Output
The PG (pin 8) output is used to indicate when the output
voltage is properly regulating at the desired set point. It is an
open-drain output that should be tied to VIN or VCC through
a 100k resistor. If no faults are detected, EN is high, and
the output voltage is within ~5% of regulation, the PG pin will
be allowed to go high. Otherwise, the open-drain NMOS will
pull PG low.
Output Voltage Selection
Users can set the output voltage of the variable version with
a resistor divider, which can be chosen based on Equation 2:
R 1

V O = 0.8   1 + -------
R

2
(EQ. 2)
fS is the switching frequency (nominally 1.4MHz)
The inductor must be able to handle IO for the RMS load
current, and to assure that the inductor is reliable, it must
handle the 2A surge current that can occur during a current
limit condition.
In addition to decoupling capacitors and inductor value, it is
important to properly size the phase-lead capacitor C4
(Refer to “Typical Application Diagram” on page 1). The
phase-lead capacitor creates additional phase margin in the
control loop by generating a zero and a pole in the transfer
function. As a general rule of thumb, C4 should be sized to
start the phase-lead at a frequency of ~2.5kHz. The zero will
always appear at lower frequency than the pole and follow
Equation 5:
1
f Z = ---------------------2R 2 C 4
(EQ. 5)
Over a normal range of R2 (~10kto 100k), C4 will range
from ~470pF to 4700pF. The pole frequency cannot be set
once the zero frequency is chosen as it is dictated by the
ratio of R1 and R2, which is solely determined by the desired
output set point. Equation 6 shows the pole frequency
relationship:
1
f P = --------------------------------------2  R 1 R 2 C 4
(EQ. 6)
Layout Considerations
The layout is very important for the converter to function
properly. The following PC layout guidelines should be
followed:
Component Selection
Because of the fixed internal compensation, the component
choice is relatively narrow. For a regulator with fixed output
voltage, only two capacitors and one inductor are required. It
is recommended to use between 10µF and 22µF multilayer
ceramic capacitors with X5R or X7R rating for both the input
and output capacitors, and 1.5µH to 2.2µH for the inductor.
The RMS current present at the input capacitor is decided by
Equation 3:
V O   V IN – V O 
I INRMS = -----------------------------------------------  I O
V IN
(EQ. 3)
This is about half of the output current IO for all the VO. This
input capacitor must be able to handle this current.
10
1. Separate the Power Ground ( ) and Signal Ground
( ); connect them only at one point right at the pins
2. Place the input capacitor as close to VIN and PGND pins
as possible
3. Make the following PC traces as small as possible:
- from LX pin to L
- from CO to PGND
4. If used, connect the trace from the FB pin to R1 and R2
as close as possible
5. Maximize the copper area around the PGND pin
6. Place several via holes under the chip to additional
ground plane to improve heat dissipation
The demo board is a good example of layout based on this
outline. Please refer to the ISL8010 Application Note.
FN6191.6
October 18, 2010
ISL8010
Mini SO Package Family (MSOP)
0.25 M C A B
D
MINI SO PACKAGE FAMILY
(N/2)+1
N
E
MDP0043
A
E1
MILLIMETERS
PIN #1
I.D.
1
B
(N/2)
e
H
C
SEATING
PLANE
0.10 C
N LEADS
0.08 M C A B
b
SYMBOL
MSOP8
MSOP10
TOLERANCE
NOTES
A
1.10
1.10
Max.
-
A1
0.10
0.10
±0.05
-
A2
0.86
0.86
±0.09
-
b
0.33
0.23
+0.07/-0.08
-
c
0.18
0.18
±0.05
-
D
3.00
3.00
±0.10
1, 3
E
4.90
4.90
±0.15
-
E1
3.00
3.00
±0.10
2, 3
e
0.65
0.50
Basic
-
L
0.55
0.55
±0.15
-
L1
0.95
0.95
Basic
-
N
8
10
Reference
Rev. D 2/07
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
L1
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
A
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
L
A1
0.25
3° ±3°
DETAIL X
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11
FN6191.6
October 18, 2010
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