DATASHEET

ISL9109
ESIGNS
R NEW D NT
O
F
D
E
E
ND
COMME
PL ACEM r a t
NO T R E
DED R E
N
te
E
n
e
M
C
M
t
O
por
c
NO REC Data
Sheet
29, 2008
ical Sup rsil.com/tsSeptember
n
h
c
e
T
r
te
ou
contact ERSIL or www.in
T
1-888-IN
FN6681.1
RF PA 1.5A DC/DC Regulator
Features
ISL9109 is 1.6MHz synchronous step-down regulator with
integrated power switches capable of delivering 1.5A output
for powering RF Power Amplifiers in cellular phones. The
ISL9109 features a standby mode which allows for rapid
startup while prolonging battery life. The supply voltage
range is from 2.7V to 5.5V allowing the use of a single Li+
cell, three NiMH cells, or a regulated 5V input. 1.6MHz
pulse-width modulation (PWM) switching frequency allows
using small external components. It has a flexible operation
mode selection of forced PWM mode and Skip (Low IQ)
mode with typical 22µA quiescent current for highest light
load efficiency to maximize battery life.
• Integrated Synchronous Buck Regulator with up to 95%
Efficiency
The ISL9109 integrates a pair of low ON-resistance
P-Channel and N-Channel MOSFETs to maximize efficiency
and minimize external component count.
• 100% Maximum Duty Cycle for Lowest Dropout
When in standby, the ISL9109 band-gap reference is
powered. This assists in a rapid power-up when the EN pin
is asserted high. Other features include soft-start,
overcurrent protection, and thermal shutdown.
• 2.7V to 5.5V Supply Voltage
• 1.5A Output Current
• 4.3µAQuiescent Supply Current in Standby Mode
• 22µA Quiescent Supply Current in Skip (Low IQ) Mode
• 3% Output Accuracy Over Temperature/Load/Line
• Selectable Forced PWM Mode or Skip Mode
• Less Than 1µA Logic Controlled Shutdown Current
• Soft-Start
• Peak Current Limiting, Short Circuit Protection
• Over-Temperature Protection
• 8 Ld 2mmx3mm DFN
• Pb-Free (RoHS Compliant)
The ISL9109 is offered in 8 Ld 2mmx3mm DFN package
with 0.9mm typical height. The complete converter can
occupy less than 1cm2 area.
Applications
Ordering Information
• RF Power Amplifier
PART
NUMBER
(Note)
ISL9109IRZ*
PART
MARKING
109
TEMP.
RANGE
(°C)
• Single Li-Ion Battery-Powered Equipment
• CPU Power
PACKAGE
(Pb-free)
-40 to +85 8 Ld 2x3 DFN
PKG.
DWG. #
L8.2x3
• PDAs and Palmtops
Pinout
ISL9109
(8 LD 2X3 DFN)
TOP VIEW
*Add “-T” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
1
VIN
1
8
SW
EN
2
7
GND
N/C
3
6
FB
MODE
4
5
STBY
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL9109
Absolute Maximum Ratings (Reference to GND)
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
EN, MODE, STBY . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V
SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V to 6.5V
FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
Thermal Resistance (Notes 1, 2)
JA (°C/W)
JC (°C/W)
2x3 DFN Package . . . . . . . . . . . . . .
55
5.5
Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Load Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1.5A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. JC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and
the typical specifications are measured at the following conditions: TA = +25°C, VIN = VEN = 3.6V, L = 2.2µH,
C1 = 10µF, C2 = 10µF, IOUT = 0A (see the“Typical Applications” on page 7).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Rising
-
2.5
2.7
V
Falling
2.2
2.4
-
V
EN = STBY = LOW (Shut Down)
TA = +25°C
-
0.05
2
µA
EN = STBY = HI for  1ms, then
EN = LOW, STBY = HI (Standby)
TA = +25°C
-
4.3
6.0
µA
EN = MODE = HI, no load at the output
-
22
30
µA
EN = HI, MODE = LOW, no load at the output,
VFB = 0.75V
-
3.6
5.5
mA
0.78
0.8
0.82
V
SUPPLY
Undervoltage Lockout Threshold
VUVLO
Quiescent Supply Current
IVIN
OUTPUT REGULATION
FB Regulation Voltage
VFB
FB Bias Current
IFB
Line Regulation
MODE = LOW
VFB = 0.75V
-
0.1
-
µA
VIN = VO + 0.5V to 5.5V (minimal 2.7V)
-
0.2
-
%/V
Design info only
-
20
-
µA/V
VIN = 3.6V, IO = 200mA
-
0.12
0.22

VIN = 2.7V, IO = 200mA
-
0.16
0.27

VIN = 3.6V, IO = 200mA
-
0.11
0.22

VIN = 2.7V, IO = 200mA
-
0.15
0.27

1.8
2.1
2.6
A
-
100
-
%
1.35
1.6
1.75
MHz
-
80
-
ns
COMPENSATION
Error Amplifier Trans-conductance
SW
P-Channel MOSFET ON-resistance
N-Channel MOSFET ON-resistance
P-Channel MOSFET Peak Current Limit
IPK
VIN = 5.5V, L = 3.3µH, VOUT shorted to GND
thru a 50mresistor
Maximum Duty Cycle
PWM Switching Frequency
fS
SW Minimum On Time
MODE = LOW (forced PWM mode)
2
FN6681.1
September 29, 2008
ISL9109
Electrical Specifications
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and
the typical specifications are measured at the following conditions: TA = +25°C, VIN = VEN = 3.6V, L = 2.2µH,
C1 = 10µF, C2 = 10µF, IOUT = 0A (see the“Typical Applications” on page 7). (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
tSS
STBY = 0, EN = _/¯
Start-Up is considered complete when VOUT
reaches 93% of final target voltage.
-
1.1
-
ms
STBY = 1 for 1mS, EN = _/¯
Start-up is considered complete when VOUT
reaches 93% of final target voltage.
-
-
60
µs
Logic Input Low
-
-
0.4
V
Logic Input High
1.4
-
-
V
-
0.1
1
µA
Thermal Shutdown
-
160
-
°C
Thermal Shutdown Hysteresis
-
25
-
°C
Soft Start-Up Time
STBY, EN, MODE
Logic Input Leakage Current
Pulled up to 5.5V
THERMAL SHUTDOWN
Pin Descriptions
PIN #
PIN
NAME
1
VIN
Input supply voltage. Connect a 10µF ceramic capacitor to power ground.
2
EN
Enable pin. Enable the output when driven to high. Shut down the chip and discharge output capacitor when driven to low. Do
not leave this pin floating
3
N/C
Do not connect; leave floating for proper device operation
4
MODE
Mode selection pin. Connect to logic high or VIN to enable skip mode; connect to logic low or ground for force PWM mode.
5
STBY
Active high enables the band-gap reference.
6
FB
7
GND
8
SW
E-PAD
-
DESCRIPTION
Buck regulator output feedback pin. Connect to the output voltage through voltage divider resistors for adjustable output
voltage.
System ground.
Switching node connection. Connect to one terminal of the inductor.
Exposed pad. It should be connected to ground for proper electrical performance. For best thermal performance, connect as
much copper as possible to this pad, either on the component layer or other layers through thermal vias.
Typical Operating Performance
100
VIN = 3.8V
90
EFFICIENCY (%)
EFFICIENCY (%)
100
VIN = 4.2V
80
VIN = 5.5V
70
60
VIN = 3.0V
90
80
VIN = 4.2V
70
VIN = 5.5V
60
50
50
0
250
500
750
1000
1250
1500
LOAD CURRENT (mA)
FIGURE 1. EFFICIENY vs LOAD CURRENT (VOUT = 3.3V)
3
0
250
500
750
1000
1250
1500
LOAD CURRENT (mA)
FIGURE 2. EFFICIENCY vs LOAD CURRENT (VOUT = 2.5V)
FN6681.1
September 29, 2008
ISL9109
Typical Operating Performance (Continued)
VIN = 2.7V
EFFICIENCY (%)
90
VIN = 3.3V
80
VIN = 5.0V
70
60
50
0
250
500
1.60
SWITCHING FREQUENCY (MHz)
100
750
1000
1250
1.55
1.50
1.45
1.40
2.7
1500
FIGURE 3. EFFICIENCY vs LOAD CURRENT (VOUT = 1.8V)
QUIESCENT CURRENT (µA)
QUIESCENT CURRENT (µA)
20
15
10
5
3.4
4.1
4.8
4
3
2
1
0
5.5
2.7
3.4
FIGURE 5. IQ vs VIN (MODE = VIN, STBY = VIN, EN = VIN,
VOUT = 1.6V, IOUT = 0)
OUTPUT VOLTAGE (V)
2.54
IOUT = 1000mA
IOUT = 500mA
1.610
IOUT = 0mA
1.605
4.1
4.8
5.5
INPUT VOLTAGE (V)
FIGURE 7. VOUT vs VIN (MODE = VIN, VOUT = 1.6V)
4
4.8
5.5
FIGURE 6. IQ vs VIN (MODE = VIN, STBY = VIN, EN = GND,
IOUT = 0)
1.620
3.4
4.1
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
5.5
5
25
1.600
2.7
4.8
FIGURE 4. SWITCHING FREQUENCY vs INPUT VOLTAGE,
(VOUT = 1.6V, IOUT = 1A, TA = +25°C)
30
1.615
4.1
INPUT VOLTAGE (V)
LOAD CURRENT (mA)
0
2.7
3.4
IOUT = 1000mA
2.53
IOUT = 500mA
2.52
2.51
2.50
2.7
IOUT = 0mA
3.4
4.1
4.8
5.5
INPUT VOLTAGE (V)
FIGURE 8. VOUT vs VIN (MODE = VIN, VOUT = 2.5V)
FN6681.1
September 29, 2008
ISL9109
Typical Operating Performance (Continued)
VOUT
5V/DIV
VOUT
5V/DIV
SW
5V/DIV
SW
5V/DIV
EN
2V/DIV
EN
2V/DIV
200µs/DIV
10µs/DIV
FIGURE 9. SOFT-START (VIN = 4.2V, VOUT = 1.6V,
STBY = 0V, IOUT = 500mA)
2V/DIV
FIGURE 10. SOFT-START (VIN = 4.2V, VOUT = 1.6V,
STBY = VIN, IOUT = 500mA)
VSW
2V/DIV
VOUT (AC COUPLED)
VSW
20mV/DIV
20mV/DIV
200mA/DIV
VOUT (AC COUPLED)
IL
IL
1A/DIV
1µs/DIV
1µs/DIV
FIGURE 11. STEADY-STATE IN SKIP MODE (VIN = 5.0V,
VOUT = 1.8V, IOUT = 35mA)
FIGURE 12. STEADY-STATE IN PWM MODE (VIN = 5.0V,
VOUT = 1.8V, IOUT = 1.2A)
2V/DIV
2V/DIV
VSW
20mV/DIV
50mV/DIV
VSW
VOUT (AC COUPLED)
VOUT (AC COUPLED)
200mA/DIV
IL
4µs/DIV
FIGURE 13. STEADY-STATE IN SKIP MODE (VIN = 5.0V,
VOUT = 3.3V, IOUT = 35mA)
5
IL
1A/DIV
1µs/DIV
FIGURE 14. STEADY-STATE IN PWM MODE (VIN = 5.0V,
VOUT = 3.3V, IOUT = 1.2A)
FN6681.1
September 29, 2008
ISL9109
Typical Operating Performance (Continued)
VSW
VSW
2V/DIV
2V/DIV
VOUT (AC COUPLED)
100mV/DIV
VOUT (AC COUPLED)
100mV/DIV
IL
IL
1A/DIV
1A/DIV
100µs/DIV
100µs/DIV
FIGURE 15. LOAD TRANSIENT TEST (MODE=GND VIN = 5.0V;
VO = 1.5V; IO = 0.01A~1A)
FIGURE 16. LOAD TRANSIENT TEST (MODE = GND,
VIN = 3.6V; VO = 1.5V; IO = 0.01A~1A)
VSW
VSW
2V/DIV
2V/DIV
VOUT (AC COUPLED)
100mV/DIV
50mV/DIV
VOUT (AC COUPLED)
IL
0.5A/DIV
IOUT
IL
1A/DIV
0.2A/DIV
100µs/DIV
FIGURE 17. LOAD TRANSIENT TEST (MODE = GND, VIN =
3.6V; VO = 2.5V; IO = 0.01A~1A)
6
100µs/DIV
FIGURE 18. LOAD TRANSIENT TEST (MODE = VIN = 5V; VO =
3.3V; IO = 0.2A~0.4A)
FN6681.1
September 29, 2008
ISL9109
Typical Applications
OUTPUT
INPUT
2.7 TO 5.5V
1.6V, 1.5
VIN
SW
2.0µH
C1
10µF
EN
C2
10µF
R1
100k
C3
120pF
GND
ISL9109
FB
N/C
R2
100k
STBY
MODE
E-PAD
PARTS
DESCRIPTION
MANUFACTURERS
PART NUMBER
SPECIFICATIONS
SIZE
L
Inductor
Toko
1098AS-2R0AM
2.0µH/1.8A/67m
3.0mmx3.2mmx1.2mm
C1
Input capacitor
Murata
GRM21BR60J106KE19L
10µF/6.3V
2.0mmx1.25mmx1.25mm
C2
Output capacitor
Murata
GRM21BR60J106KE19L
10µF/6.3V
2.0mmx1.25mmx1.25mm
C3
Capacitor
Murata
GRM1885C1H121JA01D
120pF/50V
1.6mmx0.8mmx0.8mm
R1, R2
Resistor
Various
100k SMD, 0.5%
1.6mmx0.8mmx0.45mm
FIGURE 19. TYPICAL APPLICATION DIAGRAM
7
FN6681.1
September 29, 2008
ISL9109
Block Diagram
MODE
SOFT
START
SHUTDOWN
SHUTDOWN
BANDGAP 0.8V
+
EN
+
EAMP
OSCILLATOR
VIN
COMP
PWM/PFM
LOGIC
CONTROLLER
SW
PROTECTION
SLOPE
COMP
DRIVER
+
GND
STBY
+
VREF3
SCP
FB
+
CSA
+
OCP
VREF1
+
SKIP
VREF2
N/C
ZERO-CROSS
SENSING
FIGURE 20. FUNCTIONAL BLOCK DIAGRAM
8
FN6681.1
September 29, 2008
ISL9109
Theory of Operation
The ISL9109 is a step-down switching regulator optimized
for battery-powered handheld applications. The regulator
operates at a typical 1.6MHz fixed switching frequency
under heavy load conditions to allow small external inductor
and capacitors to be used for minimal printed-circuit board
(PCB) area. At light load, the regulator can be selected to
enter skip mode to reduce the switching frequency. Unless
forced to the fixed frequency, to minimize the switching loss
and to maximize the battery life. The quiescent current under
skip mode, with no loading is typically only 22µA. The supply
current is typically only 4µA in standby mode, and 0.05µA
when the regulator is in shutdown mode.
PWM Control Scheme
The device uses the peak-current mode pulse-width
modulation (PWM) control scheme for fast transient
response and pulse-by-pulse current limiting. Figure 20
shows the circuit functional block diagram. The current loop
consists of the oscillator, the PWM comparator COMP,
current sensing circuit, and the slope compensation for the
current loop stability. The current sensing circuit consists of
the resistance of the P-Channel MOSFET when it is turned
on, and the Current Sense Amplifier (CSA). The control
reference for the current loops comes from the Error
Amplifier (EAMP) of the voltage loop.
VvEAMP
EAMP
VvCSA
CSA
SW
SW
IiL
L
VvOUT
OUT
FIGURE 21. PWM OPERATION WAVEFORMS
The PWM operation is initialized by the clock from the
oscillator. The P-Channel MOSFET is turned on at the
beginning of a PWM cycle and the current in the P-Channel
MOSFET starts ramping up. When the sum of the CSA output
and the compensation slope reaches the control reference of
the current loop, the PWM comparator COMP sends a signal
to the PWM logic to turn off the P-Channel MOSFET and to
turn on the N-Channel MOSFET. The N-MOSFET remains on
until the end of the PWM cycle. Figure 21 shows the typical
operating waveforms during the normal PWM operation. The
dotted lines illustrate the sum of the slope compensation ramp
and the CSA output.
feedback signal comes from the FB pin. The soft-start block
only affects the operation during the start-up and will be
discussed separately in “Soft Start-Up” on page 10. The
EAMP is a trans conductance amplifier, which converts the
voltage error signal to a current output. The voltage loop is
internally compensated by a RC network. The maximum
EAMP voltage output is precisely clamped to the band-gap
voltage.
Skip Mode
With the MODE pin connected to logic high, the device enters
a pulse-skipping mode at light load to minimize the switching
loss by reducing the switching frequency. Figure 22 illustrates
the skip mode operation. A zero-cross sensing circuit (as
shown in Figure 20) monitors the N-Channel MOSFET current
for zero crossing. When it is detected to cross zero for 8
consecutive cycles, the regulator enters the skip mode.
During the 8 consecutive cycles, the inductor current could be
negative. The counter is reset to zero when the sensed NChannel MOSFET current does not cross zero during any
cycle within the 8 consecutive cycles. Once the device enters
the skip mode, the pulse modulation starts being controlled by
the SKIP comparator shown in Figure 20. Each pulse cycle is
still synchronized by the PWM clock. The P-Channel
MOSFET is turned on at the rising edge of clock and turned
off when its current reaches 20% of the peak current limit. As
the average inductor current in each cycle is higher than the
average current of the load, the output voltage rises cycle over
cycle. When the output voltage reaches 1.5% above its
nominal voltage, the P-Channel MOSFET is turned off
immediately and the inductor current is fully discharged to
zero and stays at zero. The output voltage reduces gradually
due to the load current discharging the output capacitor. When
the output voltage drops to the nominal voltage, the PChannel MOSFET will be turned on again, repeating the
previous operations.
The regulator switches to PWM mode operation when the
output voltage is sensed to drop below 1.5% of its nominal
voltage value.
Enable
The enable (EN) pin allows user to enable or disable the
converter for purposes such as power-up sequencing. With
the EN pin pulled to high, the converter is enabled and the
internal reference circuit wakes up first, and then the soft
start-up begins. When the EN pin is pulled to logic low, the
converter is disabled, the P-Channel MOSFET is turned off
immediately, and the output capacitor is discharged through
internal discharge path.
Undervoltage Lockout (UVLO)
When the input voltage is below the Undervoltage Lock Out
(UVLO) threshold, the device is disabled.
The output voltage is regulated by controlling the reference
voltage to the current loop. The band-gap circuit outputs a
0.8V reference voltage to the voltage control loop. The
9
FN6681.1
September 29, 2008
ISL9109
Mode Selection
Power MOSFETs
The MODE pin is provided on ISL9109 to select the
operation mode. When it is driven to logic low or ground, the
regulator operates in forced PWM mode. Under forced PWM
mode, the device remains at the fixed PWM operation
(typical at 1.6MHz), regardless of if the load current is high
or low.
The power MOSFETs are optimized to achieve better
efficiency. The ON-resistance for the P-Channel MOSFET is
typically 0.16 and the typical ON-resistance for the
N-Channel MOSFET is 0.15.
When the MODE pin is driven to logic high or connected to
input voltage VIN, the regulator operates in either SKIP
mode or fixed PWM mode depending on the different load
conditions.
Overcurrent Protection
The overcurrent protection is provided when over load
condition happens. It is realized by monitoring the CSA output
with the OCP comparator, as shown in Figure 20. When the
current at P-Channel MOSFET is sensed to reach the current
limit, the OCP comparator is triggered to turn off the
P-Channel MOSFET immediately.
Short-Circuit Protection
As shown in Figure 20, the device has a Short-Circuit
Protection (SCP) comparator, which monitors the FB pin
voltage for output short-circuit protection. When the FB
voltage is lower than 0.2V, the SCP comparator forces the
PWM oscillator frequency to drop to 1/3 of its normal
operation frequency.
Soft Start-Up
The soft-start-up eliminates the inrush current during the
circuit start-up. The soft-start block outputs a ramp reference
to both the voltage loop and the current loop. The two ramps
limit the inductor current rising speed as well as the output
voltage speed so that the output voltage rises in a controlled
fashion. At the very beginning of the start-up, the output
voltage is less than 0.2V; hence the PWM operating
frequency is 1/3 of the normal frequency.
Low Dropout Operation
The ISL9109 features low dropout operation to maximize the
battery life. When the input voltage drops to a level that the
device can no longer operate under switching regulation to
maintain the output voltage, the P-Channel MOSFET is
completely turned on (100% duty cycle). The dropout
voltage under such condition is the product of the load
current and the ON-resistance of the P-Channel MOSFET.
Minimum required input voltage VIN under this condition is
the sum of output voltage plus the voltage drop cross the
inductor and the P-Channel MOSFET switch.
Thermal Shut Down
The ISL9109 provides built-in thermal protection function.
The thermal shutdown threshold temperature is typical
+160°C with typical +25°C hysteresis. When the internal
temperature is sensed to reach +150°C, the regulator is
completely shut down and as the temperature is sensed to
drop to +125°C (typical), the device resumes operation
starting from the soft-start-up.
STBY
The ISL9109 STBY pin enables the band-gap reference.
This provides a method to quickly start up the buck regulator
and ensure the output voltage reaches 93% of its nominal
value within 60µs when the EN pin is asserted. The
band-gap takes typical 600µs to bias up and stabilize. By
asserting STBY high at least 1ms prior to asserting the EN,
the device can provide a stable output when needed. A
detailed timing diagram is shown in Figure 23.
Standby mode is entered by asserting the EN pin low while
STBY pin is high. To achieve the specified standby operating
current, both EN and STBY pins must be asserted high for at
least 1ms after circuit start-up, before placing the device in
standby mode.
8 CYCLES
CLOCK
CLOCK
20% PEAK CURRENT LIMIT
IIL
L
00
1.015*V
OUT_NOMINAL
1.015*V
OUT_NOMINAL
VOUT
VOUT
VOUT_NOMINAL
VOUT_NOMINAL
FIGURE 22. SKIP MODE OPERATION WAVEFORMS
10
FN6681.1
September 29, 2008
ISL9109
Applications Information
VIN
STBY
EN
BAND-GAP
VOUT
400µS~1ms
1ms
BAND-GAP WAKE-UP WAIT
30µs
25µs
VOUT
BIAS UP SOFT_START
25µs
BIAS UP
BAND-GAP OFF @
30µs
VOUT SOFT-START EN=STBY=Low
400~800µs
BAND-GAP
WAKE-UP
25µs
BIAS UP
400~800µs
VOUT SOFT-START
FIGURE 23. TIMING DIAGRAM
Inductor and Output Capacitor Selection
Input Capacitor Selection
To achieve better steady state and transient response, typically
a 2.2µH inductor can be used. The peak-to-peak inductor
current ripple can be expressed as follows in Equation 1:
The main function for the input capacitor is to provide
decoupling of the parasitic inductance and to provide filtering
function to prevent the switching current from flowing back to
the battery rail. A 10µF/6.3V ceramic capacitor (X5R or X7R)
is a good starting point for the input capacitor selection.
VO 

V O   1 – ---------
V

IN
I = --------------------------------------L  fS
(EQ. 1)
Output Voltage Setting Resistor Selection
In Equation 1, usually the typical values can be used but to
have a more conservative estimation; the inductance should
consider the value with worst case tolerance. For switching
frequency fS, the minimum fS from the “Electrical
Specifications” table on page 2 can be used.
To select the inductor, its saturation current rating should be at
least higher than the sum of the maximum output current and
half of the delta calculated from Equation 1. Another more
conservative approach is to select the inductor with the current
rating higher than the P-Channel MOSFET peak current limit.
Another consideration is the inductor DC resistance since it
directly affects the efficiency of the converter. Ideally, the
inductor with the lower DC resistance should be considered
to achieve higher efficiency.
Inductor specifications could be different from different
manufacturers so please check with each manufacturer if
additional information is needed.
For the output capacitor, a ceramic capacitor can be used
because of the low ESR values, which helps to minimize the
output voltage ripple. A typical value of 10µF/6.3V ceramic
capacitor should be enough for most of the applications and
the capacitor should be X5R or X7R.
11
The voltage divider resistors, R1 and R2, (as shown in
Figure 19), set the desired output voltage value. The output
voltage can be calculated using Equation 2:
R 1

V O = V FB   1 + -------
R 2

(EQ. 2)
Where VFB is the feedback voltage (typically it is 0.8V). The
current flowing through the voltage divider resistors can be
calculated as VO/(R1 + R2), so larger resistance is desirable
to minimize this current. On the other hand, the FB pin has
leakage current that will cause error in the output voltage
setting. The leakage current has a typical value of 0.1µA. To
minimize the accuracy impact on the output voltage, select
the R2 no larger than 200k.
C3 (shown in Figure 19) is highly recommended to be added
for improving stability, and achieving better transient
response. C3 should be 120pF or less to meet the 60µs
maximum soft-startup time when STBY = 1.
Table 1 provides the recommended component values for
some output voltage options.
FN6681.1
September 29, 2008
ISL9109
Layout Recommendation
The PCB layout is a very important converter design step to
make sure the designed converter works well, especially
under the high current high switching frequency condition.
For ISL9109, the power loop is composed of the output
inductor L, the output capacitor COUT, the SW pin and the
GND pin. It is necessary to make the power loop as small as
possible and the connecting traces among them should be
direct, short and wide; the same type of traces should be
used to connect the VIN pin, the input capacitor CIN and its
ground. The switching node of the converter, the SW pin,
and the traces connected to this node are very noisy, so
keep the voltage feedback trace and other noise sensitive
traces away from these noisy traces.
The input capacitor should be placed as close as possible to
the VIN pin. The ground of the input and output capacitors
should be connected as close as possible as well.
The heat of the IC is mainly dissipated through the thermal
pad. Maximizing the copper area connected to the thermal
pad is preferable. In addition, a solid ground plane is helpful
for EMI performance.
TABLE 1. ISL9109 CIRCUIT CONFIGURATION vs VOUT
VOUT
(V)
L
(µH)
C2
(µF)
R1
(k)
C3
(pF)
R2
(k)
0.8
2.2
10
0
N/A
100
1.0
2.2
10
44.2
120
178
1.2
2.2
10
80.6
120
162
1.5
2.2
10
84.5
100
97.6
1.8
2.2
10
100
100
80.6
2.5
2.2
10
100
100
47.5
2.8
2.2
10
100
100
40.2
3.3
2.2
10
102
100
32.4
12
FN6681.1
September 29, 2008
ISL9109
Dual Flat No-Lead Plastic Package (DFN)
L8.2x3
2X
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
0.15 C A
A
D
2X
0.15 C B
E
MILLIMETERS
SYMBOL
MIN
A
0.80
A1
-
6
A3
INDEX
AREA
b
TOP VIEW
D2
//
0.10
A
SIDE VIEW
C
SEATING
PLANE
D2
(DATUM B)
C
0.08 C
0.20
A3
7
8
0.90
1.00
-
-
0.05
-
0.25
0.32
1
5,8
1.50
1.65
1.75
7,8
3.00 BSC
1.65
e
1.80
1.90
7,8
0.50 BSC
-
k
0.20
-
-
-
L
0.30
0.40
0.50
8
N
8
Nd
4
D2/2
6
INDEX
AREA
NOTES
2.00 BSC
E
E2
MAX
0.20 REF
D
B
NOMINAL
2
3
Rev. 0 6/04
2
NX k
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
(DATUM A)
E2
4. All dimensions are in millimeters. Angles are in degrees.
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
NX L
N N-1
NX b
e
8
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
5
0.10
(Nd-1)Xe
REF.
M C A B
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
BOTTOM VIEW
CL
(A1)
NX (b)
L
5
SECTION "C-C"
C C
e
TERMINAL TIP
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN6681.1
September 29, 2008
Similar pages