0.5kHz-125MHz, MHz to KHz Programmable Clock

0.5kHz-125MHz, MHz to KHz Programmable Clock T M
FEATURES
DESCRIPTION
 Designed for Very Low-Power applications
 Accepts Crystal or Reference Clock inputs
 Input Frequency:
o Fundamental crystal: 10MHz to 50MHz
o Reference Input: 1MHz to 125MHz
 Accepts >0.1V reference signal input voltage
 Output Frequency 0.5kHz to 125MHz CMOS.
o 65MHz @ 1.8V operation
o 90MHz @ 2.5V operation
o 125MHz @ 3.3V operation
 One programmable I/O pin can be configured as
OE, PDB, FSEL or CLK1
 Low current consumption:
o <1.0mA with 27MHz & 32kHz outputs
o < 5µA when PDB is activated
 Single 1.8V ~ 3.3V, ± 10% power supply
 Operating temperature range from -40C to 85C
 Available in 6-pin DFN, SOT23, and SC70
GREEN/RoHS compliant packages.
The PL611s-18 is a low-cost general purpose
frequency synthesizer and a member of PhaseLink’s
PicoPLL family, the worlds smallest programmable
clocks. PhaseLink’s PL611s-18 offers the versatility
of using a single Crystal (MHz) or Reference Clock
input and producing up to two (kHz/MHz) system
clocks, or a combination of Reference and low
frequency outputs. The PL611s-18 is designed for
low-power applications with very stringent space
requirements and consumes ~1.0mA, while
producing 2 distinct outputs of 27MHz and 32kHz.
The power down feature of PL611s-18, when
activated, allows the IC to consume less than 5µA of
power.
The PL611s-18 fits in a small DFN, SC70, or SOT23
package. Cascading of the PL611s-18 with other
PhaseLink programmable clocks allow generating
system level clocking requirements, thereby
reducing the overall system implementation cost.
In addition, one programmable I/O pin can be
configured as Output Enable (OE), Frequency
switching (FSEL), Power Down (PDB) input, or CLK1
(CLK0, F REF , F REF /2) output.
BLOCK DIAGRAM
REF
Programmable
CLoad
VCO
OUT
REF
VCO
Programmable Function
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/25/08 Page 1
0.5kHz-125MHz, MHz to KHz Programmable Clock T M
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
F OUT = F REF * M / (R * P)
Where M=8 bit
R= 5 bit
P= 14 bit
CLK0 = F OUT , F REF or F REF / (2*P)
CLK1 = F REF , F REF /2, CLK0 or CLK0/2
Output Drive Strength
Programmable
Input/Output
Three optional drive strengths to
choose from:
One output pin can be configured
as:
 Low: 4mA
 Std: 8mA (default)
 High: 16mA





OE - input
FSEL - input
PDB – input
CLK1 – output
Programmable CLoad
PACKAGE PIN CONFIGURATION AND ASSIGNMENT
6
5
4
XOUT
GND
2
XIN/FIN
3
OE,PDB,FSEL,CLK1
VDD
DFN-6L
(2.0mmx1.3mmx0.6mm)
Name
6
VDD
5
OE, PDB,
FSEL, CLK1
4
XOUT
CLK0
1
GND
2
XIN/FIN
3
SC70-6L
(2.3mmx2.25mmx1.0mm)
Pin Assignment
DFN
SC70
SOT
Pin #
Pin#
Pin#
Type
3
3
I
Crystal or Reference input pin.
GND
2
2
2
P
GND connection
CLK0
3
1
1
O
Programmable Clock Output
VDD
4
6
6
P
VDD connection
5
5
I/O
6
4
4
O
5
OE, PDB,
FSEL, CLK1
4
XOUT
This programmable I/O pin can be configured as an Output
Enable (OE) input, Power Down input (PDB), Frequency Select
input (FSEL) or CLK1 output. This pin has an internal 60KΩ
pull up resistor on OE, PDB and FSEL.
State
OE
PDB
FSEL
0
1 (default)
XOUT
VDD
Description
1
5
6
SOT23-6L
(3.0mmx3.0mmx1.35mm)
XIN, FIN
OE, PDB,
FSEL, CLK1
PL611s-18
1
2
3
PL611s-18
XIN/FIN
GND
CLK0
PL611s-18
1
CLK0
Tri-state CLK
Operating mode
Power Down Mode
Operating mode
Bank 0
Bank 1
Crystal Output pin. Do Not Connect if FIN is used.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/25/08 Page 2
0.5kHz-125MHz, MHz to KHz Programmable Clock T M
FUNCTIONAL DESCRIPTION
PL611s-18 is a highly featured, very flexible, advanced programmable PLL design for high performance, lowpower, small form-factor applications. The PL611s-18 accepts a crystal input of 10MHz to 50MHz or a reference
clock input of 1MHz to 125MHz and is capable of producing two outputs up to 125MHz. This flexible design allows
the PL611s-18 to deliver any PLL generated frequency, F REF (Crystal or Ref Clk) frequency or F REF /(2*P) to CLK0
and/or CLK1. Some of the design features of the PL611s-18 are mentioned below:
PLL Programming
The PLL in the PL611s-18 is fully programmable.
The PLL is equipped with a 5-bit input frequency
divider (R-Counter), and an 8-bit VCO frequency
feedback loop divider (M-Counter). The output of
the PLL is transferred to a 14-bit post VCO divider
(P-Counter). The output frequency is determined by
the following formula [F OUT = F REF * M / (R * P) ].
Clock Output (CLK0)
CLK0 is the main clock output. The PL611s-18 can
also be programmed to provide a second clock
output, CLK1, on the programmable I/O pin (see
OE/PDB/FSEL/CLK1 pin description below). The
output of CLK0 can be configured as the PLL output
(F VCO /(2*P)), F REF (Ref Clk Frequency) output, or
F REF /(2*P) output. The output drive level can be
programmed to Low Drive (4mA), Standard Drive
(8mA) or High Drive (16mA). The maximum output
frequency is 125MHz.
Clock Output (CLK1)
The CLK1 feature allows the PL611s-18 to have an
additional clock output. This output can be
programmed to one of the following:
F REF
F REF / 2
CLK0
CLK0 / 2
Output Enable (OE)
The Output Enable feature allows the user to enable
and disable the clock output(s) by toggling the OE
pin. The OE pin incorporates a 60kΩ pull up resistor
giving a default condition of logic “1”. Pulling the OE
pin low “0” will tri-state the output buffers.
Power-Down Control (PDB)
The Power Down (PDB) feature allows the user to put
the PL611s-18 into “Sleep Mode”. When activated
(logic ‘0’), PDB ‘Disables the PLL, the oscillator
circuitry, counters, and all other active circuitry and
tri-state the output buffers. In Power Down mode the
IC consumes <5µA of power. The PDB pin
incorporates a pull up resistor giving a default
condition of logic “1”.
Frequency Select (FSEL)
The Frequency Select (FSEL) feature allows the
PL611s-18 to switch between two pre-programmed
outputs allowing the device “On the Fly” frequency
switching. The FSEL pin incorporates a 60kΩ pull up
resistor giving a default condition of logic “1”.
Programmable CLoad
The PL611s-18 is equipped with programmable SCaps to allow the Cload to be tuned from 8pF to
12pF.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/25/08 Page 3
0.5kHz-125MHz, MHz to KHz Programmable Clock T M
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
V DD
-0.5
7
V
Input Voltage Range
VI
-0.5
V DD +0.5
V
Output Voltage Range
VO
-0.5
V DD +0.5
V
260
C
Supply Voltage Range
Soldering Temperature (Green package)
10
Data Retention @ 85C
Storage Temperature
TS
Ambient Operating Temperature*
Year
-65
150
C
-40
85
C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
DC SPECIFICATIONS
PARAMETERS
SYMBOL
CONDITIONS
MIN.
@ V DD =3.3V, 27MHz Xtal input,
F VCO =81MHz, CLK0=32.768kHz,
CLK1=27MHz, load=15pF
@ V DD =2.5V, 27MHz Xtal input,
F VCO =81MHz, CLK0=32.768kHz,
CLK1=27MHz, load=10pF
@ V DD =1.8V, 27MHz Xtal input,
F VCO =81MHz, CLK0=32.768kHz,
CLK1=27MHz, load=5pF
@ V DD =3.3V, 27MHz Xtal input,
CLK0=32.768kHz, CLK1=27MHz,
load=15pF
@ V DD =2.5V, , 27MHz Xtal input,
CLK0=32.768kHz, CLK1=27MHz,
load=10pF
@ V DD =1.8V, , 27MHz Xtal input,
CLK0=32.768kHz, CLK1=27MHz,
load=5pF
When PDB=0
Supply Current, Dynamic
I DD
Supply Current, Dynamic
I DD
Supply Current, Dynamic
I DD
PLL Off: Supply Current,
Dynamic
I DD
PLL Off: Supply Current,
Dynamic
I DD
PLL Off: Supply Current,
Dynamic
I DD
Supply Current, Dynamic
I DD
Operating Voltage
V DD
Output Low Voltage
V OL
I OL = +4mA Standard Drive
Output High Voltage
V OH
I OH = -4mA Standard Drive
Output Current, Low Drive
I OSD
Output Current, Std Drive
Output Current, High Drive
1.62
TYP.
MAX.
UNITS
3.95
mA
2.35
mA
1.30
mA
2.75
mA
1.3
mA
0.9
mA
5
µA
3.63
V
0.4
V
V DD – 0.4
V
V OL = 0.4V, V OH = 2.4V
4
mA
I OSD
V OL = 0.4V, V OH = 2.4V
8
mA
I OHD
V OL = 0.4V, V OH = 2.4V
16
mA
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/25/08 Page 4
0.5kHz-125MHz, MHz to KHz Programmable Clock T M
AC SPECIFICATIONS
PARAMETERS
Crystal Input Frequency
CONDITIONS
Fundamental Crystal
MIN.
TYP.
10
@ V DD =3.3V
Input (FIN) Frequency
@ V DD =2.5V
UNITS
50
MHz
125
1
90
@ V DD =1.8V
Input (FIN) Signal Amplitude Internally AC coupled (High Frequency)
MAX.
MHz
65
0.9
V DD
Vpp
0.1
VDD
Vpp
@ V DD =3.3V
125
MHz
@ V DD =2.5V
90
MHz
@ V DD =1.8V
65
MHz
Settling Time
At power-up (after V DD increases over 1.62V)
2
ms
Output Enable Time
OE Function; Ta=25º C, 15pF Load. Add one
clock period for a useable output.
10
ns
PDB Function; Ta=25º C, 15pF Load
2
ms
2
ppm
Input (FIN) Signal Amplitude
Output Frequency
Internally AC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
VDD Sensitivity
Frequency vs. V DD +/-10%
Output Rise Time
15pF Load, 10/90% V DD , Std. Drive, 3.3V
2.0
3.0
ns
Output Fall Time
15pF Load, 90/10% V DD , Std. Drive, 3.3V
2.0
3.0
ns
Duty Cycle
V DD /2
50
55
%
Period Jitter,Pk-to-Pk*
With capacitive decoupling between V DD and
(10,000 samples measured) GND.
-2
45
70
ps
* Note: Jitter performance depends on the programming parameters.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/25/08 Page 5
0.5kHz-125MHz, MHz to KHz Programmable Clock T M
CRYSTAL SPECIFICATIONS
PARAMETERS
Fundamental Crystal Resonator Frequency
Crystal Loading Rating
(The IC can be programmed for any value in this range.)
SYMBOL
MIN.
F XIN
C L (xtal)
TYP.
MAX.
UNITS
10
50
MHz
8
12
pF
100
W
Maximum Sustainable Drive Level
Operating Drive Level
Metal Can Crystal
Small SMD Crystal
W
30
Shunt Capacitance
ESR Max
Shunt Capacitance
ESR Max
C0
5.5
pF
ESR
50
Ω
C0
2.5
pF
ESR
80
Ω
PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION
DFN-6L Evaluation Board
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination
Considerations
Decoupling and Power Supply
Considerations
- Keep traces short!
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Trace = Inductor. With a capacitive load this
equals ringing!
- Long trace = Transmission Line. Without proper
termination this will cause reflections ( looks like
ringing ).
- Design long traces( > 1 inch ) as “striplines” or
“microstrips” with defined impedance.
- Match trace at one side to avoid reflections
bouncing back and forth.
- Multiple VDD pins should be decoupled separately
for best performance.
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency
dependant. Typical values to use are 0.1F for
designs using crystals < 50MHz and 0.01F for
designs using crystals > 50MHz.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/25/08 Page 6
0.5kHz-125MHz, MHz to KHz Programmable Clock T M
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/25/08 Page 7
0.5kHz-125MHz, MHz to KHz Programmable Clock T M
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
SOT23-6L
Symbol
A
A1
A2
b
c
D
E
H
L
e
Dimension in MM
Min.
Max.
1.05
1.35
0.05
0.15
1.00
1.20
0.30
0.50
0.08
0.20
2.80
3.00
1.50
1.70
2.60
3.0
0.35
0.55
0.95 BSC
Pin1 Dot
E
H
D
A2 A
A1
C
b
e
L
SC70-6L
Symbol
A
A1
A2
b
c
D
E
H
L
e
Dimension in MM
Min.
Max.
0.80
1.00
0.00
0.09
0.80
0.91
0.15
0.30
0.08
0.25
1.85
2.25
1.15
1.35
2.00
2.30
0.21
0.41
0.65BSC
Pin1 Dot
E
H
D
A2 A
A1
C
b
e
L
DFN-6L
D1
Symbol
A
A1
A3
b
e
D
E
D1
E1
L
Dimension in MM
Min.
Max.
0.50
0.60
0.00
0.05
0.152
0.152
0.15
0.25
0.40BSC
1.25
1.35
1.95
2.05
0.75
0.85
0.95
1.05
0.20
0.30
b
e
D
Pin 6 ID
Chamfer
E
E1
L
Pin1 Dot
A A1
A3
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/25/08 Page 8
0.5kHz-125MHz, MHz to KHz Programmable Clock T M
ORDERING INFORMATION (GREEN PACKAGE)
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
PL611s-18-XXX X X X
PART NUMBER
3 DIGIT ID Code *
(will be assigned at
programming time)
PACKAGE TYPE
G=DFN-6L
U=SC70-6L
T=SOT23-6L
NONE= TUBE
R=TAPE and REEL
TEMPERATURE
C=COMMERCIAL (0°C to 70°C)
I = INDUSTRIAL (-40°C to 85°C)
* PhaseLink will assign a unique 3-digit ID code for each approved programmed part number.
Part /Order Number
†
Marking†
Package Option
PL611s-18-XXXGC-R
XXX
6-Pin DFN (Tape and Reel)
PL611s-18-XXXUC-R
XXX
6-Pin SC70 (Tape and Reel)
PL611s-18-XXXTC-R
18XXX
6-Pin SOT23 (Tape and Reel)
Note: ‘XXX’ designates marking identifier that, at times, could be independent of the part number.
Please consult your PhaseLink sales representative for marking information.
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/25/08 Page 9