TM PRELIMINARY CT T ODU CEMEN 7 R P E A 74 T L OLE REP 00-442-7 OBS ENDED 8 M ns 1 l.com COM pplicatio Intersi E R @ NO ntral A app cent Ce : l l l i a a C or em HFA3665 CDMA/AMPS Downconverter with AGC Capability May 1999 Features Description • RF Frequency Range . . . . . . . . . . . . 869MHz to 895MHz The HFA3665 is a monolithic bipolar downconverter for CDMA/AMPS cellular applications. Manufactured in the Intersil UHF1X process, the device consists of a low noise cascode amplifier, a double balanced downconversion mixer and a pair of linearized and temperature compensated PIN diode biasing current sources for external RF AGC applications. In addition, the device offers two independent and selectable differential mixer IF output ports to be used with dual mode IF filters and requires low drive levels from the local oscillator. The HFA3665 is one of the four chips in the PRISM™ chip set and is housed in a small outline 28 lead SSOP package ideally suited for cellular handset applications. • IF Operation . . . . . . . . . . . . . . . . . . . . 10MHz to 100MHz • LNA Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16dB • LNA NF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3dB • Mixer Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16dB • Mixer NF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11dB • Single Supply Battery Operation . . . . . . . . 2.7V to 3.3V • Power Enable/Disable Control • PIN Diode Attenuator DC Control Applications Ordering Information • IS95A CDMA/AMPS Dual Mode Handsets • Wideband CDMA Handsets TEMP. RANGE (oC) PART NUMBER PKG. NO. PACKAGE • CDMA/TDMA Packet Protocol Radios HFA3665IA -40 to 85 28 Ld SSOP • Full Duplex Transceivers HFA3665IA96 -40 to 85 Tape and Reel M28.15 • Portable Battery Powered Equipment Pinout Block Diagram HFA3665 (SSOP) TOP VIEW LNA_OUT RF_IN CDMA_OUT- VCC 1 AGC_CTRL 2 PIN_O_IBIAS1 3 GND 4 PIN_O_IBIAS1 25 MIX_IND LNA_OUT 6 23 RF_RET GND 7 22 MIX_GND GND 8 21 LO_RET PIN_I_GND 11 CDMA_OUT+ 26 MIX_VCC 24 RF_IN PIN_O_IBIAS2 10 LNA 27 SEL LNA_OUT 5 LNA_IN 9 LNA_IN 28 MIX_VCC PIN_O_IBIAS2 SEL SW C T R L FM_OUTBIAS FM_OUT+ RX_PE AGC_CTRL 20 LO_IN LO_IN 19 CDMA_OUT18 CDMA_OUT+ RX_PE 12 17 FM_OUT- R_REF 13 16 FM_OUT+ BIAS_GND 14 15 BIAS_VCC PRISM™ and the PRISM™ logo are trademarks of Intersil Corporation. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Intersil Corporation 1999 1 File Number 4301.5 HFA3665 Pin Descriptions PIN NUMBER NAME DESCRIPTION 1 VCC LNA and PIN diode bias control Power Supply.Use high quality RF decoupling capacitors at the pin. 2 AGC_CTRL AGC control current input pin. Requires a 9.53K 1% resistor for scale factor and temperature compensation of the current sources. 3 PIN_O_IBIAS1 4 GND 5, 6 LNA_OUT 7, 8 GND 9 LNA_IN 10 PIN_O_IBIAS2 11 PIN_I_GND 12 RX_PE Power enable control input. HIGH for normal operation. LOW for power down. 13 R_REF Bias setting resistor. 523Ω 1% for optimum performance and parameter distribution. 14 BIAS_GND Reference circuit ground return. 15 BIAS_VCC Reference circuit Power Supply. Use high quality RF decoupling capacitors right at the pin. 16 FM_OUT+ Positive IF FM output. Open collector PNP. Requires a DC return to ground. 17 FM_OUT- Negative IF FM output. Open collector PNP. Requires a DC return to ground. 18 CDMA_OUT+ Positive IF CDMA output. Open collector PNP. Requires a DC return to ground. 19 CDMA_OUT- Negative IF CDMA output. Open collector PNP. Requires a DC return to ground. 20 LO_IN Mixer Local Oscillator input. Requires AC coupling and directly matches to 50Ω. 21 LO_RET 22 MIX_GND 23 RF_RET 24 RF_IN 25 MIX_IND Mixer common mode bias inductor. Use a RF choke to ground with high impedance at 900MHz. Low loss inductors with parallel resonance close to 900MHz are ideal. 26, 28 MIX_VCC Mixer Power Supply Pins.Use high quality RF decoupling capacitors at each one of the pins. 27 SEL Selects the CDMA or the FM output IF amplifier. HIGH selects the CDMA amplifier. LOW the FM amplifier output. Current output for a PIN diode bias control. Use a 2200pF filter capacitor to ground. LNA bias ground return. LNA open collector output. This pins are internally bonded to the same device output. LNA RF ground return. Degeneration (inductance) can be added to this pin. LNA input. Second current output for PIN diode bias control. Use a 2200pF filter capacitor to ground. PIN diode bias control ground return. Mixer Local Oscillator complementary input. Requires a bypass capacitor to ground as a return reference. Mixer ground return. MIxer RF port complementary input. Requires a bypass capacitor to ground as a return reference. Mixer RF input. Requires AC coupling and a match network to 50Ω. 2 HFA3665 Absolute Maximum Ratings Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Temperature Range . . . . . . . . . . . . . . -40oC ≤ TA ≤ 85oC Maximum Storage Temperature Range . . . . . ..-65oC ≤ TA ≤ 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (Lead Tips Only) Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 3.6V Voltage on Any Other Pin except 5 and 6 (6.0V) . -0.3 to VCC +0.3V Operating Conditions Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V to 3.3V Temperature Range . . . . . . . . . . . . . . . . . . . . . . -40oC ≤ TA ≤ 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER (NOTE 2) TEST LEVEL TEST CONDITION TEMP (oC) MIN TYP MAX UNITS LNA SPECIFICATIONS AT 885MHz, VCC = 3.0V,VLNA = 3.0V unless otherwise specified (Test schematics as in page 5) RF Frequency Range Output Match net. B 25 869 - 895 MHz Power Gain -30dBm input A 25 14 16.0 17.5 dB IP3I, Input referenced 3rd Order Intercept VLNA = 3.0V A 25 - +2 - dBm VLNA = 3.6V A 25 - +6 - dBm VLNA = 5.0V A 25 - +7.5 - dBm IP1dB, Input Referenced Compression Point VLNA = 3.6V A 25 - -7 - dBm Noise Figure B 25 - 2.3 - dB Input VSWR A 25 - 2.2:1 2.5:1 - A 25 - 1.6:1 2.0:1 - RF Frequency Range (Typical) B 25 869 - 895 MHz IF Frequency Range B 25 10 85 100 MHz LO Frequency Range (Typical) B 25 954 - 980 MHz Output VSWR Output network as in the Apps. diagram MIXER SPECIFICATIONS AT -3dBm LO at 970MHz AND IF of 85MHz Power Conversion Gain Note 3 A 25 15.1 16.7 18.3 dB Voltage Conversion Gain Differential IF output load = 2.95K B 25 - 34.4 - dB B 25 - - 0.6 dB B 25 - 10.6 11.4 dB IP3I, Input Referenced 3rd Order Intercept A 25 0 2.6 - dBm IP1dB, Input Referenced Compression Point A 25 - -10 - dBm LO Drive Level A 25 -6 -3 0 dBm LO to IF Isolation A 25 - 30 - LO to RF Isolation A 25 20 32 - dB A 25 - 1.6:1 2:1 - Gain Flatness Across the RF Freq. Range Noise Figure, SSB RF VSWR Note 3 Input network as in the Apps diagram 3 HFA3665 Electrical Specifications (Continued) (NOTE 2) TEST LEVEL TEMP (oC) MIN TYP MAX UNITS LO VSWR A 25 - 2.0:1 - - IF Output Parallel Resistance CDMA or FM port (85MHz) Single End to GND. B 25 - 12.4 - kΩ IF Output Parallel Capacitance CDMA or FM port (85MHz) Single End to GND. B 25 - 1.7 - pF PARAMETER TEST CONDITION PIN DIODE BIAS CURRENT SOURCE SPECIFICATIONS (EACH OUTPUT Terminated into 0.7V) Typical PIN diode AGC Range Application schematic. B Full 33 38 - dB AGC_CTRL Voltage control Range Rseries = 9.53K A 25 0.5 - 2.5 V PIN_O_IBIAS Max. Source Current. AGC_CTRL = 2.0V A 25 - 5.2 - mA PIN_O_IBIAS Current AGC_CTRL = 1.8 A 25 - 3.0 - mA AGC_CTRL = 1.4V A 25 - 0.47 - mA AGC_CTRL = 1.0V A 25 - 0.04 - mA PIN_O_BIAS Leakage current AGC_CTRL = 0.5V A 25 - 0.0 - mA PIN_O_IBIAS Current Vs Temperature AGC_CTRL = 1.8V B 25 - 200 - µA/oC PIN_O_IBIAS Current Vs Supply Voltage AGC_CTRL = 1.8V B 25 - 330 - µA/V Supply Voltage B 25 2.7 - 3.3 V LNA Power supply (VLNA) C 25 2.7 - 5.5 V SEL And RX_PE,VIL A 25 - - 0.8 V SEL And RX_PE,VIH A 25 2.0 - - V SEL AND RX_PE, Input Bias Currents at VCC VIH = 3.0V = 3.0V VIL = 0.0V A 25 -200 - +200 µA A 25 -200 - +200 µA LNA/Mixer Supply Current AGC_CTRL = 0.5V A 25 - 45 - mA Total PIN Diode Bias Circuit Supply Current AGC_CTRL = 1.8V B 25 - 11 - mA Power Down Supply Current RX_PE = Low A 25 - 10 100 µA B 25 - - 10 µs POWER SUPPLY AND LOGIC SPECIFICATIONS Power Down Speed NOTES: 2. A = Production Tested, B = Based on Characterization, C = By Design 3. Output differential to single end match network to 50Ω for both CDMA and FM IF ports (Production Test Diagram in page 5). 4 HFA3665 Production Test Diagram MIXER RF IN 50Ω VCC 220p 220p 0.1 1 9.53k AGC MIX_VCC VCC 47p 2 C1 47p SEL AGC_CTRL SEL 2200p 3 PIN_O_IBIAS1 4 GND MIX_V CC PIN BIAS 1 220p 0.1 18n C3 LNA OUT MIX_IND LNA_OUT 1.5p 50Ω RF_IN VLNA 4.7p 100p ? 5 15n 8.2n 100p 7 NOTE 4 8 MIX_GND R9 LNA_OUT LNA_GND 6 LO_RET 50Ω 15p 12p 100p LNA IN 50Ω 9 LO_IN LNA_IN CDMA_OUT- 10 PIN_O_IBIAS2 PIN BIAS 2 RF_LO_INPUT RF_RET 220nH 100p 7.5p 6.6K 220nH 2200p 11 PIN_I_GND CDMA_OUT+ FM_OUT- 0.01 12 RX_PE 330nH 12p PE CDMA IF OUTPUT 50Ω 13 R_REF 523 1% HFA3665 FM_OUT+ 14 BIAS_GND 220nH BIAS_VCC 7.5p 6.6K 0.33 220nH 100p 330nH 12p FM IF OUTPUT 50Ω NOTE: 4. PC trace degeneration inductor. 93mil by 8mil trace terminating in a 10mil via. Via is tied to a buried solid ground plane 12mils deep. Material is FR4 Er = 4.7. 5 Typical RF Front End AGC Application Diagram S+M B4691 8.2n L11 R3 4p 4p C7 C1 R4 12 12 12p C2 82n L1 PIN VCC 220p AGC 1 VCC 2 AGC_CTRL MIX_VCC 49.9k R2 C3 3 PIN_O_IBIAS1 4 GND MIX_VCC 6 8.2n 100p 7 LE NOTE 5 8 100p C5 C4 13p 9 RF_RET LNA_OUT LO_RET L4 PIN C6 2200p 4.7p 100p ? C9 C8 RF_LO_INPUT 15p 12p SAWTEK 855292 LO_IN LNA_IN 270n 82n 49.9K R5 L5 18n 15n L6 MIX_GND 1.5p L2 RF_IN LNA_OUT LNA_GND 5 0.1 220p MIX_IND C13 VLNA C7 SEL SEL 2200p Note 1 47p 47p C1 0.33 CDMA_OUT- 10 PIN_O_IBIAS2 100p L7 25.3p C9 CDMA OUTPUT R1 9.53k 220p 6.2K R7 11 PIN_I_GND L8 0.01 CDMA_OUT+ FM_OUT- 12 RX_PE C10 25.3p 270n PE 13 R_REF 523 1% HFA3665 R6 L9 R8 6.2K FM_OUT+ 14 BIAS_GND BIAS_VCC 6.6p C12 FM OUTPUT FROM PA L10 0.33 100p 390n 5p C11 330n MURATA SX439A PIN DIODE: MACOM MA4P282-1141 DUPLEXER: DFY2RR836CR881BHHN NOTE: 5. LNA degeneration inductance built with a PC trace to ground in combination with VLNA power supply to improve IIP3. A transmission line inductance of 1.2nH at 882MHz to a solid ground plane is typical (see Test Diagram). 6 HFA3665 DESIGN INFORMATION External AGC Application Components Description (Please refer to Typical RF and Front End AGC Application Diagram) NOTE:In order to avoid input insertion losses and maintain the Noise Figure of this application optimized, the VSWR of the LNA input attenuator scheme is directly impacted by the input shunt PIN diode impedance when AGC is in action. This mismatch is absorbed by the duplexer/filter and there is no significant impact in its duplex characteristics to both antenna and transmitter ports. LE adds degeneration to the LNA input for higher input intercept points. This combination of degeneration and a higher LNA VCC (VLNA) improves considerably the input intercept point with a slight decrease in gain. LE shall have very high Q and can be build with a small PC trace. R3 and R4 limit the output attenuation range and output VSWR. L1 and L4 permit DC biasing of the PIN diodes and RF isolation. Several types of 82nH inductors have SRF near 900MHz thus maximizing the RF isolation. R1 sets the scale factor, temperature coefficient and range of the gain control voltage. L2 and C13 are part of the output matching network and provides the DC bias path for the open collector output. R2 sets the turn-on point for the output PIN diode attenuator and R5 sets the turn-on point for the input PIN diode attenuator by shunting to ground some of the PIN diode bias current. By making R5 a smaller value than R2, the output attenuator turns on first, to optimize NF. Making R5 = R2 will turn both PIN diodes simultaneously to optimize the IIP3 during the initial AGC action. The R2/R5 combination can be tailored to specific AGC characteristics. R7 and R8 define the Real part of the CDMA and FM output ports impedances. Unloaded “Q” of the coils used for proper biasing of these ports have to be taken into account when defining these values. The total load presented to these ports also define the achievable gain of the mixers. Because there is no internal feedback between the complementary ports of the differential channel, the loads and ports can be split into independent ports referenced to ground. R6 generates the reference current which is used to set the operating point of all the major RF and IF transistors. A proportional to temperature (PTAT) voltage of about 37mVat25oC is applied to this resistor. PTAT biasing keeps the gain temperature independent. A 10% variation from 523Ω is allowed. Lower values increase the total LNA and Mixer bias currents. C1 filters noise from the gain control source to reduce unwanted AM modulation. L7, L8 and L9, L10 have two functions: They provide a DC path to ground required for proper operation of the CDMA and FM differential outputs and can also be part of the match network between these ports and IF filters. C9, C10 and C12 are part of a match network to the suggested filters. L9, L10 and C12 are part of a current summer network for a differential to single end conversion. L12, L13 and C11 form a high “Q” match network between the converter and the suggested filter for the SAW IP3 distortion optimization. C2 and C4 provide DC isolation for PIN diode biasing. Their values are chosen to provide series resonance cancelling of the diode package and PC board inductances. All other unlabeled components on the schematics are bypass/decoupling capacitors. Values are chosen based on their SRF. C3 and C6 decouple the PIN diode bias pins. Failure to decouple these pins may cause LNA oscillations. 7 HFA3665 Shrink Small Outline Plastic Packages (SSOP) M28.15 N INDEX AREA 0.25(0.010) M H 28 LEAD SHRINK NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E 1 2 INCHES GAUGE PLANE -B3 0.25 0.010 SEATING PLANE -A- h x 45o A D -C- e 0.17(0.007) M α A2 A1 B L C A M SYMBOL MIN MAX MIN MAX NOTES A 0.053 0.069 1.35 1.75 - A1 0.004 0.010 0.10 0.25 - A2 - 0.061 - 1.54 - B 0.008 0.012 0.20 0.30 9 C 0.007 0.010 0.18 0.25 - D 0.386 0.394 9.81 10.00 3 E 0.150 0.157 3.81 3.98 4 e C 0.10(0.004) B S NOTES: 0.025 BSC 0.635 BSC - H 0.228 0.244 5.80 6.19 - h 0.0099 0.0196 0.26 0.49 5 L 0.016 0.050 0.41 1.27 6 8o 0o N α 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. MILLIMETERS 28 0o 28 7 8o Rev. 0 2/95 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 8 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369