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TERSIL
1-888-IN
DATASHEET
PRAM Four-Channel Programmable Operational Amplifier
HA-2400/883
Features
HA-2400/883 is a four-channel programmable amplifier
providing a level of versatility unsurpassed by any other
monolithic operational amplifier. Versatility is achieved by
employing four input amplifier channels, any one (or none) of
which may be electronically selected and connected to a single
output stage through DTL/TTL compatible address inputs. The
device formed by the output and the selected pair of inputs is
an op amp which delivers excellent slew rate, gain bandwidth
and power bandwidth performance. Other advantageous
features for these dielectrically isolated amplifiers include high
voltage gain and input impedance coupled with low input
offset voltage and offset current. External compensation is not
required on this device at closed loop gains greater than 10.
• This Circuit is Processed in Accordance to MIL-STD-883 and
is Fully Conformant Under the Provisions of Paragraph 1.2.1.
Each channel of the HA-2400/883 can be controlled and
operated with suitable feedback networks in any of the
standard op amp configurations. This specialization makes
these amplifiers excellent components for multiplexing, signal
selection and mathematical function designs. With 20V/µs
slew rate, 20MHz gain bandwidth and low input bias currents
makes this device an ideal building block for signal generators,
active filters and data acquisition designs. Programmability,
coupled with 9mV typical offset voltage and 50nA offset
current, makes these amplifiers outstanding components for
signal conditioning circuits.
Pin Configuration
+
2
-
+IN4 3
+
-IN4
4
-
-IN1
5
-
• Wide Gain Bandwidth
- Uncompensated . . . . . . . . . . . . . . . . . . . . . . . . . . 20MHz Min
- Compensated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4MHz Min
• High Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50kV/V
• Low Offset Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50nA
• Single Capacitor Compensation for Unity Gain
• DTL/TTL Compatible Inputs
Applications
• Single Selection/Multiplexing
• Op Amp Gain Stage
• Frequency Oscillator
• Filter Characteristics
• Add-Subtract Functions
• Comparator Levels
Ordering Information
DECODE
CONTROL
33
-IN3
• High Slew Rate
- Uncompensated . . . . . . . . . . . . . . . . . . . . . . . . . 20V/µs Min
- Compensated . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/µs Min
• Integrator Characteristics
HA1-2400/883
(CERDIP)
TOP VIEW)
+IN3 1
• Digital Programmability
16 D0
PART #
15 D1
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
PKG.
DWG. #
HA1-2400/883 HA1-2400/883 -55 to +125 16 Ld CERDIP F16.3
14 ENABLE
4
13 GND
12
1
+IN1 6
+
-IN2
-
7
11
COMP
V+
10 OUT
2
+IN2 8
+
OUTPUT AMP
9
V-
TRUTH TABLE
D1
D0
EN
SELECTED CHANNEL
L
L
H
1
L
H
H
2
H
L
H
3
H
H
H
4
X
X
L
None
April 9, 2012
FN3926.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 1994, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HA-2400/883
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . 45V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VSUPPLY
Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to VDigital Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.76V to +10V
Peak Output Current (Short Circuit Protected) . . . . . . . . . . ., ISC < ±33mA)
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<2000V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
CerDIP Package (Note 1). . . . . . . . . . . . . . .
91
25
Internal Power Dissipation
Package Power Dissipation Limit at +75°C for TJ ≤ +175°C
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.11W
Package Power Dissipation Derating Factor Above +75°C
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1mW/°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . +300°C
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V
Negative Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-15V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: V+ = +15V, V- = -15V, RS = 100Ω , RL = 500kΩ, VO = 0V, unless otherwise specified. Digital Inputs: VIL = +0.5V, VIH = +2.4V, limits apply
to each of the four channels, when addressed.
PARAMETER
Offset Voltage
Input Bias Current
SYMBOL
VIO
+IB
-IB
Input Offset
Current
Common Mode
Range
IIO
+CMR
-CMR
Large Signal
Voltage Gain
Common Mode
Rejection Ratio
AV
+CMRR
-CMRR
Output Voltage
Swing
+VOUT
-VOUT
Output Current
CONDITIONS
VCM = 0V
VCM = 0V, +RS = 100kΩ, -RS = 100Ω
VCM = 0V, +RS = 100Ω, -RS = 100kΩ
VCM = 0V, +RS = 100kΩ, -RS = 100kΩ
V+ = +6V, V- = -24V, VOUT = -9V
V+ = +24V, V- = -6V, VOUT = +9V
VOUT = -10V to +10V, RL = 2kΩ
VCM = +5V, V+ = +10V, V- = -20V, VOUT = -5V
VCM = -5V, V+ = +20V, V- = -10V, VOUT = +5V
RL = 2kΩ
RL = 2kΩ
GROUP A
SUBGROUPS
TEMP (°C)
MIN
MAX
UNITS
1
+25
-9
9
mV
2, 3
+125, -55
-11
11
mV
1
+25
-200
200
nA
2, 3
+125, -55
-400
400
nA
1
+25
-200
200
nA
2, 3
+125, -55
-400
400
nA
1
+25
-50
50
nA
2, 3
+125, -55
-100
100
nA
1
+25
9
-
V
2, 3
+125, -55
9
-
V
1
+25
-
-9
V
2, 3
+125, -55
-
-9
V
4
+25
50
-
kV/V
5, 6
+125, -55
25
-
kV/V
1
+25
80
-
dB
2, 3
+125, -55
80
-
dB
1
+25
80
-
dB
2, 3
+125, -55
80
-
dB
4
+25
10
-
V
5, 6
+125, -55
10
-
V
4
+25
-
-10
V
5, 6
+125, -55
-
-10
V
+IOUT
VOUT = +10V
4
+25
10
-
mA
-IOUT
VOUT = -10V
4
+25
-
-10
mA
2
FN3926.0
April 9, 2012
HA-2400/883
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Tested at: V+ = +15V, V- = -15V, RS = 100Ω , RL = 500kΩ, VO = 0V, unless otherwise specified. Digital Inputs: VIL = +0.5V, VIH = +2.4V, limits apply
to each of the four channels, when addressed.
PARAMETER
SYMBOL
Supply Current
CONDITIONS
+ICC
TEMP (°C)
MIN
MAX
UNITS
1
+25
-
6
mA
2, 3
+125, -55
-
7
mA
1
+25
-6
-
mA
2, 3
+125, -55
-7
-
mA
1
+25
74
-
dB
2, 3
+125, -55
74
-
dB
1
+25
74
-
dB
2, 3
+125, -55
74
-
dB
VOUT = 0V
-ICC
Power Supply
Rejection Ratio
GROUP A
SUBGROUPS
VOUT = 0V
VSUP = ±5V
V+ = +20V, V- = -15V
V+ = +10V, V- = -15V
+PSRR
VSUP = ±5V
V+ = +15V, V- = -20V
V+ = +15V, V- = -10V
-PSRR
Crosstalk
CT
VIN = ±10V
1
+25
-80
-
dB
Digital Logic
Current
IIL
VIL = 0V
1
+25
-
1.5
mA
2, 3
+125, -55
-
1.5
mA
1
+25
-
1
µA
2, 3
+125, -55
-
1
µA
IIH
VIH = 5.0V
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: V+ = +15V, V- = -15V, RL = 2kΩ , CLOAD = 50pF, unless otherwise specified. Digital Inputs: VIL = +0.5V, VIH = +2.4V, limits apply to each
of the four channels, when addressed.
PARAMETER
SYMBOL
Slew Rate (Note 2)
Rise and Fall Time
Overshoot
CONDITIONS
GROUP A
SUBGROUPS
TEMP (°C)
MIN
MAX
UNITS
+SR1
VOUT = -5V to +5V
7
+25
6
-
V/µs
-SR1
VOUT = +5V to -5V
7
+25
6
-
V/µs
tR1
VOUT = 0 to +200mV
7
+25
-
45
ns
tF1
VOUT = 0 to -200mV
7
+25
-
45
ns
+OS1
VOUT = 0 to +200mV
7
+25
-
40
%
-OS1
VOUT = 0 to -200mV
7
+25
-
40
%
NOTES:
2. AV = +1, CCOMP = 15pF.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Characterized at: V+ = 15V, V- = -15V, unless otherwise specified.
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMP (°C)
MIN
MAX
UNITS
Unity Gain Bandwidth
UGBW1
AV = +1V, CCOMP = 15pF, RL = 2kΩ, CL = 50pF
3
+25
4
-
MHz
Gain Bandwidth Product
GBWP2
AV = +10V, CCOMP = 0pF, RL = 2kΩ, CL = 50pF
3
+25
20
-
MHz
Full Power Bandwidth1
FPBW1
RL = 2kΩ, AV = +1V, VO = ±10V, CL = 50pF,
CCOMP = 15pF
3, 4
+25
95
-
kHz
Full Power Bandwidth2
FPBW2
RL = 2kΩ, AV = +10V, VO = ±10V, CL = 50pF,
CCOMP = 0pF
3, 4
+25
300
-
kHz
3
+25
-
2.5
µs
Settling Time
TSET1
3
AV = +1V, CCOMP = 15pF, RL = 2kΩ, CL = 50pF,
VO = 10VP-P, to 0.1% F.V., Logic Control = +5.0V
FN3926.0
April 9, 2012
HA-2400/883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Characterized at: V+ = 15V, V- = -15V, unless otherwise specified.
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMP (°C)
MIN
MAX
UNITS
+SR2
VOUT = -5V to +5V, RL = 2kΩ, CL = 50pF, AV = +10V,
CCOMP = 0pF
3
+25
20
-
V/µs
-SR2
VOUT = +5V to -5V, RL = 2kΩ, CL = 50pF, AV = +10V,
CCOMP = 0pF
3
+25
20
-
V/µs
Output Delay
TDEL
RL = 2kΩ, CL = 50pF, CCOMP = 15pF, VIN = +5V
3
+25
-
250
ns
Minimum Closed Loop
Stability
CLS1
RL = 2kΩ, CL = 50pF, CCOMP = 15pF
3
+25
1
-
V/V
CLS2
RL = 2kΩ, CL = 50pF, CCOMP = 0pF
3
+25
10
-
V/V
Slew Rate (Note 5)
NOTES:
3. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab
characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from
multiple production runs which reflect lot to lot and within lot variation.
4. FPBW = Slew Rate/(2VPEAK).
5. AV = +10, CCOMP = 0pF.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
Interim Electrical Parameters (Pre Burn-In)
Final Electrical Test Parameters
SUBGROUPS (SEE TABLES 1 AND 2)
1
1 (Note 6), 2, 3, 4, 5, 6, 7
Group A Test Requirements
1, 2, 3, 4, 5, 6, 7
Groups C and D Endpoints
1
NOTES:
6. PDA applies to Subgroup 1 only.
7. The subgroup assignments of the parameters in these tables were patterned after DESC SMD
#5962-87783.
4
FN3926.0
April 9, 2012
HA-2400/883
Test Circuit
*Includes Stray Capacitance
All Capacitors = ±10% (µF)
All Resistors = ±1% (Ω)
DUT Pin numbers refer to 14 Ld CerDIP package
For detailed information, refer to AN514
Test Waveforms
SLEW RATE WAVEFORMS
OVERSHOOT, RISE AND FALL TIME WAVEFORMS
5
FN3926.0
April 9, 2012
HA-2400/883
Burn-In Circuit
HA-2400/883 CERAMIC DIP
NOTES:
R1 = 100kΩ/socket, 5% 1/4W (min)
C1 = C2 = 0.01µF per socket (min) or 0.1µF per row (min)
C3 = 0.001µF per socket, 10%
D1, D2 = 1N4002 or equivalent per board
| (V+) - (V-) | = 30V
f0 = 100kHz
f1 = 50kHz
f2 = 25kHz
50% Duty Cycle
Schematic Diagram
1 IN+
R2
2.4k
Q1
R3
1.8k
R1
1.6k
Q3
Q5
Q2
R12
1.6k
VE
1 IN-
R13
0.8k
Q29
Q28
R18
2.0k
R5
8.0k
Q7
Q8 Q9
R6
2.0k
Q32
R14
10k
Q25
Q34
Q98
Q101
Q99
Q12
R33
4k
Q35
Q103
Q37
Q36
Q33
Q18
Q87
Q19
Q22
Q24
Q38
Q41
Q23
VD
Q39
Q40
Q13
R11
10k
Q94 Q95
Q96
Q91
R15
10k
Q42
R16
10k
R17
1.6k
D0
6
Q93
TO ADDITIONAL
INPUT STAGES
VA
R10
10k
Q92
Q89
Q90
Q17
VB
1.2k
R32
34
OUT
R31
36.5
Q88
VC
Q14
R8
4k
R9
Q16 1.5k
Q86
R30
R35
0.75k
Q100
Q97
C1
9.0pF
V+
Q11
Q15
Q85
Q20 Q21
R7
5.6k
Q10
GND
Q102
Q26
Q27
R35
1.6k
Q84
Q80
Q31
R34
1.6k
Q83
Q6
ENABLE
+VCC
Q82
Q81
Q79
Q30
Q4
R4
22.9k
COMP
R19
1.6k
D1
R29
0.4k
-VEE
FN3926.0
April 9, 2012
HA-2400/883
Die Characteristics
DIE DIMENSIONS:
88mils x 67mils x 19mils ± 1mil
2240µm x 1710µmx 483µm ± 25.4µm
METALLIZATION:
GLASSIVATION:
Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.)
Silox Thickness: 12kÅ  2kÅ
Nitride Thickness: 3.5kÅ  1.5kÅ
WORST CASE CURRENT DENSITY:
0.7 x 105A/cm2
Type: Al, 1% Cu
Thickness: 16kÅ 2kÅ
SUBSTRATE POTENTIAL (Powered Up): Unbiased
TRANSISTOR COUNT: 251
PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
HA-2400/883
7
FN3926.0
April 9, 2012
HA-2400/883
The information contained in this section has been developed through characterization and is for use as application and design aid only. These
characteristics are not 100% tested and no product guarantee is implied.
Typical Performance Characteristics
Devices Characterized at: : VS = 15V, VIL = +0.5V, VIH = +2.4V. Values apply to each of the four channels, when addressed
PARAMETER
TEST CONDITIONS
TEMP.
(°C)
TYP
UNITS
Offset Voltage
VCM = 0V
+25
4
mV
Bias Current
VCM = 0V
+25
50
nA
Offset Current
VCM = 0V
+25
5
nA
+25
30
MΩ
Input Resistance
Large Signal Voltage Gain
RL = 2kΩVO = 20VP-P
+25
150
kV/V
Common Mode Rejection Ratio
VCM = 5VDC
Full
100
dB
Gain Bandwidth Product
RL = 2kΩ, CL = 50pF, CCOMP = 0pF, AV = +10V
+25
40
MHz
Unity Gain Bandwidth
RL = 2kΩ, CL = 50pF, CCOMP = 15pF, AV = +1V
+25
8
MHz
Output Voltage Swing
RL = 2kΩ
Full
12
V
Output Current
VOUT = ±10V
+25
20
mA
FPBW1
VP = 10V (Note 8)
+25
475
kHz
FPBW2
VP = 10V (Note 8)
+25
125
kHz
Rise Time
RL = 2kΩ, CL = 50pF, CCOMP = 15pF, AV = +1V
+25
20
ns
Overshoot
RL = 2kΩ, CL = 50pF, CCOMP = 15pF, AV = +1V
+25
25
%
Slew Rate1
AV = +1V/V
+25
8
V/µs
Slew Rate2
AV = +10V/V
+25
30
V/µs
Settling Time1
VO = 10VP-P to 0.1%
+25
1.5
µs
Digital Logic Current
VIN = +5.0V
Full
5
nA
VIN = 0V
Full
1
mA
Output Delay
To 10% of Final Value
+25
100
ns
Crosstalk
Unselected Input to Output, VIN = ±10VDC
+25
-110
dB
Supply Current
Not Loaded
+25
4.8
mA
PSRR
VS = 10V
Full
90
dB
NOTE:
8. FPBW = Slew Rate/(2VPEAK).
8
FN3926.0
April 9, 2012
HA-2400/883
The information contained in this section has been developed through characterization and is for use as application and design information only. No
guarantee is implied.
Typical Performance Curves
V± = ±15V, TA = +25°C, unless otherwise specified.
5
140
VSUPPLY = 20V
VSUPPLY = 15V
VSUPPLY = 10V
SUPPLY CURRENT (mA)
120
80
60
BIAS CURRENT
40
10
OFFSET CURRENT
5
0
-55
-50
-25
0
25
50
TEMPERATURE (°C)
75
100
3
125
1.2
-50
-25
120
BANDWIDTH
1.1
1.0
SLEW RATE
0.9
-55
-50
-25
0
25
50
TEMPERATURE (°C)
75
100
100
125
CROSSTALK REJECTION, AV = +1
0
30
80
60
60
PHASE 90
40
120
20
150
0
CCOMP = 0pF
CCOMP = 15pF
100
1k
180
GAIN
10k
100k
1M
FREQUENCY (Hz)
10M
210
100M
1.0
BANDWIDTH
SLEW RATE
15
SUPPLY VOLTAGE (V)
20
FIGURE 5. NORMALIZED AC PARAMETERS vs SUPPLY VOLTAGE
9
OPEN LOOP VOLTAGE GAIN (dB)
120
1.1
0.8
10
75
FIGURE 4. OPEN LOOP FREQUENCY AND PHASE RESPONSE
1.2
0.9
0
25
50
TEMPERATURE (°C)
100
-20
10
125
FIGURE 3. NORMALIZED AC PARAMETERS vs TEMPERATURE
NORMALIZED VALUE REFERRED TO 15V
-55
FIGURE 2. POWER SUPPLY CURRENT DRAIN AS A FUNCTION OF
TEMPERATURE
OPEN LOOP VOLTAGE GAIN (dB)
NORMALIZED VALUE REFERRED TO +25°C
FIGURE 1. INPUT BIAS CURRENT AND OFFSET CURRENT AS A
FUNCTION OF TEMPERATURE
0.8
4
PHASE ANGLE (DEGREES)
CURRENT (nA)
100
100
0pF
15pF
30pF
80
60
40
20
100pF
300pF
1000pF
0
-20
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
FIGURE 6. FREQUENCY RESPONSE vs CCOMP
FN3926.0
April 9, 2012
HA-2400/883
The information contained in this section has been developed through characterization and is for use as application and design information only. No
guarantee is implied.
Typical Performance Curves
V± = ±15V, TA = +25°C, unless otherwise specified. (Continued)
110
OUTPUT SWING (VP-P)
100
95
90
-55
-50
-25
0
25
50
TEMPERATURE (°C)
75
100
CCOMP = 0pF
CCOMP = 15pF
20
10
1.0
0.1
10k
125
FIGURE 7. OPEN LOOP VOLTAGE GAIN vs TEMPERATURE
100
INPUT NOISE (µV)
GAIN (dB)
105
VSUPPLY = 20V
VSUPPLY = 15V
VSUPPLY = 10V
100k
1M
FREQUENCY (Hz)
10M
FIGURE 8. OUTPUT VOLTAGE SWING
UPPER 3dB FREQUENCY
LOWER 3dB FREQUENCY-10Hz
BROADBAND NOISE CHARACTERISTICS
10
10k SOURCE RESISTANCE
0 SOURCE RESISTANCE
1.0
THERMAL NOISE OF 10k RESISTOR
0.1
100Hz
1kHz
10kHz
100kHz
1MHz
FIGURE 9. EQUIVALENT INPUT NOISE vs BANDWIDTH
10
FN3926.0
April 9, 2012
HA-2400/883
Typical Applications (See Application Note AN514)
I1
Sample Charging Rate ---- V/s
C
I2
Hold Drift Rate ---- V/s
C
Q
Switch Pedestal Error --C V
FIGURE 10. AMPLIFIER, NON-INVERTING PROGRAMMABLE GAIN
11
I1 ≈ 150 x 10-6A
I2 ≈ 200 x 10-9A @ +25°C
≈ 600 x 10-9A @ -55°C
≈ 100 x 10-9A @ +125°C
Q ≈ 2 x 10-12 Coulombs
FIGURE 11. SAMPLE AND HOLD
FN3926.0
April 9, 2012
HA-2400/883
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
BASE
METAL
(c)
E
M
-Bbbb S
C A-B S
Q
-C-
SEATING
PLANE
S1
b2
b
ccc M
C A-B S
eA/2
-
0.200
-
5.08
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.840
-
21.34
5
E
0.220
0.310
5.59
7.87
5
c
aaa M C A - B S D S
D S
NOTES
0.014
eA
e
MAX
b

A A
MIN
A
A
L
MILLIMETERS
MAX
M
(b)
D
BASE
PLANE
MIN
b1
SECTION A-A
D S
INCHES
SYMBOL
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
105o
90o
105o
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.

90o
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
16
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
16
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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12
FN3926.0
April 9, 2012
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