DATASHEET

HS-2510RH
TM
Data Sheet
August 1999
Radiation Hardened High Slew Rate
Operational Amplifier
FN3592.2
Features
• Electrically Screened to SMD # 5962-95686
The HS-2510RH is a radiation hardened high performance
operational amplifier which set the standard for maximum
slew rate and wide bandwidth operation in moderately
powered, internally compensated, monolithic devices. In
addition to excellent dynamic characteristics, this
dielectrically isolated amplifier also offers low offset current
and high input impedance.
The ±50V/ms minimum slew rate and fast settling time of the
HS-2510RH are ideally suited for high speed D/A, A/D, and
pulse amplification designs. The HS-2510RH superior
bandwidth and 750kHz minimum full power bandwidth are
extremely useful in RF and video applications. To insure
compliance with slew rate and transient response
specifications, all devices are 100% tested for AC
performance characteristics over full temperature limits. To
improve signal conditioning accuracy, the HS-2510RH
provides a maximum offset current of 25nA and a minimum
input impedance of 50MΩ, both at 25oC, as well as offset
voltage trim capability.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95686. A “hot-link” is provided
on our homepage for downloading.
• QML Qualified per MIL-PRF-38535 Requirements
• High Slew Rate . . . . . . . . . . . 50V/µs (Min), 65V/µs (Typ)
• Wide Power Bandwidth . . . . . . . . . . . . . . . . 750kHz (Min)
• Low Offset Current . . . . . . . . . . . . 25nA (Min), 10nA (Typ)
• High Input Impedance . . . . . . . 50MΩ (Min), 100MΩ (Typ)
• Wide Small Signal Bandwidth . . . . . . . . . . . 12MHz (Typ)
• Fast Settling Time (0.1% of 10V Step). . . . . . 250ns (Typ)
• Low Quiescent Supply Current . . . . . . . . . . . . 6mA (Max)
• Internally Compensated For Unity Gain Stability
• Total Gamma Dose . . . . . . . . . . . . . . . . . . . . 10kRAD(Si)
Applications
• Data Acquisition Systems
• RF Amplifiers
• Video Amplifiers
• Signal Generators
• Pulse Amplification
Ordering Information
INTERNAL
MKT. NUMBER
ORDERING NUMBER
TEMP. RANGE
(oC)
5962D9568601VPA
HS7-2510RH-Q
-55 to 125
5962D9568601VPC
HS7B-2510RH-Q
-55 to 125
5962D9568601VXC
HS9-2510RH-Q
-55 to 125
Pinouts
HS-2510RH GDIP1-T8 (CERDIP)
OR
HS-2510RH CDIP2-T8 (SBDIP)
TOP VIEW
BAL
1
IN-
2
IN+
V-
3
-
+
4
8
COMP
7
V+
6
OUT
5
1
BAL
HS-2510RH
CDFP3-F14 (FLATPACK)
TOP VIEW
NC 1
14 NC
COMP 2
13 V+
BAL 3
IN- 4
IN+ 5
12 OUT
-
+
11 BAL
10 V-
NC 6
9 NC
NC 7
8 NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
HS-2510RH
Test Circuit
+VCC
ACOUT
-1/10
V1
0.1
100K
1
2K
1 OPEN
S7
3
BAL
ADJ
2 S3A
S1
2
1
S2
1 S6
1
1
OPEN
FOR LOOP STABILITY,
USE MIN VALUE CAPACITOR
TO PREVENT OSCILLATION
OPEN
1
2
50K
2
DUT
500K
-
S5B 1
+
2
1
1
-
+
2
2
BUFFER
V2
2K
0.1
VAC
100
1
3
-1
+
S9
OPEN
S8
OPEN
OPEN 2
100K 2 S3B
100
S5A
1
OPEN 2
50pF (NOTE 1)
10K
-VEE
1K
x2
5K
EOUT
2
S4
ALL RESISTORS = ±1% (Ω)
ALL CAPACITORS = ±10% (µF)
1
50K
NOTE:
1. Includes stray capacitances.
FIGURE 1. SIMPLIFIED TEST CIRCUIT
Test Circuit and Waveforms
+15V
INPUT
OUTPUT
+
1K
-
2K
50pF
-15V
FIGURE 2. SIMPLIFIED TEST CIRCUIT
+200mV
+5V
INPUT
0V
INPUT
-200mV
0V
-5V
+5V
OVERSHOOT
90%
∆V
OUTPUT
90%
OUTPUT
10%
10%
-5V
SLEW
RATE
= ∆V/∆T
∆T
NOTE: Measured on both positive and negative transitions.
Capacitance at Compensation pin should be minimized.
FIGURE 3. SLEW RATE WAVEFORM
2
RISE TIME
NOTE: Measured on both positive and negative transitions.
Capacitance at Compensation pin should be minimized.
FIGURE 4. TRANSIENT RESPONSE WAVEFORM
HS-2510RH
Typical Performance Curves
Unless Otherwise Specified: TA = 25oC, VSUPPLY = ±15V
100
90
80
BIAS CURRENT
85
GAIN (dB)
CURRENT (nA)
60
40
20
VS = ±20V
VS = ±15
80
OFFSET CURRENT
VS = ±10
0
-20
75
-50
-25
0
25
50
75
100
125
-50
-55
TEMPERATURE (oC)
FIGURE 5. INPUT BIAS AND OFFSET CURRENT vs
TEMPERATURE
25
50
75
100
125
TEMPERATURE (oC)
NORMALIZED PARAMETERS
REFERRED TO VALUES AT ±15V
1.1
10K SOURCE RESISTANCE
10
0 SOURCE RESISTANCE
1.0
THERMAL NOISE OF 10K RESISTOR
SLEW RATE
1.0
BANDWIDTH
BANDWIDTH
0.9
SLEW RATE
0.8
0.1
100Hz
1kHz
10kHz
100kHz
±10V
1MHz
±15V
UPPER 3dB FREQUENCY LOWER 3dB FREQUENCY (10Hz)
FIGURE 7. EQUIVALENT INPUT NOISE vs BANDWIDTH
FIGURE 8. NORMALIZED AC PARAMETERS vs SUPPLY
VOLTAGE AT 25oC
PEAK-TO-PEAK VOLTAGE SWING
35
BANDWIDTH
SLEW RATE
1.0
SLEW RATE
BANDWIDTH
0.9
0.8
-50
-55
-25
0
25
50
75
TEMPERATURE (oC)
FIGURE 9. NORMALIZED AC PARAMETERS vs
TEMPERATURE
3
100
125
±20V
SUPPLY VOLTAGE
1.1
NORMALIZED PARAMETERS
REFERRED TO VALUES AT ±25οC
0
FIGURE 6. OPEN LOOP VOLTAGE GAIN vs TEMPERATURE
100
EQUIVALENT INPUT NOISE (µV)
-25
VS = ±20
30
25
VS = ±15
20
15
VS = ±10
10
5
0
10K
100K
1MEG
10MEG
FREQUENCY (Hz)
FIGURE 10. OUTPUT VOLTAGE SWING vs FREQUENCY
AT 25oC
HS-2510RH
Typical Performance Curves
Unless Otherwise Specified: TA = 25oC, VSUPPLY = ±15V (Continued)
4.4
100
4.2
0pF
80
CURRENT (mA)
OPEN-LOOP VOLTAGE GAIN (dB)
120
30pF
60
100pF
40
300pF
20
1000pF
0
100
VS = ±15
VS = ±10
3.8
3.6
3.4
-20
10
VS = ±20
4.0
1K
10K
100K
1M
10M
3.2
100M
-50
-55
FREQUENCY (Hz)
-25
0
25
50
75
100
125
TEMPERATURE (oC)
NOTE: External compensation components are not required for
stability, but may be added to reduce bandwidth, if desired.
FIGURE 12. POWER SUPPLY CURRENT vs TEMPERATURE
FIGURE 11. OPEN LOOP FREQUENCY RESPONSE FOR
VARIOUS VALUES OF CAPACITORS FROM
COMPENSATION PIN TO GROUND
V+
30o
100
60o
80
PHASE
60
90o
40
120o
20
150o
GAIN
20kΩ
PHASE ANGLE
OPEN LOOP VOLTAGE GAIN (dB)
120
RT
IN
BAL
180o
0
OUT
V-
-20
100
1K
10K
100K
1M
10M
100M
NOTE: Tested offset adjustment is |VOS + 1mV| minimum referred
to output typical range is ±8mV for RT = 20kΩ.
FREQUENCY (Hz)
FIGURE 14. SUGGESTED VOS ADJUSTMENT
FIGURE 13. OPEN LOOP GAIN AND PHASE RESPONSE vs
FREQUENCY
INPUT NOISE VOLTAGE (nV/√Hz)
1000
100
INPUT NOISE VOLTAGE
100
10
INPUT NOISE CURRENT
10
1
1
1
10
100
1K
10K
0.1
100K
FREQUENCY (Hz)
FIGURE 15. INPUT NOISE DENSITY vs FREQUENCY
4
INPUT NOISE CURRENT (pA/√Hz)
10
HS-2510RH
Burn-In Circuits
HS7-2510RH CERDIP
1
8
2
7
R1
+
3
HS9-2510RH CERAMIC FLATPACK
V+
6
C3
4
VD2
C1
D1
5
C2
1
14
2
13
3
12
4
11
5
10
R1
NOTES:
6
9
7
8
V+
C3
C1
D1
VC2
D2
NOTES:
2. R1 = 1MΩ, ±5%, 1/4W (Min)
7. R1 = 1MΩ, ±5%, 1/4W (Min)
3. C1 = C2 = 0.01µF/Socket (Min) or 0.1µF/Row (Min)
8. C1 = C2 = 0.01µF/Socket (Min) or 0.1µF/Row (Min)
4. C3 = 0.01µF/Socket (10%)
9. C3 = 0.01µF/Socket (±10%)
5. D1 = D2 = 1N4002 or Equivalent (Per Board)
10. D1 = D2 = 1N4002 or Equivalent (Per Board)
6. |(V+) - (V-)| = 30V
11. |(V+) - (V-)| = 31V ±1V
Irradiation Circuit
HS7-2510RH
C
1
8
2
7
3
6
4
5
R
V2
C
NOTES:
12. V1 = +15V ±10%
13. V2 = -15V ±10%
14. R = 1MΩ ±5%
15. C = 0.1µF ±10%
5
C
V1
HS-2510RH
Schematic Diagram
OFFSET
OFFSET
V+
R6
200
R5
200
Q1
R9
200
R8
200
R11
2K
R7
1.8K
Q2
Q3
R1
4K
Q6
R10
1.8K
Q8
Q10
R12
1.1K
Q16
R2
2K
C2
2.7pF
Q5
R3
960
Q7
R13
30
C1
10pF
Q11
Q9
Q14
OUTPUT
R14
30
Q4
COMP
Q17
Q12
R4
11.13K
Q40
Q37
INPUT+
Q38
Q35
Q19
1.68K
R25
Q29
1.68K
Q39
R19
6.3K
Q30
R23
3K
Q27
Q31
Q25
Q32
R20
3K
Q20
Q23
Q24
Q22
Q21
Q33
Q36
Q13
R26
Q28
Q26
Q34
Q18
Q15
R22
240
R18
1.48K
R17
1.48K
R16
1.48K
R15
740
V-
INPUT-
6
HS-2510RH
Die Characteristics
DIE DIMENSIONS:
Backside Finish:
65 mils x 57 mils x 19 mils
(1660µm x 1950µm x 483µm)
Silicon
ASSEMBLY RELATED INFORMATION:
INTERFACE MATERIALS:
Substrate Potential (Powered Up):
Glassivation:
Unbiased
Type: Nitride
Thickness: 7kÅ ±0.7kÅ
ADDITIONAL INFORMATION:
Worst Case Current Density:
Top Metallization:
<2 x 105A/cm2
Type: Aluminum
Thickness: 16kÅ ±2kÅ
Transistor Count:
40
Substrate:
Linear Bipolar, DI
Die Attach:
Temperature: CERDIP 460oC (Max)
Metallization Mask Layout
HS-2510RH
V+
OUT
BAL
V-
COMP
BAL
-IN
+IN
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
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reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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