DATASHEET

CD4518BMS,
CD4520BMS
CMOS Dual Up Counters
December 1992
Features
Pinout
• High Voltage Types (20V Rating)
CD4518BMS, CD4520BMS
TOP VIEW
• CD4518BMS Dual BCD Up Counter
• CD4520BMS Dual Binary Up Counter
• Medium Speed Operation
- 6MHz Typical Clock Frequency at 10V
CLOCK A
1
16 VDD
ENABLE A
2
15 RESET B
• Positive or Negative Edge Triggering
Q1A
3
14 Q4B
• Synchronous Internal Carry Propagation
Q2A
4
13 Q3B
• 100% Tested for Quiescent Current at 20V
Q3A
5
12 Q2B
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
Q4A
6
11 Q1B
RESET A
7
10 ENABLE B
VSS
8
9 CLOCK B
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Functional Diagram
Applications
3
• Multistage Synchronous Counting
CLOCK A
1
• Multistage Ripple Counting
ENABLE A
2
• Frequency Dividers
÷10/÷16
C
5
6
Description
R
CD4518BMS Dual BCD Up Counter and CD4520BMS Dual
Binary Up Counter each consist of two identical, internally
synchronous 4-stage counters. The counter stages are
D-type flip-flops having interchangeable CLOCK and
ENABLE lines for incrementing on either the positive-going
or negative-going transition. For single unit operation the
ENABLE input is maintained high and the counter advances
on each positive-going transition of the CLOCK. The
counters are cleared by high levels on their RESET lines.
The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while
the CLOCK input of the latter is held low.
Q1A
Q2A
Q3A
Q4A
RESET A
7
11
CLOCK B
9
ENABLE B
10
÷10/÷16
C
Q1B
12
13
14
R
Q2B
Q3B
Q4B
RESET B
15
The CD4518BMS and CD4520BMS are supplied in these
16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4518B Only
4
VSS = 8
VDD = 16
H4S
H1F
*H6P †H6W
†CD4520B Only
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1206
File Number
3342
Specifications CD4518BMS, CD4520BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
θja
θjc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
VDD = 18V
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
VDD = 18V
Output Voltage
Output Voltage
VOL15
VOH15
VDD = 15V, No Load
VDD = 15V, No Load (Note 3)
LIMITS
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
10
µA
2
+125oC
-
1000
µA
3
-55oC
-
10
µA
1
+25oC
-100
-
nA
2
+125oC
-1000
-
nA
3
-55oC
-100
-
nA
1
+25oC
-
100
nA
2
+125oC
-
1000
nA
3
-55oC
-
100
nA
1, 2, 3
+25oC,
+125oC,
-55oC
-
50
mV
1, 2, 3
+25oC,
+125oC,
-55oC
14.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1
+25oC
0.53
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25oC
1.4
-
mA
1
+25oC
3.5
-
mA
1
+25oC
-
-0.53
mA
Output Current (Sink)
Output Current (Source)
IOL15
IOH5A
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1
+25oC
-
-1.8
mA
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
+25oC
-
-1.4
mA
1
+25oC
-
-3.5
mA
1
+25oC
-2.8
-0.7
V
VSS = 0V, IDD = 10µA
1
+25oC
0.7
2.8
V
VDD = 2.8V, VIN = VDD or GND
7
+25oC
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
Output Current (Source)
N Threshold Voltage
P Threshold Voltage
Functional
IOH15
VNTH
VPTH
F
VDD = 15V, VOUT = 13.5V
VDD = 10V, ISS = -10µA
VOH > VOL <
VDD/2 VDD/2
V
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
-
1.5
V
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
3.5
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
-
4
V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
7-1207
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
Specifications CD4518BMS, CD4520BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Propagation Delay
Clock to Output
Propagation Delay
Reset to Ouput
Transition Time
(Note 2)
Maximum Clock Input
Frequency
SYMBOL
TPHL1
TPLH1
TPHL2
TTHL
TTLH
CONDITIONS (NOTE 1, 2)
GROUP A
SUBGROUPS TEMPERATURE
VDD = 5V, VIN = VDD or GND
VDD = 5V, VIN = VDD or GND
VDD = 5V, VIN = VDD or GND
FCL
VDD = 5V, VIN = VDD or GND
LIMITS
MIN
MAX
UNITS
9
+25oC
-
560
ns
10, 11
+125oC, -55oC
-
756
ns
9
+25oC
-
650
ns
10, 11
+125oC, -55oC
-
878
ns
9
+25oC
-
200
ns
10, 11
+125oC, -55oC
-
270
ns
o
9
+25 C
1.5
-
MHz
10, 11
+125oC, -55oC
1.11
-
MHz
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55oC, +25oC
-
5
µA
+125 C
-
150
µA
-55oC, +25oC
-
10
µA
+125oC
-
300
µA
o
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
-55 C, +25 C
-
10
µA
+125oC
-
600
µA
o
o
o
o
Output Voltage
VOL
VDD = 5V, No Load
1, 2
+25 C, +125 C,
-55oC
-
50
mV
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
9.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1, 2
+125oC
0.36
-
mA
-55oC
0.64
-
mA
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
1, 2
1, 2
1, 2
VDD = 5V, VOUT = 2.5V
1, 2
VDD = 10V, VOUT = 9.5V
VDD =15V, VOUT = 13.5V
1, 2
1, 2
+125oC
0.9
-
mA
-55oC
1.6
-
mA
+125oC
2.4
-
mA
-55oC
4.2
-
mA
+125oC
-
-0.36
mA
-55oC
-
-0.64
mA
+125oC
-
-1.15
mA
-55oC
-
-2.0
mA
+125oC
-
-0.9
mA
-55oC
-
-1.6
mA
+125oC
-
-2.4
mA
-55oC
-
-4.2
mA
Input Voltage Low
VIL
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25oC, +125oC,
-55oC
-
3
V
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25oC, +125oC,
-55oC
+7
-
V
7-1208
Specifications CD4518BMS, CD4520BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
TEMPERATURE
MIN
MAX
UNITS
1, 2, 3
+25oC
-
230
ns
Propagation Delay
Clock to Output
TPHL1
TPLH1
VDD = 15V
1, 2, 3
+25 C
-
160
ns
Propagation Delay
Reset to Output
TPHL2
VDD = 10V
1, 2, 3
+25oC
-
225
ns
Transition Time
TTHL
TTLH
Maximum Clock Input
Frequency
FCL
Maximum Clock Rise and
Fall Time
Minimum Enable Pulse
Width
Minimum Reset Pulse
Width
Minimum Clock Pulse
Width
TRCL
TFCL
TW
TW
TW
VDD = 10V
NOTES
CIN
o
VDD = 15V
1, 2, 3
+25 C
-
170
ns
VDD = 10V
1, 2, 3
+25oC
-
100
ns
VDD = 15V
1, 2, 3
+25oC
-
80
ns
o
VDD = 10V
1, 2, 3
+25 C
3
-
MHz
VDD = 15V
1, 2, 3
+25oC
4
-
MHz
VDD = 5V
1, 2, 3, 4
+25oC
-
15
µs
VDD = 10V
1, 2, 3, 4
+25 C
-
5
µs
VDD = 15V
1, 2, 3, 4
+25oC
-
5
µs
o
o
VDD = 5V
1, 2, 3
+25 C
-
400
ns
VDD = 10V
1, 2, 3
+25oC
-
200
ns
VDD = 15V
1, 2, 3
+25oC
-
140
ns
o
VDD = 5V
1, 2, 3
+25 C
-
250
ns
VDD = 10V
1, 2, 3
+25oC
-
110
ns
VDD = 15V
1, 2, 3
+25oC
-
80
ns
o
VDD = 5V
1, 2, 3
+25 C
-
200
ns
VDD = 10V
1, 2, 3
+25oC
-
100
ns
VDD = 15V
Input Capacitance
o
Any Input
o
1, 2, 3
+25 C
-
70
ns
1, 2
+25oC
-
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
IDD
VDD = 20V, VIN = VDD or GND
1, 4
+25oC
-
25
µA
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10µA
1, 4
+25oC
-2.8
-0.2
V
N Threshold Voltage
Delta
∆VTN
VDD = 10V, ISS = -10µA
1, 4
+25oC
-
±1
V
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
1, 4
+25oC
0.2
2.8
V
P Threshold Voltage
Delta
∆VTP
1, 4
oC
-
±1
V
Functional
F
VSS = 0V, IDD = 10µA
VDD = 18V, VIN = VDD or GND
+25
1
+25oC
VOH >
VDD/2
VOL <
VDD/2
V
1, 2, 3, 4
+25oC
-
1.35 x
+25oC
Limit
ns
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
3. See Table 2 for +25oC limit.
NOTES: 1. All voltages referenced to device GND.
4. Read and Record
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
7-1209
Specifications CD4518BMS, CD4520BMS
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
IDD
± 1.0µA
Output Current (Sink)
IOL5
± 20% x Pre-Test Reading
IOH5A
± 20% x Pre-Test Reading
Output Current (Source)
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
100% 5004
1, 7, 9, Deltas
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
100% 5004
2, 3, 8A, 8B, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
CONFORMANCE GROUP
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
Group A
Group B
Group D
READ AND RECORD
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
Group E Subgroup 2
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
Static Burn-In 1
Note 1
3-6, 11-14
1, 2, 7-10, 15
16
Static Burn-In 2
Note 1
3-6, 11-14
8
1, 2, 7, 9, 10,
15, 16
Dynamic BurnIn Note 1
-
7, 8, 15
2, 10, 16
3-6, 11-14
8
1, 2, 7, 9, 10,
15, 16
Irradiation
Note 2
9V ± -0.5V
50kHz
3-6, 11-14
1, 9
25kHz
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
7-1210
CD4518BMS, CD4520BMS
Logic Diagrams
Q1
3/11
VDD
VSS
*
Q2
4/12
D Q
C Q
R
ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
D Q
C Q
R
Q3
5/13
D Q
C Q
R
Q4
6/14
D Q
C Q
R
*
RESET
7/15
*
ENABLE
2/10
*
CLOCK
1/9
FIGURE 1. DECADE COUNTER (CD4518BMS) LOGIC DIAGRAM FOR ONE OF TWO IDENTICAL COUNTERS
VDD
Q1
3/11
Q2
4/12
Q3
5/13
Q4
6/14
VSS
*
ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
D Q
C Q
R
D Q
C Q
R
D Q
C Q
R
D Q
C Q
R
*
RESET
7/15
*
ENABLE
2/10
*
CLOCK
1/9
FIGURE 2. BINARY COUNTER (CD4520BMS) LOGIC DIAGRAM FOR ONE OF TWO IDENTICAL COUNTERS
TRUTH TABLE
CLOCK
ENABLE
RESET
1
0
Increment Counter
0
Increment Counter
0
No Change
0
No Change
0
No Change
0
X
X
0
1
X
X = Don’t Care
ACTION
0
No Change
X
1
Q1 thru Q4 = 0
1 ≡ High State
0 ≡ Low State
7-1211
CD4518BMS, CD4520BMS
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25
20
15
10V
10
5
5V
0
AMBIENT TEMPERATURE (TA) = +25oC
15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
10V
7.5
5.0
2.5
5V
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
0
-5
-10
-15
-10V
-20
-25
-15V
-30
-5
-10V
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
PROPAGATION DELAY TIME (tPLH, tPHL) (ns)
300
SUPPLY VOLTAGE (VDD) = 5V
200
10V
100
15V
50
0
20
30
40
50
60
70
80
LOAD CAPACITANCE (CL) (pF)
90
-15
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
10
-10
-15V
350
150
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
250
0
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
0
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
30
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
Typical Performance Curves
100
FIGURE 7. TYPICAL PROPAGATION DELAY vs LOAD CAPACITANCE, CLOCK OR ENABLE TO OUTPUT
350
AMBIENT TEMPERATURE (TA) = +25oC
300
SUPPLY VOLTAGE (VDD) = 5V
250
200
150
10V
100
15V
50
0
10
20
30
40
50
60
70
80 90
LOAD CAPACITANCE (CL) (pF)
100
110
FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE, RESET TO OUTPUT
7-1212
CD4518BMS, CD4520BMS
MAXIMUM CLOCK FREQUENCY (fCL MAX) (MHz)
Typical Performance Curves
TRANSITION TIME (tTHL, tTLH) (ns)
AMBIENT TEMPERATURE (TA) = +25oC
200
150
SUPPLY VOLTAGE (VDD) = 5V
100
10V
15V
50
0
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
POWER DISSIPATION /CONVERTER (PD) (µW)
FIGURE 9. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE
AMBIENT TEMPERATURE (TA) = +25oC
LOAD CAPACITANCE (CL) = 50PF
15
10
5
0
5
10
15
SUPPLY VOLTAGE (VDD) (V)
FIGURE 10. TYPICAL MAXIMUM CLOCK FREQUENCY vs
SUPPLY VOLTAGE
104 8
6
4 SUPPLY VOLTAGE (VDD) = 15V
2
103 8
6
4
2
10V
102 8
10V
6
4
2
5V
CL = 50pF
10 8
CL = 15pF
6
4
2
AMBIENT TEMPERATURE (TA) = +25oC
1
2
4 68
0.1
2
4 68
1
2
4 68
2
4 68
102
10
2
4 68
103
104
FREQUENCY (f) (kHz)
FIGURE 11. TYPICAL POWER DISSIPATION CHARACTERISTICS
Timing Diagrams
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
1
2
3
4
5
6
7
8
9
0
5
6
7
8
9
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
2
3
CLOCK
ENABLE
RESET
1
2
3
4
0
Q1
CD4518BMS
Q2
Q3
Q4
Q1
CD4520BMS
20
Q2
Q3
Q4
FIGURE 12. TIMING DIAGRAMS FOR CD4518BMS AND CD4520BMS
7-1213
4
CD4518BMS, CD4520BMS
CLOCK
INPUT
VDD
1
7
2
9
15
10
1
7
2
9
15
10
CLOCK ENABLE RESET
A
A
A
CLOCK ENABLE RESET
B
B
B
CLOCK ENABLE RESET
A
A
A
CLOCK ENABLE RESET
B
B
B
Q1A Q2A Q3A Q4A
Q1B Q2B Q3B Q4B
Q1A Q2A Q3A Q4A
Q1B Q2B Q3B Q4B
3
4
5
6
11
12
13
14
3
4
5
CD4518BMS/20BMS
6
11
12
13
14
CD4518BMS/20BMS
FIGURE 13. RIPPLE CASCADING OF FOUR COUNTERS WITH POSITIVE EDGE TRIGGERING
CD4071
CLOCK*
INPUT
1
3
2
CLOCK ENABLE RESET
A
A
A
Q1A Q2A Q3A Q4A
3
4
5
6
9
15
10
1
3
2
CLOCK ENABLE RESET
B
B
B
CLOCK ENABLE RESET
A
A
A
Q1B Q2B Q3B Q4B
Q1A Q2A Q3A Q4A
11
12
13
14
3
CD4520BMS
CD4012A
CD4071
4
5
6
9
15
10
CLOCK ENABLE RESET
B
B
B
Q1B Q2B Q3B Q4B
11
12
13
14
CD4520BMS
CD4012A
CD4012A
CD4520BMS
* For synchronous cascading, the clock transition time should be made less than or equal to the sum of the fixed propagation delay at 15pF
and the transition time of the output driver stage for the estimated capacitive load.
FIGURE 14. SYNCHRONOUS CASCADING OF FOUR BINARY COUNTERS WITH NEGATIVE EDGE TRIGGERING
7-1214
CD4518BMS, CD4520BMS
Chip Dimensions and Pad Layouts
CD4518BMS
CD4520BMS
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION:
PASSIVATION:
Thickness: 11kÅ − 14kÅ,
AL.
10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
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1215
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