DATASHEET

CD14538BMS
TM
CMOS Dual Precision
Monostable Multivibrator
November 1994
Features
Description
• High-Voltage Type (20V Rating)
• Retriggerable/Resettable Capability
• Trigger and Reset Propagation Delays Independent of RX, CX
• Triggering From Leading or Trailing Edge
• Q and Q Buffered Outputs Available
• Separate Resets
• Wide Range of Output-Pulse Widths
• Schmitt-Trigger Input Allows Unlimited Rise
and Fall Times On +TR and -TR Inputs
• 100% Tested For Maximum Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over
Full Package-Temperature Range:
- 100nA at 18V and +25oC
• Noise Margin (Full Package-Temperature
Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative
Standards No. 13B, “Standard Specifications for Description of “B” Series CMOS
Device’s
CD14538BMS dual precision monostable multivibrator provides stable retriggerable/resettable one-shot operation for any fixed-voltage timing application.
Applications
An external resistor (RX) and an external capacitor (CX) control the timing and
accuracy for the circuit. Adjustment of RX and CX provides a wide range of output pulse widths from the Q and Q terminals. The time delay from trigger input to
output transition (trigger propagation delay) and the time delay from reset input
to output transition (reset propagation delay) are independent of RX and CX. Precision control of output pulse widths is achieved through linear CMOS techniques.
Leading-edge-triggering (+TR) and trailing-edge-triggering (-TR) inputs are provided for triggering from either edge of an input pulse. An unused +TR input
should be tied to VSS. An unused -TR input should be tied to VDD. A RESET
(on low level) is provided for immediate termination of the output pulse or to prevent output pulses when power is turned on. An unused RESET input should be
tied to VDD. However, if an entire section of the CD14538BMS is not used, its
inputs must be tied to either VDD or VSS. See Table 1.
In normal operation the circuit retriggers (extends the output pulse one period)
on the application of each new trigger pulse. For operation in the non-retriggerable mode, Q is connected to -TR when leading-edge triggering (+TR) is used
or Q is connected to +TR when trailing-edge triggering (-TR) is used. The time
period (T) for this multivibrator can be calculated by: T = RXCX.
The minimum value of external resistance, RX is 4KΩ. The minimum and maximum values of external capacitance, CX, are 0pF and 100µF, respectively.
The CD14538BMS is interchangeable with type MC14538 and is similar to and
pin-compatible with the CD4098B* and CD4538B**.
* T = 0.5 RXCX for C X ≥ 1000pF.
* T = RXCX; CX min = 5000pF.
The CD14538BMS is supplied in these 16-lead outline packages:
Braze Seal DIP
H4X
Frit Seal DIP
H1L
Ceramic Flatpack H6W
• Pulse Delay and Timing
• Pulse Shaping
Pinout
Functional Diagram
CX1
CD14538BMS
TOP VIEW
VDD
1
CX1
1
16 VDD
RXCX (1)
2
15 CX2
RESET (1) 3
14 RXCX (2)
+TR (1) 4
13 RESET (2)
-TR (1) 5
12 +TR (2)
Q1 6
11 -TR (2)
Q1 7
10 Q2
8
9 Q2
VSS
RX1
2
+TR 4
-TR 5
RESET 3
6 Q1
MONO1
7 Q1
+TR 12
-TR 11
10 Q2
MONO2
RESET 13
VDD = 16
VSS = 8
9 Q2
15
14 RXCX(2)
VDD
CX2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
7-640
RXCX(1)
RX2
FN3192
Specifications CD14538BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
θja
θjc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
o
Maximum Package Power Dissipation (PD) at +125 C
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
GROUP A
SUBGROUPS
IIH
VIN = VDD or GND
TEMPERATURE
MIN
+25 C
-
10
µA
+125oC
-
1000
µA
-
10
µA
-100
-
nA
o
o
3
-55 C
1
oC
+25
oC
-1000
-
nA
VDD = 18V
3
-55oC
-100
-
nA
VDD = 20
1
+25oC
-
100
nA
-
1000
nA
-
100
nA
-
50
mV
-
V
VDD = 18V
3
+125
+125
oC
oC
-55
Output Voltage
VOL15
VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC
Output Voltage
VOH15
VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
IOL5
UNITS
2
2
Output Current (Sink)
MAX
1
2
Input Leakage Current
LIMITS
VDD = 5V, VOUT = 0.4V
1
+25
oC
0.53
-
mA
oC
1.4
-
mA
3.5
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1
+25oC
1
+25
oC
-
-0.53
mA
+25
oC
-
-1.8
mA
oC
-
-1.4
mA
-
-3.5
mA
Output Current (Source)
Output Current (Source)
IOH5A
IOH5B
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
1
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
+25
Output Current (Source)
IOH15
VDD = 15V, VOUT = 13.5V
1
+25oC
1
+25
oC
-2.8
-0.7
V
+25
oC
0.7
2.8
V
oC
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
1
VDD = 2.8V, VIN = VDD or GND
7
+25
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
VOH > VOL <
VDD/2 VDD/2
V
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
-
1.5
V
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
3.5
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
-
4
V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs
7-641
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
Specifications CD14538BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Propagation Delay
+TR or -TR to Q or Q
Propagation Delay
Reset to Q or Q
Transition Time
SYMBOL
TPHL1
TPLH1
CONDITIONS (Note 1, 2)
GROUP A
SUBGROUPS TEMPERATURE
VDD = 5V, VIN = VDD or GND
10, 11
TPHL2
TPLH2
VDD = 5V, VIN = VDD or GND
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
+25oC
9
+125
+25 C
+125
oC,
-55oC
+25oC
9
10, 11
-55oC
o
9
10, 11
oC,
+125
oC,
-55oC
LIMITS
MIN
MAX
UNITS
-
600
ns
-
810
ns
-
500
ns
-
675
ns
-
200
ns
-
270
ns
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
VDD = 5V, VIN = VDD or GND
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 2
-55oC, +25oC
-
5
µA
-
150
µA
o
+125 C
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
-55 C, +25 C
-
10
µA
+125oC
-
300
µA
-55oC, +25oC
-
10
µA
o
o
-
600
µA
Output Voltage
VOL
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
9.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1, 2
+125oC
0.36
-
mA
oC
+125
o
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
IOL10
IOL15
IOH5A
VDD = 10V, VOUT = 0.5V
1, 2
VDD = 15V, VOUT = 1.5V
1, 2
VDD = 5V, VOUT = 4.6V
1, 2
-55 C
0.64
-
mA
+125oC
0.9
-
mA
-55oC
1.6
-
mA
oC
2.4
-
mA
-55oC
4.2
-
mA
+125oC
-
-0.36
mA
+125
o
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOH5B
IOH10
IOH15
VDD = 5V, VOUT = 2.5V
1, 2
VDD = 10V, VOUT = 9.5V
1, 2
VDD =15V, VOUT = 13.5V
1, 2
-55 C
-
-0.64
mA
+125oC
-
-1.15
mA
-55oC
-
-2.0
mA
+125oC
-
-0.9
mA
-55oC
-
-1.6
mA
-
-2.4
mA
-
-4.2
mA
oC
+125
-55oC
o
o
Input Voltage Low
VIL1
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25 C, +125 C,
-55oC
-
3
V
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL <
1V
1, 2
+25oC, +125oC,
-55oC
+7
-
V
7-642
Specifications CD14538BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
Propagation Delay +TR
OR -TR to Q or Q
TPHL1
TPLH1
Propagation Delay Reset
to Q or Q
TPHL2
TPLH2
Transition Time
Output Pulse Width
Q or Q
C X =.002µF, RX = 100K
CONDITIONS
NOTES
MIN
MAX
UNITS
1, 2, 3
o
+25 C
-
300
ns
VDD = 15V
1, 2, 3
oC
+25
-
220
ns
VDD = 10V
1, 2, 3
+25oC
-
250
ns
1, 2, 3
oC
ns
VDD = 10V
VDD = 15V
1, 2, 3
+25
-
100
ns
VDD = 15V
1, 2, 3
+25oC
-
80
ns
TW
VDD = 5V
1, 2, 3
+25oC
-
230
µs
VDD = 10V
1, 2, 3
+25oC
-
232
µs
VDD = 10V
VDD = 15V
TW
TRR
Input Capacitance
TW
CIN
+25 C
-
234
µs
1, 2, 3
+25oC
-
10.5
ms
1, 2, 3
+25oC
-
10.6
ms
o
-
10.6
ms
o
+25 C
VDD = 5V
1, 2, 3
+25 C
-
1.06
s
VDD = 10V
1, 2, 3
+25oC
-
1.06
s
1, 2, 3
oC
-
1.07
s
oC
+25
VDD = 5V
1, 2, 3
+25
0
-
ns
VDD = 10V
1, 2, 3
+25oC
0
-
ns
0
-
ns
VDD = 15V
Minimum Input Pulse
Width
+TR, -TR, or Reset
1, 2, 3
o
1, 2, 3
VDD = 15V
Minimum Retrigger Time
190
VDD = 10V
TW
Output Pulse Width
C X = 10µF
R X = 100K
-
oC
+25
TTHL
TTLH
VDD = 15V
Output Pulse Width
C X = 0.1µF
R X = 100K
TEMPERATURE
o
+25 C
1, 2, 3
o
VDD = 5V
1, 2, 3
+25 C
-
140
ns
VDD = 10V
1, 2, 3
+25oC
-
80
ns
VDD = 15V
1, 2, 3
+25oC
-
60
ns
-
7.5
pF
Any Input
o
+25 C
1, 2
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on
initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
N Threshold Voltage
VNTH
N Threshold Voltage
Delta
∆VNTH
P Threshold Voltage
VPTH
P Threshold Voltage
Delta
∆VPTH
Functional
F
CONDITIONS
NOTES
VDD = 20V, VIN = VDD or GND
TEMPERATURE
1, 4
oC
+25
o
1, 4
+25 C
VDD = 10V, ISS = -10µA
1, 4
oC
+25
VSS = 0V, IDD = 10µA
1, 4
+25oC
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VDD = 18V, VIN = VDD or GND
TPHL
TPLH
VDD = 5V
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
-
25
µA
-2.8
-0.2
V
-
±1
V
0.2
2.8
V
-
±1
V
1
+25oC
VOH >
VDD/2
VOL <
VDD/2
V
1, 2, 3, 4
+25oC
-
1.35 x
+25oC
Limit
ns
4. Read and Record
7-643
UNITS
+25 C
3. See Table 2 for +25oC limit.
NOTES: 1. All voltages referenced to device GND.
MAX
1, 4
o
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
MIN
Specifications CD14538BMS
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
IDD
± 1.0µA
Output Current (Sink)
IOL5
± 20% x Pre-Test Reading
IOH5A
± 20% x Pre-Test Reading
Output Current (Source)
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
READ AND RECORD
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
100% 5004
1, 7, 9, Deltas
PDA (Note 1)
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
100% 5004
2, 3, 8A, 8B, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
PDA (Note 1)
Final Test
Group A
Group B
Group D
IDD, IOL5, IOH5A, RONDEL10
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
Group E Subgroup 2
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
Static Burn-In 1
(Note 1)
6, 7, 9, 10
1, 3 - 5, 8, 11 - 13,
15
2, 14, 16
Static Burn-In 2
(Note 1)
6, 7, 9, 10
1, 8, 15
2 - 5, 11 - 13, 14,
16
Dynamic BurnIn (Note 1)
-
1, 4, 8, 12, 15
2, 14, 16
2, 6, 7, 9, 10, 14
1, 8, 15
3 - 5, 11 - 13, 16
Irradiation
(Note 2)
9V ± -0.5V
50kHz
25kHz
6, 7, 9, 10
5, 11
3, 13
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
7-644
Specifications CD14538BMS
TABLE 9. FUNCTIONAL TERMINAL CONNECTIONS
VDD TO TERM #
FUNCTION
VSS TO TERM #
MONO1
MONO2
INPUT PULSE TO TERM #
MONO1
MONO2
MONO1
MONO2
Leading-Edge Trigger/
Retriggerable
3, 5
11, 13
4
12
Leading-Edge Trigger/
Non-Retriggerable
3
13
4
12
Trailing-Edge Trigger/
Retriggerable
3
13
5
11
Trailing-Edge Trigger/
Non-Retriggerable
3
13
5
11
4
12
OTHER CONNECTIONS
MONO1
MONO2
5-7
11 - 9
4-6
12 - 10
NOTE:
1. A triggerable one-shot multivibrator has an output pulse width
which is extended one full time period (T) after application of
the last trigger pulse.
INPUT PULSE TRAIN
RETRIGGERABLE MODE PULSE
WIDTH (+TR MODE)
2. A non-triggerable one-shot multivibrator has a time period (T)
referenced from the application of the first trigger pulse.
T
NON-RETRIGGERABLE MODE
PULSE WIDTH (+TR MODE)
T
Power-Down Mode
VDD
During a rapid power-down condition, as would occur with a
power-supply short circuit or with a poorly filtered power supply, the energy stored in CX could discharge into Pin 2 or 14.
To avoid possible device damage in this mode, when C X is ≥
0.5 microfarad, a protection diode with a 1-ampere or higher
rating (1N5395 or equivalent) and a separate ground return
for CX should be provided as shown in Figure 1.
IN5395
OR
EQUIVALENT
An alternate protection method is shown in Figure 2, where a
51-ohm current-limiting resistor is inserted in series with C X.
Note that a small pulse width decrease will occur however,
and RX must be appropriately increases to obtain the originally desired pulse width.
FIGURE 1. RAPID POWER-DOWN PROTECTION CIRCUIT
VDD
RX
+
CX
≥ 0.5µfd
2(14)
16
1(15)
8
VSS
RX
51 OHMS
+
CX
VSS
2(14)
16
1(15)
8
≥ 0.5µfd
VSS
FIGURE 2. ALTERNATE RAPID POWER-DOWN PROTECTION
CIRCUIT
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
645
CD14538BMS
Logic Diagram
16
VDD
VDD
VDD
VDD
VDD
RX
COMP
I
2(14)
R4
CX
+
-
+
-
R3
7 (9)
Q
COMP
II
R2
R1
1(15)
VSS
VDD
8 VSS
VDD
VSS
HIGH Z
Q
6 (10)
*
VDD
VSS
3(13)
R
VDD
4(12)
*
D R1 R2 Q
FF
CL
Q
CL
TR
5(11)
*
TR
CL
R1
VSS
CL
VDD
p
R2
VCC
=
*ALL INPUTS ARE
PROTECTED BY CMOS
PROTECTION NETWORK
Q
n
CL
CL
CL
p
p
n
n
R2
VSS
VSS
Q
CL
FF DETAIL
CL
R1
FIGURE 3. 1/2 OF DEVICE SHOWN
AMBIENT TEMPERATURE (TA) = +25oC
30
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
Typical Performance Characteristics
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25
20
15
10V
10
5
5V
0
5
10
15
AMBIENT TEMPERATURE (TA) = +25oC
15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
10V
7.5
5.0
2.5
5V
0
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
7-646
CD14538BMS
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
0
-5
-10
-15
-10V
-20
-25
-15V
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
-30
-5
-10V
RESETPROPAGATION DELAY TIME (tPHL, tPLH) -ns
+TR, -TR PROPAGATION DELAY TIME (tPHL, tPLH)
-ns
300
10V
15V
100
20
SUPPLY VOLTAGE (VDD) = 5V
100
10V
15V
0
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
FIGURE 10. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
SUPPLY VOLTAGE (VDD) = 5V
300
200
10V
15V
100
20
40
60
80
100
LOAD CAPACITANCE (CL) pF
FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (RESET TO Q OR Q)
PULSE WIDTH VARIATION - PERCENT NORMALIZED
TO VDD = 10V
TRANSITION TIME (tTHL, tTLH) (ns)
200
50
400
0
FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION
OF LOAD CAPACITANCE (+TR OR -TR TO Q OR Q)
150
AMBIENT TEMPERATURE (TA) = +25oC
40
60
80
100
LOAD CAPACITANCE (CL) pF
AMBIENT TEMPERATURE (TA) = +25oC
-15
FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
SUPPLY VOLTAGE (VDD) = 5V
0
-10
-15V
AMBIENT TEMPERATURE (TA) = +25oC
200
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
400
0
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
0
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
(Continued)
AMBIENT TEMPERATURE (TA) = +25o C
3
2
1
0
-1
-2
-3
4
6
8
10
12
14
16
18
VDD SUPPLY VOLTAGE (VOLTS)
FIGURE 11. TYPICAL PULSE-WIDTH VARIATION AS A
FUNCTION OF SUPPLY VOLTAGE
7-647
20
CD14538BMS
(Continued)
TYPICAL PULSE WIDTH VARIATION - PERCENT
NORMALIZED TO VDD = 10V, TA = 25 oC
TYPICAL PULSE WIDTH VARIATION - PERCENT
NORMALIZED TO VDD = 10V, TA = 25oC
Typical Performance Characteristics
3
SUPPLY VOLTAGE (VDD) = 15V
2
1
10V
0
5V
-1
-2
-3
-60
-40
-20
0
20
40
60
80
100
3
SUPPLY VOLTAGE (VDD) = 5V
2
1
10V
0
5V
-1
-2
-3
-60
120 140
-40
-20
8
6
4
CL = 50pF, RL = 200KΩ
RX = 100KΩ
AMBIENT TEMPERATURE (TA) =25 oC
ONE MONOSTABLE OPERATING
10V
10 8
15V
6
4
2
1 8
6
4
2
18V
SUPPLY VOLTAGE
(VDD) = 5V
0.1 8
40
60
80
100
120 140
RX = 100KΩ
TA = +25oC
2
100 8
6
4
2
20
FIGURE 13. TYPICAL PULSE-WIDTH VARIATION AS A FUNCTION
OF TEMPERATURE (RX = 100 KΩ, CX = 2000pF)
IDD CURRENT (µA) 50% DC
TOTAL SUPPLY CURRENT (µA)
FIGURE 12. TYPICAL PULSE-WIDTH VARIATION AS A FUNCTION
OF TEMPERATURE (RX = 100 KΩ, CX = 0.1µF)
6
4
2
1000 8
6
4
2
0
AMBIENT TEMPERATURE (oC)
AMBIENT TEMPERATURE (o C)
1000
SUPPLY VOLTAGE (VDD) = 15V
8
6
4
2
10V
100
8
6
4
2
10
5V
8
6
4
6
4
2
2
0
0.01
2 4 68
0.0001
0.001
2 4 68
0.01
2 4 68
0.1
2 4 68
2 4 68
1
10
2
2 4 68
4 68
10
100
2
100
4 68
1000
2
4 68
2
4 68
10K
2
4 68
100K
CX CAPACITANCE (pfs)
OUTPUT DUTY CYCLE (%)
FIGURE 14. TYPICAL TOTAL SUPPLY CURRENT AS A FUNCTION OF OUTPUT DUTY CYCLE
FIGURE 15. TYPICAL TOTAL SUPPLY CURRENT AS A FUNCTION OF LOAD CAPACITANCE
Chip Dimension and Pad Layout
METALLIZATION:
PASSIVATION:
BOND PADS:
Thickness: 11kÅ − 14kÅ,
AL.
10.4kÅ - 15.6kÅ, Silane
0.004 inches X 0.004 inches MIN
DIE THICKNESS:
0.0198 inches - 0.0218 inches
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)
7-648
Similar pages