CD40100BMS CMOS 32-Stage Static Left/Right Shift Register December 1992 Features Description • High Voltage Type (20V Rating) CD40100BMS is a 32-Stage shift register containing 32 D-type master-slave flip-flops. • Fully Static Operation • Shift Left/Shift Right Capability • Multiple Package Cascading • Recirculate Capability • LIFO of FIFO Capability • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Standardized, Symmetrical Output Characteristics • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications • Serial Shift Registers • Time Delay Circuits The data present at the SHIFT RIGHT INPUT is transferred into the first register stage synchronously with the positive CLOCK edge, provided the LEFT/RIGHT CONTROL is at a low level, the RECIRCULATE CONTROL is at a high level, and the CLOCK INHIBIT is low. If the LEFT/RIGHT CONTROL is at a high level and the RECIRCULATE CONTROL is also high, data at the SHIFT LEFT INPUT is transferred into the 32nd register stage synchronously with the positive CLOCK transition, provided the CLOCK INHIBIT is low. The state of the LEFT/RIGHT CONTROL, RECIRCULATE CONTROL, and CLOCK INHIBIT should not be changed when the CLOCK is high. Data is shifted one stage left or one stage right depending on the state of the LEFT/RIGHT CONTROL, synchronously with the positive CLOCK edge. Data clocked into the first or 32nd register states is available at the SHIFT LEFT or SHIFT RIGHT OUTPUT respectively, on the next negative CLOCK transition (see Data Transfer Table). No shifting occurs on the positive CLOCK edge if the CLOCK INHIBIT line is at a high level. With the RECIRCULATE CONTROL low, data in the 32nd stage is shifted into the first stage when the LEFT/ RIGHT CONTROL is low and from the first stage to the 32nd stage when the LEFT/RIGHT CONTROL is low, and from the first state to the 32nd stage when the LEFT/RIGHT control is high. The CD40100BMS is supplied in these 16-lead outline packages: • Expandable N-Bit Data Storage Stack (LIFO Operation) Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4T H2R H6W Pinout Functional Diagram CD40100BMS TOP VIEW LEFT/RIGHT CONTROL NC 1 16 VDD CLOCK INHIBIT 2 15 NC CLOCK 3 14 NC SHIFT LEFT OUT 4 13 NC 5 LEFT/RIGHT CONTROL 12 SHIFT RIGHT OUT SHIFT LEFT IN 6 11 SHIFT RIGHT IN NC 7 10 NC VSS 8 9 13 IN SHIFT RIGHT SHIFT RIGHT 11 12 OUT CLOCK 4 CLOCK INHIBIT SHIFT LEFT 2 IN RECIRCULATE CONTROL 4 SHIFT LEFT 6 9 RECIRCULATE CONTROL NC = NO CONNECTION CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 7-1277 OUT VSS = 8 VDD = 16 NC = 1, 5, 7, 10, 14, 15 File Number 3349 Specifications CD40100BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage Output Voltage VOL15 VOH15 VDD = 15V, No Load VDD = 15V, No Load (Note 3) LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 10 µA 2 +125oC - 1000 µA 3 -55oC - 10 µA 1 +25oC -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA 1, 2, 3 +25oC, +125oC, -55oC - 50 mV 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA 1 +25oC 3.5 - mA 1 +25oC - -0.53 mA Output Current (Sink) Output Current (Source) IOL15 IOH5A VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA 1 +25oC - -3.5 mA 1 +25oC -2.8 -0.7 V VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Output Current (Source) N Threshold Voltage P Threshold Voltage Functional IOH15 VNTH VPTH F VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-1278 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD40100BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTE 1, 2) Propagation Delay Clock to Shift Left/Right Output TPHL TPLH VDD = 5V, VIN = VDD or GND Transition Time TTHL TTLH VDD = 5V, VIN = VDD or GND Maximum Clock Input Frequency GROUP A SUBGROUPS TEMPERATURE VDD = 5V, VIN = VDD or GND MIN MAX UNITS 9 +25 C - 720 ns 10, 11 +125oC, -55oC - 972 ns 9 +25oC - 200 ns - 270 ns 1 - MHz .74 - MHz MIN MAX UNITS C, +25 C - 5 µA o - 150 µA - 10 µA - 300 µA - 10 µA - 600 µA 10, 11 FCL o LIMITS 9 10, 11 o o +125 C, -55 C o +25 C o o +125 C, -55 C NOTES: 1. VDD = 5V, CL = 50pF, RL = 200K 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND 1, 2 TEMPERATURE -55o o +125 C VDD = 10V, VIN = VDD or GND 1, 2 o o -55 C, +25 C o +125 C VDD = 15V, VIN = VDD or GND 1, 2 o o -55 C, +25 C o +125 C o o Output Voltage VOL VDD = 5V, No Load 1, 2 +25 C, +125 C, -55oC - 50 mV Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA +125oC - -2.4 mA -55oC - -4.2 mA Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VDD = 10V, VOUT = 0.5V 1, 2 VDD = 15V, VOUT = 1.5V 1, 2 VDD = 5V, VOUT = 4.6V 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V 1, 2 VDD =15V, VOUT = 13.5V 7-1279 1, 2 Specifications CD40100BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL Input Voltage Low VIL CONDITIONS VDD = 10V, VOH > 9V, VOL < 1V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +25oC, +125oC, - 3 V -55oC Input Voltage High VIH Propagation Delay Clock to Shift Left/Right Output Transition Time VDD = 10V, VOH > 9V, VOL < 1V +25oC - 330 ns - 230 ns TTHL VDD = 10V 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25oC - 80 ns 1, 2, 3 +25oC 2.5 - MHz 1, 2, 3 +25oC 3 - MHz 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25oC - 20 ns 1, 2, 3 +25oC - 10 ns 1, 2, 3 +25oC - 275 ns 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25oC - 75 ns 1, 2, 3 +25oC - 450 ns 1, 2, 3 +25oC - 230 ns 1, 2, 3 +25oC - 190 ns 1, 2, 3 +25oC - 280 ns 1, 2, 3 +25oC - 150 ns 1, 2, 3 +25oC - 140 ns 1, 2 +25oC - 7.5 pF VDD = 10V TS VDD = 5V VDD = 10V TH VDD = 5V VDD = 15V TWL VDD = 5V VDD = 10V VDD = 15V TWH VDD = 5V VDD = 10V VDD = 15V Input Capacitance 1, 2, 3 1, 2, 3 VDD = 10V Minimum Clock Pulse Width High Level V VDD = 15V VDD = 15V Minimum Clock Pulse Width Low Level - +25oC VDD = 15V Minimum Data Hold Time +7 VDD = 10V FCL Minimum Data Setup Time +25oC, +125oC, -55oC TPHL1 TPLH1 VDD = 15V Maximum Clock Input Frequency 1, 2 CIN Any Input NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP P Threshold Voltage Delta ∆VTP Functional F CONDITIONS NOTES TEMPERATURE VDD = 20V, VIN = VDD or GND 1, 4 +25oC VDD = 10V, ISS = -10µA 1, 4 +25oC VDD = 10V, ISS = -10µA 1, 4 +25oC VSS = 0V, IDD = 10µA 1, 4 VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND 7-1280 MIN MAX UNITS - 25 µA -2.8 -0.2 V - ±1 V +25oC 0.2 2.8 V 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V Specifications CD40100BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL Propagation Delay Time TPHL TPLH CONDITIONS VDD = 5V NOTES TEMPERATURE MIN MAX UNITS 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading RONDEL10 ± 20% x Pre-Test Reading Output Current (Source) ON Resistance TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test 1, 7, 9 100% 5004 1, 7, 9, Deltas IDD, IOL5, IOH5A 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group A Group B 100% 5004 Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 1, 4, 5, 7, 10, 12, 14, 15 2, 3, 6, 8, 9, 11, 13 16 Static Burn-In 2 Note 1 1, 4, 5, 7, 10, 12, 14, 15 8 2, 3, 6, 9, 11, 13, 16 Dynamic BurnIn Note 1 1, 5, 7, 10, 14, 15 2, 8, 13 9, 16 Irradiation Note 2 1, 4, 5, 7, 10, 12, 14, 15 8 2, 3, 6, 9, 11, 13, 16 7-1281 9V ± -0.5V 50kHz 25kHz 4, 12 3 6, 11 Specifications CD40100BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS (Continued) OSCILLATOR FUNCTION OPEN GROUND 9V ± -0.5V VDD 50kHz 25kHz NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V TABLE 9. DATA TRANSFER TABLE* INITIAL STATE CLOCK RESULTING STATE INTERNAL STAGE Q OUTPUT X 0 NC 0 0 NC 0 1 0 X 1 NC X 0 1 NC 1 X 1 1 NC NC DATA INPUT CLOCK INHIBIT INTERNAL STAGE 0 0 X 0 = Low Level 1 = High Level X = Don’t Care LEVEL CHANGE X NC = No Change * For Shift-Right Mode Data Input = SHIFT RIGHT INPUT (Term. 11) Internal Stage = Stage 1 (Q1) Output = SHIFT LEFT OUTPUT (Term. 4) For Shift Left Mode Data Input = SHIFT LEFT INPUT (Term. 6) Internal Stage = Stage 32 (Q32) Output = SHIFT RIGHT OUTPUT (Term. 12) TABLE 10. CONTROL TRUTH TABLE LEFT/RIGHT CONTROL CLOCK INHIBIT RECIRCULATE CONTROL ACTION 1 0 1 Shift Left Shift Left Input 1 0 0 Shift Left Stage 1 0 0 1 Shift Right Shift Right Input 0 0 0 Shift Right Stage 32 X 1 X No Shift INPUT BIT ORIGIN - All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. 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Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 CD40100BMS Logic Diagram CL CLOCK 3* CL CLOCK INHIBIT 2* SHIFT RIGHT 11* INPUT R S p p n n p S S p R n LEFT/RIGHT 13* CONTROL SHIFT RIGHT 12 OUTPUT CL p p STAGE 1 n R S CL CL n CL CL p n n S CL S S S CL S CL S p RECIRCULATE 9* CONTROL p STAGE 2 n R n S S R STAGES 3-30 (ALL IDENTICAL TO STAGES 2 AND 31) S CL CL S VDD p p STAGE 31 n n S S CL CL p VSS * CL STAGE 32 n ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK S R p p n n CL CL p p n n CL R SHIFT LEFT 6* INPUT D CL CL p p n n CL R S CL CL Q CL p p n n CL CL FIGURE 1. 7-1283 SHIFT RIGHT 12 OUTPUT CD40100BMS AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 5.0 2.5 0 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 0 -10 -15 -20 -25 -15V -30 -5 -10V TRANSITION TIME (tTHL, tTLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC 400 10V 15V 60 -15 FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS SUPPLY VOLTAGE (VDD) = 5V 40 -10 -15V 600 20 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V AMBIENT TEMPERATURE (TA) = +25oC 0 0 AMBIENT TEMPERATURE (TA) = +25oC FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 200 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS -5 -10V 5V 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 10V 7.5 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tPHL, tPLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 30 OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics 80 150 SUPPLY VOLTAGE (VDD) = 5V 100 10V 15V 50 0 0 100 LOAD CAPACITANCE (CL) (pF) FIGURE 6. TYPICAL PROPAGATION DELAY TIME (CLOCK TO SHIFT LEFT/RIGHT) AS A FUNCTION OF LOAD CAPACITANCE 200 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE 7-1284 CD40100BMS 105 8 6 4 2 (Continued) SUPPLY VOLTAGE (VDD) = 15V CL = 50pF 8 6 4 2 CL =15pF 104 103 102 AMBIENT TEMPERATURE (TA) = +25oC LOAD CAPACITANCE (RL) = 200KΩ INPUT RISE & FALL TIME (tr, tf) = 20ns POWER DISSIPATION (PD) (µW) Typical Performance Characteristics 10V 8 6 4 2 10V 5V 8 6 4 2 2 2 4 68 1 4 68 2 102 10 4 68 2 103 4 68 2 4 68 104 CLOCK INPUT FREQUENCY (fCL) (KHz) FIGURE 8. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY Timing Diagram tWL tWH CLOCK tS tH tPHL INPUT tPHL OUTPUT FIGURE 9. TIMING DIAGRAM DEFINING SETUP, HOLD, AND PROPAGATION DELAY TIMES Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: Thickness: 11kÅ − 14kÅ, PASSIVATION: AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches 7-1285