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1-88
CD4047BMS
CMOS Low-Power
Monostable/Astable Multivibrator
December 1992
Features
Description
• High Voltage Type (20V Rating)
CD4047BMS consists of a gatable astable multivibrator with logic techniques incorporated to permit positive or negative edge triggered
monostable multivibrator action with retriggering and external counting
options.
• Low Power Consumption: Special CMOS Oscillator
Configuration
• Monostable (One-Shot) or Astable (Free-Running)
Operation
• True and Complemented Buffered Outputs
• Only One External R and C Required
• Buffered Inputs
• 100% Tested for Quiescent Current at 20V
• Standardized, Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Monostable Multivibrator Features
• Positive or Negative Edge Trigger
• Output Pulse Width Independent of Trigger Pulse
Duration
• Retriggerable Option for Pulse Width Expansion
• Internal Power-On Reset Circuit
• Long Pulse Widths Possible Using Small RC Components by Means of External Counter Provision
• Fast Recovery Time Essentially Independent of Pulse
Width
• Pulse-Width Accuracy Maintained at Duty Cycles
Approaching 100%
Astable Multivibrator Features
• Free-Running or Gatable Operating Modes
Inputs include +TRIGGER, -TRIGGER, ASTABLE, ASTABLE,
RETRIGGER, and EXTERNAL RESET. Buffered outputs are Q, Q,
and OSCILLATOR. In all modes of operation, an external capacitor
must be connected between C-Timing and RC-Common terminals, and
an external resistor must be connected between the R-Timing and RCCommon terminals.
Astable operation is enabled by a high level on the ASTABLE input or a
low level on the ASTABLE input, or both. The period of the square wave
at the Q and Q Outputs in this mode of operation is a function of the
external components employed. “True” input pulses on the ASTABLE
input or “Complement” pulses on the ASTABLE input allow the circuit to
be used as a gatable multivibrator. The OSCILLATOR output period will
be half of the Q terminal output in the astable mode. However, a 50%
duty cycle is not guaranteed at this output.
The CD4047BMS triggers in the monostable mode when a positive
going edge occurs on the +TRIGGER input while the -TRIGGER is held
low. Input pulses may be of any duration relative to the output pulse.
If retrigger capability is desired, the RETRIGGER input is pulsed. The
retriggerable mode of operation is limited to positive going edge. The
CD4047BMS will retrigger as long as the RETRIGGER input is high,
with or without transitions (See Figure 31)
An external countdown option can be implemented by coupling “Q” to
an external “N” counter and resetting the counter with trigger pulse. The
counter output pulse is fed back to the ASTABLE input and has a duration equal to N times the period of the multivibrator.
A high level on the EXTERNAL RESET input assures no output pulse
during an “ON” power condition. This input can also be activated to terminate the output pulse at any time. For monostable operation, whenever VDD is applied, an internal power on reset circuit will clock the Q
output low within one output period (tM).
The CD4047BMS is supplied in these 14-lead outline packages:
• 50% Duty Cycle
• Oscillator Output Available
• Good Astable Frequency Stability: Frequency Deviation:
- = 2% + 0.03%/oC at 100kHz
- = 0.5% + 0.015%/oC at 10kHz (Circuits “Trimmed”
to Frequency VDD = 10V  10%
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
Pinout
CD4047BMS
TOP VIEW
Applications
Digital equipment where low power dissipation and/or high noise
immunity are primary design requirements
• Envelope Detection
• Frequency Discriminators
• Frequency Multiplication
• Timing Circuits
• Frequency Division
• Time Delay Applications
H4Q
H1B
H3W
C 1
14 VDD
R 2
13 OSC OUT
R-C COMMON 3
11 Q
ASTABLE 5
10 Q
-TRIGGER 6
9 EXT. RESET
VSS 7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-897
12 RETRIGGER
ASTABLE 4
8 +TRIGGER
File Number
3313
Specifications CD4047BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input  10mA
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 1/32 Inch (1.59mm  0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
ja
jc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
o
Maximum Package Power Dissipation (PD) at +125 C
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
GROUP A
SUBGROUPS
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
VDD = 18V
Input Leakage Current
(Pin 3)
IIL
VDD = 24V, VIN = 11V or GND
VDD = 26V, VIN = 13V or GND
MAX
UNITS
C
-
2
A
2
+125oC
-
200
A
3
-55oC
-
2
A
-100
-
nA
-1000
-
nA
-100
-
nA
1
o
+25 C
+125
oC
3
-55oC
1
oC
-
100
nA
o
-
1000
nA
+25
+125 C
o
3
-55 C
-
100
nA
1
+25oC
-300
-
nA
-10
-
A
-
300
nA
2
IIH
MIN
1
2
Input Leakage Curent
(Pin 3)
TEMPERATURE
+25o
2
VDD = 18V
LIMITS
1
o
+125 C
o
+25 C
o
2
+125 C
-
10
A
Output Voltage
VOL15
VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC
-
50
mV
Output Voltage
VOH15
VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
-
V
o
Output Current (Sink)
Q, Q, OSC Out
IOL5
VDD = 5V, VOUT = 0.4V
1
+25 C
0.53
-
mA
Output Current (Sink)
Q, Q, OSC Out
IOL10
VDD = 10V, VOUT = 0.5V
1
+25oC
1.4
-
mA
Output Current (Sink)
Q, Q, OSC Out
IOL15
VDD = 15V, VOUT = 1.5V
1
+25oC
3.5
-
mA
Output Current (Source)
Q, Q, OSC Out
IOH5A
VDD = 5V, VOUT = 4.6V
1
+25oC
-
-0.53
mA
Output Current (Source)
Q, Q, OSC Out
IOH5B
VDD = 5V, VOUT = 2.5V
1
+25oC
-
-1.8
mA
Output Current (Source)
Q, Q, OSC Out
IOH10
VDD = 10V, VOUT = 9.5V
1
+25oC
-
-1.4
mA
Output Current (Source)
Q, Q, OSC Out
IOH15
VDD = 15V, VOUT = 13.5V
1
+25oC
-
-3.5
mA
VDD = 5V, VOUT = 0.4V
1
+25oC
0.78
-
mA
1
+25oC
2.0
-
mA
1
+25
oC
5.2
-
mA
+25
oC
-
-0.78
mA
oC
Output Current (Sink)
IOL5RC
Output Current (Sink)
IOL10RC VDD = 10V, VOUT = 0.5V
Output Current (Sink)
IOL15RC VDD = 15V, VOUT = 1.5V
Output Current (Source) IOH5RC VDD = 5V, VOUT = 4.6V
1
Output Current (Source) IOH10RC VDD = 10V, VOUT = 9.5V
1
+25
-
-2
mA
Output Current (Source) IOH15RC VDD = 15V, VOUT = 13.5V
1
+25oC
-
-5.2
mA
N Threshold Voltage
1
+25oC
-2.8
-0.7
V
VNTH
VDD = 10V, ISS = -10A
7-898
Specifications CD4047BMS
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
PARAMETER
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
0.7
2.8
V
7
+25
oC
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
CONDITIONS (NOTE 1)
SYMBOL
P Threshold Voltage
Functional
VPTH
VSS = 0V, IDD = 10A
F
LIMITS
GROUP A
SUBGROUPS
VDD = 2.8V, VIN = VDD or GND
VOH > VOL <
VDD/2 VDD/2
V
-55oC
oC,
+125oC, -55oC
-
1.5
V
+25oC, +125oC, -55oC
3.5
-
V
1, 2, 3
+25oC, +125oC, -55oC
-
4
V
1, 2, 3
+25oC, +125oC, -55oC
11
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
NOTES:
1. All voltages referenced to device GND, 100% testing being implemented
2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max..
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
Propagation Delay
Astable, Astable to OSC
TPLH1
(NOTES 1, 2)
CONDITIONS
GROUP A
SUBGROUPS TEMPERATURE
VDD = 5V, VIN = VDD or GND
9
10, 11
Propagation Delay
Trigger to Q, Q
TPHL3
TPLH3
VDD = 5V, VIN = VDD or GND
Propagation Delay
(Note 2)
Astable or Astable to Q, Q
TPLH2
TPLH2
VDD = 5V, VIN = VDD or GND
Propagation Delay
(Note 2)
Retrigger to Q, Q
TPHL4
TPLH4
VDD = 5V, VIN = VDD or GND
Propagation Delay
(Note 2)
Reset to Q, Q
TPLH5
TPLH5
VDD = 5V, VIN = VDD or GND
Transition Time
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
9
10, 11
9
10, 11
NOTES:
1. VDD = 5V, CL = 50pF, RL = 200K; input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
7-899
9
+25oC
+125
oC,
-55oC
+25oC
+125
oC,
-55oC
+25oC
+125
oC,
-55oC
+25oC
o
o
LIMITS
MIN
MAX
UNITS
-
400
ns
-
540
ns
-
1000
ns
-
1350
ns
-
700
ns
-
945
ns
-
600
ns
10, 11
+125 C, -55 C
-
810
ns
9
+25oC
-
500
ns
o
o
10, 11
+125 C, -55 C
-
675
ns
9
+25oC
-
200
ns
10, 11
+125oC, -55oC
-
270
ns
Specifications CD4047BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
VDD = 5V, VIN = VDD or GND
1, 2
TEMPERATURE
-55
oC,
+25oC
o
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
MIN
MAX
UNITS
-
1
A
+125 C
-
30
A
-55oC, +25oC
-
2
A
+125oC
-
60
A
o
o
-55 C, +25 C
-
2
A
+125oC
-
120
A
o
o
Output Voltage
VOL
VDD = 5V, No Load
1, 2
+25 C, +125 C,
-55oC
-
50
mV
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
9.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1, 2
+125oC
0.36
-
mA
0.64
-
mA
o
-55 C
Output Current (Sink)
Output Current (Sink)
IOL10
IOL15
VDD = 10V, VOUT = 0.5V
o
1, 2
VDD = 15V, VOUT = 1.5V
1, 2
+125 C
0.9
-
mA
-55oC
1.6
-
mA
+125oC
2.4
-
mA
4.2
-
mA
+125oC
-
-0.36
mA
-55oC
-
-0.64
mA
-55
Output Current (Source)
Output Current (Source)
IOH5A
IOH5B
VDD = 5V, VOUT = 4.6V
1, 2
VDD = 5V, VOUT = 2.5V
1, 2
oC
+125
oC
-55oC
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1, 2
+125
-55
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
oC
oC
+125oC
1, 2
-55
oC,
oC
+125oC,
-
-1.15
mA
-
-2.0
mA
-
-0.9
mA
-
-1.6
mA
-
-2.4
mA
-
-4.2
mA
-
3
V
Input Voltage Low
VIL
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25oC, +125oC,
-55oC
+7
-
V
1, 2, 3
+25oC
-
200
ns
Propagation Delay
Astable, Astable to OSC
TPLH1
Propagation Delay
Astable or Astable to Q, Q
TPLH2
TPHL2
Propagation Delay
Trigger to Q, Q
TPHL3
TPLH3
Propagation Delay
Retrigger to Q, Q
TPHL4
TPLH4
Propagation Delay
Reset to Q, Q
TPLH5
TPLH5
Transition Time
TTHL
TTLH
VDD = 10V
-55oC
o
VDD = 15V
1, 2, 3
+25 C
-
160
ns
VDD = 10V
1, 2, 3
+25oC
-
350
ns
o
VDD = 15V
1, 2, 3
+25 C
-
250
ns
VDD = 10V
1, 2, 3
+25oC
-
450
ns
o
1, 2, 3
+25 C
-
300
ns
VDD = 10V
1, 2, 3
+25oC
-
300
ns
VDD = 15V
1, 2, 3
+25oC
-
200
ns
1, 2, 3
o
+25 C
-
200
ns
VDD = 15V
1, 2, 3
+25
oC
-
140
ns
VDD = 10V
1, 2, 3
+25oC
-
100
ns
1, 2, 3
oC
-
80
ns
VDD = 15V
VDD = 10V
VDD = 15V
7-900
+25
Specifications CD4047BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
Q or Q Deviation from
50% Duty Factor
QD
VDD = 5V
TW
Minimum Pulse Width
+ Trigger
- Trigger
Minimum Pulse Width
Reset
CIN
MIN
MAX
UNITS
1, 2, 3
+25oC
-
1
%
o
1, 2, 3
+25 C
-
1
%
1, 2, 3
+25oC
-
0.5
%
1, 2, 3
+25o
C
-
400
ns
VDD = 10V
1, 2, 3
o
+25 C
-
160
ns
VDD = 15V
1, 2, 3
+25oC
-
100
ns
o
-
200
ns
o
+25 C
1, 2, 3
VDD = 10V
1, 2, 3
+25 C
-
100
ns
VDD = 15V
1, 2, 3
+25oC
-
60
ns
o
VDD = 5V
1, 2, 3
+25 C
-
600
ns
VDD = 10V
1, 2, 3
+25oC
-
230
ns
1, 2, 3
+25
oC
-
150
ns
+25
oC
-
7.7
pF
VDD = 15V
Input Capacitance
TEMPERATURE
VDD = 15V
VDD = 5V
TW
NOTES
VDD = 10V
VDD = 5V
TW
Minimum Retrigger Pulse
Width
CONDITIONS
Any Input
1, 2
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on
initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
N Threshold Voltage
SYMBOL
IDD
VNTH
N Threshold Voltage
Delta
VTN
P Threshold Voltage
VTP
P Threshold Voltage
Delta
Functional
VTP
F
CONDITIONS
NOTES
TEMPERATURE
o
UNITS
1, 4
+25 C
-
7.5
A
VDD = 10V, ISS = -10A
1, 4
+25oC
-2.8
-0.2
V
o
VDD = 10V, ISS = -10A
1, 4
+25 C
-
1
V
VSS = 0V, IDD = 10A
1, 4
+25oC
0.2
2.8
V
1, 4
oC
-
1
V
VSS = 0V, IDD = 10A
VDD = 18V, VIN = VDD or GND
TPHL
TPLH
MAX
VDD = 20V, VIN = VDD or GND
+25
1
+25oC
VOH >
VDD/2
VOL <
VDD/2
V
1, 2, 3, 4
+25oC
-
1.35 x
+25oC
Limit
ns
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
MIN
VDD = 5V
3. See Table 2 for +25oC limit.
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
Supply Current - MSI-1
Output Current (Sink)
Output Current (Source)
SYMBOL
DELTA LIMIT
IDD
 0.2A
IOL5
 20% x Pre-Test Reading
IOH5A
 20% x Pre-Test Reading
7-901
Specifications CD4047BMS
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
CONFORMANCE GROUP
Interim Test 2 (Post Burn-In)
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
1, 7, 9
1, 7, 9, Deltas
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
IDD, IOL5, IOH5A
100% 5004
2, 3, 8A, 8B, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
Group A
Group B
100% 5004
100% 5004
Group D
READ AND RECORD
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
Group E Subgroup 2
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
Static Burn-In 1
Note 1
1, 2, 10, 11, 13
3-9, 12
14
Static Burn-In 2
Note 1
1, 2, 10, 11, 13
7
3-6, 8, 9, 12, 14
Dynamic BurnIn Note 1
-
7, 9, 12
4, 5, 14
1, 2, 10, 11, 13
7
3-6, 8, 9, 12, 14
Irradiation
Note 2
9V  -0.5V
50kHz
25kHz
1, 2, 10, 11, 13
6, 8
3
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K  5%, VDD = 18V  0.5V
2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V  0.5V
7-902
CD4047BMS
TABLE 9. FUNCTIONAL TERMINAL CONNECTIONS
In all cases External resistor between terminals 2 and 3 (Note 1)
External capacitor between terminals 1 and 3 (Note 1)
TERMINAL CONNECTIONS
FUNCTION
TO VDD
TO VSS
INPUT TO
OUTPUT PULSE
FROM
OUTPUT PERIOD OR PULSE
WIDTH
4, 5, 6, 14
7, 8, 9, 12
-
10, 11, 13
TA (10, 11) = 4.40 RC
TA (13) = 2.20 RC (Note 2)
ASTABLE MULTIVIBRATOR
Free Running
True Gating
4, 6, 14
7, 8, 9, 12
5
10, 11, 13
6, 14
5, 7, 8, 9, 12
4
10, 11, 13
Positive Edge Trigger
4, 14
5, 6, 7, 9, 12
8
10, 11
Negative Edge Trigger
4, 8, 14
5, 7, 9, 12
6
10, 11
4, 14
5, 6, 7, 9
8, 12
10, 11
14
5, 6, 7, 8, 9, 12
-
10, 11
Complement Gating
MONOSTABLE MULTIVIBRATOR
Retriggerable
External Countdown (Note 3)
tM (10, 11) = 2.48 RC
NOTES:
1. See text.
2. First positive 1/2 cycle pulse width = 2.48 RC. See note follow Monostable Mode Design Information.
3. Input Pulse to Reset of External Counting Chip External Counting Chip Output to Terminal 4.
Logic Diagrams
C
C-TIMING
3
R
1
2
OSCILLATOR OUT
RC
COMMON
5
4
6
8
12
9
ASTABLE
ASTABLE
R-TIMING
Q
ASTABLE
GATE
CONTROL
LOW POWER
ASTABLE
MULTIVIBRATOR
FREQUENCY
DIVIDER (2)
-TRIGGER
+TRIGGER
RETRIGGER
EXTERNAL
RESET
MONOSTABLE
CONTROL
RETRIGGER
CONTROL
FIGURE 1. CD4047BMS LOGIC BLOCK DIAGRAM
7-903
Q
13
10
11
CD4047BMS
Logic Diagrams
(Continued)
*
*
ASTABLE
5
ASTABLE
4
+TRIGGER
8
-TRIGGER
6
VDD
RETRIGGER 12
**
3
RC
COMMON
CTC
1
2
RTC
*
*
*
VDD
OSC
OUT
FF1
D Q
13
CL
CL
R1 R2
VDD 14
VSS
EXTERNAL
RESET
S
D Q
FF2
CL
CL Q
R
7
VSS
S
D Q
FF4
CL
CL
R
D
Q
FF3
CL
CL
R1 R2
11
*
VDD
9
VDD
*
10 Q
**
CAUTION: Terminal 3 is more sensitive
to static electrical discharge. Extra
handling precautions are recommended.
INPUTS PROTECTED
BY CMOS
PROTECTION
NETWORK
SPECIAL
RC COMMON
PROTECTION
NETWORK
VSS
VSS
FIGURE 2. CD4047BMS LOGIC DIAGRAM
CL R2 R1
CL
D
D
Q
p
n
p
n
Q
R1 R2
CL
CL
CL
CL
CL
CL
p
n
p
n
R1 R2
FF1, FF3
CL
CL
(a)
Q
CL
S
CL
S
D
Q
D
R
Q
p
Q
n
p
n
CL
CL
CL
CL
S
CL
CL
p
p
n
n
R
FF2, FF4
CL
R
CL
(b)
FIGURE 3. DETAIL LOGIC DIAGRAM FOR FLIP-FLOPS FF1 AND FF3 (a) AND FOR FLIP-FLOPS FF2 AND FF4 (b)
7-904
Q
CD4047BMS
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25
20
15
10V
10
5
5V
0
5
10
AMBIENT TEMPERATURE (TA) = +25oC
15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
10V
7.5
5.0
2.5
15
5V
0
FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
0
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-2.5
-7.5
-10V
-10
-12.5
-15V
-15
AMBIENT TEMPERATURE (TA) = +25oC
-10V
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
-7.5
FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
SUPPLY VOLTAGE (VDD) = 5V
10V
15V
o
AMBIENT TEMPERATURE (TA) = +25 C
40
60
80
LOAD CAPACITANCE (CL) (pF)
-5
-15V
300
20
0
-2.5
400
0
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
FIGURE 6. TYP. OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
100
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
-5
200
10
FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
5
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
30
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
600
SUPPLY VOLTAGE (VDD) = 5V
400
10V
200
15V
0
100
FIGURE 8. TYP. PROPAGATION DELAY TIME AS A FUNCTION OF
LOAD CAPACITANCE (ASTABLE, ASTABLE TO Q, Q)
7-905
20
40
60
80
LOAD CAPACITANCE (CL) (pF)
100
FIGURE 9. TYP. PROPAGATION DELAY TIME AS A FUNCTION
OF LOAD CAPACITANCE (+ OR - TRIGGER TO Q, Q)
CD4047BMS
Typical Performance Characteristics
(Continued)
4
200
SUPPLY VOLTAGE (VDD) = 5V
150
100
10V
20
10M
0
10M
-1
-2
RX = 1M AND
100k
10k
0
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
0
100k
10k
1M
100k
RX = 1M
-1
10M
-2
10
12
14
16
1
18
20
10k
RX = 1M AND
10k
0
-1
10k
1M AND
10M
100k
-2
10k
-3
8
2
PERIOD ACCURACY (%)
1
6
AMBIENT TEMPERATURE (TA) = +25oC
CX = 1000pF
3
10M
2
4
FIGURE 11. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD
ACCURACY vs SUPPLY VOLTAGE
AMBIENT TEMPERATURE (TA) = +25oC
CX = 0.01F
3
2
SUPPLY VOLTAGE (VDD) (V)
4
4
-3
10k
-4
-4
0
2
4
6
8
10
12
14
16
SUPPLY VOLTAGE (VDD) (V)
18
0
20
SUPPLY VOLTAGE (VDD) = 5V
0
4
6
8
10
12
14
16
18
20
FIGURE 13. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD
ACCURACY vs SUPPLY VOLTAGE
2
10V, 15V
5V
PERIOD ACCURACY (%)
CX = 1F
RX = 1M
2
SUPPLY VOLTAGE (VDD) (V)
FIGURE 12. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD
ACCURACY vs SUPPLY VOLTAGE
PERIOD ACCURACY (%)
10k
1
-3
FIGURE 10. TYP. TRANSITION TIME AS A FUNCTION OF LOAD
CAPACITANCE
-1
-2
1M AND 100k
-4
0
0
PERIOD ACCURACY (%)
2
15V
50
1
AMBIENT TEMPERATURE (TA) = +25oC
CX = 1F
3
PERIOD ACCURACY (%)
TRANSITION TIME (fTHL, fTLH) (ns)
AMBIENT TEMPERATURE (TA) = +25oC
10V, 15V
CX = 0.1F
RX = 1M
SUPPLY VOLTAGE (VDD) = 5V
1
10V
0
15V
5V
15V
-1
10V
-3
-55
-2
-15
25
65
105
AMBIENT TEMPERATURE (TA) (oC)
145
-55
-15
25
65
105
145
AMBIENT TEMPERATURE (TA) (oC)
FIGURE 14. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD
ACCURACY vs AMBIENT TEMPERATURE (ULTRA
LOW FREQ.)
FIGURE 15. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD
ACCURACY vs AMBIENT TEMPERATURE (LOW
FREQ.)
7-906
CD4047BMS
Typical Performance Characteristics
12
CX = 0.01F
RX = 100k
SUPPLY VOLTAGE (VDD) = 5V, 10V
10
15V
8
1
PERIOD ACCURACY (%)
PERIOD ACCURACY (%)
2
(Continued)
5V AND 10V
0
15V
-1
CX = 1000pF
RX = 10k
6
4
2
10V, 15V
10V AND 15V
0
-2
-2
-15
25
65
105
AMBIENT TEMPERATURE (TA) (oC)
145
8
OUTPUT PULSE-WIDTH VARIATION (%)
20
100pF
10
0.001F
0.01F, 0.1F, 1F
0
0.001F
CX = 100pF
-10
-55
1k
2
100k
10k
0
10k, 1M AND 10M
RX = 100k, 1M, 10M
-2
1k
-4
-6
5
10
15
20
SUPPLY VOLTAGE (VDD) (V)
25
FIGURE 19. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs
SUPPLY VOLTAGE
8
OUTPUT PULSE-WIDTH VARIATION (%)
2
10k, 100k, 1M AND 10M
10M
-2
4
0
4
0
145
AMBIENT TEMPERATURE (TA) = +25oC
CX = 1F
6
145
AMBIENT TEMPERATURE (TA) = +25oC
CX = 0.1F
6
125
-8
-15
25
65
105
AMBIENT TEMPERATURE (TA) (oC)
FIGURE 18. TYPICAL ASTABLE OSCILLATOR OR Q, Q PERIOD
ACCURACY vs AMBIENT TEMPERATURE
8
-5
45
85 105
-15
25
65
AMBIENT TEMPERATURE (TA) (oC)
FIGURE 17. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD
ACCURACY vs AMBIENT TEMPERATURE (HIGH
FREQ.)
RX = 10k
SUPPLY VOLTAGE (VDD) = 5V
0.01F, 0.1F, 1F
-35
-55
FIGURE 16. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD
ACCURACY vs AMBIENT TEMPERATURE (MEDIUM
FREQ.)
PERIOD ACCURACY (%)
5V
-4
-55
OUTPUT PULSE-WIDTH VARIATION (%)
SUPPLY VOLTAGE (VDD) = 5V
RX = 10k, 100k, 1M
-4
-6
-8
AMBIENT TEMPERATURE (TA) = +25oC
CX = 1000pF
6
4
2
RX = 1M AND 10
100k
10k
0
-2
-4
-6
-8
0
5
10
15
20
SUPPLY VOLTAGE (VDD) (V)
25
0
FIGURE 20. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs
SUPPLY VOLTAGE
5
10
15
20
SUPPLY VOLTAGE (VDD) (V)
25
FIGURE 21. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs
SUPPLY VOLTAGE
7-907
CD4047BMS
Typical Performance Characteristics
RX = 100k
SUPPLY VOLTAGE (VDD) = 5V
6
4
2
0.001F
0
0.1F
0.1F
0.01F
-2
0.01F
-4
-6
-55
-15
25
5
45 65
85 105 125
AMBIENT TEMPERATURE (TA) (oC)
-35
10M
2
10k
0
4
2
10k
RX = 1M
-4
100k
-6
-8
1M
-10
10M
0
0.1F, 0.01F
-2
-4
-6
0.001F
0.1F AND 0.001F
-8
-10
100pF
-50 -35 -15 5 25 45 65 85 105 125 145
AMBIENT TEMPERATURE (TA) (oC)
FIGURE 23. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs
AMBIENT TEMPERATURE
CX = 1000pF
SUPPLY VOLTAGE (VDD) = 15V
2
10k
0
-2
10M
RX = 1M
100k
10k
100k
-4
-6
-8
1M
-10
10M
-12
-12
-55
-35
5 25
45 65
85 105 125
-15
AMBIENT TEMPERATURE (TA) (oC)
-50
145
FIGURE 24. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs
AMBIENT TEMPERATURE
106
POWER DISSIPATION (PD) (W)
ASTABLE MODE
SUPPLY VOLTAGE (VDD) = 5V
C =100pF
3
C = 0.01F
10
C =1000pF
C = 0.1F
C =10pF
102
101
100
10-1
100
101
102
103
104
105
-15
5
25
45
65
85 105
AMBIENT TEMPERATURE (TA) (oC)
125
145
ASTABLE MODE
SUPPLY VOLTAGE (VDD) = 10V
105
C =100pF
104
C =1000pF
C = 0.01F
103
C =10pF
C = 0.1F
102
101
10-1
106
Q OR Q FREQUENCY (F) (Hz)
FIGURE 26. TYPICAL POWER DISSIPATION vs OUTPUT
FREQUENCY (VDD = 5V)
-35
FIGURE 25. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs
AMBIENT TEMPERATURE
105
104
0.01F
4
CX = 1000pF
SUPPLY VOLTAGE (VDD) = 5V OR 10V
100k
-2
CX = 100pF
6
145
OUTPUT PULSE-WIDTH VARIATION (%)
4
RX = 100k
SUPPLY VOLTAGE (VDD) = 10V OR 15V
-12
FIGURE 22. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs
AMBIENT TEMPERATURE
OUTPUT PULSE-WIDTH VARIATION (%)
8
0.001F
-8
POWER DISSIPATION (PD) (W)
10
OUTPUT PULSE-WIDTH VARIATION (%)
OUTPUT PULSE-WIDTH VARIATION (%)
8
(Continued)
100
101
102
103
104
105
Q OR Q FREQUENCY (F) (Hz)
FIGURE 27. TYPICAL POWER DISSIPATION vs OUTPUT
FREQUENCY (VDD = 10V)
7-908
106
CD4047BMS
Typical Performance Characteristics
(Continued)
ASTABLE MODE
SUPPLY VOLTAGE (VDD) = 15V
POWER DISSIPATION (PD) (W)
105
C =100pF
C = 0.01F
104
C =1000pF
C =10pF
C = 0.1F
103
102
10-1
100
101
102
103
104
105
106
Q OR Q FREQUENCY (F) (Hz)
FIGURE 28. TYPICAL POWER DISSIPATION vs OUTPUT FREQUENCY (VDD = 15V)
Astable Mode Design Information
Monostable Mode Design Information
Unit-to-Unit Transfer Voltage Variations
The following analysis presents variations from unit to unit as a
function of transfer voltage (VTR) shift (33% - 67% VDD) for
one shot (monostable) operation.
The following analysis presents variations from unit to unit
as a function of transfer voltage (VTR) shift (33%-67% VDD)
for free running (astable) operation.
TERMINAL 13
TERMINAL 10
t1
t2
t1
TERMINAL 8
t2
TERMINAL 13
tA/2
tA/2
TERMINAL 10
tA
t2 = -RC In
VTR
;
VDD + VTR
typically, t1 = 1.1RC
t1´ = -RC In
tM
t1´
t2
tM
VTR
;
2VDD
typically, t1´ = 1.38RC
tM = (t1´ + t2)
VDD - VTR
;
2VDD - VTR
typically, t2 = 1.1RC
tM = -RC In
(VTR)(VDD - VTR)
(2VDD - VTR)(2VDD)
where tM = Monostable mode pulse width.
Values for tM are as follows:
tA = 2(t1 + t2)
= -2RC In
t2
FIGURE 30. MONOSTABLE WAVEFORMS
FIGURE 29. ASTABLE MODE WAVEFORMS
t1 = -RC In
t1´
(VTR)(VDD - VTR)
(VDD + VTR)(2VDD - VTR)
Typ: VTR = 0.5VDD
Min: VTR = 0.33VDD
Max: VTR = 0.67VDD
Typ: VTR = 0.5VDD
Min: VTR = 0.33VDD
Max: VTR = 0.67VDD
tA = 4.40RC
tA = 4.62RC
tA = 4.62RC
tM = 2.48RC
tM = 2.71RC
tM = 2.48RC
thus if tM = 2.48RC is used, the variation will be +9.3%,
-0% due to variations in transfer voltage.
thus if tA = 4.40RC is used, the variation will be +5%, -0%
due to variations in transfer voltage.
Variations Due to VDD and Temperature Changes
In addition to variations from unit to unit, the astable period
varies with VDD and temperature, Typical variations are presented in graphical form in Figures 11 to 18 with 10V as reference for voltage variations curves and +25oC as reference
for temperature variations curves.
NOTES:
1. In the astable mode, the first positive half cycle has a duration of
tM; succeeding durations are tA/s.
2. In addition to variations from unit to unit, the monostable pulse
width varies with VDD and temperature. These variations are
presented in graphical form in Figures 19 to 26 with 10V as reference for voltage variation curves and +25oC as reference for
temperature variation curves.
7-909
CD4047BMS
Retrigger Mode Operation
The CD4047BMS can be used in the retrigger mode to extend
the output pulse duration, or to compare the frequency of an
input signal with that of the internal oscillator. In the retrigger
mode the input pulse is applied to terminal 12, and the output is
taken from terminal 10 or 11. As shown in Figure 31 normal
monostable action is obtained when one retrigger pulse is
applied. Extended pulse duration is obtained when more than
one pulse is applied.
For two input pulses, tRE = t1´ + t1 + 2t2. For more than two
pulses, the output pulse width is an integral number of time periods, with the first time period being t1´ + t2, typically, 2.48RC,
and all subsequent time periods being t1 + t2, typically, 2.2RC.
External Counter Option
Time tM can be extended by any amount with the use of external
counting circuitry. Advantages include digitally controlled pulse
duration, small timing capacitors for long time periods, and
extremely fast recovery time. A typical implementation is shown
in Figure 32. The pulse duration at the output is
text = (N - 1) (tA) + (tM + tA/2)
where text = pulse duration of the circuitry, and N is the number
of counts used.
However, in consideration of accuracy, C must be much larger
than the inherent stray capacitance in the system (unless this
capacitance can be measured and taken into account). R must
be much larger than the CMOS “ON” resistance in series with it,
which typically is hundreds of . In addition, with very large values of R, some short term instability with respect to time may
be noted.
The recommended values for these components to maintain
agreement with previously calculated formulas without trimming
should be:
C  100pF, up to any practical value, for astable modes;
C  1000pF, up to any practical value for monostable modes.
10k  R  1M
Power Consumption
In the standby mode (Monostable or Astable), power dissipation will be a function of leakage current in the circuit, as shown
in the static electrical characteristics. For dynamic operation,
the power needed to charge the external timing capacitor C is
given by the following formula:
Astable Mode:
P = 2CV2f. (Output at terminal No. 13)
CD4047BMS
Q
P = 4CV2f. (Output at terminal Nos. 10 and 11)
OPTIONAL
BUFFER
AST
CD4017BMS
CL
R
Monostable Mode:
OUT
12
P=
11
INPUT
PULSE
TEXT
(2.9CV2) (Duty Cycle)
T
(Output at terminal Nos. 10 to 11)
Timing Component Limitations
The circuit is designed so that most of the total power is consumed in the external components. In practice, the lower the
values of frequency and voltage used, the closer the actual
power dissipation will be to the calculated value.
The capacitor used in the circuit should be non polarized and
have low leakage (i.e. the parallel resistance of the capacitor
should be at least an order of magnitude greater than the external resistor used). There is no upper or lower limit for either R or
C value to maintain oscillation.
Because the power dissipation does not depend on R, a
design for minimum power dissipation would be a small value
of C. The value of R would depend on the desired period
(within the limitations discussed above). See Figures 26, 27,
and 28 for typical power consumption in astable mode.
FIGURE 32. IMPLEMENTATION OF EXTERNAL COUNTER OPTION
+TRIGGER &
RETRIGGER
TERMINALS
8 & 12
OSC OUTPUT
TERMINAL 13
Q OUTPUT
TERMINAL 10
t1´
t2
tRE
t1´
t2
t1´ t2
t1´ t2
tRE
t1´ t2
t1´ t2
t1´
tRE
FIGURE 31. RETRIGGER MODE WAVEFORMS
7-910
t2
t1´
t2
t1´
t2
tRE
t1´ t2
CD4047BMS
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION: Thickness: 11kÅ 14kÅ,
AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9001 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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