DATASHEET

DG401, DG403
®
Data Sheet
November 20, 2006
FN3284.11
Monolithic CMOS Analog Switches
Features
The DG401 and DG403 monolithic CMOS analog switches
have TTL and CMOS compatible digital inputs.
• ON Resistance (Max) . . . . . . . . . . . . . . . . . . . . . . . . . 45Ω
These switches feature low analog ON resistance (<45Ω)
and fast switch time (tON<150ns). Low charge injection
simplifies sample and hold applications.
• Fast Switching Action
- tON (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150ns
- tOFF (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ns
The improvements in the DG401, DG403 series are made
possible by using a high voltage silicon-gate process. An
epitaxial layer prevents the latch-up associated with older
CMOS technologies. The 44V maximum voltage range
permits controlling 30VP-P signals. Power supplies may be
single-ended from +5V to +34V, or split from ±5V to ±17V.
• Low Charge Injection
The analog switches are bilateral, equally matched for AC or
bidirectional signals. The ON resistance variation with analog
signals is quite low over a ±15V analog input range. The three
different devices provide the equivalent of two SPST (DG401)
or two SPDT (DG403) relay switch contacts with CMOS or
TTL level activation. The pinout is similar, permitting a
standard layout to be used, choosing the switch function as
needed.
• Pb-Free Plus Anneal Available (RoHS Compliant)
• Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . .<35μW
• DG401 Dual SPST; Same Pinout as HI-5041
• DG403 Dual SPDT; DG190, IH5043, IH5151, HI-5051
• TTL, CMOS Compatible
• Single or Split Supply Operation
Applications
• Audio Switching
• Battery Operated Systems
• Data Acquisition
• Hi-Rel Systems
• Sample and Hold Circuits
Pinouts
DG401
(16 LD SOIC, TSSOP)
TOP VIEW
• Communication Systems
• Automatic Test Equipment
Ordering Information
D1 1
16 S1
NC 2
15 IN1
NC 3
14 V-
NC 4
13 GND
DG401DY*
DG401DY
-40 to +85
16 Ld SOIC
M16.15
NC 5
12 VL
-40 to +85
16 Ld SOIC
(Pb-free)
M16.15
11 V+
DG401DYZ*
(Note)
DG401DYZ
NC 6
NC 7
10 IN2
DG401 DVZ
-40 to +85
D2 8
9 S2
DG401DVZ*
(Note)
16 Ld TSSOP M16.173
(Pb-free)
DG403DY*
DG403DY
-40 to +85
16 Ld SOIC
M16.15
DG403DYZ*
(Note)
DG403DYZ
-40 to +85
16 Ld SOIC
(Pb-free)
M16.15
DG403DVZ*
(Note)
DG403 DVZ
-40 to +85
16 Ld TSSOP M16.173
(Pb-free)
DG403
(16 LD SOIC, TSSOP)
TOP VIEW
PART
NUMBER*
PART
TEMP.
MARKING RANGE (°C)
PACKAGE
PKG.
DWG. #
D1 1
16 S1
*Add “-T” suffix for tape and reel.
NC 2
15 IN1
D3 3
14 V-
S3 4
13 GND
S4 5
12 VL
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
D4 6
11 V+
NC 7
10 IN2
D2 8
9 S2
NOTE: (NC) No Connection.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 1999, 2002-2004, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
TRUTH TABLE
DG401
DG403
LOGIC
SWITCH
SWITCH 1, 2
SWITCH 3, 4
0
OFF
OFF
ON
1
ON
ON
OFF
NOTE:
Logic “0” ≤0.8V. Logic “1” ≥2.4V.
Functional Diagrams
DG401
VL
DG403
V+
12
S1
VL
11
16
12
1
S1
D1
S3
IN1 15
IN2
S2
V+
11
16
1
4
3
D1
D3
IN1 15
10
IN2
9
8
D2
S2
S4
13
14
GND
10
9
8
5
6
13
V-
GND
D2
D4
14
V-
SWITCHES SHOWN FOR LOGIC “1” INPUT
Schematic Diagram
V+
SOURCE
VVL
VIN
V+
GND
DRAIN
V-
2
FN3284.11
November 20, 2006
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V
GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to (V+) +0.3V
Digital Inputs VS , VD (Note 1) . . . . . (V-) -2V to (V+) + 2V or 30mA,
Whichever Occurs First
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle, Max) . . 100mA
Thermal Resistance (Typical, Note 2)
θJA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
115
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
150
Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . -65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
(SOIC and TSSOP- Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20V (Max)
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max)
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min)
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20ns
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Signals on SX , DX , or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Test Conditions: V+ = +15V, V- = -15V, VIN = 2.4V, 0.8V (Note 3), VL = 5V,
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
TEMP
(°C)
(NOTE 4)
MIN
(NOTE 5)
TYP
(NOTE 4)
MAX
+25
-
100
150
ns
+25
-
60
100
ns
UNITS
DYNAMIC CHARACTERISTICS
RL = 300Ω, CL = 35pF
Turn-ON Time, tON
Turn-OFF Time, tOFF
Break-Before-Make Time Delay (DG403), tD
RL = 300Ω, CL = 35pF
+25
5
12
-
ns
Charge Injection, Q (Figure 3)
CL = 10nF, VG = 0V, RG = 0Ω
+25
-
60
-
pC
OFF Isolation (Figure 4)
RL = 100Ω, CL = 5pF, f = 1MHz
+25
-
72
-
dB
+25
-
-90
-
dB
+25
-
12
-
pF
Drain OFF Capacitance, CD(OFF)
+25
-
12
-
pF
Channel ON Capacitance, CD(ON) + CS(ON)
+25
-
39
-
pF
Crosstalk (Channel-to-Channel) (Figure 6)
Source OFF Capacitance, CS(OFF)
f = 1MHz, VS = VD = 0V (Figure 7)
DIGITAL INPUT CHARACTERISTICS
Input Current with VIN Low, IIL
VIN Under Test = 0.8V, All Others = 2.4V
Full
-1
0.005
1
μA
Input Current with VIN High, IIH
VIN Under Test = 2.4V, All Others = 0.8V
Full
-1
0.005
1
μA
Full
-15
-
15
V
+25
-
20
45
Ω
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
Drain-Source ON Resistance, rDS(ON)
V+ = 13.5V, V- = -13.5V,
IS = 10mA, VD = ±10V
Full
-
-
55
Ω
rDS(ON) Matching Between Channels, ΔrDS(ON) V+ = 16.5V, V- = -16.5V,
IS = -10mA, VD = 5, 0, -5V
+25
-
3
3
Ω
Full
-
-
5
Ω
V+ = 16.5V, V- = -16.5
VD = ±15.5V, VS = 15.5V
+25
-0.5
-0.01
0.5
nA
Full
-5
-
5
nA
+25
-0.5
-0.01
0.5
nA
Full
-5
-
5
nA
+25
-1
-0.04
1
nA
Full
-10
-
10
nA
Source OFF Leakage Current, IS(OFF)
Drain OFF Leakage Current, ID(OFF)
Channel ON Leakage Current, ID(ON) + IS(ON)
3
V± = ±16.5V, VD = VS = ±15.5V
FN3284.11
November 20, 2006
Electrical Specifications
Test Conditions: V+ = +15V, V- = -15V, VIN = 2.4V, 0.8V (Note 3), VL = 5V,
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
TEMP
(°C)
(NOTE 4)
MIN
(NOTE 5)
TYP
(NOTE 4)
MAX
+25
-
0.01
1
μA
Full
-
-
5
μA
+25
-1
-0.01
-
μA
Full
-5
-
-
μA
+25
-
0.01
1
μA
Full
-
-
5
μA
+25
-1
-0.01
-
μA
Full
-5
-
-
μA
UNITS
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 16.5V, V- = -16.5V,
VIN = 0V or 5V
Negative Supply Current, I-
Logic Supply Current, IL
Ground Current, IGND
NOTES:
3. VIN = input voltage to perform proper function.
4. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
5. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Test Circuits and Waveforms
3V
LOGIC
INPUT
tr < 20ns
tf < 20ns
50%
VL
0V
tOFF
SWITCH
INPUT
SWITCH
INPUT
VS
+15V
RL = 300Ω
CL = 35pF
V+
VO
D1
S1
IN1
VO
SWITCH
OUTPUT
5V
90%
90%
RL
LOGIC
INPUT
0V
GND
tON
CL
V-
10%
SWITCH
INPUT -VS
(NOTE 7)
0V
NOTES:
6. Logic input waveform is inverted for switches that have the
opposite logic sense.
7. VS = 10V for tON , VS = -10V for tOFF.
-15V
Repeat test for IN2 and S2.
For load conditions, see Specifications. CL includes fixture and stray
capacitance.
RL
V O = V S -----------------------------------R L + r DS ( ON )
FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
4
FN3284.11
November 20, 2006
Test Circuits and Waveforms
(Continued)
5V
3V
LOGIC
INPUT
+15V
VL
RL = 300Ω
CL = 35pF
V+
0V
SWITCH
OUTPUT
(VO1)
D2
VS2 = 10V
90%
VO1
D1
VS1 = 10V
VS1
VO2
GND
90%
V-
0V
tD
tD
CL2
RL2
LOGIC
INPUT
VS2
0V
CL1
IN1
0V
SWITCH
OUTPUT
(VO2)
RL1
-15V
CL includes fixture and stray capacitance.
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. BREAK-BEFORE-MAKE TIME
5V
+15V
VL
SWITCH
OUTPUT
VO
ΔVO
ON
INX
V+
RG
VO
VG
ON
OFF
D1
CL
V-
GND
Q = ΔVO x CL
0V
FIGURE 3A. MEASUREMENT POINTS
-15V
FIGURE 3B. TEST CIRCUIT
FIGURE 3. CHARGE INJECTION
C
SIGNAL
GENERATOR
V+
+15V
+5V
VL
C
C
SIGNAL
GENERATOR
VS
INX
RL
GND
C
-15V
FIGURE 4. OFF ISOLATION TEST CIRCUIT
5
+5V
VL
C
VS
INX
0V, 2.4V
VD
ANALYZER
V-
+15V
0V, 2.4V
VD
ANALYZER
V+
RL
GND
V-
C
-15V
FIGURE 5. INSERTION LOSS TEST CIRCUIT
FN3284.11
November 20, 2006
Test Circuits and Waveforms
V+
C
(Continued)
+5V
+15V
VL
C
+15V
C
SIGNAL
GENERATOR
VS1
+5V
V+
VL
C
50Ω
VD1
VS
IN1
0V, 2.4V
IN2
0V, 2.4V
AS REQUIRED
IMPEDANCE
ANALYZER
VS2
VD2
ANALYZER
INX
0V, 2.4V
VD
NC
C
RL
V-
GND
-15V
C
V-
GND
-15V
FIGURE 7. CAPACITANCES TEST CIRCUIT
FIGURE 6. CROSSTALK TEST CIRCUIT
Application Information
Dual Slope Integrators
Peak Detector
The DG403 is well suited to configure a selectable slope
integrator. One control signal selects the timing capacitor C1
or C2 . Another one selects eIN or discharges the capacitor in
preparation for the next integration cycle.
A3 acting as a comparator provides the logic drive for
operating SW1 . The output of A2 is fed back to A3 and
compared to the analog input eIN . If eIN > eOUT the output of
A3 is high keeping SW1 closed. This allows C1 to charge up
to the analog input voltage. When eIN goes below eOUT, A3
goes negative, turning SW1 off. The system will therefore
store the most positive analog input experienced.
+5V
+15V
VL
eIN
V+
S1
D1
S3
D2
eOUT
RESET
SW2
IN1
TTL
INTEGRATE/
RESET
S2
D3
S4
D4
C1
+
SW1
DG403
V-
A2
eOUT
C1
C2
GND
R1
+
-
eIN
IN2
SCOPE
SELECT
A1
+
A3
DG401
-15V
FIGURE 8. DUAL SLOPE INTEGRATOR
6
FIGURE 9. POSITIVE PEAK DETECTOR
FN3284.11
November 20, 2006
Typical Performance Curves
10
4
V+ = 15V
V- = -15V
TA = 20°C
8
VL = 5V
TA = 25°C
3
VT (V)
VT (V)
6
DG403
SW3, 4
4
2
1
2
0
0
0
2
4
6
8
10
12
VL (V)
14
16
18
20
0
2
4
6
8
10
12
14
SUPPLY VOLTAGE (±V)
16
18
20
FIGURE 11. INPUT SWITCHING THRESHOLD vs
POWER SUPPLY VOLTAGE
FIGURE 10. INPUT SWITCHING THRESHOLD vs LOGIC
SUPPLY VOLTAGE
60
40
V+ = 15V
V- = -15V
VL = 5V
35
TA = 25°C
50
125°C
rDS(ON) (Ω)
rDS(ON) (Ω)
30
25
85°C
20
25°C
15
-40°C
40
V+ = 12V, V- = -12V
V+ = 15V, V- = -15V
V+ = 20V, V- = -20V
V+ = 6V, V- = -6V
V+ = 10V, V- = -10V
V+ = 22V, V- = -22V
30
0°C
20
-55°C
10
-15
10
-10
-5
0
VD (V)
5
10
15
-25
-15
5
15
25
VD (V)
FIGURE 13. rDS(ON) vs VD AND POWER SUPPLY VOLTAGE
FIGURE 12. rDS(ON) vs VD AND TEMPERATURE
70
200
V- = 0V
TA = 25°C
V+ = 15V
V- = -15V
VL = 5V
180
60
160
V+ = 7.5V
CL = 10nF
140
50
120
V+ = 10V
Q (pC)
rDS(ON) (Ω)
-5
40
V+ = 12V
80
V+ = 15V
30
60
V+ = 20V
40
V+ = 22V
20
CL = 1nF
100
CL = 100pF
20
0
10
0
5
10
15
20
25
VD (V)
FIGURE 14. rDS(ON) vs VD AND SINGLE SUPPLY VOLTAGE
7
-15
-10
-5
0
5
10
15
VS (V)
FIGURE 15. CHARGE INJECTION vs SOURCE VOLTAGE
FN3284.11
November 20, 2006
Typical Performance Curves
(Continued)
0.0
100.0
-0.5
10.0
1.0
IS(OFF) (nA)
LOSS (dB)
RL = 600Ω
-1.0
RL = 75Ω
-1.5
RL = 50Ω
V+ = 15V, V- = -15V
VL = 5V, VS = 1VRMS
SEE INSERTION LOSS TEST SETUP
(FIGURE 5)
-2.0
V+ = 15V
V- = -15V
VL = 5V
VD = ±14V
TYPICAL
0.1
0.01
0.001
0.0001
10K
100K
1M
FREQUENCY (Hz)
-55 -35
10M
10.0
ID(ON) + IS(ON) (nA)
ID(OFF) (nA)
100.0
1.0
TYPICAL
0.1
0.01
0.001
65
85
105
125
105
125
V+ = 15V
V- = -15V
VL = 5V
VD = ±14V
1.0
TYPICAL
0.1
0.01
0.0001
-55 -35
-15
5
25
45
65
85
105
-55 -35
125
-15
5
25
45
65
85
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 18. ID(OFF) vs TEMPERATURE
60
45
0.001
0.0001
90
25
FIGURE 17. IS(OFF) vs TEMPERATURE
V+ = 15V
V- = -15V
VL = 5V
VD = ±14V
10.0
5
TEMPERATURE (°C)
FIGURE 16. INSERTION LOSS vs FREQUENCY
100.0
-15
FIGURE 19. ID(ON) + IS(ON) vs TEMPERATURE
10.0
WHEN VANALOG EXCEEDS POWER
SUPPLY, SWITCH SUBSTRATE
DIODES BEGIN TO CONDUCT
1.0
I+
V+ = 15V
V- = -15V
VL = 5V
IL
0
I+, I -, IL , (μA)
IS , ID (pA)
30
ID(OFF) , IS(OFF)
-30
ID(ON) + IS(ON)
-60
I0.1
0.01
V+ = 15V, V- = -15V
-90
VL = 5V, TA = 25°C
ID(OFF) , VS = 0V
IS(OFF) , VD = 0V
-120
-150
-20
-15
-10
-5
0
VS , VD (V)
5
10
15
20
FIGURE 20. LEAKAGE CURRENTS vs ANALOG VOLTAGE
8
0.001
IL
I0.0001
-55 -35
-15
5
25
45
65
85
105
125
TEMPERATURE (°C)
FIGURE 21. SUPPLY CURRENT vs TEMPERATURE
FN3284.11
November 20, 2006
Typical Performance Curves
(Continued)
20
40
V+ = 15V
V- = -15V
VL = 5V
10
30
VS (V)
5
0
NOT MEASURABLE DUE TO
CAPACITIVE FEEDTHROUGH
-5
VL = 5V
35
tON , tOFF (ns)
15
-10
VS = 10V
25
20
VS = -10V
15
10
-20
5
SEE BBM TEST SETUP (FIGURE 2)
SEE BBM TEST SETUP (FIGURE 2)
0
-15
0
10
20
30
40
50
0
5
BREAK-BEFORE-MAKE TIME (ns)
600
240
V+ = 15V
V- = -15V
VL = 5V
480
tON , tOFF (ns)
tON , tOFF (ns)
300
240
tON , VS = 10V
tON , VS = -10V
tON , VS = 10V
150
120
tOFF , VS = -10V
90
tON , VS = -10V
60
tOFF, VS = 10V
tOFF, VS = 10V
30
60
tOFF, VS = -10V
0
0
1
2
3
0
4
5
-55 -35
6
-15
VIN (V)
200
140
VL = 5V
tON , tOFF (ns)
100
VS = -5V
tOFF
80
V- = 0V
270
VS = 5V
tOFF
120
45
65
85
105 125
FIGURE 25. SWITCHING TIME vs TEMPERATURE (NOTE 8)
VS = -5V
tON
160
25
300
VS = 5V
tON
180
5
TEMPERATURE (°C)
FIGURE 24. SWITCHING TIME vs INPUT LOGIC VOLTAGE
(NOTE 8)
tON , tOFF (ns)
25
180
360
120
20
V+ = 15V
V- = -15V
VL = 5V
210
420
180
15
FIGURE 23. BREAK-BEFORE-MAKE vs POWER
SUPPLY VOLTAGE
FIGURE 22. BREAK-BEFORE-MAKE vs ANALOG VOLTAGE
540
10
SUPPLY VOLTAGE (±V)
240
V- = -5V
210
V+V-= =-15V
-15
VS = 5V
tON
180
tON
V- = -15V
150
tON
120
60
90
40
60
20
30
V- = 0V
V- = -5V
V- = 0V
tOFF
0
0
0
5
10
15
SUPPLY VOLTAGE (±V)
20
25
FIGURE 26. SWITCHING TIME vs POWER SUPPLY VOLTAGE
(NOTE 8)
9
0
5
10
15
20
25
POSITIVE SUPPLY (V)
FIGURE 27. SWITCHING TIME vs POSITIVE SUPPLY
VOLTAGE (NOTE 8)
FN3284.11
November 20, 2006
Typical Performance Curves
(Continued)
300
VS = -5V
270
240
tON , tOFF (ns)
210
180
V- = -5V
150
V- = -15V
tON
120
V- = -15V
tON
90
tOFF
V- = -5V
60
tOFF
30
0
0
5
10
15
20
25
POSITIVE SUPPLY (V)
FIGURE 28. SWITCHING TIME vs POSITIVE SUPPLY VOLTAGE (NOTE 8)
NOTE:
8. Refer to Figure 1 for test conditions.
10
FN3284.11
November 20, 2006
Thin Shrink Small Outline Plastic Packages (TSSOP)
M16.173
N
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
E
0.25(0.010) M
2
INCHES
E1
GAUGE
PLANE
-B1
B M
L
0.05(0.002)
-A-
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.043
-
1.10
-
A1
3
A
D
-C-
e
α
c
0.10(0.004)
C A M
0.05
0.15
-
A2
0.033
0.037
0.85
0.95
-
b
0.0075
0.012
0.19
0.30
9
c
0.0035
0.008
0.09
0.20
-
B S
0.002
D
0.193
0.201
4.90
5.10
3
0.169
0.177
4.30
4.50
4
0.026 BSC
E
0.246
L
0.020
N
α
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
0.006
E1
e
A2
A1
b
0.10(0.004) M
0.25
0.010
SEATING PLANE
MILLIMETERS
0.65 BSC
0.256
6.25
0.028
0.50
16
0°
-
6.50
-
0.70
6
16
8°
0°
7
8°
Rev. 1 2/02
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
11
FN3284.11
November 20, 2006
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
N
INDEX
AREA
H
0.25(0.010) M
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
B M
INCHES
E
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.3859
0.3937
9.80
10.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
16
0°
16
8°
0°
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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12
FN3284.11
November 20, 2006
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