DATASHEET

ISL54058
®
Data Sheet
September 29, 2006
Ultra Low ON-Resistance, Low-Voltage,
Single Supply, Dual 4 to 1 Analog
Multiplexer
The Intersil ISL54058 device contains precision, bidirectional,
analog switches configured as a dual 4-channel
multiplexer/demultiplexer, designed to operate from a single
+1.6V to +3.6V supply.
ON resistance is 0.41Ω with a +3V supply and 0.61Ω with a
single +1.8V supply. Each switch can handle rail to rail
analog signals. The off-leakage current is only 4nA max at
+25°C or 40nA max at +85°C with a +3.3V supply.
FN6380.0
Features
• Pb-Free Plus Anneal Available (RoHS Compliant)
• ON Resistance (RON)
- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.41Ω
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.61Ω
• RON Matching Between Channels. . . . . . . . . . . . . . . . 0.09Ω
• RON Flatness Across Signal Range . . . . . . . . . . . . . . 0.07Ω
• Single Supply Operation. . . . . . . . . . . . . . . . . +1.6V to +3.6V
• Low Power Consumption (PD). . . . . . . . . . . . . . . . . <0.18µW
All digital inputs are 1.8V logic-compatible when using a
single +3V supply.
• Fast Switching Action (VS = +3V)
- tRANS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29ns
• Break-Before-Make
The ISL54058 is a dual 4 to 1 multiplexer device that is
offered in a 16 Ld 2.6x1.8x0.5mm µTQFN package.
• High Current Handling Capacity (300mA Continuous)
• Available in 16 Ld 2.6x1.8x0.5mm µTQFN
Table 1 summarizes the performance of this family.
• 1.8V CMOS-Logic Compatible (+3V Supply)
TABLE 1. FEATURES AT A GLANCE
Applications
ISL54058
Configuration
Dual 4:1 Mux
3V RON
0.41Ω
3V tRANS
29ns
1.8V RON
0.61Ω
1.8V tRANS
34ns
Packages
16 Ld 2.6x1.8x0.5mm µTQFN
• Battery Powered, Handheld, and Portable Equipment
- Cellular/Mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
Ordering Information
PART NUMBER (NOTE)
ISL54058IRUZ-T
PART MARKING
GAC
TEMP. RANGE (°C)
-40 to +85
PACKAGE
16 Ld Thin µQFN Tape and Reel (Pb-free)
PKG. DWG. #
L16.2.6x1.8A
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54058
Pinouts
(Note 1)
8
B3
9
4
ADDA0
7
B0
10
3
A1
ADDB1
6
COMB
11
2
A3
ADDB0
GND
5
B1
13
14
1
A2
COMA
A0
15
V+
16
B2
12
ISL54058
(16 LD µTQFN)
TOP VIEW)
ADDA1
NOTE:
1. 2.6mmx1.8mmx0.5mm
Truth Table
Pin Descriptions
ISL54058
PIN
FUNCTION
ADDA1
ADDA0
ADDB1
ADDB0
SWITCH ON
V+
System Power Supply Input (1.6V to 3.6V)
0
0
X
X
A0
GND
0
1
X
X
A1
COMA
Analog Switch Channel A Output
1
0
X
X
A2
COMB
Analog Switch Channel B Output
1
1
X
X
A3
A0-A3
Analog Switch Channel A Input
X
X
0
0
B0
B0-B3
Analog Switch Channel B Input
X
X
0
1
B1
ADDAx
Address Input Pin
X
X
1
0
B2
ADDBx
Address Input Pin
X
X
1
1
B3
Ground Connection
NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V, with a 3V supply.
X = Don’t Care.
2
FN6380.0
September 29, 2006
ISL54058
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V
Input Voltages
Ax, Bx, ADDx (Note 2) . . . . . . . . . . . . . . . . . . -0.3 to (V+) + 0.3V
Output Voltages
COMx (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V+) + 0.3V
Continuous Current NO or COM . . . . . . . . . . . . . . . . . . . . . ±300mA
Peak Current NO or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA
ESD Rating
HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4kV
MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300V
CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1kV
Thermal Resistance (Typical, Note 3)
θJA (°C/W)
µTQFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
93
Maximum Junction Temperature (Plastic Package) . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . . . -65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
(Lead Tips Only)
Operating Conditions
Temperature Range
ISL54058IRUZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. Signals on Ax, Bx, COMx, ADDx exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications: 3V Supply
PARAMETER
Test Conditions: VSUPPLY = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4,
8), Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
Full
0
-
V+
V
25
-
0.43
0.75
Ω
Full
-
-
0.8
Ω
25
-
0.09
0.2
Ω
TYP
(NOTE 5)
MAX
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 2.7V, ICOM = 100mA, VAx or VBx = 0V to V+
(See Figure 4)
RON Matching Between Channels,
∆RON
V+ = 2.7V, ICOM = 100mA, VAx or VBx = Voltage at max
RON (Note 6)
RON Flatness, RFLAT(ON)
V+ = 2.7V, ICOM = 100mA, VAx or VBx = 0V t0 V+
(Note 7)
Ax or Bx OFF Leakage Current,
IAx(OFF) or IBx(OFF)
V+ = 3.3V, VCOM = 0.3V, 3V, VAx or VBx = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V+ = 3.3V, VCOM = VAx or VBx = 0.3V, 3V
Full
-
-
0.2
Ω
25
-
0.07
0.15
Ω
Full
-
-
0.15
Ω
nA
25
-4
-
4
Full
-40
-
40
nA
25
-8
-
8
nA
Full
-60
-
60
nA
Input Voltage High, VINH, VADDH
Full
1.4
-
-
V
Input Voltage Low, VINL, VADDL
Full
-
-
0.5
V
V+ = 3.3V, VINH = VADD = 0V or V+
Full
-0.5
-
0.5
µA
V+ = 2.7V, VAx or VBx = 1.5V, RL = 50Ω, CL = 35pF
(See Figure )
25
-
29
-
ns
Full
-
40
-
ns
25
-
4
-
ns
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL, IADDH,
IADDL
DYNAMIC CHARACTERISTICS
Address Transition Time, tTRANS
Break-Before-Make Time, tBBM
V+ = 3.3V, VAx or VBx = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 2)
Full
-
1
-
ns
Ax or Bx OFF Capacitance, COFF
f = 1MHz, VAx or VBx = VCOM = 0V (See Figure 6)
25
-
44
-
pF
COM ON Capacitance, CCOM(ON)
f = 1MHz, VAx or VBx = VCOM = 0V (See Figure 6)
25
-
201
-
pF
OFF Isolation
RL = 50Ω, CL = 35pF, f = 100kHz (See Figures 3 and 5)
Crosstalk (Note 9)
3
25
-
65
-
dB
25
-
-100
-
dB
FN6380.0
September 29, 2006
ISL54058
Electrical Specifications: 3V Supply
PARAMETER
Test Conditions: VSUPPLY = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4,
8), Unless Otherwise Specified (Continued)
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
Full
1.6
3.6
V
25
-
-
0.05
µA
Full
-
-
1.1
µA
TYP
(NOTE 5)
MAX
UNITS
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = 3.3V, VINH, VADD = 0V or V+, Switch On or Off
NOTES:
4. VIN = Input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. RON matching between channels is calculated by subtracting the channel with the highest max RON value from the channel with lowest max
RON value.
7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
8. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
9. Between any two switches.
Electrical Specifications: 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Note 4, 8),
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(NOTE 5)
Full
0
-
V+
V
25
-
0.61
0.85
Ω
Full
-
-
0.9
Ω
Ω
TYP
MAX
(NOTE 5) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 1.8V, ICOM = 10.0mA, VAx or VBx = 1.0V
(See Figure 4)
RON Matching Between Channels,
∆RON)
V+ = 1.8V, ICOM = 10.0mA, VAx or VBx = 1.0V (Note 6)
RON Flatness, RFLAT(ON)
V+ = 1.8V, ICOM = 10.0mA, VAx or VBx = 0V, 0.9V,
1.6V (Note 7)
25
-
0.11
-
Full
-
0.12
-
Ω
25
-
0.19
-
Ω
Full
-
0.19
-
Ω
Input Voltage High, VINH, VADDH
Full
1
-
-
V
Input Voltage Low, VINL, VADDL
Full
-
-
0.4
V
V+ = 1.8V, VINH, VADD = 0V or V+
Full
-0.5
-
0.5
µA
V+ = 1.8V, VAx or VBx = 1.0V, RL = 50Ω, CL =
35pF(See Figure 1)
25
-
34
-
ns
Full
-
44
-
ns
25
-
9
-
ns
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL, IADDH,
IADDL
DYNAMIC CHARACTERISTICS
Address Transition Time, tTRANS
Break-Before-Make Time, tBBM
V+ = 1.8V, VAx or VBx = 1.0V, RL = 50Ω, CL = 35pF
(See Figure 2)
4
FN6380.0
September 29, 2006
ISL54058
Test Circuits and Waveforms
V+
LOGIC
INPUT
tr < 5ns
tf < 5ns
50%
V+
C
C
0V
tTRANS
V+
B1-B3
90%
SWITCH
OUTPUT
ADD1-0 GND
VOUT
RL
50Ω
LOGIC
INPUT
10%
0V
COMA
COMB
A1-A3
VOUT
VA0, VB0
A0,B0
CL
35pF
0V
tTRANS
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for other switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (NO or NC) -----------------------------R L + R ( ON )
FIGURE 1B. ADDRESS tTRANS TEST CIRCUIT
FIGURE 1A. ADDRESS tTRANS MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
V+
tr < 5ns
tf < 5ns
V+
C
C
LOGIC
INPUT
0V
A0-A3
B0-B3
V+
ADD1-0
90%
SWITCH
OUTPUT
VOUT
0V
COMA
COMB
VOUT
RL
50Ω
CL
35pF
LOGIC
INPUT
tBBM
GND
FIGURE 2A. tBBM MEASUREMENT POINTS
Repeat test for other switches. CL includes fixture and stray
capacitance.
FIGURE 2B. tBBM TEST CIRCUIT
FIGURE 2. BREAK-BEFORE-MAKE TIME
5
FN6380.0
September 29, 2006
ISL54058
Test Circuits and Waveforms (Continued)
V+
V+
C
SIGNAL
GENERATOR
C
RON = V1/100mA
Ax or Bx
Ax or Bx
VNX
100mA
0V or V+
ADDX
ANALYZER
COMx
0V or V+
V1
ADDX
COMx
GND
GND
RL
FIGURE 4. RON TEST CIRCUIT
FIGURE 3. OFF ISOLATION TEST CIRCUIT
V+
SIGNAL
GENERATOR
V+
C
50Ω
Ax
0V or V+
Ax or Bx
COMA
0V or V+
ADDX
COMB
ADDX
IMPEDANCE
ANALYZER
Bx
ANALYZER
C
N.C.
COMx
GND
GND
RL
FIGURE 5. CROSSTALK TEST CIRCUIT
Detailed Description
The ISL54058 analog switches offer precise switching
capability from a single 1.6V to 3.6V supply with low
on-resistance (0.41Ω) and high speed operation
(tRANS = 29ns). The device is especially well suited to
portable battery powered equipment thanks to the low
operating supply voltage (1.6V), low power consumption
(0.17µW), low leakage currents (60nA max) , and the tiny
µTQFN package. The ultra low on-resistance and RON
flatness provide very low insertion loss and distortion to
applications that require signal reproduction.
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 7). To prevent forward biasing these diodes, V+ must
6
FIGURE 6. CAPACITANCE TEST CIRCUIT
be applied before any input signals, and the input signal
voltages must remain between V+ and GND.
OPTIONAL
SCHOTTKY
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
ADDX
Ax or Bx
VCOMX
GND
OPTIONAL
SCHOTTKY
DIODE
FIGURE 7. OVERVOLTAGE PROTECTION
FN6380.0
September 29, 2006
ISL54058
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
Logic inputs can be protected by adding a 1kΩ resistor in
series with the logic input (see Figure 7). The resistor limits
the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low RON switch. Connecting schottky
diodes to the signal pins as shown in Figure 7 will shunt the
fault current to the supply or to ground thereby protecting the
switch. These schottky diodes must be sized to handle the
expected fault current.
Power-Supply Considerations
The ISL54058 construction is typical of most CMOS analog
switches, in that they have two supply pins: V+ and GND. V+
and GND drive the internal CMOS switches and set their
analog voltage limits. Unlike switches with a 4V maximum
supply voltage, the ISL54058 4.7V maximum supply voltage
provides plenty of room for the 10% tolerance of 3.6V
supplies, as well as room for overshoot and noise spikes.
The minimum recommended supply voltage is 1.6V but the
part will operate with a supply below 1.5V. It is important to
note that the input signal range, switching times, and
on-resistance degrade at lower supply voltages. Refer to the
electrical specification tables and Typical Performance
curves for details.
V+ and GND power the internal logic (thus setting the digital
switching point) and level shifters. The level shifters convert
the logic levels to switched V+ and V- signals to drive the
analog switch gate terminals.
High-Frequency Performance
In 50Ω systems, signal response is reasonably flat even past
10MHz with a -3dB bandwidth of 70MHz (see Figure 12).
The frequency response is very consistent over a wide V+
range, and for varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal feed
through from a switch’s input to its output. Off Isolation is the
resistance to this feed through, while Crosstalk indicates the
amount of feed through from one switch to another.
Figure 11 details the high Off Isolation and Crosstalk
rejection provided by this family. At 100kHz, Off Isolation is
about 65dB in 50Ω systems, decreasing approximately 20dB
per decade as frequency increases. Higher load
impedances decrease Off Isolation and Crosstalk rejection
due to the voltage divider action of the switch OFF
impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND.
One of these diodes conducts if any analog signal exceeds
V+ or GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
Logic-Level Thresholds
This device is 1.8V CMOS compatible (0.5V and 1.4V) over
a supply range of 2.7V to 3.6V. At 2.7V the VIL level is about
0.54V. This is still above the 1.8V CMOS guaranteed low
output maximum level of 0.5V but noise margin is reduced.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
7
FN6380.0
September 29, 2006
ISL54058
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
0.8
0.5
V+ = 3V
ICOM = 100mA
ICOM = 100mA
0.7
0.45
0.6
0.4
+85°C
0.35
+25°C
RON (Ω)
RON (Ω)
V+ = 1.65V
V+ = 1.8V
0.5
0.3
V+ = 2.7V
0.4
-40°C
V+ = 3V
0.3
V+ = 3.6V
0
1
2
0.25
3
4
0
0.5
1
1.5
2
2.5
FIGURE 9. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 8. ON RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0
+85°C
CROSSTALK (dB)
0.6
+25°C
0.55
-40°C
0.5
0.45
-10
20
-20
30
-30
40
-40
50
-50
60
ISOLATION
-60
70
-70
80
-80
0.4
90
CROSSTALK
-90
0
0.5
1
1.5
VCOM (V)
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
8
2
-100
1k
OFF ISOLATION (dB)
V+ = 1.8V
ICOM = 100mA
0.65
RON (Ω)
10
V+ = 3V
0.7
0.35
3
VCOM (V)
VCOM (V)
10k
100k
1M
10M
100
110
100M 500M
FREQUENCY (Hz)
FIGURE 11. CROSSTALK AND OFF ISOLATION
FN6380.0
September 29, 2006
ISL54058
NORMALIZED GAIN (dB)
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
Die Characteristics
V+ = 3V
0
SUBSTRATE POTENTIAL (POWERED UP):
GAIN
GND
-10
TRANSISTOR COUNT:
228
0
PHASE
PROCESS:
20
Submicron CMOS
60
80
RL = 50Ω
VIN = 0.2VP-P to 2VP-P
0.1
PHASE (°)
40
100
1
10
100
FREQUENCY (MHz)
FIGURE 12. FREQUENCY RESPONSE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
FN6380.0
September 29, 2006
ISL54058
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D
L16.2.6x1.8A
B
16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
6
INDEX AREA
2X
A
N
SYMBOL
E
0.10 C
1 2
2X
MIN
NOMINAL
MAX
NOTES
A
0.45
0.50
0.55
-
A1
-
-
0.05
-
0.10 C
A3
TOP VIEW
0.10 C
C
A
0.05 C
0.127 REF
-
b
0.15
0.20
0.25
5
D
2.55
2.60
2.65
-
E
1.75
1.80
1.85
-
e
0.40 BSC
-
SEATING PLANE
A1
SIDE VIEW
L
0.35
0.40
0.45
-
L1
0.45
0.50
0.55
-
N
16
2
Nd
4
3
Ne
4
3
e
PIN #1 ID
θ
1 2
0
-
NX L
L1
(DATUM A)
4
Rev. 4 8/06
NX b 5
16X
0.10 M C A B
0.05 M C
(DATUM B)
12
BOTTOM VIEW
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
CL
(A1)
NX (b)
L
5
8. Maximum allowable burrs is 0.076mm in all directions.
e
SECTION "C-C"
7. Maximum package warpage is 0.05mm.
TERMINAL TIP
C C
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
3.00
1.80
1.40
1.40
2.20
0.90
0.40
0.20
0.50
0.20
0.40
10 LAND PATTERN
10
FN6380.0
September 29, 2006
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