DATASHEET

NS
ESI G
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W
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O R N EN T P A
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C EM
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M M E D R E PLA
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2A Data Sheet
RE
DE
NOT OMMEN ISL5422
C
RE
ISL54222
®
May 27, 2009
High-Speed USB 2.0 (480Mbps)
Multiplexer
FN6835.1
Features
• High-Speed (480Mbps) and Full-Speed (12Mbps)
Signaling Capability per USB 2.0
The Intersil ISL54222 is a single supply dual 2:1 multiplexer
that can operate from a single 1.8V to 3.3V supply. It contains
two SPDT (Single Pole/Double Throw) switches configured as
a DPDT. The part was designed for switching or routing of
USB High-Speed signals and/or USB Full-speed signals in
portable battery powered products.
• 1.8V Logic Compatible
• Enable Pin to Open all Switches
• Power OFF Protection
• D-/D+ Pins are Overvoltage Tolerant to 5.5V
The 5.5Ω switches can swing rail-to-rail and were specifically
designed to pass USB full speed data signals that range from
0V to 3.3V and USB high speed data signals that range from
0V to 400mV with a single supply as low as 1.8V. They have
high bandwidth and low capacitance to pass USB high speed
data signals with minimal distortion.
• -3dB Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . 782MHz
• Low ON Capacitance. . . . . . . . . . . . . . . . . . . . . . . . 6.5pF
• Low ON-Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 5.5Ω
• Single Supply Operation (VDD) . . . . . . . . . . . . 1.8V to 3.3V
• Available in µTQFN, TDFN, and MSOP Packages
The part can be used in Personal Media Players and other
portable battery powered devices that need to route USB
high-speed signals and/or full-speed signals to different
transceiver sections of the device while connected to a single
USB host (computer).
• Pb-Free (RoHS Compliant)
• Compliant with USB 2.0 Short Circuit and Overvoltage
Requirements Without Additional External Components
Applications
The digital logic inputs are 1.8V logic compatible when
operated with a 1.8V to 3.3V supply. The ISL54222 has an
output enable pin to open all the switches. It can be used to
facilitate proper bus disconnect and connection when
switching between the USB sources.
• MP3 and other Personal Media Players
• Cellular/Mobile Phones
• PDA’s
The ISL54222 is available in 10 Ld 1.8mmx1.4mm µTQFN,
10 Ld TDFN and 10 Ld MSOP packages. It operates over a
temperature range of -40 to +85°C.
• Digital Cameras and Camcorders
• USB Switching
Application Block Diagram
µCONTROLLER
VDD
ISL54222
SEL
USB CONNECTOR
OE
LOGIC CIRCUITRY
VBUS
HSD1-
D-
D-
HSD1+
D+
D+
HSD2HSD2+
GND
GND
USB
HIGH-SPEED
OR
FULL-SPEED
TRANSCEIVER
#1
USB
HIGH_SPEED
OR
FULL-SPEED
TRANSCEIVER
#2
PORTABLE MEDIA DEVICE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54222
Pinouts
ISL54222
(10 LD MSOP, TDFN)
TOP VIEW
ISL54222
(10 LD 1.8 X 1.4 µTQFN)
TOP VIEW
HSD1-
HSD2-
7
6
9
VDD
LOGIC
CONTROL
OE 8
SEL 10
1
2
HSD1+
HSD2+
5
D-
4
3
LOGIC
CONTROL
SEL
1
GND
HSD1+
2
9
OE
D+
HSD2+
3
8
HSD1-
D+
4
7
HSD2-
GND
5
6
D-
10 VDD
NOTE:
1. Switches Shown for SEL = Logic “1” and OE = Logic “0”.
Truth Table
Pin Descriptions
OE
SEL
HSD1-, HSD1+
HSD2-, HSD2+
PIN NAME
0
0
ON
OFF
VDD
Power Supply
0
1
OFF
ON
GND
Ground Connection
1
X
OFF
OFF
SEL
Select Logic Control Input
OE
Bus Switch Enable
Logic “0” when ≤ 0.5V, Logic “1” when ≥ 1.4V with a 1.8V to 3.3V
Supply.
DESCRIPTION
D+, D-, HSDx+, HSDx- USB Data Port
Ordering Information
PART
NUMBER
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL54222IRUZ-T* (Note
NOTES:)
J
-40 to +85
10 Ld 1.8 x 1.4mm µTQFN (Tape and Reel)
L10.1.8x1.4A
ISL54222IRTZ (Note 3)
4222
-40 to +85
10 Ld 3x3 TDFN
L10.3x3A
ISL54222IRTZ-T* (Note 3)
4222
-40 to +85
10 Ld 3x3 TDFN (Tape and Reel)
L10.3x3A
ISL54222IUZ (Note 3)
54222
-40 to +85
10 Ld MSOP
M10.118
ISL54222IUZ-T* (Note 3)
54222
-40 to +85
10 Ld MSOP (Tape and Reel)
M10.118
ISL54222IRUEVAL1Z
Evaluation Board
*Please refer to TB347 for details on reel specifications.
NOTES:
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
2
FN6835.1
May 27, 2009
ISL54222
Absolute Maximum Ratings
Thermal Information
VDD to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 3.5V
Input Voltages
HSD2x, HSD1x (Note 4). . . . . . . . . . . . . . . . . . . . . - 0.3V to 6.0V
SEL, OE (Note 4) . . . . . . . . . . . . . . . . . . . -0.3V to ((VDD) + 0.3V)
Output Voltages
D+, D- (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Continuous Current (HSD2x, HSD1x) . . . . . . . . . . . . . . . . . . ±40mA
Peak Current (HSD2x, HSD1x)
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±100mA
ESD Rating:
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>2kV
Thermal Resistance (Typical)
θJA (°C/W)
θJC (°C/W)
10 Ld µTQFN Package (Note 5) . . . . .
160
N/A
10 Ld TDFN Package (Notes 6, 7). . . .
55
18
10 Ld MSOP Package (Note 5) . . . . . .
165
N/A
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . 1.8V to 3.3V
Logic Control Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 0V to VDD
Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to VDD
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. Signals on HSD1x, HSD2x, D+, D- exceeding GND by specified amount are clamped. Signals on OE and SEL exceeding VDD or GND by
specified amount are clamped. Limit current to maximum current ratings.
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications - 1.8V to 3.3V Supply Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V,
VOEH = 1.4V, VOEL = 0.5V, (Note 8), Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 9, 10)
TYP
MAX
(Notes 9, 10) UNITS
ANALOG SWITCH CHARACTERISTICS
VDD = VDD, SEL = 0V or VDD, OE = 0V
Analog Signal Range, VANALOG
ON-Resistance, rON (High-Speed) VDD = 1.8V, SEL = 0.5V or 1.4V, OE = 0.5V, IDx = 40mA,
VHSD1x or VHSD2 x = 0V to 400mV (see Figure 3,
Note 13)
rON Matching Between Channels, VDD = 1.8V, SEL = 0.5V or 1.4V, OE = 0.5V, IDx = 40mA,
ΔrON (High-Speed)
VHSD1x or VHSD2 x = Voltage at max rON, (Notes 12, 13)
rON Flatness, RFLAT(ON)
(High-Speed)
VDD = 1.8V, SEL = 0.5V or 1.4V, OE = 0.5V, IDx = 40mA,
VHSD1x or VHSD2 x = 0V to 400mV, (Notes 11, 13)
OFF Leakage Current,
IHSD1x(OFF)
VDD = 3.3V, SEL = VDD and OE = 0V or OE = VDD,
VDx = 0.3V, 3V, VHSD1X = 3V, 0.3V, VHSD2x = 0.3V, 3V
ON Leakage Current, IHSD1x(ON) VDD = 3.3V, SEL = OE = 0V, VDx = 0.3V, 3V,
VHSD1X = 0.3V, 3V, VHSD2x = 3V, 0.3V
OFF Leakage Current,
IHSD2x(OFF)
VDD = 3.3V, SEL = OE = 0V or OE = VDD, VDx = 3V, 0.3V,
VHSD2x = 0.3V, 3V, VHSD1X = 3V, 0.3V
ON Leakage Current, IHSD2x(ON) VDD = 3.3V, SEL = VDD, OE = 0V, VDx = 0.3V, 3V,
VHSD2x = 0.3V, 3V, VHSD1X = 3V, 0.3V
Power OFF Leakage Current, IOFF VDD = 0V, VD+ = 0V to 5.25V, VD-= 0V to 5.25V
Full
0
-
VDD
V
25
-
5.5
8
Ω
Full
-
-
10
Ω
25
-
0.072
0.5
Ω
Full
-
-
0.55
Ω
25
-
0.44
1.2
Ω
Full
-
-
1.3
Ω
25
-15
0.35
15
nA
Full
-20
-
20
nA
25
-20
2.5
20
nA
Full
-25
-
25
nA
25
-15
0.26
15
nA
Full
-20
-
20
nA
25
-20
1.65
20
nA
Full
-25
-
25
nA
25
-
0.005
0.025
µA
Full
-
-
0.5
µA
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
VDD = 3.3V, VIN = 3V, RL = 50Ω, CL = 50pF (see Figure 1)
25
-
50
-
ns
Turn-OFF Time, tOFF
VDD = 3.3V, VIN = 3V, RL = 50Ω, CL = 50pF (see Figure 1)
25
-
33
-
ns
3
FN6835.1
May 27, 2009
ISL54222
Electrical Specifications - 1.8V to 3.3V Supply Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V,
VOEH = 1.4V, VOEL = 0.5V, (Note 8), Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 9, 10)
TYP
MAX
(Notes 9, 10) UNITS
Break-Before-Make Time Delay, tD VDD = 3.3V, VIN = 3V, RL = 50Ω, CL = 50pF (see Figure 2)
25
-
12
-
ns
VDD = 3.3V, VIN = 3V, RL = 15kΩ, CL = 50pF, Time out of
All-Off state
25
-
42
-
ns
Turn-OFF Disable Time, tDISABLE VDD = 3.3V, VIN = 3V, RL = 15kΩ, CL = 50pF, Time into
All-Off state, Time is highly dependent on the load
(RL, CL) time constant.
25
-
75
-
ns
Skew, (tSKEWOUT - tSKEWIN)
VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, RL = 45Ω,
CL = 10pF, tR = tF = 500ps at 480Mbps,
(Duty Cycle = 50%) (see Figure 6)
25
-
53
-
ps
Rise/Fall Degradation
(Propagation Delay), tPD
VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, RL = 45Ω,
CL = 10pF, (see Figure 6)
25
-
250
-
ps
Crosstalk
VDD = 3.3V, RL = 50Ω, f = 240MHz (see Figure 5)
25
-
-25
-
dB
OFF-Isolation
VDD = 3.3V, OE = 3.3V, RL = 50Ω, f = 240MHz
25
-
-27
-
dB
-3dB Bandwidth
Signal = 0dBm, 0.2VDC offset, RL = 50Ω
25
-
782
-
MHz
OFF Capacitance, CHSxOFF
f = 1MHz, VDD = 3.3V, SEL = 0V, OE = 3.3V, VHSD1x or
VHSD2x = VDx = 0V (see Figure 4)
25
-
2.5
-
pF
COM ON Capacitance, CDX(ON)
f = 1MHz, VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V,
VHSD1x or VHSD2x = VDx = 0V (see Figure 4)
25
-
6.5
-
pF
Full
1.8
3.3
V
25
-
32
40
µA
Full
-
-
50
µA
25
-
5.8
7.5
µA
Full
-
-
8
µA
VDD = 1.8V to 3.3V
Full
-
-
0.5
V
Input Voltage High, VSELH, VOEH VDD = 1.8V to 3.3V
Full
1.4
-
VDD
V
Input Current, ISELL, IOEL
VDD = 3.3V, SEL = 0V, OE = 0V
Full
-
104
-
nA
Input Current, ISELH
VDD = 3.3V, SEL = 3.3V
Full
-
-1.5
-
nA
Input Current, IOEH
VDD = 3.3V, OE = 3.3V
Full
-
-1.6
-
nA
Turn-ON Enable Time, tENABLE
POWER SUPPLY CHARACTERISTICS
Power Supply Range, VDD
Positive Supply Current, IDD
VDD = 3.3V, SEL = 0V or VDD, OE = 0V or VDD
Positive Supply Current, IDD
VDD = 1.8V, SEL = 0V, OE = 0V or VDD
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VSELL, VOEL
NOTES:
8. VLOGIC = Input voltage to perform proper function.
9. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
11. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range.
12. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON
value, between HSD2+ and HSD2- or between HSD1+ and HSD1-.
13. Limits established by characterization and are not production tested.
4
FN6835.1
May 27, 2009
ISL54222
Test Circuits and Waveforms
VDD
LOGIC
INPUT
VDD
tr < 20ns
tf < 20ns
50%
0V
VINPUT
tOFF
SWITCH
INPUT VINPUT
SWITCH
INPUT
VOUT
HSDxx
Dx
SEL
VOUT
90%
90%
SWITCH
OUTPUT
C
VIN
CL
RL
OE
GND
0V
tON
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (INPUT) -----------------------R L + r ON
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
VDD
LOGIC
INPUT
C
VDD
HSD2x
VINPUT
0V
VOUT
Dx
HSD1x
RL
CL
SEL
SWITCH
OUTPUT
VOUT
90%
GND
VIN
0V
OE
tD
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. BREAK-BEFORE-MAKE TIME
VDD
C
rON = V1/40mA
HSDx
VHSDX
SEL
V1
40mA
OV OR VDD
Dx
GND
OE
Repeat test for all switches.
FIGURE 3. rON TEST CIRCUIT
5
FN6835.1
May 27, 2009
ISL54222
Test Circuits and Waveforms (Continued)
VDD
VDD
C
C
HSDxx
SIGNAL
GENERATOR
HSD1x
50Ω
Dx
SEL
SEL
IMPEDANCE
ANALYZER
0V OR
VDD
Dx
GND
VIN
OE
HSD2x
Dx
ANALYZER
GND
RL
NC
OE
Repeat test for all switches.
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 5. CROSSTALK TEST CIRCUIT
FIGURE 4. CAPACITANCE TEST CIRCUIT
VDD
C
tri
90%
DIN+
10%
50%
VIN
tskew_i
DIN-
90%
SEL
15.8Ω
DIN+
50%
143Ω
10%
DIN-
tfi
tro
15.8Ω
OUT+
D2
COMD2
45Ω
CL
COMD1
143Ω
OUT-
D1
OE
45Ω
CL
90%
OUT+
OUT-
10%
50%
GND
tskew_o
50%
90%
10%
tf0
|tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals.
|tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals
|tskew_0| Change in Skew through the Switch for Output Signals.
|tskew_i| Change in Skew through the Switch for Input Signals.
FIGURE 6A. MEASUREMENT POINTS
FIGURE 6B. TEST CIRCUIT
FIGURE 6. SKEW TEST
6
FN6835.1
May 27, 2009
ISL54222
Application Block Diagram
µCONTROLLER
VDD
ISL54222
SEL
USB CONNECTOR
OE
LOGIC CIRCUITRY
VBUS
HSD1-
D-
D-
HSD1+
D+
D+
HSD2HSD2+
GND
GND
USB
HIGH-SPEED
OR
FULL-SPEED
TRANSCEIVER
#1
USB
HIGH_SPEED
OR
FULL-SPEED
TRANSCEIVER
#2
PORTABLE MEDIA DEVICE
Detailed Description
The ISL54222 device is a dual single pole/double throw
(SPDT) analog switch configured as a DPDT that operates
from a single DC power supply in the range of 1.8V to 3.3V.
It was designed to function as a dual 2-to-1 multiplexer to
select between two USB high-speed differential data signals
in portable battery powered products. It is offered in a TDFN,
MSOP, and a small µTQFN packages for use in MP3
players, cameras, PDAs, cellphones, and other personal
media players. The device has an enable pin to open all
switches.
The part consists of four 5.5Ω high speed (HSx) switches.
These switches have high bandwidth and low capacitance to
pass USB high-speed (480Mbps) differential data signals
with minimal edge and phase distortion. They can also swing
from 0V to VDD to pass USB full speed (12Mbps) differential
data signals with minimal distortion.
The ISL54222 was designed for MP3 players, cameras,
cellphones, and other personal media player applications
that have multiple high-speed or full-speed transceivers
sections and need to multiplex between these USB sources
to a single USB host (computer). A typical application block
diagram of this functionality is previously shown.
A detailed description of the HS switches is provided in the
following section.
High-Speed (HSx) Switches
The HSx switches (HSD1-, HSD1+, HSD2-, HSD2+) are
bi-directional switches that can pass rail-to-rail signals.
When powered with a 1.8V supply, these switches have a
nominal rON of 5.5Ω over the signal range of 0V to 400mV
with a rON flatness of 0.44Ω. The rON matching between the
HSD1 and HSD2 switches over this signal range is only
0.072Ω, ensuring minimal impact by the switches to USB
7
high speed signal transitions. As the signal level increases,
the rON switch resistance increases. At signal level of 1.8V,
the switch resistance is nominally 12Ω. See Figures 7, 8, 9,
10, 11, 12 in the “Typical Performance Curves” beginning on
page 9.
The HSx switches were specifically designed to pass USB
2.0 high-speed (480Mbps) differential signals in the range of
0V to 400mV. They have low capacitance (6.5pF) and high
bandwidth to pass the USB high-speed signals with
minimum edge and phase distortion to meet USB 2.0 high
speed signal quality specifications. See Figure 13 in the
“Typical Performance Curves” on page 10 for USB
High-speed Eye Pattern taken with switches in the
differential signal paths.
The HSx switches can also pass USB full-speed signals
(12Mbps) with minimal distortion and meet all the USB
requirements for USB 2.0 full-speed signaling. See Figure 14
and 15 in the “Typical Performance Curves” on page 11 for
USB Full-speed Eye Pattern taken with switches in the
differential signal paths.
The maximum normal operating signal range for the HSx
switches is from 0V to VDD. The signal voltage should not be
allow to exceed the VDD voltage rail or go below ground by
more than -0.3V for normal operation.
However, in the event that the USB 5.25V VBUS voltage gets
shorted to one or both of the D-/D+ pins, the ISL54222 has
special fault protection circuitry to prevent damage to the
ISL54222 part. The fault circuitry allows the signal pins (D-,
D+, HSD1-, HSD1+, HSD2-, HSD2+) to be driven up to 5.5V
while the VDD supply voltage is in the range of 0V to 3.3V. In
this condition the part draws < 300µA of IDD current and
causes no stress to the IC. In addition when VDD is at 0V
(ground) all switches are OFF and the fault voltage is
isolated from the other side of the switch. When VDD is in the
FN6835.1
May 27, 2009
ISL54222
range of 1.8V to 3.3V the fault voltage will pass through to
the output of an active switch channel. During the fault
condition normal operation is not guaranteed until the fault is
removed. See the “USB 2.0 VBUS Short Requirements”
section below.
When a computer or USB hub is plugged into the common
USB connector and Channel 1 is active, a link will be
established between the USB 1 transceiver section of the
media player and the computer. The device will be able to
transmit and receive data from the computer.
The HS1 channel switches are active (turned ON) whenever
the SEL voltage is Logic ”0” (Low) and the OE voltage is
Logic ”0”(Low).
HSD2 USB Channel
The HS2 channel switches are active (turned ON) whenever
the SEL voltage is Logic “1” (High) and the OE voltage is
Logic “0” (Low).
ISL54222 Operation
The following will discuss using the ISL54222 shown in the
“Application Block Diagram” on page 7.
POWER
The power supply connected at the VDD pin provides the DC
bias voltage required by the ISL54222 part for proper
operation. The ISL54222 can be operated with a VDD
voltage in the range of 1.8V to 3.3V.
A 0.01µF or 0.1µF decoupling capacitor should be
connected from the VDD pin to ground to filter out any power
supply noise from entering the part. The capacitor should be
located as close to the VDD pin as possible.
LOGIC CONTROL
The state of the ISL54222 device is determined by the
voltage at the SEL pin and the OE pin. SEL is only active
when the OE pin is Logic “0” (Low). Refer to the “Truth Table”
on page 2.
The ISL54222 logic pins are designed to minimize current
consumption when the logic control voltage is lower than the
VDD supply voltage. With VDD = 3.3V and logic pins at 1.4V
the part typically draws only 35µA of IDD current. With
VDD = 1.8V and logic pins at 1.4V the part typically draws
only 6µA of IDD current. Driving the logic pins to the VDD
supply rail minimizes power consumption.
The logic pins must be held High or Low and must not float.
Logic Control Voltage Levels
With VDD supply voltage in the range of 1.8V to 3.3V the
logic levels are:
OE = Logic “0” (Low) when VOE ≤ 0.5V
OE = Logic “1” (High) when VOE ≥ 1.4V
SEL = Logic “0” (Low) when VSEL ≤ 0.5V
SEL = Logic “1” (High) when VSEL ≥ 1.4V
HSD1 USB Channel
If the SEL pin = Logic “0” and the OE pin = Logic “0”,
high-speed Channel 1 will be ON. The HSD1- and HSD1+
switches are ON and the HSD2- and HSD2+ switches are
OFF (high impedance).
8
If the SEL pin = Logic “1” and the OE pin = Logic “0”,
high-speed Channel 2 will be ON. The HSD2- and HSD2+
switches are ON and the HSD1- and HSD1+ switches are
OFF (high impedance).
When a USB cable from a computer or USB hub is
connected at the common USB connector and Channel 2 is
active, a link will be established between the USB 2
transceiver section of the media player and the computer.
The device will be able to transmit and receive data from the
computer.
All Switches OFF Mode
If the SEL pin = Logic “0” or Logic “1” and the OE pin =
Logic “1”, all of the switches will turn OFF (high impedance).
The “All OFF” state can be used to switch between the two
USB sections of the media player. When switching from one
USB transceiver section to the other USB transceiver
section, you can momentarily put the ISL54222 switch in the
“ALL OFF” state, in order to get the computer to disconnect
from the current USB section, so it can properly connect to
the other USB transceiver section when that channel is
turned ON.
USB 2.0 VBUS Short Requirements
The USB 2.0 specification in chapter 7, section 7.1.1 states
a USB device must be able to withstand a VBUS short to the
D+ or D- signal lines when the device is either powered off or
powered on for at least 24 hours. The ISL54222 part has
special fault protection circuitry to meet these short circuit
requirements.
The fault protection circuitry allows the signal pins (D-, D+,
HSD1-, HSD1+, HSD2-, HSD2+) to be driven up to 5.5V
while the VDD supply voltage is in the range of 0V to 3.3V. In
this overvoltage condition the part draws < 300µA of IDD
current and causes no stress/damage to the IC.
In addition when VDD is at 0V (ground), all switches are OFF
and the shorted VBUS voltage is isolated from the other side
of the switch.
When VDD is in the range of 1.8V to 3.3V, the shorted VBUS
voltage will pass through to the output of an active (turned
ON) switch channel but not through a turned OFF channel.
Any components connected on the active channel must be
able to withstand the overvoltage condition.
Note: During the fault condition normal operation of the USB
channel is not guaranteed until the fault condition is
removed.
FN6835.1
May 27, 2009
ISL54222
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
6.0
14
ICOM = 40mA
ICOM = 1mA
5.5
12
1.8V
1.8V
10
rON (Ω)
rON (Ω)
5.0
2.7V
4.5
3.3V
4.0
2.7V
8
3.0V
3.3V
6
3.0V
3.5
4
3.0
0
2
0.1
0.2
VCOM (V)
0.3
0.4
0
0.5
1.0
1.5
2.5
2.0
3.0
3.3
VCOM (V)
FIGURE 8. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
FIGURE 7. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
8
16
V+ = 1.8V
ICOM = 40mA
V+ = 1.8V
ICOM = 1mA
14
7
12
+85°C
6
5
+25°C
4
-40°C
rON (Ω)
rON (Ω)
10
+85°C
8
+25°C
6
-40°C
4
3
2
2
0
0.1
0.2
0.3
0
0.4
0
0.2
0.4
0.6
VCOM (V)
FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE
5.5
9
4.0
rON (Ω)
rON (Ω)
1.6
1.8
7
+85°C
6
+25°C
3.5
+25°C
5
4
-40°C
3
-40°C
3.0
1.4
V+ = 3.3V
ICOM = 1mA
8
+85°C
4.5
1.2
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
V+ = 3.3V
ICOM = 40mA
5.0
0.8
1.0
VCOM (V)
2
2.5
1
0
2.0
0
0.1
0.2
0.3
VCOM (V)
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
9
0.4
0
0.5
1.0
1.5
2.0
2.5
3.0
3.3
VCOM (V)
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
FN6835.1
May 27, 2009
ISL54222
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
VOLTAGE SCALE (0.1V/DIV)
VDD = 1.8V
TIME SCALE (0.2ns/DIV)
FIGURE 13. EYE PATTERN: 480Mbps WITH USB SWITCHES IN THE SIGNAL PATH
10
FN6835.1
May 27, 2009
ISL54222
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
VOLTAGE SCALE (0.5V/DIV)
VDD = 1.8V
TIME SCALE (10ns/DIV)
FIGURE 14. EYE PATTERN: 12Mbps WITH USB SWITCHES IN THE SIGNAL PATH
VOLTAGE SCALE (0.5V/DIV)
VDD = 3.3V
TIME SCALE (10ns/DIV)
FIGURE 15. EYE PATTERN: 12Mbps WITH USB SWITCHES IN THE SIGNAL PATH
11
FN6835.1
May 27, 2009
ISL54222
1
-10
0
-20
-1
-30
-2
-40
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
-3
-4
RL = 50Ω
VIN = 0dBm, 0.2VDC BIAS
RL = 50Ω
VIN = 0dBm, 0.2VDC BIAS
-50
-60
-70
-80
-90
-100
1M
10M
100M
1G
-110
1k
10k
100k
FREQUENCY (Hz)
FIGURE 16. FREQUENCY RESPONSE
100M
500M
Die Characteristics
RL = 50Ω
VIN = 0dBm, 0.2VDC BIAS
SUBSTRATE POTENTIAL (POWERED UP):
GND
-30
NORMALIZED GAIN (dB)
10M
FIGURE 17. OFF-ISOLATION
-10
-20
1M
FREQUENCY (Hz)
TRANSISTOR COUNT:
-40
325
-50
-60
PROCESS:
Submicron CMOS
-70
-80
-90
-100
-110
1k
10k
100k
1M
10M
100M
500M
FREQUENCY (Hz)
FIGURE 18. CROSSTALK
12
FN6835.1
May 27, 2009
ISL54222
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D
6
INDEX AREA
A
L10.1.8x1.4A
B
N
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
MILLIMETERS
E
SYMBOL
2X
MIN
NOMINAL
MAX
NOTES
0.10 C
1
2X
2
0.10 C
TOP VIEW
0.45
0.50
0.55
-
A1
-
-
0.05
-
A3
0.10 C
C
A
0.05 C
A
0.127 REF
0.15
0.20
0.25
5
D
1.75
1.80
1.85
-
E
1.35
1.40
1.45
-
e
SEATING PLANE
A1
SIDE VIEW
(DATUM A)
PIN #1 ID
NX L
1
NX b 5
10X
0.10 M C A B
0.05 M C
2
L1
5
(DATUM B)
7
-
b
0.40 BSC
-
L
0.35
0.40
0.45
L1
0.45
0.50
0.55
-
N
10
2
Nd
2
3
Ne
3
3
θ
0
-
12
4
Rev. 3 6/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
e
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
BOTTOM VIEW
4. All dimensions are in millimeters. Angles are in degrees.
NX (b)
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
CL
(A1)
5
L
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
SECTION "C-C"
e
8. Maximum allowable burrs is 0.076mm in all directions.
TERMINAL TIP
C C
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
2.20
1.00
0.60
1.00
0.50
1.80
0.40
0.20
0.20
0.40
10 LAND PATTERN
13
FN6835.1
May 27, 2009
ISL54222
Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
E
INCHES
SYMBOL
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X θ
0.25
(0.010)
R1
R
GAUGE
PLANE
A
SEATING
PLANE -C-
A2
A1
b
-He
D
0.10 (0.004)
4X θ
L
SEATING
PLANE
C
-A0.20 (0.008)
C
C
a
SIDE VIEW
CL
E1
0.20 (0.008)
C D
-B-
END VIEW
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.007
0.011
0.18
0.27
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
e
L1
MIN
0.020 BSC
0.50 BSC
-
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
L1
0.037 REF
0.95 REF
-
N
10
10
7
R
0.003
-
0.07
-
-
R1
0.003
-
0.07
-
-
θ
5o
15o
5o
15o
-
α
0o
6o
0o
6o
Rev. 0 12/02
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B -
to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
14
FN6835.1
May 27, 2009
ISL54222
Thin Dual Flat No-Lead Plastic Package (TDFN)
L10.3x3A
2X
0.10 C A
A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
MILLIMETERS
2X
0.10 C B
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.70
0.75
0.80
-
A1
-
-
0.05
-
E
A3
6
INDEX
AREA
TOP VIEW
B
//
A
C
SEATING
PLANE
0.08 C
b
0.20
0.25
0.30
5, 8
D
2.95
3.0
3.05
-
D2
2.25
2.30
2.35
7, 8
E
2.95
3.0
3.05
-
E2
1.45
1.50
1.55
7, 8
e
0.50 BSC
-
k
0.25
-
-
-
L
0.25
0.30
0.35
8
A3
SIDE VIEW
D2
(DATUM B)
0.10 C
0.20 REF
7
8
N
10
2
Nd
5
3
Rev. 3 3/06
D2/2
NOTES:
6
INDEX
AREA
1
2
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
NX k
3. Nd refers to the number of terminals on D.
(DATUM A)
4. All dimensions are in millimeters. Angles are in degrees.
E2
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N
N-1
NX b
8
e
(Nd-1)Xe
REF.
BOTTOM VIEW
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
0.10 M C A B
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Compliant to JEDEC MO-229-WEED-3 except for D2
dimensions.
CL
NX (b)
(A1)
L1
5
9 L
e
SECTION "C-C"
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
15
FN6835.1
May 27, 2009
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