DATASHEET

HSP50306
®
Digital QPSK Demodulator
July 2004
Features
Description
• 25.6MHz or 26.97MHz Clock Rates
The HSP50306 is a 6-bit QPSK demodulator chip designed
for use in high signal to noise environments which have some
multipath distortion. The part recovers 2.048 MBPS data from
samples of a QPSK modulated 10.7MHz or 2.1MHz carrier.
The chip coherently demodulates the waveform, recovers
symbol timing, adaptively equalizes the signal to remove
multipath distortion, differentially decodes and multiplexes the
data decisions. 8-A lock signal is provided to indicate when
the tracking loops are locked and the data decisions are valid.
To optimize performance, a gain error feedback signal is
provided which can be filtered and used to close an I.F. AGC
loop around the A/D converter.
• Single Chip QPSK Demodulator with 10kHz Tracking
Loop
• Square Root of Raised Cosine (α = 0.4) Matched
Filtering
• 2.048 MBPS Reconstructed Output Data Stream
• Bit Synchronization with 3kHz Loop Bandwidth
• Internal Equalization for Multipath Distortion
• 6-Bit Real Input: Digitized 10.7MHz or 2.1MHz IF
• Level Detection for External IF AGC Loop
• 0.1s Acquisition Time
• 10-9 BER
• <116mA on +5.0V Supply
Applications
• Cable Data Link Receivers
• Cable Control Channel Receivers
Ordering Information
PART NUMBER
HSP50306SC-27
TEMP.
RANGE (°C)
0 to 70
PACKAGE
16 Ld SOIC
PKG.
DWG. #
The QPSK demodulator derives all timing from CLKIN. The
chip divides this clock by 2 to provide the sample clock for the
external A/D converter. The -27 version operates at a clock
input of 26.97MHz and demodulates a 10.7MHz QPSK signal
to recover the 2048 KSPS data. The -25 version operates at a
clock input of 25.6MHz and demodulates a 2.1MHz QPSK
signal to recover the 2048 KSPS data. Variation from these
CLKIN frequencies will progressively degrade the receive
data rate, the receive IF, acquisition sweep rate, acquisition
sweep range and loop bandwidths as the deviation increases
from normal CLKIN. Details on the maximum allowable deviation are found in the Input Characteristics section. The
HSP50306 processes 6-bit offset binary data. 4-bit data provides adequate performance for many applications.
M16.3
Block Diagram
I
DIN0-5
4 TAP
ADAPTIVE
EQUALIZER
Q
6
I
COS
AGCOUT
LEVEL
DETECT
SIN
NCO
ADCLK
CLKIN
RESET
TEST
Q
BIT PHASE
DETECTOR
TIMING
GENERATOR
BIT SYNC
LOOP FILTER
CARRIER
PHASE
DETECT
DIFF.
DECODE/
MUX
LOCK
DETECT
DATAOUT
LOCK
CLKOUT
CARRIER
LOOP FILTER
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright Harris Corp. 1998, Copyright Intersil Americas Inc. 2004. All Rights Reserved
1
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FN4162.3
HSP50306
Pinout
16 LEAD SOIC
TOP VIEW
AGCOUT 1
16 VCC
CLKOUT 2
15 ADCLK
DATAOUT 3
14 DIN0
LOCK
4
13 DIN1
RESET
5
12 DIN2
TEST 6
11 DIN3
CLKIN 7
10 DIN4
8
9 DIN5
GND
Pin Description
NAME
SOIC PIN
TYPE
DESCRIPTION
VCC
16
-
+5V Power Supply
GND
8
-
Ground
CLKIN
7
I
Clock input. This is the processing clock for the part. All timing is derived from this clock.
DIN (5:0)
9-14
I
I.F. input samples from the A/D converter. These bits interpreted as offset binary format. DIN5 is the
MSB. If fewer than 6 bits are used, the bits from the A/D should be connected to the MSBs of the
input and the unused LSBs grounded.
ADCLK
15
O
This output clock is the clock for the A/D converter.
AGCOUT
1
O
This output indicates whether the magnitude of the input samples are above or below the expected
level. This output is provided as an error detector for an external AGC loop. The output is low when
the input is greater than nominal, and high when the input is lower than nominal.
DATAOUT
3
O
This is the recovered data.
CLKOUT
2
O
This is the recovered clock.
LOCK
4
O
This signal indicates that the carrier tracking loop is locked and data on the DOUT pin should be valid.
RESET
5
I
This input is provided to for initialization and test. Active low.
TEST
6
I
This input is provided for test. Pull high for normal operation.
2
HSP50306
The Block Diagram of the QPSK Demodulator is shown on
page 1. To demodulate the data, the I.F. samples are multiplied by sine and cosine samples from a numerically controlled oscillator. The digital mixer outputs are then low pass
filtered to remove mixer products. The filtered data is then
equalized by a 4 tap equalizer (1 precursor, one reference
tap, and a 2 tap Decision Feedback Equalizer (DFE) to
remove distortion caused by multipath. The output of the
equalizer is differentially decoded and multiplexed into the
output data stream. The carrier tracking loop providing the
L.O. for the digital mixer is a second order digital Costas loop
with a tracking bandwidth of ~10kHz. A sweep circuit
searches the carrier uncertainty using a triangle sweep algorithm during acquisition. A lock detector controls the sweep
and indicates when valid data is available. The recovered
data rate clock is generated by another numerically controlled
oscillator. The timing recovery loop is a first order decision
directed digital phase locked with a loop bandwidth of ~3kHz.
The Level Detect circuitry generates the AGC error signal by
rectifying the I.F. input samples and comparing them against
a threshold. The error signal is low if the signal magnitude is
above the upper threshold, high if the magnitude is below the
lower limit.
Figure 1 shows the circuit of a typical demodulator application.
The typical Bit Error Rate (BER) performance is shown in
Figure 2 for both 4-bit and 6-bit quantized inputs. The
theoretical QPSK BER Performance Curve is provided for
reference. Note that the BER performance shown in Figure 2
includes a multipath distortion element at the input, in addition
to the desired signal. This multipath distortion is
representative of receive signal distortions found in cable data
links.
Table 1 details the BER, Acquisition and Delay Performance
Specifications of the HSP50306 QPSK demodulator chip,
based on an input that complies with the specifications
detailed in Table 2.
Application Example
(25.6MHz)
26.97MHz
HSP50306
OSC
CLKIN
CLKOUT
CA3304/6
I.F. FILTER
DIGITIZED
10.7MHz (2.1MHz)
IF INPUT
A/D
6
DIN0-5
DATAOUT
2.048 MBPS
OUTPUT
DATA/CLK
ADCLK
LOCK
AGCOUT
V+
RESET
TEST
FIGURE 1. APPLICATIONS CIRCUIT EXAMPLE
0.01
0.001
BIT ERROR RATE (BER)
0.0001
0.00001
1E-06
1E-07
1E-08
4-BIT DATA
1E-09
THEORETICAL
1E-10
6-BIT DATA
1E-11
1E-12
11
12
13
14
15
16
17
18
19
20
21
22
23
ES /NO
NOTE: Simulation performed using alpha = 0.4 Root Raised Cosine Transmit Filtering, Multipath -10dBc at 72° at 1.6µs.
FIGURE 2. TYPICAL BIT ERROR RATE PERFORMANCE
3
HSP50306
TABLE 1. PERFORMANCE SPECIFICATIONS
SPECIFICATION
PERFORMANCE
BER
Better than 1.0 x 10-9 with specified input signal characteristics. (See Figure 1.)
Acquisition Time
Acquisition within 0.1s from applying an input signal with the specified characteristics.
Carrier Loop Bandwidth
10kHz
Bit Sync Loop Bandwidth
3kHz
Throughput Delay
Less than 6 output bit times.
TABLE 2. INPUT SIGNAL CHARACTERISTICS (NOTE 1)
PARAMETER
SPECIFICATION
Carrier Frequency
10.7 x 106 ±40kHz.
Bit Rate
2.048 x 106 ±0.01%.
Modulation Format
QPSK w/differential encoding specified as:
00:
0° phase change
01: -90° phase change
10: +90° phase change
11: 180° phase change
(Note 2)
Filtering
Square root of raised cosine matched filtering (α = 0.4).
Input RMS Signal Level
Set input p-p signal to full scale on the A/D converter.
Input Data Format
6 bits, offset binary.
Input Clock Frequency
26.97MHz ±0.015% (Note 3) for -27; 25.6MHz ±0.015% for -25.
SINAD
>25.5dB SNR (thermal (AWGN)), >28dB (adjacent channel interference).
Multipath Distortion
Total energy in multipath distortion -10dBc
>95% of multipath energy within 2µs from main path. If the multipath changes rapidly, the bit error rate
may exceed the above specification until the equalizer has readjusted.
NOTES:
1. All frequencies are relative to the input clock frequency. For example, the bit rate is actually ~0.075936 * fCLK. The frequencies provided
in this document are only valid for a 26.97MHz or 25.6MHz clock.
2. Each pair of input bits is encoded into a phase change relative to the previous symbol. In the HSP50306, the symbol to symbol phase
change is decoded into the transmitted bit pair which is multiplexed into the output data stream.
3. While the device is static CMOS and can be clocked down to close to DC, the specified range indicates the accuracy needed to maintain
the data rate inside the bit sync tracking loop bandwidth assuming 50ppm tx and 100ppm rx crystal accuracies.
4
HSP50306
Two Versions: Different Applications
RECEIVE IF
The -27 and -25 versions of the HSP50306 Digital QPSK
Demodulator are not simply different speed grades of the
same device, but are designs which have proportionally
scaled clocks and bandwidths for different applications.
NOTE: While these parts are pin for pin compatible, in
most applications they cannot be used as functional
equivalent substitutes for each other. Key differences
are:
DC 2.79
DEMOD INPUT IF
10.7 FS 16.27
24.19 FCLK 29.76
FIGURE 3. SAMPLED SPECTRUM FOR THE -27 VERSIONS
(fCLK = 26.97MHz)
• The -27 version of the HSP50306 has an input IF of
10.7MHz with an input clock of 26. 97MHz.
DEMOD INPUT IF
RECEIVE IF
• The -25 version of the HSP50306 has an input IF of
2.1MHz with an input clock of 25. 6MHz.
DC
In both the -27 and -25 designs, the sample rate clock for the
input IF signal is half of the CLK frequency. NOTE: Sample
rate clock is designated by fS = fCLK/2. Aside from input
IF and input clock, all other performance parameters of the
two parts are identical for their respective IF inputs.
2.1
10.7 FS 14.9
23.5 FCLK 27.7
FIGURE 4. SAMPLED SPECTRUM FOR THE -25 VERSIONS
(fCLK = 25.6MHz)
TABLE 3. DIFFERENTIAL ENCODING REQUIRED FOR THE -27
AND -25 DEMODULATORS RECEIVING 10.7MHz IF
10.7MHz Input IF Applications
Both the -27 and -25 parts can be used in 10.7MHz IF Applications. Figures 3 and 4 show the frequency spectrum for the
sampled 10.7MHz IF input signals for both the -27 and -25 versions, respectively. In the 10.7MHz IF Application, the -25 version offers tighter filtering capability than the -27 version
because the lower IF allows use of low pass filtering. Also, the
lower IF of the -25 version has inherently lower internal processing spectral spurs than the -27 version. Note that the
receive IF for the HSP50306SC-27 is the input IF to the demodulator. For the HSP50306SC-25, the receive IF is 10.7MHz, but
the processing is done on the spectral image at 2.1MHz. Examine the spectral inversion between the 10.7MHz Receive IF and
the 2.1MHz demodulator input in Figure 4. The transmit differential encoder must take into account this spectral reversal. The required encoding is shown in Table 3. This part was
designed to be paired with the HSP50307 Burst Modulator, and
can be operated from the same 25.6MHz reference clock.
5
INPUT
BITS
PHASE CHANGE
REQUIRED FOR -27
DEMODULATION
PHASE CHANGE
REQUIRED FOR -25
DEMODULATION
00
0o
0o
01
-90o
90o
10
90o
-90o
11
180o
180o
HSP50306
Absolute Maximum Ratings TA = 25°C
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to VCC +0.5V
Typical Derating Factor . . . . . . . . . . . .4mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical, Note 4)
θJA (°C/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . .4.75V to 5.25V
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to 70°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
4. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
VCC = 5.0V ±5%, TA = 0°C to 70°C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
Power Supply Current
ICCOP
VCC = Max, CLK = 28.6MHz
(Notes 5, 6)
-
114
mA
Standby Power Supply Current
ICCSB
VCC = Max, Outputs Not Loaded
-
500
µA
VCC = Max, Input = 0V or VCC
-10
10
µA
3.7
-
V
-
0.4
V
Input Leakage Current
II
CMOS Output High (ADCLK, AGCOUT)
VOHC
VCC = Min, IOH = -400µA
CMOS Output Low (ADCLK, AGCOUT)
VOLC
VCC = Min, IOL = 2mA
Logical One Input Voltage
VIH
VCC = Max
2.0
-
V
Logical Zero Input Voltage
VIL
VCC = Min
-
0.8
V
Logical One Output Voltage
VOH
IOH = -400µA, VCC = Min
2.4
-
V
Logical Zero Output Voltage
VOL
IOL = 2mA, VCC = Min
-
0.4
V
Input Capacitance
CIN
CLK = 1MHz
All measurements referenced to GND.
TA = 25°C, (Note 7)
-
10
pF
-
10
pF
Output Capacitance
COUT
NOTES:
5. Power supply current is proportional to frequency. Typical rating is 4mA/MHz.
6. Output load per test circuit and CL = 40pF.
7. Not tested, but characterized at initial design and at major process/design changes.
6
HSP50306
AC Electrical Specifications
27MHz Clock Rate, VCC = 5.0V ±5%, TA = 0°C to 70°C (Note 8)
PARAMETER
SYMBOL
NOTES
MIN
MAX
UNITS
CLK Period
tCP
36
-
ns
CLK High
tCH
12
-
ns
CLK Low
tCL
12
-
ns
Setup RESET to CLK
tRS
15
-
ns
Hold Time RESET to CLK
tRH
1
-
ns
Setup Time DIN0-5 to ADCLK
tDS
9
15
-
ns
Hold Time DIN0-5 to ADCLK
tDH
9
2
-
ns
CLK to DATAOUT, LOCK, AGCOUT
tPD
-
25
ns
Output Rise, Fall Time
tRF
10
-
8
ns
Output Rise, Fall Time (CMOS Outputs)
tTC
10
-
12
ns
NOTES:
8. AC Testing is performed as follows: Input levels 0.0V to 3.0V. Timing reference levels = 1.5V. Output load circuit with CL = 40pF. Output
transition measured at VOH_1.5V and VOL_1.5V.
9. The set up and hold times for DIN (5:0) are with respect to the rising edge of ADCLKOUT. These parameters are guaranteed by design
and characterization but not tested. An A/D converter with a clock to data out specification of 55ns and a data hold from clock specification
of 2ns will meet these requirements at an oscillator clock frequency of 26.97MHz. Intersil recommends the CA3304 or CA3306 A/D converters for use with the HSP50306.
10. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design
changes.
AC Test Load Circuit
S1
DUT
CL
(NOTE)
IOH
±
2.5V
EQUIVALENT CIRCUIT
SWITCH S1 OPEN FOR ICCSB AND ICCOP
NOTE: Test head capacitance
7
IOL
HSP50306
Waveforms
tCP
tCH
tCL
CLKIN
tPD
ADCLK
tRS
tRH
RESET
tDS
tDH
DIN0-5
tPD
CLKOUT
DATAOUT,
LOCK,
AGCOUT
FIGURE 5.
DATAOUT,
LOCK,
CLKOUT
tRF
tRF
tTC
AGCOUT,
ADCLK
2.0V
0.8V
FIGURE 6. OUTPUT RISE AND FALL TIMES
tTC
3.2V
0.8V
FIGURE 7. OUTPUT RISE AND FALL TIMES
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accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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