DATASHEET

®
NS
E SI G
D
NE W
CT
FO R P R O D U
D
E
EN D
U TE
O M M U B STI T 6 A
C
E
S
R
LE
4511
NOT Data
SIBSheet
H SP
PO S
HSP45116
July 2004
FN2485.8
Numerically Controlled
Oscillator/Modulator
Features
The Intersil HSP45116 combines a high performance
quadrature Numerically Controlled Oscillator (NCO) and a
high speed 16-bit Complex Multiplier/Accumulator (CMAC)
on a single IC. This combination of functions allows a
complex vector to be multiplied by the internally generated
(cos, sin) vector for quadrature modulation and
demodulation. As shown in the Block Diagram, the
HSP45116 is divided into three main sections. The
Phase/Frequency Control Section (PFCS) and the
Sine/Cosine Section together form a complex NCO. The
CMAC multiplies the output of the Sine/ Cosine Section with
an external complex vector.
• 15MHz, 25.6MHz, 33MHz Versions
• NCO and CMAC on One Chip
The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The phase resolution of the PFCS is 32 bits, which results in
frequency resolution better than 0.008Hz at 33MHz. The
output of the PFCS is the argument of the sine and cosine.
The spurious free dynamic range of the complex sinusoid is
greater than 90dBc.
The output vector from the Sine/Cosine Section is one of the
inputs to the Complex Multiplier/Accumulator. The CMAC
multiplies this (cos, sin) vector by an external complex vector
and can accumulate the result. The resulting complex vectors
are available through two 20-bit output ports which maintain
the 90dB spectral purity. This result can be accumulated
internally to implement an accumulate and dump filter.
• 32-Bit Frequency Control
• 16-Bit Phase Modulation
• 16-Bit CMAC
• 0.008Hz Tuning Resolution at 33MHz
• Spurious Frequency Components < -90dBc
• Fully Static CMOS
Applications
• Frequency Synthesis
• Modulation - AM, FM, PSK, FSK, QAM
• Demodulation, PLL
• Phase Shifter
• Polar to Cartesian Conversions
Ordering Information
PART NUMBER
TEMP.
RANGE (°C)
HSP45116VC-25
0 to 70
PACKAGE
PKG.
DWG. #
160 Ld MQFP Q160.28x28
A quadrature down converter can be implemented by
loading a center frequency into the Phase/Frequency
Control Section. The signal to be down converted is the
Vector Input of the CMAC, which multiplies the data by the
rotating vector from the Sine/Cosine Section. The resulting
complex output is the down converted signal.
Block Diagram
VECTOR INPUT
R
I
MICROPROCESSOR
INTERFACE
INDIVIDUAL
CONTROL SIGNALS
PHASE/
FREQUENCY
CONTROL
SECTION
SINE/
COSINE
ARGUMENT
SIN
SINE/
COSINE
SECTION
COS
CMAC
R
I
VECTOR OUTPUT
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 1999, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
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60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
IMIN0
RIN18
RIN17
RIN16
RIN15
RIN14
GND
RIN13
RIN12
RIN11
RIN10
RIN9
RIN8
RIN7
RIN6
RIN5
RIN4
RIN3
RIN2
GND
RIN1
VCC
RIN0
SH1
SH0
ACC
ENPHREG
ENOFREG
PEAK
RBYTILD
BINFMT
GND
TICO
VCC
MOD1
MOD0
PACI
LOAD
PMSEL
NC
CLROFR
ENCFREG
ENPHAC
ENTIREG
ENI
MODPI/2PI
CS
GND
CLK
VCC
AD1
AD0
WR
C15
C14
C13
C12
C11
C10
C9
C8
GND
C7
C6
C5
C4
C3
C2
C1
C0
OUTMUX1
OUTMUX0
GND
OER
VCC
OEREXT
OEIEXT
OEI
PACO
NC
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
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141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
NC
VCC
IMIN1
GND
IMIN2
IMIN3
IMIN4
IMIN5
IMIN6
IMIN7
IMIN8
IMIN9
IMIN10
IMIN11
IMIN12
VCC
IMIN13
GND
IMIN14
IMIN15
IMIN16
IMIN17
IMIN18
IO19
IO18
IO17
IO16
IO15
VCC
GND
IO14
IO13
IO12
IO11
IO10
GND
VCC
IO9
IO8
IO7
HSP45116
Pinout
160 LEAD MQFP
TOP VIEW
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83
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81
2
NC
GND
IO6
IO5
IO4
IO3
GND
IO2
IO1
VCC
IO0
RO19
GND
RO18
RO17
RO16
RO15
RO14
VCC
RO13
RO12
RO11
GND
RO10
RO9
VCC
RO8
RO7
GND
RO6
RO5
RO4
RO3
VCC
RO2
RO1
RO0
GND
DET1
DET0
HSP45116
Pin Description
NAME
NUMBER
TYPE
DESCRIPTION
VCC
A1, A9, A15, G1,
J15, Q1, Q7, Q15
-
+5V Power supply input.
GND
A8, A14, B1, H1,
H15, P15, Q2, Q8
-
Power supply ground input.
C0-15
N8-11, P8-13,
Q9-14
I
Control input bus for loading phase and frequency data into the PFCS. C15 is the MSB.
AD0-1
N7, P7
I
Address pins for selecting destination of C0-15 data.
CS
P6
I
Chip Select (active low).
WR
Q6
I
Write Enable. Data is clocked into the register selected by AD0-1 on the rising edge of WR when
the CS line is low.
CLK
Q5
I
Clock. All registers, except the control registers clocked with WR, are clocked (when enabled)
by the rising edge of CLK.
ENPHREG
M1
I
Phase Register Enable (active low). Registered on chip by CLK. When active, after being
clocked onto chip, ENPHREG enables the clocking of data into the phase register.
ENOFREG
N1
I
Frequency Offset Register Enable (active Low). Registered on chip by CLK. When active, after
being clocked onto chip, ENOFREG enables clocking of data into the frequency offset register.
ENCFREG
N5
I
Center Frequency Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENCFREG enables clocking of data into the center frequency register.
ENPHAC
Q3
I
Phase Accumulator Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENPHAC enables clocking of the phase accumulator register.
ENTIREG
P5
I
Time Interval Control Register Enable (active low). Registered on chip by CLK. When active,
after being clocked onto chip, ENTIREG enables clocking of data into the time accumulator
register.
ENI
Q4
I
Real and Imaginary Data Input Register (RIR, IIR) Enable (active low). Registered on chip by
CLK. When active, after being clocked onto chip, ENI enables clocking of data into the real and
imaginary input data register.
MODPI/2PI
N6
I
Modulo π/2π Select. When low, the Sine and Cosine ROMs are addressed modulo 2π (360
degrees). When high, the most significant address bit is held low so that the ROMs are
addressed modulo π (180 degrees). This input is registered on chip by clock.
CLROFR
P4
I
Frequency Offset Register Output Zero (active low). Registered on chip by CLK. When active,
after being clocked onto chip, CLROFR zeros the data path from the frequency offset register to
the frequency adder. New data can still be clocked into the frequency offset register; CLROFR
does not affect the contents of the register.
LOAD
N4
I
Phase Accumulator Load Control (active low). Registered on chip by CLK. Zeroes feedback
path in the phase accumulator without clearing the phase accumulator register.
MOD0-1
M3, N3
I
External Modulation Control Bits. When selected with the PMSEL line, these bits add a 0, 90,
180, or 270 degree offset to the current phase in the phase accumulator. The lower 14 bits of
the phase control path are set to zero.
These bits are loaded into the phase register when ENPHREG is low.
PMSEL
P3
I
Phase Modulation Select Line. This line determines the source of the data clocked into the phase
register. When high, the phase control register is selected. When low, the external modulation pins
(MOD0-1) are selected for the most significant two bits and the least significant two bits and the
least significant 14 bits are set to zero. This control is registered by CLK.
RBYTILD
L3
I
ROM Bypass, Timer Load. Active low, registered by CLK. This input bypasses the sine/ cosine
ROM so that the 16-bit phase adder output and lower 16 bits of the phase accumulator go
directly to the CMAC’s sine and cosine inputs, respectively. It also enables loading of the timer
accumulator register by zeroing the feedback in the accumulator.
PACI
P2
I
Phase Accumulator Carry Input (active low). A low on this pin causes the phase accumulator to
increment by one, in addition to the values in the phase accumulator register and frequency
adder.
3
HSP45116
Pin Description
(Continued)
NAME
NUMBER
TYPE
DESCRIPTION
PACO
L13
O
Phase Accumulator Carry Output. Active low and registered by CLK. A low on this output
indicates that the phase accumulator has overflowed, i.e., the end of one sine/cosine cycle has
been reached.
TICO
P1
O
Time Interval Accumulator Carry Output. Active low, registered by CLK. This output goes low
when a carry is generated by the time interval accumulator. This function is provided to time out
control events such as synchronizing register clocking to data timing.
RIN0-18
C1, C2, D1, D2, E13, F1-3, G2, G3,
H2, H3, J1-3, K1,
K2
I
Real Input Data Bus. This is the external real component into the complex multiplier. The bus is
clocked into the real input data register by CLK when ENI is asserted; two’s complement.
IMIN0-18
A2-7, B2-7, C3-8,
D3
I
Imaginary Input Data Bus. This is the external imaginary component into the complex multiplier.
The bus is clocked into the real input data register by CLK when ENI is asserted; two’s
complement.
SH0-1
K3, L1
I
Shift Control Inputs. These lines control the input shifters of the RIN and IIN inputs of the
complex multiplier. The shift controls are common to the shifters on both of the busses.
ACC
L2
I
Accumulate/Dump Control. This input controls the complex accumulators and their holding
registers. When high, the accumulators accumulate and the holding registers are disabled.
When low, the feedback in the accumulators is zeroed to cause the accumulators to load.
The holding registers are enabled to clock in the results of the accumulation. This input is
registered by CLK.
BINFMT
N2
I
This input is used to convert the two’s complement output to offset binary (unsigned) for
applications using D/A converters. When low, bits RO19 and IO19 are inverted from the internal
two’s complement representation. This input is registered by CLK.
PEAK
M2
I
This input enables the peak detect feature of the block floating point detector. When high, the
maximum bit growth in the output holding registers is encoded and output on the DET0-1 pins.
When the PEAK input is asserted, the block floating point detector output will track the maximum
growth in the holding registers, including the data in the holding registers at the time that PEAK
is activated.
OUTMUX0-1
N12, N13
I
These inputs select the data to be output on RO0-19 and IO0-19.
RO0-19
C15, D14, D15,
E14, E15, F13-15,
G13-15, H13, H14,
J13, J14, K13-15,
L15, M15
O
Real Output Data Bus. These Three-state outputs are controlled by OER and OEREXT.
OUTMUX0-1 select the data output on the bus.
IO0-19
A10-13, B8-15, C914, D13, E13
O
Imaginary Output Data Bus. These Three-state outputs are controlled by OEI and OEIEXT.
OUTMUX0-1 select the data output on the bus.
DET0-1
N15, L14
O
These output pins indicate the number of bits of growth in the accumulators. While PEAK is low,
these pins indicate the peak growth. The detector examines bits 15-18, real and imaginary
accumulator holding registers and bits 30-33 of the real and imaginary CMAC holding registers.
The bits indicate the largest growth of the four registers.
OER
P14
I
Three-state control for bits RO0-15. Outputs are enabled when the line is low.
OEREXT
M13
I
Three-state control for bits RO16-19. Outputs are enabled when the line is low.
OEI
M14
I
Three-state control for bits IO0-15. Outputs are enabled when the line is low.
OEIEXT
N14
I
Three-state control for bits IO16-19. Outputs are enabled when the line is low.
4
Functional Block Diagram
IMIN(18:0)
RIN(18:0)
R
E
>G
R.PMSEL
R.ENPHREG
R.ENCFREG
R.ENOFREG
R.CLROFR
R.LOAD
R.ENPHAC
R.MODPI/2PI
R.RBYTILD
R.ENTIREG
CLK
R.SH(1:0)
R.ENI
R.ACC
R.PEAK
R.BINFMT
2
14
16
16
R
E
>G
R
E
>G
32
32
R.CLROFR
A
D
D
E
R
32
A
D
D
E
R
CLK
R
E
>G
R
E
>G
16
15
32
CLK
R
E
>G
CLK
IMIN(18:0)
RIN(18:0)
PHASE
SIN 16
COS 16
R
E
>G
TICO PACO
R.RBYTILD
R.SH(1:0)
R.ENI
R.ACC
R.PEAK
R.BINFMT
PHASE
ADDER
A
D
D
E
R
16
PHASE
ACCUMULATOR
32
16
SINE/COSINE
GENERATOR 16
SIN/COS
ARGUMENT
20
PACO
0
16 MSBs
16 LSBs
0
32
TICO
R.MODPI/2PI
R
E
>G
R
E
>G
TIME ACCUMULATOR
CLK
CLK
32
CARRY OUT
32
PHASE
ACCUMULATOR
REGISTER MSB
CLK
R.ENPHAC
32
PACI
PHASE
ACCUMULATOR
ADDER
32
32
R.LOAD
FREQUENCY
ADDER
PHASE
REGISTER
HSP45116
R.ENPHREG
CLK
32
CLK
32
R.ENOFREG
0
0
32
32
R
E
G
CLK >
OFFSET
FREQUENCY
R.ENCFREG REGISTER
CENTER FREQUENCY
REGISTER
R.PMSEL
ENCODE
PHASE
INPUT
0
REGISTER
PHEN
16
MS INPUT
REGISTER
R
E
>G
R
E
LSEN
>G
LS INPUT
REGISTER
16
MSEN
R
E
G
DECODER
16
MOD(1:0)
C(15:0)
AD(1:0)
CS
WR
>
R
E
G
32
TIME
ACCUMULATOR
REGISTER
R
E
>G
32
1
MUX
0
PMSEL
ENPHREG
ENCFREG
ENOFREG
CLROFR
LOAD
ENPHAC
MODPI/2PI
RBYTILD
ENTIREG
CLK
PACI
CLK
>
0
MUX
1
TIME
32
INCREMENT
CLK
R.ENTIREG
1
MUX
0
SH(1:0)
ENI
ACC
PEAK
BINFMT
OEI
OEIEXT
OER
OEREXT
OUTMUX(1:0)
5
ADDER
1
MUX
0
0
MUX
1
(Continued)
Functional Block Diagram
IMIN(18:0)
RIN(18:0)
PHASE
SIN
R.RBYTILD
COS
0
MUX
1
<
<
CLK
SIN
R
E
>G
19
CLK
R
E
>G
19
0
0
MUX
1
R.SH(1:0)
HSP45116
R.ENI
IMIN0-18
SHIFTER
> REG
SHIFTER
CLK
> REG
COMPLEX
MULTIPLIER
33
CLK
1
MUX
0
> REG
DET(1:0)
CLK
> REG
ADDER
20
0
0
MUX
> REG
REG
<
CLK
CLK
20
16
16
<
3
REG
ADDER
CLK
1
MUX
4
R.ENI
IO(19-16) IO(15:0)
R.BINFMT FMT
OUTMUX(1:0)
See Table 4
> REG
> REG
R1.ACC
CLK
0
ROUND
0
CLK
MUX
GROWTH
DETECT
1
0
CMAC
ACCUMULATOR
CLK
OUTMUX(1:0)
R.PEAK
CLK
ADDER
<
> REG
16
35
REG
CLK
33
16
> REG
> REG
ADDER
CLK
> REG
3
MUX
35
FMT
16
RO(19-16) RO(15:0)
4
COMPLEX
ACCUMULATOR
16
RIN0-18
CLK
R
E
>G
16
CLK
1
<
>G
R
E
MUX
CLK
CLK
COS
16
0
REG
CLK
OEI
OEIEXT
OER
OUTMUX(1:0)
See Table 4
CLK
CLK
0
ROUND
REG
REG
R.ENI
R.SH(1:0)
R.PEAK
R.BINFMT
OEREXT
OUTMUX(1:0)
6
R.SH(1:0)
R2.ACC
R1.ACC
R.ACC
HSP45116
Functional Description
The Numerically Controlled Oscillator/Modulator (NCOM)
produces a digital complex sinusoid waveform whose
amplitude, phase and frequency are controlled by a set of
input command words. When used as a Numerically
Controlled Oscillator (NCO), it generates 16-bit sine and
cosine vectors at a maximum sample rate of 33MHz. The
NCOM can be preprogrammed to produce a constant (CW)
sine and cosine output for Direct Digital Synthesis (DDS)
applications. Alternatively, the phase and frequency inputs
can be updated in real time to produce a FM, PSK, FSK, or
MSK modulated waveform. The Complex Multiplier/
Accumulator (CMAC) can be used to multiply this waveform
by an input signal for AM and QAM signals. By stepping the
phase input, the output of the ROM becomes an FFT twiddle
factor; when data is input to the Vector Inputs (see Block
Diagram), the NCOM calculates an FFT butterfly.
As shown in the Block Diagram, the NCOM consists of three
parts: Phase and Frequency Control Section (PFCS),
Sine/Cosine Generator, and CMAC. The PFCS stores the
phase and frequency inputs and uses them to calculate the
phase angle of a rotating complex vector. The Sine/Cosine
Generator performs a lookup on this phase and outputs the
appropriate values for the sine and cosine. The sine and
cosine form one set of inputs to the CMAC, which multiplies
them by the input vector to form the modulated output.
Phase and Frequency Control Section
The phase and frequency of the internally generated sine
and cosine are controlled by the PFCS (Block Diagram). The
PFCS generates a 32-bit word that represents the current
phase of the sine and cosine waves being generated; the
Sine/ Cosine Argument. Stepping this phase angle from 0
through full scale (232 - 1) corresponds to the phase angle of
a sinusoid starting at 0o and advancing around the unit circle
counterclockwise. The PFCS automatically increments the
phase by a preprogrammed amount on every rising edge of
the external clock. The value of the phase step (which is the
sum of the Center and Offset Frequency Registers) is:
32
Signal Frequency
Phase Step = ---------------------------------------------- × 2
Clock Frequency
The PFCS is divided into two sections: the Phase
Accumulator uses the data on C0-15 to compute the phase
angle that is the input to the Sine/Cosine Section
(Sine/Cosine Argument); the Time Accumulator supplies a
pulse to mark the passage of a preprogrammed period of
time.
The Phase Accumulator and Time Accumulator work on the
same principle: a 32-bit word is added to the contents of a
32-bit accumulator register every clock cycle; when the sum
causes the adder to overflow, the accumulation continues
with the 32 bits of the adder going into the accumulator
7
register. The overflow bit is used as an output to indicate the
timing of the accumulation overflows. In the Time
Accumulator, the overflow bit generates TICO, the Time
Accumulator carry out (which is the only output of the Time
Accumulator). In the Phase Accumulator, the overflow is
inverted to generate the Phase Accumulator Carry Out,
PACO.
The output of the Phase Accumulator goes to the Phase
Adder, which adds an offset to the top 16 bits of the phase.
This 32-bit number forms the argument of the sine and
cosine, which is passed to the Sine/Cosine Generator.
Both accumulators are loaded 16 bits at a time over the
C0-15 bus. Data on C0-15 is loaded into one of the three
input registers when CS and WR are low. The data in the
Most Significant Input Register and Least Significant Input
Register forms a 32-bit word that is the input to the Center
Frequency Register, Offset Frequency Register and Time
Accumulator. These registers are loaded by enabling the
proper register enable signal; for example, to load the
Center Frequency Register, the data is loaded into the LS
and MS Input Registers, and ENCFREG is set to zero; the
next rising edge of CLK will pass the registered version of
ENCFREG, R.ENCFREG, to the clock enable of the Center
Frequency Register; this register then gets loaded on the
following rising edge of CLK. The contents of the Input
Registers will be continuously loaded into the Center
Frequency Register as long as R.ENCFREG is low.
The Phase Register is loaded in a similar manner. Assuming
PMSEL is high, the contents of the Phase Input Register is
loaded into the Phase Register on every rising clock edge
that R.ENPHREG is low. If PMSEL is low, MOD0-1 supply
the two most significant bits into the Phase Register (MOD1
is the MSB) and the least significant 14 bits are loaded with
0. MOD0-1 are used to generate a Quad Phase Shift Keying
(QPSK) signal (Table 2).
TABLE 1. AD0-1 DECODING
AD1
AD0
CS
WR
FUNCTION
0
0
0
↑
Load least significant bits
of frequency input.
0
1
0
↑
Load most significant bits
of frequency input.
1
0
0
↑
Load phase register.
1
1
X
X
Reserved.
X
X
1
X
No Operation.
The Phase Accumulator consists of registers and adders
that compute the value of the current phase at every clock. It
has three inputs: Center Frequency, which corresponds to
the carrier frequency of a signal; Offset Frequency, which is
the deviation from the Center Frequency; and Phase, which
HSP45116
The sum of the values in Center and Offset Frequency
Registers corresponds to the desired phase increment
(modulo 232) from one clock to the next. For example,
loading both registers with zero will cause the Phase
Accumulator to add zero to its current output; the output of
the PFCS will remain at its current value; i.e., the output of
the NCOM will be a DC signal. If a hexadecimal 00000001 is
loaded into the Center Frequency Control Register, the
output of the PFCS will increment by one after every clock.
This will step through every location in the Sine/Cosine
Generator, so that the output will be the lowest frequency
above DC that can be generated by the NCOM, i.e., the
clock frequency divided by 232. If the input to the Center
Frequency Control Register is hex 80000000, the PFCS will
step through the Generator with half of the maximum step
size, so that frequency of the output waveform will be half of
the sample rate.
The operation of the Offset Frequency Control Register is
identical to that of the Center Frequency Control Register;
having two separate registers allows the user to generate an
FM signal by loading the carrier frequency in the Center
Frequency Control Register and updating the Offset
Frequency Control Register with the value of the frequency
offset - the difference between the carrier frequency and the
frequency of the output signal. A logic low on CLROFR
disables the output of the Offset Frequency Register without
clearing the contents of the register.
TABLE 2. MOD0-1 DECODE
MOD1
MOD0
PHASE SHIFT (DEGREES)
0
0
0
0
1
90
1
0
270
1
1
180
Initializing the Phase Accumulator Register is done by putting
a low on the LOAD line. This zeroes the feedback path to the
accumulator, so that the register is loaded with the current
value of the phase increment summer on the next clock.
The final phase value going to the Generator can be
adjusted using MODPI/2PI to force the range of the phase to
be 0o to 180o (modulo π) or 0o to 360o (modulo 2π). Modulo
2π is the mode used for modulation, demodulation, direct
digital synthesis, etc. Modulo π is used to calculate FFTs.
This is explained in greater detail in the Applications Section.
The Phase Register adds an offset to the output of the
Phase Accumulator. Since the Phase Register is only 16
bits, it is added to the top 16 bits of the Phase Accumulator.
8
The Time Accumulator consists of a register which is
incremented on every clock. The amount by which it
increments is loaded into the Input Registers and is latched
into the Time Accumulator Register on rising edges of CLK
while ENTIREG is low. The output of the Time Accumulator
is the accumulator carry out, TICO. TICO can be used as a
timer to enable the periodic sampling of the output of the
NCOM. The number programmed into this register equals
232 x CLK period/desired time interval. TICO is disabled and
its phase is initialized by zeroing the feedback path of the
accumulator with RBYTILD.
Sine/Cosine Section
The Sine/Cosine Section (Figure 1) converts the output of
the PFCS into the appropriate values for the sine and
cosine. It takes the most significant 20 bits of the PFCS
output and passes them through a look up table to form the
16-bit sine and cosine inputs to the CMAC.
32
16
SIN/COS
ARGUMENT
is a 16-bit number that is added to the current phase for PSK
modulation schemes. These three values are used by the
Phase Accumulator and Phase Adder to form the phase of
the internally generated sine and cosine.
MUX
32
20
16
SINE/COSINE
GENERATOR 16
REG 16
16
SIN
COS
16
CLK
CLK
R.RBYTILD
FIGURE 1. SINE/COSINE SECTION
The 20-bit word maps into 2π radians so that the angular
resolution is 2π/220. An address of zero corresponds to
0 radians and an address of hex FFFFF corresponds to
2π- (2π/220) radians. The outputs of the Generator Section
are 2’s complement sine and cosine values. The sine and
cosine outputs range from hexadecimal 8001, which
represents negative full scale, to 7FFF, which represents
positive full scale. Note that the normal range for two’s
complement numbers is 8000 to 7FFF; the output range of
the SIN/COS generator is scaled by one so that it is
symmetric about 0.
The sine and cosine values are computed to reduce the
amount of ROM needed. The magnitude of the error in the
computed value of the complex vector is less than -90.2dB.
The error in the sine or cosine alone is approximately 2dB
better.
If RBYTILD is low, the output of the PFCS goes directly to
the inputs of the CMAC. If the real and imaginary inputs of
the CMAC are programmed to hex 7FFF and 0 respectively,
then the output of the PFCS will appear on output bits 0
through 15 of the NCOM with the output multiplexers set to
bring out the most significant bits of the CMAC output
(OUTMUX = 00). The most significant 16 bits out of the
HSP45116
PFCS appears on IOUT0-15 and the least significant bits
come out on ROUT0-15.
Complex Multiplier/Accumulator
The CMAC (Figure 2) performs two types of functions:
complex multiplication/accumulation for modulation and
demodulation of digital signals, and the operations
necessary to implement an FFT butterfly. Modulation and
demodulation are implemented using the complex multiplier
and its associated accumulator; the rest of the circuitry
in this section, i.e., the complex accumulator, input shifters
and growth detect logic are used along with the complex
multiplier/accumulator for FFTs. The complex multiplier
performs the complex vector multiplication on the output of
the Sine/Cosine Section and the vector represented by the
real and imaginary inputs RIN and IIN. The two vectors are
combined in the following manner:
ROUT = COS x RIN - SIN x IIN
IOUT = COS x IIN + SIN x RIN
RIN and IIN are latched into the input registers and passed
through the shift stages. Clocking of the input registers is
enabled with a low on ENI. The amount of shift on the
latched data is programmed with SH0-1 (Table 3). The
output of the shifters is sent to the CMAC and the auxiliary
accumulators.
The 33-bit real and imaginary outputs of the Complex
Multiplier are latched in the Multiplier Registers and then go
through the Accumulator Section of the CMAC. If the ACC
line is high, the feedback to the accumulators is enabled; a
low on ACC zeroes the feedback path, so that the next set of
real and imaginary data out of the complex multiplier is
stored in the CMAC Output Registers.
The data in the CMAC Output Registers goes to the
Multiplexer, the output of which is determined by the
OUTMUX0-1 lines (Table 4). BINFMT controls whether the
output of the Multiplexer is presented in two’s complement or
unsigned format; BINFMT = 0 inverts ROUT19 and IOUT19
for unsigned output, while BINFMT = 1 selects two’s
complement.
TABLE 4. OUTPUT MULTIPLEXER SELECTION
OUT OUT
MUX MUX
0
1
RO16-19
RO0-15
IO16-19
IO0-15
0
0
Real CMAC Real CMAC Imag CMAC Imag CMAC
31-34
15-30
31-34
15-30
0
1
Real CMAC 0, Real
Imag CMAC 0, Imag
31-34
CMAC 0-14 31-34
CMAC 0-14
1
0
Real ACC
16-19
Real ACC
0-15
Imag ACC
16-19
Imag ACC
0-15
1
1
Reserved
Reserved
Reserved
Reserved
TABLE 3. INPUT SHIFT SELECTION
SH1
SH0
SELECTED BITS
0
0
RIN0-15, IMIN0-15
0
1
RIN1-16, IMIN1-16
1
0
RIN2-17, IMIN2-17
1
1
RIN3-18, IMIN3-18
9
The Complex Accumulator duplicates the accumulator in the
CMAC. The input comes from the data shifters, and its 20-bit
complex output goes to the Multiplexer. ACC controls
whether the accumulator is enabled or not. OUTMUX0-1
determines whether the accumulator output appears on
ROUT and IOUT.
HSP45116
RIN0-18
19
IMIN0-18
19
R.ENI
REG
REG
SHIFTER
SHIFTER
R.SH0-1
16
REG
COS
16
REG
ADDER
MUX
0
REG
ADDER
REG
MUX
0
REG
REG
REG
COMPLEX
ACCUMULATOR
REG
ADDER
ADDER
MUX
0
33
REG
R2.ACC
MUX
COMPLEX
MULTIPLIER
33
0
REG
R1.ACC
REG
16
REG
REG
SIN
16
CMAC
ACCUMULATOR
REG
REG
REG
R1.ACC
35
35
20
20
0
R.PEAK
MUX
OUTMUX0-1
R.BINFMT
GROWTH
DETECT
3
FMT
16
OEREXT
16
ACC
R.ENI
R.SH0-1
REG
PEAK
BINFMT
REG
FMT
4
DET0-1
IO16-19
R1.ACC
REG
16
OEI
R2.ACC
R.PEAK
R.BINFMT
FIGURE 2. COMPLEX MULTIPLIER/ACCUMULATOR; ALL REGISTERS CLOCKED BY CLK
10
3
OEIEXT
RO16-19 RO0-15
ENI
SH0-1
MUX
OUTMUX0-1
R.BINFMT
REG
OER
4
MUX
16
IO0-15
HSP45116
The Growth Detect circuitry outputs a two bit value that
signifies the amount of growth on the data in the CMAC and
Complex Accumulator. Its output, DET0-1, is encoded as
shown in Table 5. If PEAK is low, the highest value of
DET0-1 is latched in the Growth Detect Output Register.
TABLE 5. GROWTH ENCODING
DET 1
DET 0
NUMBER OF BITS
OF GROWTH ABOVE 2o
0
0
0
0
1
1
1
0
2
1
1
3
The relative weighting of the bits at the inputs and outputs of
the CMAC is shown in Figure 3. Note that the binary point of
the sine, cosine, RIN and IIN is to the right of the most
significant bit, while the binary point of RO and IO is to the
right of the fifth most significant bit. These CMAC external
input and output busses are aligned with each other to
facilitate cascading NCOMs for FFT applications.
SIN/COS INPUT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-20 . 2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
↑
Radix Point
COMPLEX MULTIPLIER/ACCUMULATOR INPUT (RIN, IIN)
SH = 00
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-20 . 2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
↑
Radix Point
COMPLEX MULTIPLIER/ACCUMULATOR OUTPUT (RO, IO)
OUTMUX = 00
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-24
23
22
21
-20 . 2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
↑
Radix Point
COMPLEX MULTIPLIER/ACCUMULATOR OUTPUT (RO, IO)
OUTMUX = 01
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-24
23
22
21
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
2-29
2-30
0
COMPLEX ACCUMULATOR OUTPUT (RO, IO)
OUTMUX = 10
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-24
23
22
21
-20 . 2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
↑
Radix Point
FIGURE 3. BIT WEIGHTING
11
HSP45116
Applications
RIN IMIN
16
32
PFCS
CLK
16
CMAC
16
16
Modulation/Demodulation
SIGNAL INPUT
CLK
SINE/COSINE
GENERATOR
CENTER
FREQUENCY
16
PFCS
RO
RIN
SIN
CMAC
16
LO
XMTR
D/A
Figure 4 shows a block diagram of an AM modulator. In this
example, the phase increment for the carrier frequency is
loaded into the center frequency register, and the
modulating input is clocked into the real input of the CMAC,
with the imaginary input set to 0. The modulated output is
obtained at the real output of the CMAC. With a sixteen bit,
two’s complement signal input, the output will be a 16-bit real
number, on ROUT0-15 (with OUTMUX = 00).
32
16
NCOM
SINE/COSINE
GENERATOR
CENTER
FREQUENCY
The NCOM can be used for Amplitude, Phase and Frequency
modulation, as well as in variations and combinations of these
techniques, such as QAM. It is most effective in applications
requiring multiplication of a rotating complex sinusoid by an
external vector. These include AM and QAM modulators and
digital receivers. The NCOM implements AM and QAM
modulation on a single chip, and is a element in demodulation,
where it performs complex down conversion. It can be
combined with the Intersil HSP43220 Decimating Digital Filter
to form the front end of a digital receiver.
FIGURE 5. QUADRATURE AMPLITUDE MODULATION (QAM)
The NCOM also works with the HSP43220 Decimating
Digital Filter to implement down conversion and low pass
filtering in a digital receiver (Figure 6). The NCOM performs
complex down conversion on the wideband input signal by
multiplying the input vector and the internally generated
complex sinusoid. The resulting signal has components at
twice the center frequency and at DC. Two HSP43220s, one
each on the real and imaginary outputs of the HSP45116,
perform low pass filtering and decimation on the down
converted data, resulting in a complex baseband signal.
HSP45116
NCOM
RO
MODULATED OUTPUT
LO
FIGURE 4. AMPLITUDE MODULATION
SAMPLED
INPUT
DATA
By replacing the real input with a complex vector, a similar
setup can generate QAM signals (Figure 5). In this case, the
carrier frequency is loaded into the center frequency register as
before, but the modulating vector now carries both amplitude
and phase information. Since the input vector and the internally
generated sine and cosine waves are both 16 bits, the number
of states is only limited by the characteristics of the
transmission medium and by the analog electronics in the
transmitter and receiver.
The phase and amplitude resolution for the Sine/Cosine section
(16-bit output), delivers a spectral purity of greater than 90dBc.
This means that the unwanted spectral components due to
phase uncertainty (phase noise) will be greater than 90dB
below the desired output (dBc, decibels below the carrier). With
a 32-bit phase accumulator in the Phase/Frequency Control
Section, the frequency tuning resolution equals the clock
frequency divided by 232. For example, a 25MHz clock gives a
tuning resolution of 0.006Hz.
12
HSP43220
DDF
COS (wt)
XMTR
16
D/A
NCOM
SIN (wt)
INPUT
0
10MHz
NCOM
OUTPUT
0
20MHz
DDF
OUTPUT
0
FIGURE 6. CHANNELIZED RECEIVER CHIP SET
HSP45116
Absolute Maximum Ratings
Thermal Information
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
Input, Output or I/O Voltage Applied . . . . . GND -0.5V to VCC +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical, Note 1)
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V
Operating Temperature Range . . . . . . . . . . . . . . . . . . . 0°C to 70°C
θJA (°C/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.0
Maximum Junction Temperature
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(MQFP - Lead Tips Only)
Die Characteristics
Component Count . . . . . . . . . . . . . . . . . . . . . . . 103,000 Transistors
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
Logical One Input Voltage
VIH
VCC = 5.25V
2.0
-
V
Logical Zero Input Voltage
VIL
VCC = 4.75V
-
0.8
V
High Level Clock Input
VIHC
VCC = 5.25V
3.0
-
V
Low Level Clock Input
VILC
VCC = 4.75V
-
0.8
V
Output HIGH Voltage
VOH
IOH = -400mA, VCC = 4.75V
2.6
-
V
Output LOW Voltage
VOL
IOL = 2.0mA, VCC = 4.75V
-
0.4
V
Input Leakage Current
II
VIN = VCC or GND, VCC = 5.25V
-10
10
μA
I/O Leakage Current
IO
VOUT = VCC or GND, VCC = 5.25V
-10
10
μA
Standby Power Supply Current
ICCSB
VIN = VCC or GND VCC = 5.25V, Note 4
-
500
μA
Operating Power Supply Current
ICCOP
f = 15MHz, VIN = VCC or GND, VCC = 5.25V,
Notes 2 and 4
-
182
mA
Capacitance TA = 25°C, Note 3
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
Input Capacitance
CIN
-
15
pF
Output Capacitance
CO
FREQ = 1MHz, VCC = Open, All measurements
are referenced to device ground
-
15
pF
NOTES:
2. Power supply current is proportional to operating frequency. Typical rating for ICCOP is 10mA/MHz.
3. Not tested, but characterized at initial design and at major process/design changes.
4. Output load per test load circuit with switch open and CL = 40pF.
13
HSP45116
AC Electrical Specifications
VCC = 5.0V ±5%, TA = 0°C to 70°C (Note 5)
-15 (15MHz)
PARAMETER
SYMBOL
NOTES
-25 (25.6MHz)
-33 (33MHz)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CLK Period
tCP
66
-
39
-
30
-
ns
CLK High
tCH
26
-
15
-
12
-
ns
CLK Low
tCL
26
-
15
-
12
-
ns
WR Low
tWL
26
-
15
-
12
-
ns
WR High
tWH
26
-
15
-
12
-
ns
Setup Time; AD0-1, CS to WR Going High
tAWS
18
-
13
-
13
-
ns
Hold Time; AD0, AD1, CS from WR Going High
tAWH
0
-
0
-
0
-
ns
Setup Time C0-15 from WR Going High
tCWS
20
-
15
-
15
-
ns
Hold Time C0-15 from WR Going High
tCWH
0
-
0
-
0
-
ns
20
-
16
-
12
-
ns
Setup time WR High to CLK High
tWC
Setup Time MOD0-1 to CLK Going High
tMCS
20
-
15
-
15
-
ns
Hold Time MOD0-1 from CLK Going High
tMCH
0
-
0
-
0
-
ns
Setup Time PACI to CLK Going High
tPCS
25
-
15
-
11
-
ns
Hold Time PACI from CLK Going High
tPCH
0
-
0
-
0
-
ns
Setup ENPHREG, ENCFREG, ENOFREG,
ENPHAC, ENTIREG, CLROFR, PMSEL, LOAD, ENI,
ACC, BINFMT, PEAK, MODPI/2PI, SH0-1, RBYTILD
from CLK Going High
tECS
18
-
12
-
12
-
ns
Hold Time ENPHREG, ENCFREG, ENOFREG,
ENPHAC, ENTIREG, CLROFR, PMSEL, LOAD, ENI,
ACC, BINFMT, PEAK, MODPI/2PI, SH0-1, RBYTILD
from CLK Going High
tECH
0
-
0
-
0
-
ns
Setup Time RIN0-18, IMIN0-18 to CLK
Going High
tDS
18
-
12
-
12
-
ns
Hold Time RIN0-18, IMIN0-18 from CLK
Going High
tDH
0
-
0
-
0
-
ns
CLK to Output Delay RO0-19, IO0-19
tDO
-
40
-
24
-
19
ns
tDEO
-
40
-
27
-
20
ns
CLK to Output Delay PACO
tPO
-
30
-
20
-
12
ns
CLK to Output Delay TICO
tTO
-
30
-
20
-
12
ns
Output Enable Time OER, OEI, OEREXT, OEIEXT
tOE
-
25
-
20
-
20
ns
OUTMUX0-1 to Output Delay
tMD
-
40
-
28
-
26
ns
Output Disable Time
tOD
6
-
20
-
15
-
15
ns
Output Rise, Fall Time
tRF
6
-
8
-
8
-
6
ns
CLK to Output Delay DET0-1
7
NOTES:
5. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; input levels (all other inputs) 0V and 3.0V; timing reference levels (CLK)
2.0V; all others 1.5V. Output load per test load circuit with switch closed and CL = 40pF. Output transition is measured at VOH ≥ 1.5V and VOL
≤ 1.5V.
6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design
changes.
7. Applicable only when outputs are being monitored and ENCFREG, ENPHREG, or ENTIREG is active.
14
HSP45116
AC Test Load Circuit
S1
DUT
CL (NOTE)
IOH
SWITCH S1 OPEN FOR ICCSB AND ICCOP
±
1.5V
IOL
EQUIVALENT CIRCUIT
NOTE: Test head capacitance.
Waveforms
tCP
tCH
tCL
CLK
tMCS
tMCH
MOD0-1
tPCH
tPCS
PACI
tECS
tECH
CONTROL
INPUTS
tDS
tDH
RIN0-19
IIN0-19
tDO
ROUT0-19
IOUT0-19
tDEO
DET0-1
tPO
PACO
tTO
TICO
FIGURE 7. INPUT AND OUTPUT TIMING
15
HSP45116
Waveforms
(Continued)
tWC
CLK
tWL
WR
tWH
tAWS
tAWH
tAWS
tAWH
CS
AD0-1
tCWS
tCWH
C0-15
FIGURE 8. CONTROL BUS TIMING
OER
OEI
OEREXT
OEIEXT
RO0-19
IO0-19
OUTMUX0-1
1.5V
1.5V
tOE
HIGH
IMPEDANCE
tOD
tMD
1.7V
1.3V
RO0-19
HIGH
IMPEDANCE
IO0-19
FIGURE 9. OUTPUT ENABLE, DISABLE TIMING
FIGURE 10. MULTIPLEXER TIMING
2.0V
0.8V
tRF
tRF
FIGURE 11. OUTPUT RISE AND FALL TIMES
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
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