DATASHEET

ICM7244
®
Data Sheet
January 22, 2009
8-Character, Microprocessor Compatible,
LED Display Decoder Driver
The ICM7244 is an 8-character, alphanumeric display driver
and controller which provides all the circuitry required to
interface a microprocessor or digital system to a 16-segment
display with internal pull-up resistors. It is primarily intended
for use in microprocessor systems, where it minimizes
hardware and software overhead. Incorporated on-chip are a
64-character ASClI decoder, 8x6 memory, high power
character and segment drivers, and the multiplex scan
circuitry.
6-bit ASCll data to be displayed is written into the memory
directly from the microprocessor data bus. Data location
depends upon the selection of either Sequential
(MODE = 1) or Random access mode (MODE = 0). In the
Sequential Access mode the first entry is stored in the
lowest location and displayed in the “left-most” character
position. Each subsequent entry is automatically stored in
the next higher location and displayed to the immediate
“right” of the previous entry. A DISPlay FULL signal is
provided after 8 entries; this signal can be used for
cascading devices together. A CLR pin is provided to clear
the memory and reset the location counter. The Random
Access mode allows the processor to select the memory
address and display digit for each input word.
FN6675.1
Features
• 6-Segment Fonts with Decimal Point
• Has Internal Pull-Up Resistors of 617Ω Typ.
• Mask Programmable for Other Font-Sets Up to 64
Characters
• Microprocessor Compatible
• Directly Drives LED Common Cathode Displays
• Cascadable Without Additional Hardware
• Standby Feature Turns Display Off; Puts Chip in Low
Power Mode
• Sequential Entry or Random Entry of Data Into Display
• Single +5V Operation
• Character and Segment Drivers, All MUX Scan Circuitry,
8x6 Static Memory and 64-Character ASCll Font
Generator Included On-Chip
• Pb-Free (RoHS Compliant)
The character multiplex scan runs whenever data is not
being entered. It scans the memory and CHARacter drivers,
and ensures that the decoding from memory to display is
done in the proper sequence. Intercharacter blanking is
provided to avoid display ghosting.
Ordering Information
PART NUMBER
(Note)
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG. DWG. #
ICM7244AIM44Z
ICM7244 AIM44Z
-25°C to +85°C
44 Ld MQFP
Q44.10x10
ICM7244AIM44ZT
ICM7244 AIM44Z
-25°C to +85°C
44 Ld MQFP (Tape and Reel)
Q44.10x10
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ICM7244
Pinout
SEG f
SEG i
SEG b
SEG g2
SEG l
VDD
SEG m
SEG e
SEG g1
SEG d2
SEG a1
44 43 42 41 40 39 38 37 36 35 34
33
2
32
SEG a2
3
31
SEG h
D0
4
30
SEG j
D1
5
29
MODE
D2
6
28
A0/SEN
D3
7
27
A1/CLR
D4
8
26
A2/DISP FULL
D5
9
25
OSC/OFF
CS
10
24
CHAR1
NC
11
23
12 13 14 15 16 17 18 19 20 21 22
DP
NC
NC
CHAR2
CHAR3
VSS
CHAR4
CHAR5
CHAR6
CHAR7
CHAR8
NC
1
WR
SEG d1
2
SEG k
SEG c
ICM7244 (16-SEGMENT CHARACTER)
(44 LD MQFP)
TOP VIEW
FN6675.1
January 22, 2009
ICM7244
Functional Block Diagram
Q
DATA INPUT
D0 to D5
DATA
D LATCHES
CL
8x6
6
DATA
D0
MEMORY
CLR
CL
ADR
D1
ONE
SHOT
WR
17
64x17
ROM
SEGMENT
DRIVERS
8
SEGMENT
OUTPUTS
SEG x
WITH INT
PULL-UP
RESISTOR
OF 617Ω
TYP.
CS
CL
MODE
3
SEL
CL
D ADDRESS
LATCHES
MUX
CL
D
Q
CONTROL
LATCH
A0/SEN
A1/CLR
8
D
A2/DISP FULL
8
CHARACTER
CHARACTER
DRIVERS
CHAR N
CHARACTER
OUTPUTS
SEL
CL
EN
SEQUENTIAL
SEQUENTIAL
ADDRESS
3
COUNTER
CLR
ADDRESS
MULITPLEXER
MULTIPLEXER
AND
DECODER
OVERFLOW
3
OSC/OFF
3
OSCILLATOR
MULTIPLEX
OSCILLATOR
CHARACTER
MULTIPLEX
COUNTER
INTER-CHARACTER BLANKING
FN6675.1
January 22, 2009
ICM7244
Absolute Maximum Ratings
Thermal Information
Supply Voltage VDD - VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
Input Voltage (Any Terminal) . . . . . . . . . . VDD + 0.3V to VSS - 0.3V
CHARacter Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA
SEGment Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-25°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
VDD = 5V, VSS = 0V, TA = +25°C, Unless Otherwise Specified
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
4.75
5.0
5.25
V
VSUPP = 5.25V, 10 Segments ON, All 8 Characters
-
180
-
mA
VSUPP = 5.25V, OSC/OFF Pin < 0.5V, CS = VSS
-
30
250
µA
DC CHARACTERISTICS
Supply Voltage (VDD - VSS)
VSUPP
Operating Supply Current
IDD
Quiescent Supply Current
ISTBY
Input High Voltage
VIH
2
-
-
V
Input Low Voltage
VIL
-
-
0.8
V
Input Current
-10
-
+10
µA
VSUPP = 5V, VOUT = 1V
140
190
-
mA
-
-
100
µA
VSUPP = 5V, VOUT = 2.5V
3.3
4.5
5.5
mA
-
0.01
10
µA
-
-
0.4
V
IIN
CHARacter Drive Current
ICHAR
CHARacter Leakage Current
ICHLK
SEGment Drive Current
ISEG
SEGment Leakage Current
ISLK
DISPlay FULL Output Low
VOL
IOL = 1.6mA
DISPlay FULL Output High
VOH
lIH = 100µA
2.4
-
-
V
Display Scan Rate
fDS
-
400
-
Hz
Electrical Specifications
Drive levels 0.4V and 2.4V, timing measured at 0.8V and 2.0V. VDD = 5V, TA = +25°C,
Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
300
250
-
ns
AC CHARACTERISTICS
WR, CLeaR Pulse Width Low
tWPI
WR, CLeaR Pulse Width High (Note 2)
tWPH
-
250
-
ns
tDH
0
-100
-
ns
Data Setup Time
tDS
250
150
-
ns
Address Hold Time
tAH
125
-
-
ns
Address Setup Time
tAS
40
15
-
ns
CS Setup Time
tCS
0
-
-
ns
Data Hold Time
tT
-
-
100
ns
SEN Setup Time
Pulse Transition Time
tSEN
0
-25
-
ns
Display Full Delay
tWDF
760
540
-
ns
Capacitance
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Capacitance
ClN
(Note 3)
-
5
-
pF
Output Capacitance
CO
(Note 3)
-
5
-
pF
2. In Sequential mode WR high must be ≥ TSEN +TWDF .
3. For design reference only, not tested.
4
FN6675.1
January 22, 2009
ICM7244
Timing Waveforms
CS
tCS
tAH
tAS
ADDRESS
VALID
tWPI
tWC
tWHP
WRITE
tDS
tT
DATA
tT
tDH
VALID
FIGURE 1. RANDOM ACCESS TIMING
CHAR
1
WR
CHAR
2
CHAR
8
tSEN
tWPH
CLEAR
SEN
tWDF
DISPLAY FULL
FIGURE 2. SEQUENTIAL ACCESS MODE TIMING (MODE = 1)
~5µs
~300µs
INTERNAL
INTER-CHARACTER
BLANKING
SIGNAL
CHAR 1
CHAR 2
CHAR 3
CHARACTERS
DRIVE
SIGNALS
CHAR 4
CHAR 5
INTER-CHARACTER BLANKING
CHAR 6
CHAR 7
CHAR 8
FIGURE 3. DISPLAY CHARACTERS MULTIPLEX TIMING DIAGRAM
5
FN6675.1
January 22, 2009
ICM7244
Pin Descriptions
SIGNAL
PIN
FUNCTION
D0 - D5
4 thru 9
CS
10
Chip Select from µP address decoder, etc.
WR
13
WRite pulse input pin (active low). For an active high write pulse, CS can be used.
MODE
29
Selects data entry MODE. High selects Sequential Access (SA) mode where first entry is displayed
in “leftmost” character and subsequent entries appear to the “right”. Low selects the Random
Access (RA) mode where data is displayed on the character addressed via A0 thru A2 Address pins.
A0/SEN
28
In RA mode it is the LSB of the character Address. In SA mode it is used for cascading devices for
displays of more than 8 characters (active high enables device controller).
A1/CLR
27
In RA mode this is the second bit of the address. In SA mode, a low input will CLeaR the Serial
Address Counter, the Data Memory and the display.
A2/DISP FULL
26
In RA mode this is the MSB of the Address. In SA mode, the output goes high after 8 entries,
indicating DISPlay FULL.
OSC/OFF
25
OSCillator input pin. Adding capacitance to VDD will lower the internal oscillator frequency. An external
oscillator can be applied to this pin. A low at this input sets the device into a (shutdown) mode, shutting
OFF the display and oscillator but retaining data stored in memory.
SEG d1, SEG a1,
SEG a2,
SEG j, SEG h, DP,
SEG d2, SEG f,
SEG i, SEG b, SEG
g2, SEG I,
SEG m, SEG e,
SEG g1, SEG k,
SEG c
1 thru 3,
30 thru 38
CHAR8 thru
CHAR5,
CHAR4 thru
CHAR2,
CHAR1
14 thru 17,
19 thru 21,
24
6-Bit ASCll Data input pins (active high).
SEGment driver outputs.
40 thru 44
6
CHARacter driver outputs.
FN6675.1
January 22, 2009
ICM7244
Test Circuit
17 SEGMENTS
CHAR 8 CHAR 7 CHAR 6 CHAR 5 CHAR 4 CHAR 3 CHAR 2 CHAR 1
SEG d1
SEG a2
SEG f
SEG i
SEG b
SEG g2
SEG l
VDD
SEG m
SEG e
SEG g1
3
31
D0
4
30
D1
5
29
D2
6
28
D3
7
27
D4
8
26
SEG d2
DP
SEG h
MODE (SA/RA)
A0/SEN
A2/DISP FULL
NC
DISPLAY
FULL
OUTPUT
VDD
NC (FOR SA MODE)
NC
CHAR2
NC
CHAR3
CHAR1
11
23
12 13 14 15 16 17 18 19 20 21 22
CHAR4
OSC/OFF
24
CHAR5
VSS
25
CHAR6
9
10
CHAR7
VDD
A1/CLR
D5
CHAR8
SEGMENTS
SEG j
CS
NC
VDD
44 43 42 41 40 39 38 37 36 35 34
33
2
32
1
WR
SEGMENTS
SEG a1
SEG k
SEG c
SEGMENTS
FIGURE 4.
7
FN6675.1
January 22, 2009
ICM7244
Typical Applications
8 CHARACTERS
8 CHARACTERS
+5V
CHAR
SEG
CHAR
SEG
RRI
RBR8
CLR
RBR7
CS
SEN
UART
WR
RBR1 - RBR6
CS
ICM7244
HD6402
DRR
CLR
DISP
SEN
FULL
FULL
ETC.
WR
D0 - D5
CS
D0 - D5
CS
D0 - D5
CS
D0 - D5
CS
6 BIT BUS
DR
+5V
+5V
+5V
20k
OUT
ICM7244
DISP
WR
WR
CS
CS
V+
SEN
SEN
ICM7244
TR
ICM7244
DISP
ICL7555
DISP
FULL
CHAR
TH
FULL
CLR
CLR
DELAY
ETC.
SEG
CHAR
SEG
200pF
8 CHARACTERS
8 CHARACTERS
FIGURE 5. DRIVING TWO ROWS OF CHARACTERS FROM A SERIAL INPUT
8
FN6675.1
January 22, 2009
ICM7244
Typical Applications
(Continued)
8-CHARACTER LED DISPLAY
8
CLR
CLR
8-CHARACTER LED DISPLAY
8
NOTE
CLR
CHAR
SEN
+5V
MODE
DATA
BUS
+5V
+5V
VDD
VSS
CS
6
CLR
SEN
MODE
WR
D0 - D5
SEG
DISP FULL
CS
SEN
MODE
WR
D0 - D5
+5V
+5V
VDD
VSS
6
NOTE
CHAR
SEG
DISP FULL
WR
D0 - D5
8
NOTE
CHAR
SEG
+5V
8-CHARACTER LED DISPLAY
DISP FULL
VDD
VSS
CS
+5V
6
WR
CS,
(WR)
FIRST 8 CHARACTERS
SECOND 8 CHARACTERS
NTH 8 CHARACTERS
NOTE: 17 for ICM7244.
FIGURE 6. MULTICHARACTER DISPLAY USING SEQUENTIAL ACCESS MODE
+5V
+5V
+5V
+5V
+5V
1k
1.4APEAK
2N6034
617Ω
617Ω
1mA
2N2219
SEG
SEG
300Ω
14Ω (100mAPEAK)
ICM7244
1k
ICM7244
25Ω
r ON = 4Ω
(100mAPEAK)
CHAR
CHAR
2N2219
14mA
2N6034
r ON = 4Ω
1k
1.4APEAK
GND
GND
GND
GND
GND
FIGURE 7A. COMMON CATHODE DISPLAY
FIGURE 7B. COMMON ANODE DISPLAY
FIGURE 7. DRIVING LARGE DISPLAYS
9
FN6675.1
January 22, 2009
ICM7244
Typical Applications
(Continued)
8 CHARACTERS
8 CHARACTERS
8 CHARACTERS
8 CHARACTERS
ICM7244
ICM7244
ICM7244
ICM7244
CS A2 A1 A0 D0 - D5 WR
CS A2 A1 A0 D0 - D5 WR
CS A2 A1 A0 D0 - D5 WR
CS A2 A1 A0 D0 - D5 WR
P22
P21
P20
80C35
80C48
DB7
DB6
6 BIT BUS
DB5 - DB0
WR
FIGURE 8. RANDOM ACCESS 32-CHARACTER DISPLAY IN A 80C48 SYSTEM
Display Font and Segment Assignments
a1
f
h
a2
i
g1
e
m
g2
l
d2
D5, D4
0
0
0
1
1
0
1
1
b
j
k
c
d1
DP
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FIGURE 9. 16-SEGMENT CHARACTER FONT WITH DECIMAL POINT
10
FN6675.1
January 22, 2009
ICM7244
Display Font and Segment Assignments
(Continued)
VDD
SEGMENT
DRIVER
VLED = 1.6V
RTYPICAL = 617Ω
R
SEG x
DISPLAY
CHARACTER
DRIVER
CHAR N
rDS(ON) ~ 4mΩ
SEGMENT LEDs
VSS
FIGURE 10. SEGMENT AND CHARACTER DRIVERS OUTPUT CIRCUIT
Detailed Description
WR, CS
These pins are immediately functionally ANDed, so all
actions described as occurring on an edge of WR, with CS
enabled, will occur on the equivalent (last) enabling or
(first) disabling edge of any of these inputs. The delays
from CS pins are slightly (about 5ns) greater than from WR
due to the additional inverter required on the former.
MODE
The MODE pin input is latched on the falling edge of WR
(or its equivalent, see WR description). The location (in
Data Memory) where incoming data will be placed is
determined either from the Address pins or the Sequential
Address Counter. This is controlled by MODE input. MODE
also controls the function of A0/SEN, A1/CLR, and
A2/DlSPlay FULL lines.
Random Access Mode
When the internal mode latch is set for Random Access
(RA) (MODE latched low), the Address input on A0, A1 and
A2 will be latched by the falling edge of WR (or its
equivalent). Subsequent changes on the Address lines will
not affect device operation. This allows use of a
multiplexed 6-bit bus controlling both address and data,
with timing controlled by WR.
Sequential Access Mode
If the internal latch is set for Sequential Access (SA),
(MODE latched high), the Serial ENable input or SEN will
be latched on the falling edge of WR (or its equivalent). The
CLR input is asynchronous, and will force-clear the
Sequential Address Counter to address 000 (CHARacter
1), and set all Data Memory contents to 100000 (blank) at
any time. The DISPlay FULL output will be active in SA
mode to indicate the overflow status of the Sequential
11
Address Counter. If this output is low, and SEN is (latched)
high, the contents of the Counter will be used to establish
the Data Memory location for the Data input. The Counter
is then incremented on the rising edge of WR. If SEN is
low, or DISPlay FULL is high, no action will occur. This
allows easy “daisy-chaining” of display drivers for multiple
character displays in a Sequential Access mode.
Changing Modes
Care must be exercised in any application involving
changing from one mode to another. The change will occur
only on a falling edge of WR (or its equivalent). When
changing mode from Sequential Access to Random
Access, note that A2/DlSPlay FULL will be an output until
WR has fallen low, and an Address drive here could cause
a conflict. When changing from Random Access to
Sequential Access, A1/CLR should be high to avoid
inadvertent clearing of the Data Memory and Sequential
Address Counter. DISPlay FULL will become active
immediately after the rising edge of WR.
Data Entry
The input Data is latched on the rising edge of WR (or its
equivalent) and then stored in the Data Memory location
determined as described above. The six Data bits can be
multiplexed with the Address information on the same lines
in Random Access mode. Timing is controlled by the WR
input.
OSC/OFF
The device includes a relaxation oscillator with an internal
capacitor and a nominal frequency of 200kHz. By adding
external capacitance to VDD at the OSC/OFF pin, this
frequency can be reduced as far as desired. Alternatively,
an external signal can be injected on this pin. The oscillator
(or external) frequency is pre-divided by 64, and then
further divided by 8 in the Multiplex Counter, to drive the
FN6675.1
January 22, 2009
ICM7244
CHARacter drive lines ( Figure 3). An inter-character
blanking signal is derived from the pre-divider. An
additional comparator on the OSC/OFF input detects a
level lower than the relaxation oscillator's range, and
blanks the display, disables the DISPlay FULL output (if
active), and clears the pre-divider and Multiplex Counter.
This puts the circuit in a low-power-dissipation mode in
which all outputs are effectively open circuits, except for
parasitic diodes to the supply lines. Thus a display
connected to the output may be driven by another circuit
(including another ICM7244) without driver conflicts.
Display Output
The output of the Multiplex Counter is decoded and
multiplexed into the address input of the Data Memory,
except during WR operations (in Sequential Access mode,
with SEN high and DISPlay FULL low), when it scans
through the display data. The address decoder also drives
12
the CHARacter outputs, except during the inter-character
blanking interval (nominally about 5µs). Each CHARacter
output lasts nominally about 300µs, and is repeated
nominally every 2.5ms, i.e., at a 400Hz rate (times are
based on internal oscillator without external capacitor).
The 6 bits read from the Data Memory are decoded in the
ROM to the 17 segment signals, which drive the SEGment
outputs. Both CHARacter and SEGment outputs are
disabled during WR operations (with SEN high and
DISPlay FULL Low for Sequential Access mode). The
outputs may also be disabled by pulling OSC/OFF low.
The decode pattern from 6 bits to 17 segments is done by a
ROM pattern according to the ASCll font shown. Custom
decode patterns can be arranged, within these limitations,
by consultation with the factory.
FN6675.1
January 22, 2009
ICM7244
Metric Plastic Quad Flatpack Packages (MQFP)
D
Q44.10x10 (JEDEC MS-022AB ISSUE B)
44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
D1
-D-
INCHES
-A-
-B-
E E1
e
PIN 1
-H-
A
SEATING
PLANE
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.096
-
2.45
-
A1
0.004
0.010
0.10
0.25
-
A2
0.077
0.083
1.95
2.10
-
b
0.012
0.018
0.30
0.45
6
b1
0.012
0.016
0.30
0.40
-
D
0.515
0.524
13.08
13.32
3
D1
0.389
0.399
9.88
10.12
4, 5
E
0.516
0.523
13.10
13.30
3
E1
0.390
0.398
9.90
10.10
4, 5
L
0.029
0.040
0.73
1.03
N
44
44
e
0.032 BSC
0.80 BSC
7
Rev. 2 4/99
NOTES:
0.076
0.003
12o-16o
0.40
0.016 MIN
-C0.20
M
0.008
C A-B S
0o MIN
D S
b
A2 A1
0o-7o
L
12o-16o
b1
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane -C- .
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
0.13/0.17
0.005/0.007
6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.
BASE METAL
WITH PLATING
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
7. “N” is the number of terminal positions.
0.13/0.23
0.005/0.009
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN6675.1
January 22, 2009
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