DATASHEET

8-Character, 16-Segment, Microprocessor Compatible,
LED Display Decoder Driver
ICM7245
Features
The ICM7245 is an 8-character, alphanumeric display driver
and controller which provides all the circuitry required to
interface a microprocessor or digital system to a 16-segment
display with internal pull-up resistors. It is primarily intended
for use in microprocessor systems, where it minimizes
hardware and software overhead. Incorporated on-chip are a
64-character ASClI decoder, 8x6 memory, high power
character and segment drivers, and the multiplex scan
circuitry.
• Single supply +3.3V operation
6-bit ASCll data to be displayed is written into the memory
directly from the microprocessor data bus. Data location
depends upon the selection of either Sequential (MODE = 1) or
Random access mode (MODE = 0). In the Sequential Access
mode the first entry is stored in the lowest location and
displayed in the “left-most” character position. Each
subsequent entry is automatically stored in the next higher
location and displayed to the immediate “right” of the previous
entry. A DISPlay FULL signal is provided after 8 entries; this
signal can be used for cascading devices together. A CLR pin is
provided to clear the memory and reset the location counter.
The Random Access mode allows the processor to select the
memory address and display digit for each input word.
• Standby feature turns display off; puts chip in low power
mode
• 16-Segment fonts with decimal point
• Up to 8 character display driver
• Has internal pull-up resistors of 136Ω Typical
• Microprocessor compatible
• Directly drives LED common cathode displays
• Cascadable without additional hardware
• Sequential entry or random entry of data into display
• Character and segment drivers, All MUX scan circuitry, 8x6
static memory and 64-character ASCll font generator
included on-chip
• Pb-free (RoHS compliant)
The character multiplex scan runs whenever data is not being
entered. It scans the memory and CHARacter drivers, and
ensures that the decoding from memory to display is done in
the proper sequence. Intercharacter blanking is provided to
avoid display ghosting.
Ordering Information
PART NUMBER
(Note 2)
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG. DWG. #
ICM7245AIM44Z
ICM7245 AIM44Z
-25°C to +85°C
44 Ld MQFP
Q44.10x10
ICM7245AIM44ZT (Note 1)
ICM7245 AIM44Z
-25°C to +85°C
44 Ld MQFP (Tape and Reel)
Q44.10x10
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ICM7245. For more information on MSL, please see tech brief TB363.
October 29, 2013
FN8587.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ICM7245
Pin Configuration
SEG f
SEG i
SEG b
SEG g2
SEG l
VDD
SEG m
SEG e
SEG g1
SEG k
SEG c
ICM7245 (16-SEGMENT CHARACTER)
(44 LD MQFP)
TOP VIEW
SEG a1
44 43 42 41 40 39 38 37 36 35 34
33
2
32
SEG a2
3
31
SEG h
D0
4
30
SEG j
D1
5
29
MODE
D2
6
28
A0/SEN
D3
7
27
A1/CLR
D4
8
26
A2/DISP FULL
SEG d1
1
SEG d2
DP
NC
NC
CHAR2
CHAR3
VSS
CHAR4
CHAR5
11
23
12 13 14 15 16 17 18 19 20 21 22
CHAR6
CHAR1
NC
CHAR7
OSC/OFF
24
CHAR8
25
NC
9
10
WR
D5
CS
Pin Descriptions
SIGNAL
PIN
FUNCTION
D0 - D5
4 thru 9
CS
10
Chip Select from µP address decoder, etc.
6-Bit ASCll Data input pins (active high).
WR
13
WRite pulse input pin (active low). For an active high write pulse, CS can be used.
MODE
29
Selects data entry MODE. High selects Sequential Access (SA) mode where first entry is displayed
in “leftmost” character and subsequent entries appear to the “right”. Low selects Random Access
(RA) mode where data is displayed on the character addressed via A0 thru A2 Address pins.
A0/SEN
28
In RA mode it is the LSB of the character Address. In SA mode it is used for cascading devices for
displays of more than 8 characters (active high enables device controller).
A1/CLR
27
In RA mode this is the second bit of the address. In SA mode, a low input will CLeaR the Serial
Address Counter, the Data Memory and the display.
A2/DISP FULL
26
In RA mode this is the MSB of the Address. In SA mode, the output goes high after 8 entries,
indicating DISPlay FULL.
OSC/OFF
25
OSCillator input pin. Adding capacitance to VDD will lower the internal oscillator frequency. An
external oscillator can be applied to this pin. A low at this input sets the device into a (shutdown)
mode, shutting OFF the display and oscillator but retaining data stored in memory.
SEG d1, SEG a1, SEG a2;
SEG j, SEG h, DP, SEG d2, SEG f, SEG i,
SEG b, SEG g2, SEG I;
SEG m, SEG e, SEG g1, SEG k, SEG c
1 thru 3,
30 thru 38
CHAR8 thru CHAR5,
CHAR4 thru CHAR2, CHAR1
SEGment driver outputs.
40 thru 44
14 thru 17, CHARacter driver outputs.
19 thru 21, 24
VSS
18
Supply Ground.
VDD
39
Positive Power Supply +3.0V to +3.6V.
NC
11, 12, 22, 23 No connection.
2
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ICM7245
Functional Block Diagram
DATA INPUT
D0 to D5
DATA
D LATCHES
Q
CL
8x6
6
DATA
D0
MEMORY
CLR
CL
ADR
D1
ONE
SHOT
WR
17
64x17
ROM
SEGMENT
DRIVERS
SEGMENT
OUTPUTS
SEG x with
INT PULL-UP
RESISTOR
OF 136Ω TYP.
8
CS
CL
MODE
8
D
SEL
CL
D ADDRESS
LATCHES
MUX
D
A0/SEN
A1/CLR
CL
Q
CONTROL
LATCH
A2/DISP FULL
3
8
CHARACTER
CHARACTER
DRIVERS
CHAR N
CHARACTER
OUTPUTS
SEL
CL
EN
SEQUENTIAL
SEQUENTIAL
ADDRESS
3
COUNTER
CLR
ADDRESS
MULITPLEXER
MULTIPLEXER
AND
DECODER
OVERFLOW
3
OSC/OFF
3
OSCILLATOR
MULTIPLEX
OSCILLATOR
CHARACTER
MULTIPLEX
COUNTER
INTER-CHARACTER BLANKING
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ICM7245
Absolute Maximum Ratings
Thermal Information
Supply Voltage VDD - VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
Input Voltage (Any Terminal) . . . . . . . . . . . . . . . . . .VDD + 0.3V to VSS - 0.3V
CHARacter Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA
SEGment Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
44 Ld MQFP Package (Notes 4, 5) . . . . . . .
70
21
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications
PARAMETER
VDD = 3.3V, VSS = 0V, TA = +25°C, Unless Otherwise Specified.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
3
3.3
3.6
V
VSUPP = 3.6V, 10 Segments ON, All 8 Characters
-
50
-
mA
VSUPP = 3.6V, OSC/OFF Pin < 0.5V, CS = VSS
-
3.2
25
µA
DC CHARACTERISTICS
Supply Voltage (VDD - VSS)
VSUPP
Operating Supply Current
IDD
Quiescent Supply Current
ISTBY
Input High Voltage
VIH
2.0
-
-
V
Input Low Voltage
VIL
-
-
0.8
V
Input Current
IIN
-10
-
+10
µA
VSUPP = 3.3V, VOUT = 1V
70
135
-
mA
VSUPP = 3.0V, VOUT = 2V
120
175
235
mA
-
-
100
µA
3.7
5.1
6.7
mA
-
0.02
10
µA
CHARacter Drive Current
ICHAR
CHARacter Leakage Current
ICHLK
SEGment Drive Current
ISEG
SEGment Leakage Current
ISLK
DISPlay FULL Output Low
VOL
IOL = 1.6mA
-
-
0.4
V
DISPlay FULL Output High
VOH
lIH = 100µA
2.4
-
-
V
Display Scan Rate
fDS
-
300
-
Hz
Electrical Specifications
Unless Otherwise Specified.
PARAMETER
VSUPP = 3.3V, VOUT = 2V
Drive levels 0.4V and 2.4V, timing measured at 0.8V and 2.0V. VDD = 3.3V, TA = +25°C,
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
AC CHARACTERISTICS
WR, CLeaR Pulse Width Low
tWPI
500
250
-
ns
WR, CLeaR Pulse Width High (Note 6)
tWPH
-
250
-
ns
Data Hold Time
tDH
0
-100
-
ns
Data Setup Time
tDS
250
150
-
ns
Address Hold Time
tAH
125
-
-
ns
Address Setup Time
tAS
100
-
-
ns
CS Setup Time
tCS
0
-
-
ns
tT
-
-
100
ns
SEN Setup Time
tSEN
0
-25
-
ns
Display Full Delay
tWDF
760
540
-
ns
Pulse Transition Time
4
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ICM7245
Capacitance
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Capacitance
ClN
(Note 7)
-
5
-
pF
Output Capacitance
CO
(Note 7)
-
5
-
pF
NOTES:
6. In Sequential mode WR high must be ≥ TSEN +T WDF .
7. For design reference only, not tested.
Timing Waveforms
CS
tCS
tAS
ADDRESS
tAH
VALID
tWPI
tWC
tWHP
WRITE
tDS
tT
DATA
tT
tDH
VALID
FIGURE 1. RANDOM ACCESS TIMING
CHAR
1
WR
CHAR
2
tSEN
CHAR
8
tWPH
CLEAR
SEN
tWDF
DISPLAY FULL
FIGURE 2. SEQUENTIAL ACCESS MODE TIMING (MODE = 1)
5
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ICM7245
Timing Waveforms
(Continued)
~5µs
~300µs
INTERNAL
INTER-CHARACTER
BLANKING
SIGNAL
CHAR 1
CHAR 2
CHAR 3
CHARACTERS
DRIVE
SIGNALS
CHAR 4
CHAR 5
INTER-CHARACTER BLANKING
CHAR 6
CHAR 7
CHAR 8
FIGURE 3. DISPLAY CHARACTERS MULTIPLEX TIMING DIAGRAM
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ICM7245
Test Circuit
17 SEGMENTS
CHAR 8 CHAR 7 CHAR 6 CHAR 5 CHAR 4 CHAR 3 CHAR 2 CHAR 1
SEG d1
SEG a2
SEG f
SEG i
SEG b
SEG g2
SEG l
VDD
SEG m
SEG e
SEG g1
3
31
SEG d2
DP
SEG h
SEGMENTS
SEG j
D0
4
30
D1
5
29
D2
6
28
D3
7
27
8
26
A2/DISP FULL
D4
MODE (SA/RA)
A0/SEN
A1/CLR
NC
VDD
DISPLAY
FULL
OUTPUT
VDD
NC (FOR SA MODE)
NC
CHAR2
CHAR3
NC
CHAR4
CHAR1
11
23
12 13 14 15 16 17 18 19 20 21 22
CHAR5
VSS
OSC/OFF
24
CHAR6
25
CHAR7
9
10
NC
D5
CS
CHAR8
VDD
44 43 42 41 40 39 38 37 36 35 34
33
2
32
1
WR
SEGMENTS
SEG a1
SEG k
SEG c
SEGMENTS
FIGURE 4.
7
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ICM7245
Typical Applications
8 CHARACTERS
+3.3V
CHAR
RRI
RBR8
CLR
RBR7
CS
HD6402
SEN
UART
WR
RBR1 - RBR6
DRR
8 CHARACTERS
SEG
CHAR
CLR
CS
ICM7245
DISP
ICM7245
DISP
SEN
FULL
FULL
ETC.
WR
D0 - D5
CS
D0 - D5
CS
D0 - D5
CS
D0 - D5
CS
6 BIT BUS
DR
+3.3V
+3.3V
+3.3V
20k
OUT
SEG
V+
WR
CS
WR
CS
DISP
SEN
FULL
ICM7245
TR
DISP
SEN
ICM7245
FULL
ETC.
ICL7555
CLR
CLR
DELAY
CHAR
TH
SEG
CHAR
SEG
200pF
8 CHARACTERS
8 CHARACTERS
FIGURE 5. DRIVING TWO ROWS OF CHARACTERS FROM A SERIAL INPUT
8
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ICM7245
Typical Applications
(Continued)
8-CHARACTER LED DISPLAY
8-CHARACTER LED DISPLAY
17
8
CLR
CLR
SEN
+3.3V
MODE
DATA
BUS
+3.3V
+3.3V
VDD
VSS
CS
6
CLR
SEN
MODE
WR
D0 - D5
SEG
DISP FULL
CS
SEN
MODE
WR
D0 - D5
+3.3V
+3.3V
VDD
VSS
6
17
CHAR
SEG
DISP FULL
WR
D0 - D5
8
CHAR
SEG
+3.3V
17
8
CLR
CHAR
8-CHARACTER LED DISPLAY
DISP FULL
VDD
VSS
CS
+3.3V
6
WR
CS,
(WR)
FIRST 8 CHARACTERS
SECOND 8 CHARACTERS
NTH 8 CHARACTERS
FIGURE 6. MULTICHARACTER DISPLAY USING SEQUENTIAL ACCESS MODE
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
1k
1.4APEAK
2N6034
136Ω
136Ω
1mA
2N2219
SEG
SEG
300Ω
14Ω (100mAPEAK)
ICM7245
1k
ICM7245
25Ω
r ON = 6Ω
(100mAPEAK)
CHAR
r ON = 6Ω
CHAR
14mA
2N2219
2N6034
1.4APEAK
1k
GND
GND
GND
FIGURE 7A. COMMON CATHODE DISPLAY
GND
GND
FIGURE 7B. COMMON ANODE DISPLAY
FIGURE 7. DRIVING LARGE DISPLAYS
9
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ICM7245
Typical Applications
(Continued)
8 CHARACTERS
8 CHARACTERS
8 CHARACTERS
8 CHARACTERS
ICM7245
ICM7245
ICM7245
ICM7245
CS A2 A1 A0 D0 - D5 WR
CS A2 A1 A0 D0 - D5 WR
CS A2 A1 A0 D0 - D5 WR
CS A2 A1 A0 D0 - D5 WR
P22
P21
P20
80C35
80C48
DB7
DB6
6 BIT BUS
DB5 - DB0
WR
FIGURE 8. RANDOM ACCESS 32-CHARACTER DISPLAY IN A 80C48 SYSTEM
Display Font and Segment Assignments
a1
f
h
a2
i
g1
e
m
D5, D4
0
0
1
1
0
1
1
b
g2
l
d2
0
j
k
c
d1
DP
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FIGURE 9. 16-SEGMENT CHARACTER FONT WITH DECIMAL POINT
10
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ICM7245
Display Font and Segment Assignments
(Continued)
VDD
SEGMENT
DRIVER
VLED = 2V
RTYPICAL =136Ω
R
SEG x
DISPLAY
CHARACTER
DRIVER
CHAR N
rDS(ON) ~ 7.4Ω
SEGMENT LEDs
VSS
FIGURE 10. SEGMENT AND CHARACTER DRIVERS OUTPUT CIRCUIT
Detailed Description
WR, CS
These pins are immediately functionally ANDed, so all actions
described as occurring on an edge of WR, with CS enabled, will
occur on the equivalent (last) enabling or (first) disabling edge
of any of these inputs. The delays from CS pins are slightly
(about 5ns) greater than from WR due to the additional
inverter required on the former.
MODE
The MODE pin input is latched on the falling edge of WR (or its
equivalent, see WR description). The location (in Data
Memory) where incoming data will be placed is determined
either from the Address pins or the Sequential Address
Counter. This is controlled by MODE input. MODE also controls
the function of A0/SEN, A1/CLR, and A2/DlSPlay FULL lines.
Random Access Mode
When the internal mode latch is set for Random Access (RA)
(MODE latched low), the Address input on A0, A1 and A2 will
be latched by the falling edge of WR (or its equivalent).
Subsequent changes on the Address lines will not affect device
operation. This allows use of a multiplexed 6-bit bus controlling
both address and data, with timing controlled by WR.
Sequential Access Mode
If the internal latch is set for Sequential Access (SA), (MODE
latched high), the Serial ENable input or SEN will be latched on
the falling edge of WR (or its equivalent). The CLR input is
asynchronous, and will force-clear the Sequential Address
Counter to address 000 (CHARacter 1), and set all Data
Memory contents to 100000 (blank) at any time. The DISPlay
FULL output will be active in SA mode to indicate the overflow
status of the Sequential Address Counter. If this output is low,
and SEN is (latched) high, the contents of the Counter will be
used to establish the Data Memory location for the Data input.
The Counter is then incremented on the rising edge of WR. If
11
SEN is low, or DISPlay FULL is high, no action will occur. This
allows easy “daisy-chaining” of display drivers for multiple
character displays in a Sequential Access mode.
Changing Modes
Care must be exercised in any application involving changing
from one mode to another. The change will occur only on a
falling edge of WR (or its equivalent). When changing mode
from Sequential Access to Random Access, note that
A2/DlSPlay FULL will be an output until WR has fallen low, and
an Address drive here could cause a conflict. When changing
from Random Access to Sequential Access, A1/CLR should be
high to avoid inadvertent clearing of the Data Memory and
Sequential Address Counter. DISPlay FULL will become active
immediately after the rising edge of WR.
Data Entry
The input Data is latched on the rising edge of WR (or its
equivalent) and then stored in the Data Memory location
determined as described above. The six Data bits can be
multiplexed with the Address information on the same lines in
Random Access mode. Timing is controlled by the WR input.
OSC/OFF
The device includes a relaxation oscillator with an internal
capacitor and a nominal frequency of 200kHz. By adding
external capacitance to VDD at the OSC/OFF pin, this
frequency can be reduced as far as desired. Alternatively, an
external signal can be injected on this pin. The oscillator (or
external) frequency is pre-divided by 64, and then further
divided by 8 in the Multiplex Counter, to drive the CHARacter
drive lines (Figure 3). An inter-character blanking signal is
derived from the pre-divider. An additional comparator on the
OSC/OFF input detects a level lower than the relaxation
oscillator's range, and blanks the display, disables the DISPlay
FULL output (if active), and clears the pre-divider and Multiplex
Counter. This puts the circuit in a low-power-dissipation mode
FN8587.0
October 29, 2013
ICM7245
in which all outputs are effectively open circuits, except for
parasitic diodes to the supply lines. Thus a display connected to
the output may be driven by another circuit (including another
ICM7245) without driver conflicts.
Display Output
The output of the Multiplex Counter is decoded and multiplexed
into the address input of the Data Memory, except during WR
operations (in Sequential Access mode, with SEN high and
DISPlay FULL low), when it scans through the display data. The
address decoder also drives the CHARacter outputs, except
during the inter-character blanking interval (nominally about
5µs). Each CHARacter output lasts nominally about 300µs, and
is repeated nominally every 2.5ms, i.e., at a 400Hz rate (times
are based on internal oscillator without external capacitor).
The 6 bits read from the Data Memory are decoded in the ROM
to the 17 segment signals, which drive the SEGment outputs.
Both CHARacter and SEGment outputs are disabled during WR
operations (with SEN high and DISPlay FULL Low for Sequential
Access mode). The outputs may also be disabled by pulling
OSC/OFF low.
The decode pattern from 6 bits to 17 segments is done by a ROM
pattern according to the ASCll font shown. Custom decode
patterns can be arranged, within these limitations, by contacting
Intersil sales support.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web
to make sure that you have the latest revision.
DATE
REVISION
October 29, 2013
FN8587.0
CHANGE
Initial Release
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN8587.0
October 29, 2013
ICM7245
Metric Plastic Quad Flatpack Packages (MQFP)
Q44.10x10 (JEDEC MS-022AB ISSUE B)
44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
D
D1
-D-
INCHES
-A-
-B-
E E1
e
PIN 1
SEATING
A PLANE
-H-
0.076
0.003
-C-
12o-16o
0.40
0.016 MIN
0.20
M
0.008
C A-B S
0o MIN
A2 A1
0o-7o
L
MAX
MIN
MAX
NOTES
-
0.096
-
2.45
-
A1
0.004
0.010
0.10
0.25
-
A2
0.077
0.083
1.95
2.10
-
b
0.012
0.018
0.30
0.45
6
b1
0.012
0.016
0.30
0.40
-
D
0.515
0.524
13.08
13.32
3
D1
0.389
0.399
9.88
10.12
4, 5
E
0.516
0.523
13.10
13.30
3
E1
0.390
0.398
9.90
10.10
4, 5
L
0.029
0.040
0.73
1.03
N
44
44
e
0.032 BSC
0.80 BSC
7
Rev. 2 4/99
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI Y14.5M-1982.
b
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.
7. “N” is the number of terminal positions.
BASE METAL
13
MIN
A
3. Dimensions D and E to be determined at seating plane -C- .
b1
WITH PLATING
SYMBOL
D S
0.13/0.17
0.005/0.007
12o-16o
MILLIMETERS
0.13/0.23
0.005/0.009
FN8587.0
October 29, 2013
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