NXP I2C/SPI master bridges SC18IS600/601, SC18IS602/603, and SC18IM700 Connect I2C/SPI slave or UART to I2C/SPI master or GPIO These compact protocol converters create seamless, low-power, low-voltage interface connections, so they make it quick and easy to add I2C/SPI master and GPIO capability to any application that has an I2C/SPI bus or UART host interface. The result is increased design flexibility with reduced complexity and software overhead, and faster time-to-market. SC18IS600/601 features 4 2.4- to 3.6-V operation with 5-V-tolerant I/O pins 4 High-speed SPI bus slave up to 3 Mbps 4 Fast I2C-bus (up to 400 kbps) with multi-master capability 4 Up to four GPIO and two quasibidirectional I/O pins 4 96-byte transmit and receive buffers 4 Power-down mode with a wake-up pin 4 Active-low interrupt output 4 Industrial temperature range (-40 to +85 °C) 4 16-pin TSSOP package SC18IS602/603 features 4 2.4- to 3.6-V operation with 5-V-tolerant I/O pins 4 High-speed SPI bus master up to 4 Mbps 4 Fast I2C bus slave (up to 400 KHz) 4 Up to four slave select outputs 4 Up to four programmable I/O pins 4 200-byte data buffers 4 Low-power mode 4 Active-low interrupt output 4 Industrial temperature range (-40 to +85 °C) 4 16-pin TSSOP package SC18IM700 features 4 2.3- to 3.6-V operation with 5-V-tolerant I/O pins 4 UART host interface with baud rates up to 460.8 kbps 4 Fast I2C-bus (up to 400 kbps) with multi-master capability 4 Up to eight GPIO 4 16-byte transmit and receive FIFOs 4 8N1 RS-232 format 4 Sleep mode (power-down) with a wake-up pin 4 Industrial temperature range (-40 to +85 °C) 4 16-pin TSSOP package Both devices support 2.4- to 3.6-V operation and offer up to four GPIO and two quasi-bidirectional I/O pins. The I/O pins are tolerant to 5 V. Both have 96-byte on-chip transmit and receive buffers, use a wake-up pin to support power-down mode, and provide an active-low interrupt output. They operate in the industrial temperature range and are available in a 16-pin TSSOP package. GPIO0 1 16 IO5 CS 2 15 WAKEUP/IO4 RESET 3 14 INT VSS 4 13 GPIO3 MISO 5 12 VDD MOSI 6 11 SCLK SDA 7 10 GPIO2 SCL 8 9 GPIO1 SC18IS600/601 SC18IS600/601 pinout diagram Smart card A/D D/A I2C ASIC CPU FPGA MCU SPI LCD / LED Sensor SC18IS600 SC18IS601 Status LED GPIO Applications 4 Handheld computers 4 Industrial control / monitoring 4 Telecom / Networking 4 Portable medical equipment 4 Sensor 4 Storage 4 Gaming machines 4 Metering 4 Point of sale 4 Mobile communication 4 Robotic SC18IS600/601 The NXP I2C master bridges SC18IS600 and SC18IS601 let a host with an SPI bus communicate transparently with I2C-bus devices like LCD displays, temperature/voltage sensors, and EEPROM data storage. The I2C-bus controller has multi-master capability, so it can share the bus with a microcontroller or another I2C master. The high-speed SPI bus slave operates at up to 3 Mbps. SPI These low-power bridge ICs simplify design and reduce system cost by making it easy to add devices to an application. They provide an I2C/SPI master interface control to the I2C/SPI bus without a remote host processor. They also provide access to GPIO, so it’s easy to expand the host system to support additional functions: 4 System monitoring 4 Diagnostics 4 LCD display control 4 Fan control 4 LED lighting/blinking 4 Button/keypad press detection 4 Status information 4 EEPROM data storage Fan control Reset signal Push button SC18IS600/601 usage scenario SC18IS602/603 The NXP I2C/SPI master bridges SC18IS602 and SC18IS603 let a host with an I2C bus communicate transparently with SPI-bus devices like LED/LCD displays, temperature/voltage sensors, and EEPROM data storage. The SPI-bus controller can select up to four SPI slave devices. The high-speed SPI bus slave operates at up to 4 Mbps. SC18IM700 The NXP I2C/SPI master bridge SC18IM700 lets a host with an RS-232 connection communicate with remote I2C devices such as temperature sensors, LCD displays, A/D converters, and smart card readers. The same RS-232 connection can also be used to let the host communicate with remote GPIO. Both devices support 2.4- to 3.6-V operation and offer up to four GPIO pins when they are used to select SPI slave devices. The I/O pins are tolerant to 5 V. The device supports 2.3- to 3.6-V operation and offers up to eight GPIO. The UART host interface delivers baud rates up to 460.8 kbps, and the fast I2C-bus, which supports multi-master capability, operates up to 400 kbps. Both have 200-byte on-chip data buffers, support low power mode, and provide active-low interrupt output. They operate in the industrial temperature range and are available in a 16pin TSSOP package. It integrates 16-byte transmit and receive FIFOs, supports the 8N1 RS-232 format, and uses a wake-up pin to support powerdown mode. It operates in the industrial temperature range and is available in a 16-pin TSSOP package. GPIO0 1 16 A2 GPIO0 1 16 GPIO7 GPIO1 2 15 A1 GPIO1 2 15 GPIO4 RESET 3 14 A0 RESET 3 14 GPIO5 13 SS3 (SC18IS602) CLKIN (SC18IS603) VSS 4 13 WAKEUP GND 4 MISO 5 12 VCC GPIO2 5 12 VDD MOSI 6 11 SCLX GPIO3 6 11 GPIO6 SDA 7 10 SS2 SDA 7 10 TX SCL 8 9 INT SCL 8 9 RX SC18IS602/603 SC18IS602/603 pinout diagram SC18IM700 SC18IM700 pinout diagram LCD/ LED SC18IS602 SC18IS603 EE PROM A/D D/A I2C UART UART ASIC CPU FPGA MCU SPI master I2C slave ASIC CPU FPGA MCU I2C master Smart card LCD / LED Sensor SC18IM700 GPIO SPI SS/GPIO Status LED Status LED Push button SC18IS602/603 usage scenario Fan control Reset signal Push button SC18IM700 usage scenario Feature summary Type number SC18IS600IPW SC18IS601IPW SC18IS602IPW SC18IS603IPW SC18IM700IPW SPI speed 1 Mbps 3 Mbps 1.8 Mbps 4 Mbps N/A UART speed N/A N/A N/A N/A 460.8 kbps I2C bus 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz Number of GPIO 4 3 4 3 8 Quasi-bidirectional I/O 2 2 0 0 0 4 3 SPI chip-select pins Clock Internal External Internal External Internal Package TSSOP16 TSSOP16 TSSOP16 TSSOP16 TSSOP16 Dimensions 5.0 x 4.4 x 1.1 mm 5.0 x 4.4 x 1.1 mm 5.0 x 4.4 x 1.1 mm 5.0 x 4.4 x 1.1 mm 5.0 x 4.4 x 1.1 mm For more information, please visit: www.nxp.com/interface For technical support, please send questions to: [email protected] www.nxp.com © 2006 NXP N.V. All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The Date of release: November 2006 information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and Document order number: 9397 750 15763 may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof Printed in the USA does not convey nor imply any license under patent- or other industrial or intellectual property rights.