Data Sheet

PCA9534
8-bit I2C-bus and SMBus low power I/O port with interrupt
Rev. 03 — 6 November 2006
Product data sheet
1. General description
The PCA9534 is a 16-pin CMOS device that provide 8 bits of General Purpose parallel
Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to
enhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvements
include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O
configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a
simple solution when additional I/O is needed for ACPI power switches, sensors,
push buttons, LEDs, fans, etc.
The PCA9534 consists of an 8-bit Configuration register (Input or Output selection); 8-bit
Input register, 8-bit Output register and an 8-bit Polarity Inversion register (active HIGH or
active LOW operation). The system master can enable the I/Os as either inputs or outputs
by writing to the I/O configuration bits. The data for each input or output is kept in the
corresponding Input or Output register. The polarity of the Input Port register can be
inverted with the Polarity Inversion register. All registers can be read by the system
master. Although pin-to-pin and I2C-bus address compatible with the PCF8574 series,
software changes are required due to the enhancements and are discussed in Application
Note AN469.
The PCA9534 is identical to the PCA9554 except for the removal of the internal I/O pull-up
resistor which greatly reduces power consumption when the I/Os are held LOW.
The PCA9534 open-drain interrupt output is activated when any input state differs from its
corresponding input port register state and is used to indicate to the system master that
an input state has changed. The power-on reset sets the registers to their default values
and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I2C-bus address and allow up to eight
devices to share the same I2C-bus/SMBus.
2. Features
n
n
n
n
n
n
n
n
n
8-bit I2C-bus GPIO
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant I/Os
Polarity Inversion register
Active LOW interrupt output
Low standby current
Noise filter on SCL/SDA inputs
No glitch on power-up
Internal power-on reset
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
n 8 I/O pins which default to 8 inputs
n 0 Hz to 400 kHz clock frequency
n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
n Offered in four different packages: SO16, TSSOP16, and HVQFN16 (4 × 4 × 0.85 mm
and 3 × 3 × 0.85 mm versions)
3. Ordering information
Table 1.
Ordering information
Tamb = −40 °C to +85 °C.
Type number
Topside
mark
Package
Name
Description
Version
PCA9534D
PCA9534D
SO16
plastic small outline package; 16 leads; body width 7.5 mm
SOT162-1
PCA9534PW
PCA9534
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
PCA9534BS
9534
HVQFN16
plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 4 × 4 × 0.85 mm
SOT629-1
PCA9534BS3
P34
HVQFN16
plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 3 × 3 × 0.85 mm
SOT758-1
4. Block diagram
PCA9534
A0
A1
A2
IO0
IO1
8-bit
SCL
SDA
INPUT
FILTER
I2C-BUS/SMBus
CONTROL
write pulse
VDD
IO2
INPUT/
OUTPUT
PORTS
IO3
IO4
IO5
IO6
read pulse
POWER-ON
RESET
IO7
VDD
VSS
INT
LP
FILTER
002aac469
All I/Os are set to inputs at reset.
Fig 1. Block diagram of PCA9534
PCA9534_3
Product data sheet
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Rev. 03 — 6 November 2006
2 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
5. Pinning information
5.1 Pinning
A0
1
A1
2
16 VDD
15 SDA
A0
1
A1
2
16 VDD
15 SDA
14 SCL
A2
3
14 SCL
A2
3
IO0
4
13 INT
IO0
4
IO1
5
12 IO7
IO1
5
IO2
6
11 IO6
IO2
6
11 IO6
IO3
7
10 IO5
IO3
7
10 IO5
VSS
8
9
VSS
8
IO4
IO0
2
12 SCL
A2
1
11 INT
IO0
2
13 SDA
16 A1
terminal 1
index area
15 A0
Fig 3. Pin configuration for TSSOP16
13 SDA
14 VDD
15 A0
16 A1
1
IO4
002aac466
Fig 2. Pin configuration for SO16
A2
12 IO7
9
002aac465
terminal 1
index area
13 INT
PCA9534PW
14 VDD
PCA9534D
12 SCL
11 INT
PCA9534BS
PCA9534BS3
Transparent top view
6
7
8
VSS
IO4
IO5
002aac467
5
9
IO6
IO3
4
8
IO2
IO5
IO2
7
10 IO7
6
3
9
IO4
IO1
4
VSS
10 IO7
5
3
IO3
IO1
IO6
002aac468
Transparent top view
Fig 4. Pin configuration for HVQFN16
(SOT629-1; 4 × 4 × 0.85 mm)
Fig 5. Pin configuration for HVQFN16
(SOT758-1; 3 × 3 × 0.85 mm)
5.2 Pin description
Table 2.
Symbol
Pin description
Pin
Description
SO16, TSSOP16
HVQFN16
A0
1
15
address input 0
A1
2
16
address input 1
A2
3
1
address input 2
IO0
4
2
input/output 0
IO1
5
3
input/output 1
IO2
6
4
input/output 2
IO3
7
5
input/output 3
VSS
8
6[1]
ground supply voltage
IO4
9
7
input/output 4
IO5
10
8
input/output 5
PCA9534_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
3 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
Table 2.
Symbol
Pin description …continued
Pin
Description
SO16, TSSOP16
HVQFN16
IO6
11
9
input/output 6
IO7
12
10
input/output 7
INT
13
11
interrupt output (open-drain)
SCL
14
12
serial clock line
SDA
15
13
serial data line
VDD
16
14
supply voltage
[1]
HVQFN package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be
connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level
performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the
board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in
the thermal pad region.
6. Functional description
Refer to Figure 1 “Block diagram of PCA9534”.
6.1 Registers
6.1.1 Command byte
Table 3.
Command byte
Command
Protocol
Function
0
read byte
Input Port register
1
read/write byte
Output Port register
2
read/write byte
Polarity Inversion register
3
read/write byte
Configuration register
The command byte is the first byte to follow the address byte during a write transmission.
It is used as a pointer to determine which of the following registers will be written or read.
6.1.2 Register 0 - Input Port register
This register is a read-only port. It reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by Register 3. Writes to this register
have no effect.
The default ‘X’ is determined by the externally applied logic level.
PCA9534_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
4 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
Table 4.
Register 0 - Input Port register bit description
Bit
Symbol
Access
Value
Description
7
I7
read only
X
determined by externally applied logic level
6
I6
read only
X
5
I5
read only
X
4
I4
read only
X
3
I3
read only
X
2
I2
read only
X
1
I1
read only
X
0
I0
read only
X
6.1.3 Register 1 - Output Port register
This register reflects the outgoing logic levels of the pins defined as outputs by Register 3.
Bit values in this register have no effect on pins defined as inputs. Reads from this register
return the value that is in the flip-flop controlling the output selection, not the actual pin
value.
Table 5.
Register 1 - Output Port register bit description
Legend: * default value.
Bit
Symbol
Access
Value
Description
7
6
O7
R
1*
O6
R
1*
reflects outgoing logic levels of pins defined as
outputs by Register 3
5
O5
R
1*
4
O4
R
1*
3
O3
R
1*
2
O2
R
1*
1
O1
R
1*
0
O0
R
1*
6.1.4 Register 2 - Polarity Inversion register
This register allows the user to invert the polarity of the Input Port register data. If a bit in
this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in
this register is cleared (written with a ‘0’), the Input Port data polarity is retained.
Table 6.
Register 2 - Polarity Inversion register bit description
Legend: * default value.
Bit
Symbol
Access
Value
Description
7
N7
R/W
0*
inverts polarity of Input Port register data
6
N6
R/W
0*
0 = Input Port register data retained (default value)
5
N5
R/W
0*
1 = Input Port register data inverted
4
N4
R/W
0*
3
N3
R/W
0*
2
N2
R/W
0*
1
N1
R/W
0*
0
N0
R/W
0*
PCA9534_3
Product data sheet
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Rev. 03 — 6 November 2006
5 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
6.1.5 Register 3 - Configuration register
This register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in
this register is cleared, the corresponding port pin is enabled as an output. At reset, the
I/Os are configured as inputs.
Table 7.
Register 3 - Configuration register bit description
Legend: * default value.
Bit
Symbol
Access
Value
Description
7
C7
R/W
1*
configures the directions of the I/O pins
6
C6
R/W
1*
0 = corresponding port pin enabled as an output
5
C5
R/W
1*
4
C4
R/W
1*
1 = corresponding port pin configured as input
(default value)
3
C3
R/W
1*
2
C2
R/W
1*
1
C1
R/W
1*
0
C0
R/W
1*
6.2 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9534 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA9534 registers and state machine will initialize to their default states.
Thereafter, VDD must be lowered below 0.2 V to reset the device.
For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the
operating voltage.
6.3 Interrupt output
The open-drain interrupt output is activated when one of the port pins change state and
the pin is configured as an input. The interrupt is deactivated when the input returns to its
previous state or the Input Port register is read.
Note that changing an I/O from and output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register.
6.4 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the
state of the Output Port register. Care should be exercised if an external voltage is applied
to an I/O configured as an output because of the low-impedance paths that exist between
the pin and either VDD or VSS.
PCA9534_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
6 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
data from
shift register
output port
register data
configuration
register
data from
shift register
D
VDD
Q1
Q
FF
write configuration
pulse
CK
D
Q
Q
FF
IO0 to IO7
write pulse
CK
Q2
output port
register
VSS
input port
register
D
Q
input port
register data
FF
read pulse
CK
to INT
polarity inversion
register
data from
shift register
D
polarity inversion
register data
Q
FF
write polarity
pulse
CK
002aac470
Remark: At power-on reset, all registers return to default values.
Fig 6. Simplified schematic of IO0 to IO7
6.5 Device address
slave address
0
1
0
0
fixed
A2
A1
A0 R/W
hardware
selectable
002aac471
Fig 7. PCA9534 device address
6.6 Bus transactions
Data is transmitted to the PCA9534 registers using the Write mode as shown in Figure 8
and Figure 9. Data is read from the PCA9534 registers using the Read mode as shown in
Figure 10 and Figure 11. These devices do not implement an auto-increment function, so
once a command byte has been sent, the register which was addressed will continue to
be accessed by reads until a new command byte has been sent.
PCA9534_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
7 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
SCL
1
2
3
4
5
6
7
8
9
slave address
SDA S
0
1
0
command byte
0 A2 A1 A0 0
START condition
A
0
0
0
0
0
0
data to port
0
1
A
acknowledge
from slave
R/W
acknowledge
from slave
A
DATA 1
P
STOP
condition
acknowledge
from slave
write to port
tv(Q)
data out
from port
data 1 valid
002aac472
Fig 8. Write to Output Port register
SCL
1
2
3
4
5
6
7
8
9
slave address
SDA S
0
1
0
command byte
0 A2 A1 A0 0
START condition
A
0
0
0
0
0
1 1/0 A
acknowledge
from slave
R/W
acknowledge
from slave
data to
register
0
data to register
A
DATA
P
STOP
condition
acknowledge
from slave
002aac473
Fig 9. Write to Configuration register or Polarity Inversion register
slave address
SDA S
0
1
0
0 A2 A1 A0 0
START condition
A
acknowledge
from slave
R/W
acknowledge
from slave
data from register
slave address
(cont.) S
0
1
0
0 A2 A1 A0 1
(repeated)
START condition
(cont.)
A
command byte
A
R/W
acknowledge
from slave
DATA (first byte)
data from register
A
acknowledge
from master
DATA (last byte)
NA
no acknowledge
from master
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
P
STOP
condition
002aac474
Fig 10. Read from register
PCA9534_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
8 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
SCL
1
2
3
4
5
6
7
8
9
slave address
SDA S
0
1
0
data from port
0 A2 A1 A0 1
START condition
DATA 1
A
A
DATA 2
tv(INT_N)
NA P
no acknowledge
from master
STOP
condition
tsu(D)
th(D)
data into
port
DATA 4
acknowledge
from master
R/W
acknowledge
from slave
read from
port
data from port
DATA 3
DATA 4
trst(INT_N)
INT
002aac475
This figure assumes the command byte has previously been programmed with 00h.
Transfer of data can be stopped at any moment by a STOP condition.
Fig 11. Read Input Port register
PCA9534_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
9 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
7. Application design-in information
5V
VDD (5 V)
10 kΩ
10 kΩ
10 kΩ
2 kΩ
10 kΩ
VDD
100 kΩ
(× 3)
VDD
MASTER
CONTROLLER
SCL
SCL
IO0
SUBSYSTEM 1
(e.g., temp. sensor)
SDA
SDA
IO1
INT
INT
INT
PCA9534
IO2
RESET
IO3
SUBSYSTEM 2
(e.g., counter)
IO4
VSS
IO5
A
IO6
IO7
A2
controlled switch
(e.g., CBT device)
enable
A1
B
A0
VSS
ALARM
SUBSYSTEM 3
(e.g., alarm system)
VDD
002aac476
Device address configured as 0100 100X for this example.
IO0, IO1, IO2 configured as outputs.
IO3, IO4, IO5 configured as inputs.
IO6, IO7 are not used and must be configured as outputs.
Fig 12. Typical application
7.1 Minimizing IDD when the I/O us used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to VDD through a
resistor as shown in Figure 12. Since the LED acts as a diode, when the LED is off the
I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes
lower than VDD.
Designs needing to minimize current consumption, such as battery power applications,
should consider maintaining the IOn pins greater than or equal to VDD when the LED is
off. Figure 13 shows a high value resistor in parallel with the LED. Figure 14 shows VDD
less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the
I/O VI at or above VDD and prevents additional supply current consumption when the LED
is off.
PCA9534_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
10 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
3.3 V
VDD
VDD
VDD
100 kΩ
LED
IOn
5V
LED
IOn
002aac660
002aac661
Fig 13. High value resistor in parallel with
the LED
Fig 14. Device supplied by a lower voltage
8. Limiting values
Table 8.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
II
Conditions
Min
Max
Unit
supply voltage
−0.5
+6.0
V
input current
-
±20
mA
VI/O
voltage on an input/output pin
VSS − 0.5
5.5
V
IO(IOn)
output current on pin IOn
-
±50
mA
IDD
supply current
-
85
mA
ISS
ground supply current
-
100
mA
Ptot
total power dissipation
-
200
mW
Tstg
storage temperature
−65
+150
°C
Tamb
ambient temperature
−40
+85
°C
PCA9534_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
11 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
9. Static characteristics
Table 9.
Static characteristics
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.3
-
5.5
V
-
104
175
µA
-
0.25
1
µA
-
0.25
1
µA
-
1.5
1.65
V
Supplies
VDD
supply voltage
IDD
supply current
operating mode; VDD = 5.5 V;
no load; fSCL = 100 kHz
Istb
standby current
Standby mode; VDD = 5.5 V; no load;
fSCL = 0 kHz; I/O = inputs
VI = VSS
VI = VDD
VPOR
power-on reset voltage
no load; VI = VDD or VSS
[1]
Input SCL; input/output SDA
VIL
LOW-level input voltage
−0.5
-
+0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
IOL
LOW-level output current
VOL = 0.4 V
3
6
-
mA
IL
leakage current
VI = VDD = VSS
−1
-
+1
µA
Ci
input capacitance
VI = VSS
-
5
10
pF
−0.5
-
+0.8
V
I/Os
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
IOL
LOW-level output current
VOH
HIGH-level output voltage
ILI
input leakage current
Ci
input capacitance
2.0
-
5.5
V
VOL = 0.5 V; VDD = 2.3 V
[2]
8
10
-
mA
VOL = 0.7 V; VDD = 2.3 V
[2]
10
13
-
mA
VOL = 0.5 V; VDD = 3.0 V
[2]
8
14
-
mA
VOL = 0.7 V; VDD = 3.0 V
[2]
10
19
-
mA
VOL = 0.5 V; VDD = 4.5 V
[2]
8
17
-
mA
VOL = 0.7 V; VDD = 4.5 V
[2]
10
24
-
mA
IOH = −8 mA; VDD = 2.3 V
[3]
1.8
-
-
V
IOH = −10 mA; VDD = 2.3 V
[3]
1.7
-
-
V
IOH = −8 mA; VDD = 3.0 V
[3]
2.6
-
-
V
IOH = −10 mA; VDD = 3.0 V
[3]
2.5
-
-
V
IOH = −8 mA; VDD = 4.75 V
[3]
4.1
-
-
V
IOH = −10 mA; VDD = 4.75 V
[3]
4.0
-
-
V
−1
-
+1
µA
-
5
10
pF
3
-
-
mA
VI = VDD = VSS
Interrupt INT
IOL
LOW-level output current
VOL = 0.4 V
Select inputs A0, A1, A2
VIL
LOW-level input voltage
−0.5
-
0.8
V
VIH
HIGH-level input voltage
2.0
-
5.5
V
ILI
input leakage current
−1
-
1
µA
PCA9534_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
12 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
[1]
VDD must be lowered to 0.2 V in order to reset part.
[2]
Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
[3]
The total current sourced by all I/Os must be limited to 85 mA.
10. Dynamic characteristics
Table 10.
Dynamic characteristics
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode I2C-bus
Min
Max
Min
Max
0
100
0
400
Unit
fSCL
SCL clock frequency
kHz
tBUF
bus free time between a STOP and
START condition
4.7
-
1.3
-
µs
tHD;STA
hold time (repeated) START condition
4.0
-
0.6
-
µs
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
µs
tSU;STO
set-up time for STOP condition
4.0
-
0.6
-
µs
tHD;DAT
data hold time
0
-
0
-
µs
data valid acknowledge time
[1]
0.3
3.45
0.1
0.9
µs
tVD;DAT
data valid time
[2]
300
-
50
-
ns
tSU;DAT
data set-up time
250
-
100
-
ns
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
µs
tHIGH
HIGH period of the SCL clock
4.0
-
0.6
tVD:ACK
-
µs
0.1Cb[3]
tr
rise time of both SDA and SCL signals
-
1000
20 +
300
ns
tf
fall time of both SDA and SCL signals
-
300
20 + 0.1Cb[3]
300
µs
tSP
pulse width of spikes that must be
suppressed by the input filter
-
50
-
50
ns
tv(Q)
data output valid time
-
200
-
200
ns
tsu(D)
data input setup time
100
-
100
-
ns
th(D)
data input hold time
1
-
1
-
µs
Port timing
Interrupt timing
tv(INT_N)
valid time on pin INT
-
4
-
4
µs
trst(INT_N)
reset time on pin INT
-
4
-
4
µs
[1]
tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2]
tVD;DAT = minimum time for SDA data output to be valid following SCL LOW.
[3]
Cb = total capacitance of one bus line in pF.
PCA9534_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
13 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
SDA
tr
tBUF
tf
tHD;STA
tSP
tLOW
SCL
tHD;STA
P
tSU;STA
tHD;DAT
S
tHIGH
tSU;DAT
tSU;STO
Sr
P
002aaa986
Fig 15. Definition of timing
protocol
START
condition
(S)
tSU;STA
bit 7
MSB
(A7)
tLOW
bit 6
(A6)
tHIGH
bit 0
(R/W)
acknowledge
(A)
STOP
condition
(P)
1/f
SCL
SCL
tBUF
tr
tf
SDA
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
002aab175
Rise and fall times refer to VIL and VIH.
Fig 16. I2C-bus timing diagram
PCA9534_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
14 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
11. Test information
VDD
PULSE
GENERATOR
VI
RL
500 Ω
VO
6.0 V
open
VSS
D.U.T.
CL
50 pF
RT
002aab393
RL = load resistor.
CL = load capacitance includes jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse
generators.
Fig 17. Test circuitry for switching times
500 Ω
from output
under test
CL
50 pF
S1
2VDD
open
VSS
500 Ω
002aab881
Fig 18. Test circuit
Table 11.
Test
tv(Q)
Test data
Load
Switch
CL
RL
50 pF
500 Ω
PCA9534_3
Product data sheet
2VDD
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
15 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
12. Package outline
SO16: plastic small outline package; 16 leads; body width 7.5 mm
SOT162-1
D
E
A
X
c
HE
y
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
8
1
e
detail X
w M
bp
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.32
0.23
10.5
10.1
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.01
0.019 0.013
0.014 0.009
0.41
0.40
0.30
0.29
0.05
0.419
0.043
0.055
0.394
0.016
inches
0.1
0.012 0.096
0.004 0.089
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT162-1
075E03
MS-013
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 19. Package outline SOT162-1 (SO16)
PCA9534_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
16 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
MO-153
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 20. Package outline SOT403-1 (TSSOP16)
PCA9534_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
17 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 4 x 4 x 0.85 mm
A
B
D
SOT629-1
terminal 1
index area
A A
1
E
c
detail X
e1
C
1/2 e
e
8
y
y1 C
v M C A B
w M C
b
5
L
9
4
e
e2
Eh
1/2 e
1
12
terminal 1
index area
16
13
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A(1)
max.
A1
b
1
0.05
0.00
0.38
0.23
c
D (1)
Dh
E (1)
Eh
0.2
4.1
3.9
2.25
1.95
4.1
3.9
2.25
1.95
e
e1
0.65
1.95
e2
L
v
w
y
y1
1.95
0.75
0.50
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT629-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
01-08-08
02-10-22
Fig 21. Package outline SOT629-1 (HVQFN16)
PCA9534_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
18 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3 x 3 x 0.85 mm
A
B
D
SOT758-1
terminal 1
index area
A
E
A1
c
detail X
e1
C
1/2 e
e
5
y
y1 C
v M C A B
w M C
b
8
L
4
9
e
e2
Eh
1/2 e
12
1
16
terminal 1
index area
13
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A(1)
max.
A1
b
1
0.05
0.00
0.30
0.18
c
D (1)
Dh
E (1)
Eh
0.2
3.1
2.9
1.75
1.45
3.1
2.9
1.75
1.45
e
e1
1.5
0.5
e2
L
v
w
y
y1
1.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT758-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
02-03-25
02-10-21
Fig 22. Package outline SOT758-1 (HVQFN16)
PCA9534_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
19 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
13. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling.
However, to be completely safe you must take normal precautions appropriate to handling
integrated circuits.
14. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus PbSn soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
PCA9534_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
20 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 23) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 12 and 13
Table 12.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 13.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 23.
PCA9534_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
21 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 23. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. Abbreviations
Table 14.
Abbreviations
Acronym
Description
ACPI
Advanced Configuration and Power Interface
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
FET
Field-Effect Transistor
GPIO
General Purpose Input/Output
HBM
Human Body Model
I2C-bus
Inter-Integrated Circuit bus
I/O
Input/Output
LED
Light-Emitting Diode
MM
Machine Model
POR
Power-On Reset
SMBus
System Management Bus
PCA9534_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
22 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
16. Revision history
Table 15.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9534_3
20061106
Product data sheet
-
PCA9534_2
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
•
•
•
•
•
•
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
•
•
pin names I/O0 through I/O7 changed to IO0 through IO7
added HVQFN16 (SOT758-1) package
symbol (tpv and tPV) changed to tv(Q)
symbol (tph and tPH) changed to th(D)
symbol (tps and tPS) changed to tsu(D)
symbol (tiv and tIV) changed to tv(INT_N)
symbol (tir and tIR) changed to trst(INT_N)
Figure 6 “Simplified schematic of IO0 to IO7”: removed ESD diodes
Table 8 “Limiting values”: symbol “II/O, DC output current on an I/O” changed to “IO(IOn), output
current on pin IOn”
Table 9 “Static characteristics”, sub-section “I/Os”: symbol IIL changed to ILI
added Section 15 “Abbreviations”
PCA9534_2
(9397 750 13506)
20040930
Product data sheet
-
PCA9534_1
PCA9534_1
(9397 750 12454)
20031202
Product data
ECN 853-2319 01-A14517
of 14 Nov 2003
-
PCA9534_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
23 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
17.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
18. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
PCA9534_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 6 November 2006
24 of 25
PCA9534
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt
19. Contents
1
2
3
4
5
5.1
5.2
6
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
6.5
6.6
7
7.1
8
9
10
11
12
13
14
14.1
14.2
14.3
14.4
15
16
17
17.1
17.2
17.3
17.4
18
19
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 4
Register 0 - Input Port register . . . . . . . . . . . . . 4
Register 1 - Output Port register. . . . . . . . . . . . 5
Register 2 - Polarity Inversion register . . . . . . . 5
Register 3 - Configuration register . . . . . . . . . . 6
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6
Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 6
I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device address . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 7
Application design-in information . . . . . . . . . 10
Minimizing IDD when the I/O us used to
control LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11
Static characteristics. . . . . . . . . . . . . . . . . . . . 12
Dynamic characteristics . . . . . . . . . . . . . . . . . 13
Test information . . . . . . . . . . . . . . . . . . . . . . . . 15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Handling information. . . . . . . . . . . . . . . . . . . . 20
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Introduction to soldering . . . . . . . . . . . . . . . . . 20
Wave and reflow soldering . . . . . . . . . . . . . . . 20
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 20
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 21
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 23
Legal information. . . . . . . . . . . . . . . . . . . . . . . 24
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Contact information. . . . . . . . . . . . . . . . . . . . . 24
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2006.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 6 November 2006
Document identifier: PCA9534_3
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