dsPIC33FJ32GS406 DATA SHEET (07/14/2014) DOWNLOAD

dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610
16-Bit Digital Signal Controllers with High-Speed PWM,
ADC and Comparators
Operating Conditions
Timers/Output Compare/Input Capture
• 3.0V to 3.6V, -40ºC to +85ºC, DC to 50 MIPS
• 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS
• Six General Purpose Timers:
- Five 16-bit and up to two 32-bit timers/counters
• Four Output Compare (OC) modules Configurable as
Timers/Counters
• Quadrature Encoder Interface (QEI) module
Configurable as Timer/Counter
• Four Input Capture (IC) modules
Core: 16-Bit dsPIC33F
•
•
•
•
•
Code-Efficient (C and Assembly) Architecture
Two 40-Bit Wide Accumulators
Single-Cycle (MAC/MPY) with Dual Data Fetch
Single-Cycle Mixed-Sign MUL plus Hardware Divide
32-Bit Multiply Support
Clock Management
•
•
•
•
•
±1% Internal Oscillator
Programmable PLLs and Oscillator Clock Sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer (WDT)
Fast Wake-up and Start-up
Power Management
•
•
•
•
Low-Power Management modes (Sleep, Idle, Doze)
Integrated Power-on Reset and Brown-out Reset
1.7 mA/MHz Dynamic Current (typical)
50 µA IPD Current (typical)
High-Speed PWM
•
•
•
•
Up to 9 PWM Pairs with Independent Timing
Dead Time for Rising and Falling Edges
1.04 ns PWM Resolution
PWM Support for:
- DC/DC, AC/DC, Inverters, PFC, Lighting
- BLDC, PMSM, ACIM, SRM
• Programmable Fault Inputs
• Flexible Trigger Configurations for ADC Conversions
Advanced Analog Features
• High-Speed ADC module:
- 10-bit resolution with up to two Successive
Approximation Register (SAR) converters
(up to 4 Msps)
- Up to 24 input channels grouped into
12 conversion pairs plus two voltage reference
monitoring inputs
- Dedicated result buffer for each analog channel
• Flexible and Independent ADC Trigger Sources
• Up to 4 High-Speed Comparators with Direct
Connection to the PWM module:
- 10-bit Digital-to-Analog Converter (DAC) for each
comparator
- DAC reference output
- Programmable references with 1024 voltage points
 2009-2014 Microchip Technology Inc.
Communication Interfaces
• Two UART modules (12.5 Mbps):
- With support for LIN/J2602 2.0 protocols and IrDA®
• Two 4-Wire SPI modules (15 Mbps)
• ECAN™ module (1 Mbaud) with ECAN 2.0B Support
• Two I2C™ modules (up to 1 Mbaud) with SMBus
Support
Direct Memory Access (DMA)
• 4-Channel DMA with User-Selectable Priority
Arbitration
• UART, SPI, ECAN, IC, OC and Timers
Input/Output
• Sink/Source 18 mA on 18 Pins, 10 mA on 1 Pin or
6 mA on 66 Pins
• 5V Tolerant Pins
• Selectable Open-Drain and Pull-ups
• 29 External Interrupts
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1, -40ºC to +125ºC)
• Class B Safety Library, IEC 60730, VDE Certified
Debugger Development Support
•
•
•
•
In-Circuit and In-Application Programming
Two Program and Two Complex Data Breakpoints
IEEE 1149.2 Compatible (JTAG) Boundary Scan
Trace and Run-Time Watch
DS7000591F-page 1
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610
PRODUCT FAMILIES
The device names, pin counts, memory sizes and
peripheral availability of each device are listed in Table 1.
The following pages show their pinout diagrams.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
CONTROLLER FAMILIES
Program Flash Memory (Kbytes)
RAM (Bytes)
16-Bit Timers
Input Capture
Output Compare
UART
Quadrature Encoder Interfaces
SPI
ECAN™
DMA Channels
PWM
Analog Comparators
External Interrupts
DAC Output
I2C™
SARs
Sample-and-Hold (S&H) Circuits
Analog-to-Digital Inputs
I/O Pins
Packages
ADC
Pins
TABLE 1:
dsPIC33FJ32GS406 64
32
4K
5
4
4
2
1
2
0
0
6x2
0
5
0
2
1
5
16
58
PT,
MR
dsPIC33FJ32GS606 64
32
4K
5
4
4
2
2
2
0
0
6x2
4
5
1
2
2
6
16
58
PT,
MR
dsPIC33FJ32GS608 80
32
4K
5
4
4
2
2
2
0
0
8x2
4
5
1
2
2
6
18
74
PT
dsPIC33FJ32GS610 100 32
4K
5
4
4
2
2
2
0
0
9x2
4
5
1
2
2
6
24
85
PT,
PF
dsPIC33FJ64GS406 64
64
8K
5
4
4
2
1
2
0
0
6x2
0
5
0
2
1
5
16
58
PT,
MR
dsPIC33FJ64GS606 64
64
9K(1)
5
4
4
2
2
2
1
4
6x2
4
5
1
2
2
6
16
58
PT,
MR
dsPIC33FJ64GS608 80
64
9K(1)
5
4
4
2
2
2
1
4
8x2
4
5
1
2
2
6
18
74
PT
dsPIC33FJ64GS610 100 64
9K(1)
5
4
4
2
2
2
1
4
9x2
4
5
1
2
2
6
24
85
PT,
PF
Device
Note 1:
RAM size is inclusive of 1-Kbyte DMA RAM.
DS7000591F-page 2
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Pin Diagrams
64-Pin TQFP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM1H/RE1
PWM1L/FLT8/RE0
RF1
SYNCI4/RF0
VDD
VCAP
PWM5H/UPDN1/CN16/RD7
PWM5L/CN15/RD6
PWM6H/CN14/RD5
PWM6L/CN13/RD4
OC4/SYNCO1/RD3
OC3/FLT7/RD2
OC2/SYNCO2/FLT6/RD1
= Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33FJ32GS406
dsPIC33FJ64GS406
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/QEB1/FLT5/RD0
IC4/QEA1/FLT4/INT4/RD11
IC3/INDX1/FLT3/INT3/RD10
IC2/FLT2/U1CTS/INT2/RD9
IC1/FLT1/SYNCI1/INT1/RD8
VSS
OSC2/REFCLKO/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
AVDD
AVSS
AN8/U2CTS/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
AN14/SS1/U2RTS/RB14
AN15/CN12/RB15
U2RX/SDA2/FLT17/CN17/RF4
U2TX/SCL2/FLT18/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SCK2/FLT12/CN8/RG6
SDI2/FLT11/CN9/RG7
SDO2/FLT10/CN10/RG8
MCLR
SS2/FLT9/SYNCI2/CN11/RG9
VSS
VDD
AN5/AQEB1/CN7/RB5
AN4/AQEA1/CN6/RB4
AN3/AINDX1/CN5/RB3
AN2/ASS1/CN4/RB2
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
 2009-2014 Microchip Technology Inc.
DS7000591F-page 3
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM1H/RE1
PWM1L/FLT8/RE0
RF1
SYNCI4/RF0
VDD
VCAP
PWM5H/UPDN1/CN16/RD7
PWM5L/CN15/RD6
PWM6H/CN14/RD5
PWM6L/CN13/RD4
OC4/SYNCO1/RD3
OC3/FLT7/RD2
OC2/SYNCO2/FLT6/RD1
64-Pin QFN
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SCK2/FLT12/CN8/RG6
SDI2/FLT11/CN9/RG7
SDO2/FLT10/CN10/RG8
MCLR
SS2/FLT9/SYNCI2/CN11/RG9
VSS
VDD
AN5/AQEB1/CN7/RB5
AN4/AQEA1/CN6/RB4
AN3/AINDX1/CN5/RB3
AN2/ASS1/CN4/RB2
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33FJ32GS406
dsPIC33FJ64GS406
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/QEB1/FLT5/RD0
IC4/QEA1/FLT4/INT4/RD11
IC3/INDX1/FLT3/INT3/RD10
IC2/FLT2/U1CTS/INT2/RD9
IC1/FLT1/SYNCI1/INT1/RD8
VSS
OSC2/REFCLKO/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
AVDD
AVss
AN8/U2CTS/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
AN14/SS1/U2RTS/RB14
AN15/CN12/RB15
U2RX/SDA2/FLT17/CN17/RF4
U2TX/SCL2/FLT18/CN18/RF5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
DS7000591F-page 4
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Pin Diagrams (Continued)
64-Pin TQFP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM1H/RE1
PWM1L/FLT8/RE0
RF1
SYNCI4/RF0
VDD
VCAP
PWM5H/UPDN1/CN16/RD7
PWM5L/CN15/RD6
PWM6H/CN14/RD5
PWM6L/CN13/RD4
OC4/SYNCO1/RD3
OC3/FLT7/RD2
OC2/SYNCO2/FLT6/RD1
= Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33FJ32GS606
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/QEB1/FLT5/RD0
IC4/QEA1/FLT4/INT4/RD11
IC3/INDX1/FLT3/INT3/RD10
IC2/FLT2/U1CTS/INT2/RD9
IC1/FLT1/SYNCI1/INT1/RD8
VSS
OSC2/REFCLKO/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/CMP3C/CMP4A/OCFA/RB6
PGED1/AN7/CMP4B/RB7
AVDD
AVSS
AN8/U2CTS/RB8
AN9/DACOUT/RB9
TMS/AN10/INDX2/RB10
TDO/AN11/EXTREF/RB11
VSS
VDD
TCK/AN12/CMP1D/RB12
TDI/AN13/CMP2D/RB13
AN14/CMP3D/SS1/U2RTS/RB14
AN15/CMP4D/CN12/RB15
U2RX/SDA2/QEA2/FLT17/CN17/RF4
U2TX/SCL2/QEB2/FLT18/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SCK2/FLT12/CN8/RG6
SDI2/FLT11/CN9/RG7
SDO2/FLT10/CN10/RG8
MCLR
SS2/FLT9/SYNCI2/T5CK/CN11/RG9
VSS
VDD
AN5/CMP3B/AQEB1/CN7/RB5
AN4/CMP2C/CMP3A/AQEA1/CN6/RB4
AN3/CMP2B/AINDX1/CN5/RB3
AN2/CMP1C/CMP2A/ASS1/CN4/RB2
PGEC3/AN1/CMP1B/CN3/RB1
PGED3/AN0/CMP1A/CMP4C/CN2/RB0
 2009-2014 Microchip Technology Inc.
DS7000591F-page 5
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Pin Diagrams (Continued)
64-Pin TQFP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM1H/RE1
PWM1L/FLT8/RE0
C1TX/RF1
C1RX/SYNCI4/RF0
VDD
VCAP
PWM5H/UPDN1/CN16/RD7
PWM5L/CN15/RD6
PWM6H/CN14/RD5
PWM6L/CN13/RD4
OC4/SYNCO1/RD3
OC3/FLT7/RD2
OC2/SYNCO2/FLT6/RD1
= Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33FJ64GS606
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/QEB1/FLT5/RD0
IC4/QEA1/FLT4/INT4/RD11
IC3/INDX1/FLT3/INT3/RD10
IC2/FLT2/U1CTS/INT2/RD9
IC1/FLT1/SYNCI1/INT1/RD8
VSS
OSC2/REFCLKO/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/CMP3C/CMP4A/OCFA/RB6
PGED1/AN7/CMP4B/RB7
AVDD
AVSS
AN8/U2CTS/RB8
AN9/DACOUT/RB9
TMS/AN10/INDX2/RB10
TDO/AN11/EXTREF/RB11
VSS
VDD
TCK/AN12/CMP1D/RB12
TDI/AN13/CMP2D/RB13
AN14/CMP3D/SS1/U2RTS/RB14
AN15/CMP4D/CN12/RB15
U2RX/SDA2/QEA2/FLT17/CN17/RF4
U2TX/SCL2/QEB2/FLT18/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SCK2/FLT12/CN8/RG6
SDI2/FLT11/CN9/RG7
SDO2/FLT10/CN10/RG8
MCLR
SS2/FLT9/SYNCI2/T5CK/CN11/RG9
VSS
VDD
AN5/CMP3B/AQEB1/CN7/RB5
AN4/CMP2C/CMP3A/AQEA1/CN6/RB4
AN3/CMP2B/AINDX1/CN5/RB3
AN2/CMP1C/CMP2A/ASS1/CN4/RB2
PGEC3/AN1/CMP1B/CN3/RB1
PGED3/AN0/CMP1A/CMP4C/CN2/RB0
DS7000591F-page 6
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM1H/RE1
PWM1L/FLT8/RE0
RF1
SYNCI4/RF0
VDD
VCAP
PWM5H/UPDN1/CN16/RD7
PWM5L/CN15/RD6
PWM6H/CN14/RD5
PWM6L/CN13/RD4
OC4/SYNCO1/RD3
OC3/FLT7/RD2
OC2/SYNCO2/FLT6/RD1
64-Pin QFN
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SCK2/FLT12/CN8/RG6
SDI2/FLT11/CN9/RG7
SDO2/FLT10/CN10/RG8
MCLR
SS2/FLT9/SYNCI2/T5CK/CN11/RG9
VSS
VDD
AN5/CMP3B/AQEB1/CN7/RB5
AN4/CMP2C/CMP3A/AQEA1/CN6/RB4
AN3/CMP2B/AINDX1/CN5/RB3
AN2/CMP1C/CMP2A/ASS1/CN4/RB2
PGEC3/AN1/CMP1B/CN3/RB1
PGED3/AN0/CMP1A/CMP4C/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33FJ32GS606
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/QEB1/FLT5/RD0
IC4/QEA1/FLT4/INT4/RD11
IC3/INDX1/FLT3/INT3/RD10
IC2/FLT2/U1CTS/INT2/RD9
IC1/FLT1/SYNCI1/INT1/RD8
VSS
OSC2/REFCLKO/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/CMP3C/CMP4A/OCFA/RB6
PGED1/AN7/CMP4B/RB7
AVDD
AVSS
AN8/U2CTS/RB8
AN9/DACOUT/RB9
TMS/AN10/INDX2/RB10
TDO/AN11/EXTREF/RB11
VSS
VDD
TCK/AN12/CMP1D/RB12
TDI/AN13/CMP2D/RB13
AN14/CMP3D/SS1/U2RTS/RB14
AN15/CMP4D/CN12/RB15
U2RX/SDA2/QEA2/FLT17/CN17/RF4
U2TX/SCL2/QEB2/FLT18/CN18/RF5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
 2009-2014 Microchip Technology Inc.
DS7000591F-page 7
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM1H/RE1
PWM1L/FLT8/RE0
C1TX/RF1
C1RX/SYNCI4/RF0
VDD
VCAP
PWM5H/UPDN1/CN16/RD7
PWM5L/CN15/RD6
PWM6H/CN14/RD5
PWM6L/CN13/RD4
OC4/SYNCO1/RD3
OC3/FLT7/RD2
OC2/SYNCO2/FLT6/RD1
64-Pin QFN
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SCK2/FLT12/CN8/RG6
SDI2/FLT11/CN9/RG7
SDO2/FLT10/CN10/RG8
MCLR
SS2/FLT9/SYNCI2/T5CK/CN11/RG9
VSS
VDD
AN5/CMP3B/AQEB1/CN7/RB5
AN4/CMP2C/CMP3A/AQEA1/CN6/RB4
AN3/CMP2B/AINDX1/CN5/RB3
AN2/CMP1C/CMP2A/ASS1/CN4/RB2
PGEC3/AN1/CMP1B/CN3/RB1
PGED3/AN0/CMP1A/CMP4C/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33FJ64GS606
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/QEB1/FLT5/RD0
IC4/QEA1/FLT4/INT4/RD11
IC3/INDX1/FLT3/INT3/RD10
IC2/FLT2/U1CTS/INT2/RD9
IC1/FLT1/SYNCI1/INT1/RD8
VSS
OSC2/REFCLKO/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/CMP3C/CMP4A/OCFA/RB6
PGED1/AN7/CMP4B/RB7
AVDD
AVSS
AN8/U2CTS/RB8
AN9/DACOUT/RB9
TMS/AN10/INDX2/RB10
TDO/AN11/EXTREF/RB11
VSS
VDD
TCK/AN12/CMP1D/RB12
TDI/AN13/CMP2D/RB13
AN14/CMP3D/SS1/U2RTS/RB14
AN15/CMP4D/CN12/RB15
U2RX/SDA2/QEA2/FLT17/CN17/RF4
U2TX/SCL2/QEB2/FLT18/CN18/RF5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
DS7000591F-page 8
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
61
66
65
QEA2/RD12
PWM7H/OC4/SYNCO1/RD3
OC3/FLT7/RD2
OC2/SYNCO2/FLT6/RD1
PWM5L/CN15/RD6
68
67
63
62
PWM5H/UPDN1/CN16/RD7
69
64
C1TX/RF1
C1RX/RF0
VDD
VCAP
PWM6H/CN14/RD5
PWM6L/CN13/RD4
PWM7L/CN19/RD13
QEB2/RG1
73
72
70
INDX2/SYNCI4/RG0
74
71
PWM1L/FLT8/RE0
75
PWM2L/RE2
PWM1H/RE1
77
76
PWM2H/RE3
78
80
79
PWM3L/RE4
80-Pin TQFP
PWM3H/RE5
1
60
PWM4L/RE6
2
59
PWM4H/RE7
AN16/T2CK/RC1
AN17/T3CK/RC2
SCK2/FLT12/CN8/RG6
SDI2/FLT11/CN9/RG7
SDO2/FLT10/CN10/RG8
MCLR
3
58
4
57
5
56
6
55
7
54
8
53
9
52
SS2/FLT9/T5CK/CN11/RG9
VSS
VDD
TMS/FLT13/INT1/RE8
TDO/FLT14/INT2/RE9
AN5/CMP3B/AQEB1/CN7/RB5
AN4/CMP2C/CMP3A/AQEA1/CN6/RB4
AN3/CMP2B/AINDX1/CN5/RB3
10
51
AN2/CMP1C/CMP2A/ASS1/CN4/RB2
PGEC3/AN1/CMP1B/CN3/RB1
PGED3/AN0/CMP1A/CMP4C/CN2/RB0
dsPIC33FJ32GS608
11
50
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/QEB1/FLT5/RD0
IC4/QEA1/FLT4/RD11
IC3/INDX1/FLT3/RD10
IC2/FLT2/RD9
IC1/FLT1/SYNCI1/RD8
SDA2/INT4/FLT19/RA15
SCL2/INT3/FLT20/RA14
VSS
OSC2/REFCLKO/CLKO/RC15
OSC1/CLKIN/RC12
 2009-2014 Microchip Technology Inc.
28
29
30
31
32
33
34
35
36
37
38
39
40
AN10/RB10
AN11/EXTREF/RB11
VSS
VDD
TCK/AN12/CMP1D/RB12
TDI/AN13/CMP2D/RB13
AN14/CMP3D/SS1/U2RTS/RB14
AN15/CMP4D/CN12/RB15
U1CTS/FLT15/SYNCI3/CN20/RD14
U1RTS/FLT16/SYNCI2/CN21/RD15
U2RX/FLT17/CN17/RF4
U2TX/FLT18/CN18/RF5
U1RX/RF2
U1TX/RF3
AN9/DACOUT/RB9
41
27
20
AN8/U2CTS/RB8
SDO1/RF8
42
26
43
19
AVSS
18
25
SCK1/INT0/RF6
SDI1/RF7
AVDD
44
PWM8H/RA10
45
17
24
46
16
23
15
22
47
PWM8L/RA9
48
14
21
13
PGED1/AN7/CMP4B/RB7
49
PGEC1/AN6CMP3C/CMP4A/OCFA/RB6
12
VDD
SCL1/RG2
SDA1/RG3
DS7000591F-page 9
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
61
66
65
62
PWM5L/CN15/RD6
68
67
QEA2/RD12
PWM7H/OC4/SYNCO1/RD3
OC3/FLT7/RD2
OC2/SYNCO2/FLT6/RD1
PWM5H/UPDN1/CN16/RD7
69
64
63
QEB2/RG1
C1TX/RF1
C1RX/RF0
VDD
VCAP
74
PWM6H/CN14/RD5
PWM6L/CN13/RD4
PWM7L/CN19/RD13
INDX2/SYNCI4/RG0
75
70
PWM1L/FLT8/RE0
76
71
PWM2L/RE2
PWM1H/RE1
73
72
PWM2H/RE3
78
77
PWM3L/RE4
80
79
80-Pin TQFP
PWM3H/RE5
1
60
PWM4L/RE6
2
59
PWM4H/RE7
AN16/T2CK/RC1
AN17/T3CK/RC2
SCK2/FLT12/CN8/RG6
SDI2/FLT11/CN9/RG7
SDO2/FLT10/CN10/RG8
MCLR
3
58
4
57
5
56
6
55
7
54
8
53
52
9
SS2/FLT9/T5CK/CN11/RG9
VSS
VDD
TMS/FLT13/INT1/RE8
TDO/FLT14/INT2/RE9
AN5/CMP3B/AQEB1/CN7/RB5
AN4/CMP2C/CMP3A/AQEA1/CN6/RB4
AN3/CMP2B/AINDX1/CN5/RB3
10
51
dsPIC33FJ64GS608
DS7000591F-page 10
29
30
31
32
33
34
35
36
37
38
39
AN11/EXTREF/RB11
VSS
VDD
TCK/AN12/CMP1D/RB12
TDI/AN13/CMP2D/RB13
AN14/CMP3D/SS1/U2RTS/RB14
AN15/CMP4D/CN12/RB15
U1CTS/FLT15/SYNCI3/CN20/RD14
U1RTS/FLT16/SYNCI2/CN21/RD15
U2RX/FLT17/CN17/RF4
OC1/QEB1/FLT5/RD0
IC4/QEA1/FLT4/RD11
IC3/INDX1/FLT3/RD10
IC2/FLT2/RD9
IC1/FLT1/SYNCI1/RD8
SDA2/INT4/FLT19/RA15
SCL2/INT3/FLT20/RA14
VSS
OSC2/REFCLKO/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
U2TX/FLT18/CN18/RF5
40
28
41
AN10/RB10
20
AN9/DACOUT/RB9
PGED3/AN0/CMP1A/CMP4C/CN2/RB0
AN8/U2CTS/RB8
42
27
43
19
26
18
25
AN2/CMP1C/CMP2A/ASS1/CN4/RB2
PGEC3/AN1/CMP1B/CN3/RB1
AVSS
44
AVDD
45
17
24
46
16
PWM8H/RA10
15
23
47
22
48
14
PWM8L/RA9
13
21
49
PGED1/AN7/CMP4B/RB7
50
12
PGEC1/AN6CMP3C/CMP4A/OCFA/RB6
11
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM9H/RG13
PWM9L/RG12
SYNCO1/FLT23/RG14
PWM1H/RE1
PWM1L/FLT8/RE0
AN23/CN23/RA7
AN22/CN22/RA6
INDX2/RG0
QEB2/RG1
C1TX/RF1
C1RX/RF0
VDD
VCAP
PWM5H/UPDN1/CN16/RD7
PWM5L/CN15/RD6
PWM6H/CN14/RD5
PWM6L/CN13/RD4
PWM7L/CN19/RD13
QEA2/RD12
PWM7H/OC4/RD3
OC3/FLT7/RD2
OC2/SYNCO2/FLT6/RD1
100-Pin TQFP
SYNCI1/RG15
VDD
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
AN16/T2CK/RC1
AN17/T3CK/RC2
AN18/T4CK/RC3
AN19/T5CK/RC4
SCK2/FLT12/CN8/RG6
SDI2/FLT11/CN9/RG7
SDO2/FLT10/CN10/RG8
MCLR
SS2/FLT9/CN11/RG9
VSS
VDD
TMS/RA0
2
3
4
5
6
7
8
9
10
11
12
73
72
71
70
69
68
67
66
dsPIC33FJ32GS610
13
14
15
16
17
18
19
20
65
64
63
62
61
60
59
58
57
56
21
22
23
24
25
55
54
53
52
51
Vss
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/CN1/RC13
OC1/QEB1/FLT5/RD0
IC4/QEA1/FLT4/RD11
IC3/INDX1/FLT3/RD10
IC2/FLT2/RD9
IC1/FLT1/RD8
INT4/FLT19/SYNCI4/RA15
INT3/FLT20/RA14
VSS
OSC2/REFCLKO/CLKO/RC15
OSC1/CLKIN/RC12
VDD
TDO/RA5
TDI/RA4
SDA2/FLT21/RA3
SCL2/FLT22/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGEC1/AN6/CMP3C/CMP4A/OCFA/RB6
PGED1/AN7/CMP4B/RB7
PWM8L/RA9
PWM8H/RA10
AVDD
AVSS
AN8/RB8
AN9/DACOUT/RB9
AN10/RB10
AN11/EXTREF/RB11
VSS
VDD
TCK/RA1
U2RTS/RF13
U2CTS/RF12
AN12/CMP1D/RB12
AN13/CMP2D/RB13
AN14/CMP3D/SS1/RB14
AN15/CMP4D/CN12/RB15
VSS
VDD
U1CTS/FLT15/SYNCI3/CN20/RD14
U1RTS/FLT16/SYNCI2/CN21/RD15
U2RX/FLT17/CN17/RF4
U2TX/FLT18/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AN20/FLT13/INT1/RE8
AN21/FLT14/INT2/RE9
AN5/CMP3B/AQEB1/CN7/RB5
AN4/CMP2C/CMP3A/AQEA1/CN6/RB4
AN3/CMP2B/AINDX1/CN5/RB3
AN2/CMP1C/CMP2A/ASS1/CN4/RB2
PGEC3/AN1/CMP1B/CN3/RB1
PGED3/AN0/CMP1A/CMP4C/CN2/RB0
75
74
1
 2009-2014 Microchip Technology Inc.
DS7000591F-page 11
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM9H/RG13
PWM9L/RG12
SYNCO1/FLT23/RG14
PWM1H/RE1
PWM1L/FLT8/RE0
AN23/CN23/RA7
AN22/CN22/RA6
INDX2/RG0
QEB2/RG1
C1TX/RF1
C1RX/RF0
VDD
VCAP
PWM5H/UPDN1/CN16/RD7
PWM5L/CN15/RD6
PWM6H/CN14/RD5
PWM6L/CN13/RD4
PWM7L/CN19/RD13
QEA2/RD12
PWM7H/OC4/RD3
OC3/FLT7/RD2
OC2/SYNCO2/FLT6/RD1
100-Pin TQFP
SYNCI1/RG15
VDD
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
AN16/T2CK/RC1
AN17/T3CK/RC2
AN18/T4CK/RC3
AN19/T5CK/RC4
SCK2/FLT12/CN8/RG6
SDI2/FLT11/CN9/RG7
SDO2/FLT10/CN10/RG8
MCLR
SS2/FLT9/CN11/RG9
VSS
VDD
TMS/RA0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
dsPIC33FJ64GS610
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Vss
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/CN1/RC13
OC1/QEB1/FLT5/RD0
IC4/QEA1/FLT4/RD11
IC3/INDX1/FLT3/RD10
IC2/FLT2/RD9
IC1/FLT1/RD8
INT4/FLT19/SYNCI4/RA15
INT3/FLT20/RA14
VSS
OSC2/REFCLKO/CLKO/RC15
OSC1/CLKIN/RC12
VDD
TDO/RA5
TDI/RA4
SDA2/FLT21/RA3
SCL2/FLT22/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGEC1/AN6/CMP3C/CMP4A/OCFA/RB6
PGED1/AN7/CMP4B/RB7
PWM8L/RA9
PWM8H/RA10
AVDD
AVSS
AN8/RB8
AN9/DACOUT/RB9
AN10/RB10
AN11/EXTREF/RB11
VSS
VDD
TCK/RA1
U2RTS/RF13
U2CTS/RF12
AN12/CMP1D/RB12
AN13/CMP2D/RB13
AN14/CMP3D/SS1/RB14
AN15/CMP4D/CN12/RB15
VSS
VDD
U1CTS/FLT15/SYNCI3/CN20/RD14
U1RTS/FLT16/SYNCI2/CN21/RD15
U2RX/FLT17/CN17/RF4
U2TX/FLT18/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AN20/FLT13/INT1/RE8
AN21/FLT14/INT2/RE9
AN5/CMP3B/AQEB1/CN7/RB5
AN4/CMP2C/CMP3A/AQEA1/CN6/RB4
AN3/CMP2B/AINDX1/CN5/RB3
AN2/CMP1C/CMP2A/ASS1/CN4/RB2
PGEC3/AN1/CMP1B/CN3/RB1
PGED3/AN0/CMP1A/CMP4C/CN2/RB0
1
DS7000591F-page 12
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Table of Contents
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Product Families ............................................................... 2
1.0 Device Overview ........................................................................................................................................................................ 17
2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers.......................................................................................... 23
3.0 CPU............................................................................................................................................................................................ 33
4.0 Memory Organization ................................................................................................................................................................. 45
5.0 Flash Program Memory............................................................................................................................................................ 109
6.0 Resets ..................................................................................................................................................................................... 115
7.0 Interrupt Controller ................................................................................................................................................................... 123
8.0 Direct Memory Access (DMA) .................................................................................................................................................. 179
9.0 Oscillator Configuration ............................................................................................................................................................ 189
10.0 Power-Saving Features............................................................................................................................................................ 203
11.0 I/O Ports ................................................................................................................................................................................... 213
12.0 Timer1 ...................................................................................................................................................................................... 217
13.0 Timer2/3/4/5 features .............................................................................................................................................................. 219
14.0 Input Capture............................................................................................................................................................................ 225
15.0 Output Compare....................................................................................................................................................................... 227
16.0 High-Speed PWM..................................................................................................................................................................... 231
17.0 Quadrature Encoder Interface (QEI) Module ........................................................................................................................... 261
18.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 265
19.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................ 271
20.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 279
21.0 Enhanced CAN (ECAN™) Module........................................................................................................................................... 285
22.0 High-Speed, 10-Bit Analog-to-Digital Converter (ADC)............................................................................................................ 313
23.0 High-Speed Analog Comparator .............................................................................................................................................. 345
24.0 Special Features ...................................................................................................................................................................... 349
25.0 Instruction Set Summary .......................................................................................................................................................... 357
26.0 Development Support............................................................................................................................................................... 365
27.0 Electrical Characteristics .......................................................................................................................................................... 369
28.0 50 MIPS Electrical Characteristics ........................................................................................................................................... 417
29.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 423
30.0 Packaging Information.............................................................................................................................................................. 427
Appendix A: Migrating from dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 to dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610 Devices ................................................................................................................... 441
Appendix B: Revision History............................................................................................................................................................. 442
Index ................................................................................................................................................................................................. 449
The Microchip Web Site ..................................................................................................................................................................... 457
Customer Change Notification Service .............................................................................................................................................. 457
Customer Support .............................................................................................................................................................................. 457
Product Identification System ............................................................................................................................................................ 459
 2009-2014 Microchip Technology Inc.
DS7000591F-page 13
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at [email protected] We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS7000591F-page 14
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Referenced Sources
This device data sheet is based on the following individual chapters of the “dsPIC33/PIC24 Family Reference
Manual”. These documents should be considered as the
primary reference for the operation of a particular module
or device feature.
Note 1: To access the documents listed below,
browse to the documentation section
of the dsPIC33FJ64GS610 product
page of the Microchip web site
(www.microchip.com) to select a family
reference manual section from the
following list.
In addition to parameters, features and
other documentation, the resulting page
provides links to the related family
reference manual sections.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
“CPU” (DS70204)
“Data Memory” (DS70202)
“Program Memory” (DS70203)
“Flash Programming” (DS70191)
“Reset” (DS70192)
“Watchdog Timer (WDT) and Power-Saving Modes” (DS70196)
“I/O Ports” (DS70193)
“Timers” (DS70205)
“Input Capture” (DS70198)
“Output Compare” (DS70005157)
“Quadrature Encoder Interface (QEI)” (DS70208)
“Analog-to-Digital Converter (ADC)” (DS70183)
“UART” (DS70188)
“Serial Peripheral Interface (SPI)” (DS70206)
“Inter-Integrated Circuit™ (I2C™)” (DS70000195)
“ECAN™” (DS70185)
“Direct Memory Access (DMA)” (DS70182)
“CodeGuard™ Security” (DS70199)
“Programming and Diagnostics” (DS70207)
“Device Configuration” (DS70194)
“Development Tool Support” (DS70200)
“Oscillator (Part IV)” (DS70307)
“High-Speed PWM” (DS70000323)
“High-Speed 10-Bit ADC” (DS70000321)
“High-Speed Analog Comparator” (DS70296)
“Interrupts (Part V)” (DS70597)
 2009-2014 Microchip Technology Inc.
DS7000591F-page 15
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS7000591F-page 16
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
1.0
Note:
DEVICE OVERVIEW
This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the latest sections in the
“dsPIC33/PIC24
Family
Reference
Manual”, which are available from the
Microchip web site (www.microchip.com).
The information in this data sheet
supersedes the information in the FRM.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 families of devices
contain extensive Digital Signal Processor (DSP) functionality with a high-performance 16-bit microcontroller
(MCU) architecture.
Figure 1-1 shows a general block diagram of the core
and peripheral modules in the dsPIC33FJ32GS406/
606/608/610 and dsPIC33FJ64GS406/606/608/610
devices. Table 1-1 lists the functions of the various pins
shown in the pinout diagrams.
This document contains device-specific information for
the following dsPIC33F Digital Signal Controller (DSC)
devices:
•
•
•
•
•
•
•
•
dsPIC33FJ32GS406
dsPIC33FJ32GS606
dsPIC33FJ32GS608
dsPIC33FJ32GS610
dsPIC33FJ64GS406
dsPIC33FJ64GS606
dsPIC33FJ64GS608
dsPIC33FJ64GS610
 2009-2014 Microchip Technology Inc.
DS7000591F-page 17
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 1-1:
DEVICE BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
16
8
PORTA
DMA
RAM
16
16
16
Data Latch
Data Latch
PCU PCH PCL
Program Counter
X RAM
Y RAM
Loop
Control
Logic
Address
Latch
Address
Latch
16
23
23
Stack
Control
Logic
PORTB
DMA
Controller
16
23
16
16
16
PORTC
Address Generator Units
Address Latch
Program Memory
EA MUX
Data Latch
24
Instruction Reg
Control Signals
to Various Blocks
FRC/LPRC
Oscillators
VCAP
Note:
PORTE
16
Divide Support
16 x 16
W Register Array
16
PORTF
Oscillator
Start-up Timer
Power-on
Reset
16-Bit ALU
Watchdog
Timer
Voltage
Regulator
16
DSP Engine
Power-up
Timer
Timing
Generation
Literal Data
16
Instruction
Decode and
Control
OSC2/CLKO
OSC1/CLKI
PORTD
ROM Latch
16
PORTG
Brown-out
Reset
VDD, VSS
MCLR
Timers
1-5
UART1/2
ECAN1
ADC1
OC1-4
PWM
9x2
Analog
Comparator 1-4
IC1-4
QEI1,2
CNx
I2C1/2
SPI1,2
Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features
present on each device.
DS7000591F-page 18
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin Name
Pin
Type
Buffer
Type
AN0-AN23
I
CLKI
CLKO
I
O
ST/CMOS External clock source input. Always associated with OSC1 pin function.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
OSC1
I
OSC2
I/O
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
SOSCI
SOSCO
I
O
CN0-CN23
I
ST
Change Notification inputs. Can be software programmed for internal
weak pull-ups on all inputs.
C1RX
C1TX
I
O
ST
—
ECAN1 bus receive pin.
ECAN1 bus transmit pin.
IC1-IC4
I
ST
Capture Inputs 1 through 4.
INDX1, INDX2, AINDX1
QEA1, QEA2, AQEA1
I
I
ST
ST
QEB1, QEB2, AQEB1
I
ST
UPDN1
O
CMOS
Quadrature Encoder Index Pulse input.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Position Up/Down Counter Direction State.
OCFA
OC1-OC4
I
O
ST
—
Compare Fault A input.
Compare Outputs 1 through 4.
INT0
INT1
INT2
INT3
INT4
I
I
I
I
I
ST
ST
ST
ST
ST
External Interrupt 0.
External Interrupt 1.
External Interrupt 2.
External Interrupt 3.
External Interrupt 4.
RA0-RA15
I/O
ST
PORTA is a bidirectional I/O port.
RB0-RB15
I/O
ST
PORTB is a bidirectional I/O port.
RC0-RC15
I/O
ST
PORTC is a bidirectional I/O port.
RD0-RD15
I/O
ST
PORTD is a bidirectional I/O port.
RE0-RE9
I/O
ST
PORTE is a bidirectional I/O port.
RF0-RF13
I/O
ST
PORTF is a bidirectional I/O port.
RG0-RG15
I/O
ST
PORTG is a bidirectional I/O port.
I
I
I
I
I
ST
ST
ST
ST
ST
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
T1CK
T2CK
T3CK
T4CK
T5CK
Analog
Description
Analog input channels.
ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise.
—
32.768 kHz low-power oscillator crystal output.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-Transistor Logic
 2009-2014 Microchip Technology Inc.
Analog = Analog input
P = Power
I = Input
O = Output
DS7000591F-page 19
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
U1CTS
U1RTS
U1RX
U1TX
U2CTS
U2RTS
U2RX
U2TX
I
O
I
O
I
O
I
O
ST
—
ST
—
ST
—
ST
—
UART1 Clear-to-Send.
UART1 Request-to-Send.
UART1 receive.
UART1 transmit.
UART2 Clear-to-Send.
UART2 Request-to-Send.
UART2 receive.
UART2 transmit.
SCK1
SDI1
SDO1
SS1, ASS1
SCK2
SDI2
SDO2
SS2
I/O
I
O
I/O
I/O
I
O
I/O
ST
ST
—
ST
ST
ST
—
ST
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
Synchronous serial clock input/output for SPI2.
SPI2 data in.
SPI2 data out.
SPI2 slave synchronization or frame pulse I/O.
SCL1
SDA1
SCL2
SDA2
I/O
I/O
I/O
I/O
ST
ST
ST
ST
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Synchronous serial clock input/output for I2C2.
Synchronous serial data input/output for I2C2.
TMS
TCK
TDI
TDO
I
I
I
O
TTL
TTL
TTL
—
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
CMP1A
CMP1B
CMP1C
CMP1D
CMP2A
CMP2B
CMP2C
CMP2D
CMP3A
CMP3B
CMP3C
CMP3D
CMP4A
CMP4B
CMP4C
CMP4D
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
DACOUT
O
—
EXTREF
I
Analog
REFCLK
O
—
Pin Name
Description
Comparator 1 Channel A.
Comparator 1 Channel B.
Comparator 1 Channel C.
Comparator 1 Channel D.
Comparator 2 Channel A
Comparator 2 Channel B.
Comparator 2 Channel C.
Comparator 2 Channel D.
Comparator 3 Channel A.
Comparator 3 Channel B.
Comparator 3 Channel C.
Comparator 3 Channel D.
Comparator 4 Channel A.
Comparator 4 Channel B.
Comparator 4 Channel C.
Comparator 4 Channel D.
DAC output voltage.
External voltage reference input for the reference DACs.
REFCLK output signal is a postscaled derivative of the system clock.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-Transistor Logic
DS7000591F-page 20
Analog = Analog input
P = Power
I = Input
O = Output
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
FLT1-FLT23
SYNCI1-SYNCI4
SYNCO1-SYNCO2
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM4L
PWM4H
PWM5L
PWM5H
PWM6L
PWM6H
PWM7L
PWM7H
PWM8L
PWM8H
PWM9L
PWM9H
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
ST
ST
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Fault inputs to PWM module.
External synchronization signal to PWM master time base.
PWM master time base for external device synchronization.
PWM1 low output.
PWM1 high output.
PWM2 low output.
PWM2 high output.
PWM3 low output.
PWM3 high output.
PWM4 low output.
PWM4 high output.
PWM5 low output.
PWM5 high output.
PWM6 low output.
PWM6 high output.
PWM7 low output.
PWM7 high output.
PWM8 low output.
PWM8 high output.
PWM9 low output.
PWM9 high output.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
Data I/O pin for Programming/Debugging Communication Channel 1.
Clock input pin for Programming/Debugging Communication Channel 1.
Data I/O pin for Programming/Debugging Communication Channel 2.
Clock input pin for Programming/Debugging Communication Channel 2.
Data I/O pin for Programming/Debugging Communication Channel 3.
Clock input pin for Programming/Debugging Communication Channel 3.
MCLR
I/P
ST
Master Clear (Reset) input. This pin is an active-low Reset to the
device.
AVDD
P
P
Pin Name
Description
Positive supply for analog modules.
AVSS
P
P
Ground reference for analog modules.
VDD
P
—
Positive supply for peripheral logic and I/O pins.
VCAP
P
—
CPU logic filter capacitor connection.
VSS
P
—
Ground reference for logic and I/O pins.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-Transistor Logic
 2009-2014 Microchip Technology Inc.
Analog = Analog input
P = Power
I = Input
O = Output
DS7000591F-page 21
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS7000591F-page 22
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
DIGITAL SIGNAL
CONTROLLERS
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in
this data sheet, refer to the “dsPIC33/
PIC24 Family Reference Manual”.
Please see the Microchip web site
(www.microchip.com) for the latest
dsPIC33/PIC24 Family Reference Manual sections. The information in this
data sheet supersedes the information
in the FRM.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2.1
Basic Connection Requirements
Getting started with the dsPIC33FJ32GS406/606/
608/610 and dsPIC33FJ64GS406/606/608/610
family of 16-bit Digital Signal Controllers (DSC)
requires attention to a minimal set of device pin
connections before proceeding with development.
The following is a list of pin names, which must
always be connected:
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins (regardless if ADC module
is not used)
(see Section 2.2 “Decoupling Capacitors”)
• VCAP
(see Section 2.3 “Capacitor on Internal Voltage
Regulator (VCAP)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
 2009-2014 Microchip Technology Inc.
2.2
Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: Recommendation of
0.1 µF (100 nF), 10-20V. This capacitor should be a
low-ESR and have resonance frequency in the
range of 20 MHz and higher. It is recommended that
ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close to
the pins as possible. It is recommended to place the
capacitors on the same side of the board as the
device. If space is constricted, the capacitor can be
placed on another layer on the PCB using a via;
however, ensure that the trace length from the pin to
the capacitor is within one-quarter inch (6 mm) in
length.
• Handling high-frequency noise: If the board is
experiencing high-frequency noise, upward of tens
of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor.
The value of the second capacitor can be in the
range of 0.01 µF to 0.001 µF. Place this second
capacitor next to the primary decoupling capacitor.
In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the
power and ground pins as possible. For example,
0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first, and
then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB track inductance.
DS7000591F-page 23
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
0.1 µF
Ceramic
R
R1
2.4
VSS
VCAP
VDD
22 µF
Tantalum
VDD
• Device Reset
• Device programming and debugging
C
dsPIC33F
VSS
VDD
VSS
VDD
AVSS
VDD
AVDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
L1(1)
Note 1:
As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1 and the inductor
capacity greater than 10 mA.
Where:
F CNV
f = -------------2
1
f = ---------------------- 2 LC 
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
MCLR
0.1 µF
Ceramic
The placement of this capacitor should be close to the
VCAP. It is recommended that the trace length not
exceed one-quarter inch (6 mm). Refer to Section 24.2
“On-Chip Voltage Regulator” for details.
(i.e., ADC conversion rate/2)
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS(1,2)
VDD
2
1
L =  ----------------------
  2f C 
R
R1
MCLR
2.2.1
TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that connects the power supply source to the device and the
maximum current drawn by the device in the application. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
2.3
Capacitor on Internal Voltage
Regulator (VCAP)
JP
dsPIC33F
C
Note 1:
R  10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2:
R1  470 will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
A low-ESR (< 0.5 Ohms) capacitor is required on the
VCAP pin, which is used to stabilize the voltage
regulator output voltage. The VCAP pin must not be
connected to VDD, and must have a minimum capacitor
of 22 µF, 16V connected to ground. The type can be
ceramic or tantalum. Refer to Section 27.0 “Electrical
Characteristics” for additional information.
DS7000591F-page 24
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2.5
ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes, and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 3 or MPLAB REAL ICE™.
For more information on ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip web
site.
• “Using MPLAB® ICD 3” (poster) (DS51765)
• “MPLAB® ICD 3 Design Advisory” (DS51764)
• “MPLAB® REAL ICE™ In-Circuit Debugger
User’s Guide” (DS51616)
• “Using MPLAB® REAL ICE™” (poster) (DS51749)
2.6
External Oscillator Pins
Many DSCs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 9.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
FIGURE 2-3:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
Main Oscillator
13
Guard Ring
14
15
Guard Trace
Secondary
Oscillator
16
17
18
19
20
 2009-2014 Microchip Technology Inc.
DS7000591F-page 25
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2.7
Oscillator Value Conditions on
Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 4 MHz < FIN < 8 MHz to comply with device PLL
start-up conditions. This means that if the external
oscillator frequency is outside this range, the
application must start-up in the FRC mode first. The
default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration Word.
2.8
Configuration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 3 or REAL ICE is selected as a
debugger, it automatically initializes all of the Analogto-Digital input pins (ANx) as “digital” pins, by setting all
bits in the ADPCFG and ADPCFG2 registers.
If your application needs to use certain Analog-toDigital pins as analog input pins during the debug
session, the user application must clear the
corresponding bits in the ADPCFG and ADPCFG2
registers during initialization of the ADC module.
When MPLAB ICD 3 or REAL ICE is used as a
programmer, the user application firmware must
correctly configure the ADPCFG and ADPCFG2
registers. Automatic initialization of these registers is
only done during debugger operation. Failure to
correctly configure the register(s) will result in all
Analog-to-Digital pins being recognized as analog input
pins, resulting in the port value being read as a logic ‘0’,
which may affect user application functionality.
2.9
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state.
Alternatively, connect a 1k to 10k resistor between VSS
and unused pins and drive the output to logic low.
2.10
Typical Application Connection
Examples
Examples of typical application connections are shown
in Figure 2-4 through Figure 2-11.
The bits in the registers that correspond to the Analog-toDigital pins that are initialized by MPLAB ICD 2, ICD 3, or
REAL ICE, must not be cleared by the user application
firmware; otherwise, communication errors will result
between the debugger and the device.
DS7000591F-page 26
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 2-4:
DIGITAL PFC
IPFC
VHV_BUS
|VAC|
k1
k3
VAC
ADC Channel
k2
FET
Driver
ADC Channel
PWM
Output
ADC Channel
dsPIC33FJ32GS406
FIGURE 2-5:
BOOST CONVERTER IMPLEMENTATION
IPFC
VINPUT
VOUTPUT
k1
k3
ADC Channel
k2
FET
Driver
ADC
Channel
PWM
Output
ADC Channel
dsPIC33FJ32GS406
 2009-2014 Microchip Technology Inc.
DS7000591F-page 27
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 2-6:
SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER
12V Input
5V Output
I5V
PWM
ADC
Channel
PWM
FET
Driver
k7
k1
k2
Analog
Comp.
ADC
Channel
dsPIC33FJ32GS606
FIGURE 2-7:
MULTIPHASE SYNCHRONOUS BUCK CONVERTER
3.3V Output
12V Input
PWM
dsPIC33FJ32GS608
PWM
FET
Driver
PWM
ADC
Channel
FET
Driver
PWM
k6
k7
PWM
PWM
Analog Comparator
FET
Driver
k3
Analog Comparator
k4
Analog Comparator
k5
ADC Channel
DS7000591F-page 28
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 2-8:
OFF-LINE UPS
VDC
Push-Pull Converter
Full-Bridge Inverter
VOUT+
VBAT
+
VOUTGND
GND
FET
Driver
FET
Driver
PWM
PWM
k2
k1
ADC ADC
or
Analog Comp.
k3
FET
Driver
FET
Driver
FET
Driver
FET
Driver
PWM
PWM
PWM
PWM
dsPIC33FJ64GS610
ADC
k4
k5
ADC
ADC
ADC
PWM
FET
Driver
k6
+
Battery Charger
 2009-2014 Microchip Technology Inc.
DS7000591F-page 29
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 2-9:
INTERLEAVED PFC
VOUT+
|VAC|
k4
VAC
k3
k2
k1
VOUTFET
Driver
ADC Channel
ADC Channel
DS7000591F-page 30
PWM
FET
Driver
ADC
Channel
PWM
ADC
Channel
ADC
Channel
dsPIC33FJ32GS608
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 2-10:
PHASE-SHIFTED FULL-BRIDGE CONVERTER
VIN+
Gate 6
Gate 3
Gate 1
VOUT+
S1
S3
VOUT-
Gate 2
Gate 4
Gate 5
Gate 6
Gate 5
VIN-
FET
Driver
k2
PWM
ADC
Channel
k1
Analog
Ground
Gate 1
S1
FET
Driver
PWM
Gate 3
S3
FET
Driver
ADC
Channel
dsPIC33FJ32GS606
PWM
Gate 2
Gate 4
 2009-2014 Microchip Technology Inc.
DS7000591F-page 31
AC-TO-DC POWER SUPPLY WITH PFC AND THREE OUTPUTS (12V, 5V AND 3.3V)
ZVT with Current Doubler Synchronous Rectifier
VHV_BUS
Isolation
Barrier
VOUT
IZVT
3.3V Multiphase Buck Stage
3.3V Output
12V Input
I3.3V_1
FET
Driver
FET
Driver
k4
FET
Driver
5V Output
5V Buck Stage
I3.3V_2
ADC
ADC
Channel Channel
FET
Driver
PWM
UART
RX
PWM
Output
ADC
Ch.
ADC
Channel
FET
Driver
k7
Analog
Comp.
ADC
Channel
Secondary Controller
dsPIC33FJ64GS610
PFC Stage
k2
UART
TX
FET Driver
FET
Driver
I3.3V_3
k6
PWM
PWM
ADC
Ch.
k5
PWM
PWM
PWM
ADC
Ch.
Primary Controller
dsPIC33FJ64GS610
PWM
PWM
PWM
PWM
PWM
PWM
I5V
PWM
PWM
Analog Comparator
k8
Analog Comparator
k9
Analog Comparator
k10
ADC Channel
 2009-2014 Microchip Technology Inc.
VAC
k3
k1
|VAC|
VHV_BUS
IPFC
FET
Driver
k11
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 32
FIGURE 2-11:
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
3.0
CPU
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “CPU” (DS70204) in the
“dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
The information in this data sheet
supersedes the information in the FRM.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 CPU module has a
16-bit (data) modified Harvard architecture with an
enhanced instruction set, including significant support
for DSP. The CPU has a 24-bit instruction word with a
variable length opcode field. The Program Counter
(PC) is 23 bits wide and addresses up to 4M x 24 bits
of user program memory space. The actual amount of
program memory implemented varies from device to
device. A single-cycle instruction prefetch mechanism is
used to help maintain throughput and provides
predictable execution. All instructions execute in a single
cycle, with the exception of instructions that change the
program flow, the double-word move (MOV.D) instruction
and the table instructions. Overhead-free program loop
constructs are supported using the DO and REPEAT
instructions, both of which are interruptible at any point.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices have sixteen, 16-bit Working registers in the programmer’s
model. Each of the Working registers can serve as a
data, address or address offset register. The sixteenth
Working register (W15) operates as a Software Stack
Pointer (SSP) for interrupts and calls.
There are two classes of instruction in the
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices: MCU and
DSP. These two instruction classes are seamlessly
integrated into a single CPU. The instruction set includes
many addressing modes and is designed for optimum C
compiler efficiency. For most instructions, the
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices are capable
of executing a data (or program data) memory read, a
Working register (data) read, a data memory write and a
program (instruction) memory read per instruction cycle.
 2009-2014 Microchip Technology Inc.
As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a
single cycle.
A block diagram of the CPU is shown in
Figure 3-1, and the programmer’s model for
the
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 is shown in
Figure 3-2.
3.1
Data Addressing Overview
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through
the X memory AGU, which accesses the entire
memory map as one linear data space. Certain DSP
instructions operate through the X and Y AGUs to
support dual operand reads, which splits the data
address space into two parts. The X and Y data space
boundary is device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data space mapping feature lets any
instruction access program space as if it were data
space.
3.2
DSP Engine Overview
The DSP engine features a high-speed, 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating
accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up
to 16 bits, right or left, in a single cycle. The DSP
instructions operate seamlessly with all other
instructions and have been designed for optimal realtime performance. The MAC instruction and other
associated instructions can concurrently fetch two data
operands from memory while multiplying two W
registers and accumulating and optionally saturating
the result in the same cycle. This instruction
functionality requires that the RAM data space be split
for these instructions and linear for all others. Data
space partitioning is achieved in a transparent and
flexible manner through dedicating certain Working
registers to each address space.
DS7000591F-page 33
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
3.3
Special MCU Features
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 supports 16/16 and
32/16 divide operations, both fractional and integer. All
divide instructions are iterative operations. They must
be executed within a REPEAT loop, resulting in a total
execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 features a 17-bit by
17-bit single-cycle multiplier that is shared by both the
MCU ALU and DSP engine. The multiplier can perform
signed, unsigned and mixed sign multiplication. Using
a 17-bit by 17-bit multiplier for 16-bit by 16-bit
multiplication not only allows you to perform mixed sign
multiplication, it also achieves accurate results for
special operations, such as (-1.0) x (-1.0).
FIGURE 3-1:
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 CPU
CORE BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
8
16
16
16
16
Data Latch
Data Latch
X RAM
Y RAM
Address
Latch
Address
Latch
23
23
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
16
23
16
16
Address Generator Units
Address Latch
Program Memory
EA MUX
Data Latch
ROM Latch
24
Instruction Reg
16
Literal Data
Instruction
Decode and
Control
16
16
Control Signals
to Various Blocks
DSP Engine
Divide Support
16 x 16
W Register Array
16
16-Bit ALU
16
To Peripheral Modules
DS7000591F-page 34
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 3-2:
PROGRAMMER’S MODEL
D15
D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3
Legend
W4
W5
DSP Operand
Registers
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write-Back
W14/Frame Pointer
W15/Stack Pointer
Stack Pointer Limit Register
SPLIM
AD39
DSP
Accumulators
AD15
AD31
AD0
ACCA
ACCB
PC22
PC0
0
Program Counter
0
7
TBLPAG
Data Table Page Address
7
0
PSVPAG
Program Space Visibility Page Address
15
0
RCOUNT
REPEAT Loop Counter
15
0
DCOUNT
DO Loop Counter
22
0
DOSTART
DO Loop Start Address
DOEND
DO Loop End Address
22
15
0
Core Configuration Register
CORCON
OA
OB
SA
SB OAB SAB DA
SRH
 2009-2014 Microchip Technology Inc.
DC
IPL2 IPL1 IPL0 RA
N
OV
Z
C
STATUS Register
SRL
DS7000591F-page 35
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
3.4
CPU Control Registers
REGISTER 3-1:
SR: CPU STATUS REGISTER
R-0
OA
R-0
R/C-0
R/C-0
OB
SA(1)
(1)
SB
R-0
OAB
R/C-0
(1,4)
SAB
R-0
R/W-0
DA
DC
bit 15
bit 8
R/W-0(3)
IPL2
R/W-0(3)
(2)
IPL1
(2)
R/W-0(3)
IPL0
(2)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
RA
N
OV
Z
C
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
OA: Accumulator A Overflow Status bit
1 = Accumulator A has overflowed
0 = Accumulator A has not overflowed
bit 14
OB: Accumulator B Overflow Status bit
1 = Accumulator B has overflowed
0 = Accumulator B has not overflowed
bit 13
SA: Accumulator A Saturation ‘Sticky’ Status bit(1)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
bit 12
SB: Accumulator B Saturation ‘Sticky’ Status bit(1)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
bit 11
OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulator A or B has overflowed
0 = Neither Accumulator A or B has overflowed
bit 10
SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit(1,4)
1 = Accumulator A or B is saturated or has been saturated at some time in the past
0 = Neither Accumulator A or B is saturated
bit 9
DA: DO Loop Active bit
1 = DO loop in progress
0 = DO loop not in progress
bit 8
DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1:
2:
3:
4:
This bit can be read or cleared (not set).
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>).
Clearing this bit will clear SA and SB.
DS7000591F-page 36
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 3-1:
SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4
RA: REPEAT Loop Active bit
1 = REPEAT loop is in progress
0 = REPEAT loop is not in progress
bit 3
N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1
Z: MCU ALU Zero bit
1 = An operation that affects the Z bit has set it at some time in the past
0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
bit 0
C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
3:
4:
This bit can be read or cleared (not set).
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>).
Clearing this bit will clear SA and SB.
 2009-2014 Microchip Technology Inc.
DS7000591F-page 37
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 3-2:
CORCON: CORE CONTROL REGISTER
U-0
—
bit 15
U-0
—
R/W-0
SATA
bit 7
R/W-0
SATB
bit 11
bit 10-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
R/W-0
US
R/W-0
EDT(1)
R-0
DL2
R-0
DL1
R-0
DL0
bit 8
Legend:
R = Readable bit
-n = Value at POR
bit 15-13
bit 12
U-0
—
R/W-1
SATDW
R/W-0
ACCSAT
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R/C-0
IPL3(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
bit 0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
US: DSP Multiply Unsigned/Signed Control bit
1 = DSP engine multiplies are unsigned
0 = DSP engine multiplies are signed
EDT: Early DO Loop Termination Control bit(1)
1 = Terminates executing DO loop at the end of the current loop iteration
0 = No effect
DL<2:0>: DO Loop Nesting Level Status bits
111 = 7 DO loops are active
•
•
•
001 = 1 DO loop is active
000 = 0 DO loops are active
SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation is enabled
0 = Accumulator A saturation is disabled
SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation is enabled
0 = Accumulator B saturation is disabled
SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation is enabled
0 = Data space write saturation is disabled
ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
PSV: Program Space Visibility in Data Space Enable bit
1 = Program space is visible in data space
0 = Program space is not visible in data space
RND: Rounding Mode Select bit
1 = Biased (conventional) rounding is enabled
0 = Unbiased (convergent) rounding is enabled
IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode is enabled for DSP multiply operations
0 = Fractional mode is enabled for DSP multiply operations
This bit will always read as ‘0’.
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
DS7000591F-page 38
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
3.5
Arithmetic Logic Unit (ALU)
3.6
DSP Engine
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 ALU is 16 bits wide
and is capable of addition, subtraction, bit shifts and logic
operations. Unless otherwise mentioned, arithmetic
operations are 2’s complement in nature. Depending on
the operation, the ALU can affect the values of the Carry
(C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry
(DC) Status bits in the SR register. The C and DC Status
bits operate as Borrow and Digit Borrow bits, respectively,
for subtraction operations.
The DSP engine consists of a high-speed, 17-bit x 17-bit
multiplier, a barrel shifter and a 40-bit adder/subtracter
(with two target accumulators, round and saturation logic).
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
The DSP engine can also perform inherent
accumulator-to-accumulator operations that require no
additional data. These instructions are ADD, SUB and
NEG.
Refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157) for information on the SR
bits affected by each instruction.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 CPU incorporates
hardware support for both multiplication and division. This
includes a dedicated hardware multiplier and support
hardware for 16-bit divisor division.
3.5.1
MULTIPLIER
Using the high-speed, 17-bit x 17-bit multiplier of the DSP
engine, the ALU supports unsigned, signed or mixed sign
operation in several MCU multiplication modes:
•
•
•
•
•
•
•
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 is a single-cycle
instruction flow architecture; therefore, concurrent
operation of the DSP engine with MCU instruction flow
is not possible. However, some MCU ALU and DSP
engine resources can be used concurrently by the
same instruction (for example, ED, EDAC).
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
•
•
•
•
•
•
Fractional or integer DSP multiply (IF)
Signed or unsigned DSP multiply (US)
Conventional or convergent rounding (RND)
Automatic saturation on/off for ACCA (SATA)
Automatic saturation on/off for ACCB (SATB)
Automatic saturation on/off for writes to data
memory (SATDW)
• Accumulator Saturation mode selection
(ACCSAT)
A block diagram of the DSP engine is shown in
Figure 3-3.
TABLE 3-1:
Instruction
DSP INSTRUCTIONS
SUMMARY
Algebraic
Operation
ACC
Write-Back
Yes
CLR
A=0
ED
A = (x – y)2
No
2
EDAC
A = A + (x – y)
No
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
MAC
A = A + (x * y)
Yes
•
•
•
•
3.5.2
DIVIDER
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0 and
the remainder in W1. 16-bit signed and unsigned DIV
instructions can specify any W register for both the 16-bit
divisor (Wn) and any W register (aligned) pair
(W(m + 1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both 32-bit/
16-bit and 16-bit/16-bit instructions take the same
number of cycles to execute.
 2009-2014 Microchip Technology Inc.
x2
No
MAC
A=A+
MOVSAC
No change in A
Yes
MPY
A=x*y
No
MPY
A = x2
No
MPY.N
A=–x*y
No
MSC
A=A–x*y
Yes
DS7000591F-page 39
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 3-3:
DSP ENGINE BLOCK DIAGRAM
40
S
a
40 Round t 16
u
Logic r
a
t
e
40-Bit Accumulator A
40-Bit Accumulator B
Carry/Borrow Out
Saturate
Carry/Borrow In
Adder
Negate
40
40
40
16
X Data Bus
Barrel
Shifter
40
Y Data Bus
Sign-Extend
32
16
Zero Backfill
32
33
17-Bit
Multiplier/Scaler
16
16
To/From W Array
DS7000591F-page 40
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
3.6.1
MULTIPLIER
The 17-bit x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler is a 33-bit value that is sign-extended
to 40 bits. Integer data is inherently represented as a
signed 2’s complement value, where the Most
Significant bit (MSb) is defined as a sign bit. The range
of an N-bit 2’s complement integer is -2N-1 to 2N-1 – 1.
• For a 16-bit integer, the data range is -32768
(0x8000) to 32767 (0x7FFF) including 0.
• For a 32-bit integer, the data range is
-2,147,483,648 (0x8000 0000) to 2,147,483,647
(0x7FFF FFFF).
When the multiplier is configured for fractional
multiplication, the data is represented as a 2’s
complement fraction, where the MSb is defined as a
sign bit and the radix point is implied to lie just after the
sign bit (QX format). The range of an N-bit 2’s
complement fraction with this implied radix point is -1.0
to (1 – 21-N). For a 16-bit fraction, the Q15 data range
is -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0
and has a precision of 3.01518x10-5. In Fractional
mode, the 16 x 16 multiply operation generates a
1.31 product that has a precision of 4.65661 x 10-10.
The same multiplier is used to support the MCU
multiply instructions, which include integer 16-bit
signed, unsigned and mixed sign multiply operations.
The MUL instruction can be directed to use byte or
word-sized operands. Byte operands will direct a 16-bit
result and word operands will direct a 32-bit result to
the specified register(s) in the W array.
3.6.2
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its preaccumulation
source
and
post-accumulation
destination. For the ADD and LAC instructions, the data
to be accumulated or loaded can be optionally scaled
using the barrel shifter prior to accumulation.
 2009-2014 Microchip Technology Inc.
3.6.2.1
Adder/Subtracter, Overflow and
Saturation
The adder/subtracter is a 40-bit adder with an optional
zero input into one side and either true or complement
data into the other input.
• In the case of addition, the Carry/Borrow input is
active-high and the other input is true data (not
complemented).
• In the case of subtraction, the Carry/Borrow input
is active-low and the other input is complemented.
The adder/subtracter generates Overflow Status bits,
SA/SB and OA/OB, which are latched and reflected in
the STATUS Register (SR):
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits, 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block that
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described
previously
and
the
SAT<A:B>
(CORCON<7:6>) and ACCSAT (CORCON<4>) mode
control bits to determine when and to what value to
saturate.
Six STATUS Register bits support saturation and
overflow:
• OA: ACCA overflowed into guard bits
• OB: ACCB overflowed into guard bits
• SA: ACCA saturated (bit 31 overflow and
saturation)
or
ACCA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
• SB: ACCB saturated (bit 31 overflow and
saturation)
or
ACCB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
• OAB: Logical OR of OA and OB
• SAB: Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the corresponding Overflow Trap Flag Enable bits (OVATE, OVBTE) in
the INTCON1 register are set (refer to Section 7.0
“Interrupt Controller”). This allows the user application to take immediate action, for example, to correct
system gain.
DS7000591F-page 41
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
The SA and SB bits are modified each time data
passes through the adder/subtracter, but can only be
cleared by the user application. When set, they indicate
that the accumulator has overflowed its maximum
range (bit 31 for 32-bit saturation or bit 39 for 40-bit
saturation) and will be saturated (if saturation is
enabled). When saturation is not enabled, SA and SB
default to bit 39 overflow and thus, indicate that a catastrophic overflow has occurred. If the COVTE bit in the
INTCON1 register is set, SA and SB bits will generate
an arithmetic warning trap when saturation is disabled.
The Overflow and Saturation Status bits can optionally be
viewed in the STATUS Register (SR) as the logical OR of
OA and OB (in bit OAB) and the logical OR of SA and SB
(in bit SAB). Programmers can check one bit in the
STATUS Register to determine if either accumulator has
overflowed, or one bit to determine if either accumulator
has saturated. This is useful for complex number
arithmetic, which typically uses both accumulators.
The device supports three Saturation and Overflow
modes:
• Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive
9.31 (0x7FFFFFFFFF) or maximally negative
9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set
until cleared by the user application. This
condition is referred to as ‘super saturation’ and
provides protection against erroneous data or
unexpected algorithm problems (such as
gain calculations).
• Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive
1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user application. When
this Saturation mode is in effect, the guard bits are
not used, so the OA, OB or OAB bits are
never set.
• Bit 39 Catastrophic Overflow:
The bit 39 Overflow Status bit from the adder is
used to set the SA or SB bit, which remains set
until cleared by the user application. No saturation
operation is performed, and the accumulator is
allowed to overflow, destroying its sign. If the
COVTE bit in the INTCON1 register is set, a
catastrophic overflow can initiate a trap exception.
DS7000591F-page 42
3.6.3
ACCUMULATOR ‘WRITE-BACK’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following addressing modes are supported:
• W13, Register Direct:
The rounded contents of the non-target accumulator
are written into W13 as a 1.15 fraction.
• [W13] + = 2, Register Indirect with Post-Increment:
The rounded contents of the non-target
accumulator are written into the address pointed
to by W13 as a 1.15 fraction. W13 is then
incremented by 2 (for a word write).
3.6.3.1
Round Logic
The round logic is a combinational block that performs
a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It generates a 16-bit,
1.15 data value that is passed to the data space write
saturation logic. If rounding is not indicated by the
instruction, a truncated 1.15 data value is stored and
the least significant word is simply discarded.
Conventional rounding zero-extends bit 15 of the accumulator and adds it to the ACCxH word (bits 16 through
31 of the accumulator).
• If the ACCxL word (bits 0 through 15 of the
accumulator) is between 0x8000 and 0xFFFF
(0x8000 included), ACCxH is incremented.
• If ACCxL is between 0x0000 and 0x7FFF, ACCxH
is left unchanged.
A consequence of this algorithm is that over a
succession of random rounding operations, the value
tends to be biased slightly positive.
Convergent (or unbiased) rounding operates in the same
manner as conventional rounding, except when ACCxL
equals 0x8000. In this case, the Least Significant bit
(bit 16 of the accumulator) of ACCxH is examined:
• If it is ‘1’, ACCxH is incremented.
• If it is ‘0’, ACCxH is not modified.
Assuming that bit 16 is effectively random in nature, this
scheme removes any rounding bias that may accumulate.
The SAC and SAC.R instructions store either a truncated
(SAC), or rounded (SAC.R) version of the contents of the
target accumulator to data memory via the X bus, subject
to data saturation (see Section 3.6.3.2 “Data Space
Write Saturation”). For the MAC class of instructions, the
accumulator write-back operation functions in the same
manner, addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data is
always subject to rounding.
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
3.6.3.2
Data Space Write Saturation
3.6.4
BARREL SHIFTER
In addition to adder/subtracter saturation, writes to data
space can also be saturated, but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15
fractional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These inputs
are combined and used to select the appropriate
1.15 fractional value as output to write to data space
memory.
The barrel shifter can perform up to 16-bit arithmetic or
logic right shifts, or up to 16-bit left shifts in a single
cycle. The source can be either of the two DSP
accumulators or the X bus (to support multi-bit shifts of
register or memory data).
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly:
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is
presented to the barrel shifter between bit positions 16
and 31 for right shifts, and between bit positions 0 and
16 for left shifts.
• For input data greater than 0x007FFF, data
written to memory is forced to the maximum
positive 1.15 value, 0x7FFF.
• For input data less than 0xFF8000, data written to
memory is forced to the maximum negative
1.15 value, 0x8000.
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.
The Most Significant bit of the source (bit 39) is used to
determine the sign of the operand being tested.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
 2009-2014 Microchip Technology Inc.
DS7000591F-page 43
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS7000591F-page 44
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
MEMORY ORGANIZATION
Note:
This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the dsPIC33/PIC24 Family
Reference Manual, Program Memory”
(DS70203), which is available from the
Microchip web site (www.microchip.com).
The information in this data sheet
supersedes the information in the FRM.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 architecture features
separate program and data memory spaces and buses.
This architecture also allows the direct access to program
memory from the data space during code execution.
User Memory Space
FIGURE 4-1:
4.1
Program Address Space
The program address memory space is 4M instructions. The space is addressable by a 24-bit value
derived either from the 23-bit Program Counter (PC)
during program execution, or from table operation or
data space remapping as described in Section 4.6
“Interfacing Program and Data Memory Spaces”.
User application access to the program memory space
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
The memory maps are shown in Figure 4-1.
PROGRAM MEMORY MAPS FOR dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610 DEVICES
dsPIC33FJ32GS406/606/608/610
0x000000
GOTO Instruction
0x000002
Reset Address
0x000004
Interrupt Vector Table
0x0000FE
0x000100
Reserved
0x000104
Alternate Vector Table
0x0001FE
0x000200
User Program
Flash Memory
(11008 instructions)
0x0057FE
0x005800
User Memory Space
4.0
dsPIC33FJ64GS406/606/608/610
0x000000
GOTO Instruction
0x000002
Reset Address
0x000004
Interrupt Vector Table
0x0000FE
0x000100
Reserved
0x000104
Alternate Vector Table
0x0001FE
0x000200
User Program
Flash Memory
(21760 instructions)
0x00ABFE
0x00AC00
Unimplemented
Unimplemented
(Read ‘0’s)
(Read ‘0’s)
0x7FFFFE
0x800000
0x7FFFFE
0x800000
Reserved
Device Configuration
Registers
0xF7FFFE
0xF80000
0xF80017
0xF80018
Reserved
DEVID (2)
Reserved
 2009-2014 Microchip Technology Inc.
0xFEFFFE
0xFF0000
0xFF0002
0xFFFFFE
Configuration Memory Space
Configuration Memory Space
Reserved
Device Configuration
Registers
0xF7FFFE
0xF80000
0xF80017
0xF80018
Reserved
0xFEFFFE
DEVID (2)
Reserved
0xFF0000
0xFF0002
0xFFFFFE
DS7000591F-page 45
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
4.1.1
PROGRAM MEMORY
ORGANIZATION
4.1.2
All
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices reserve the
addresses between 0x00000 and 0x000200 for hardcoded program execution vectors. A hardware Reset
vector is provided to redirect code execution from the
default value of the PC on device Reset to the actual
start of code. A GOTO instruction is programmed by the
user application at 0x000000, with the actual address
for the start of code at 0x000002.
The program memory space is organized in wordaddressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (see Figure 4-2).
Program memory addresses are always word-aligned
on the lower word and addresses are incremented or
decremented by two during the code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space accessible.
FIGURE 4-2:
msw
Address
least significant word
most significant word
16
8
PC Address
(lsw Address)
0
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
DS7000591F-page 46
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices also have
two Interrupt Vector Tables (IVT), located from
0x000004 to 0x0000FF and 0x000100 to 0x0001FF.
These vector tables allow each of the device interrupt
sources to be handled by separate Interrupt Service
Routines (ISRs). A more detailed discussion of the
Interrupt Vector Tables is provided in Section 7.1
“Interrupt Vector Table”.
PROGRAM MEMORY ORGANIZATION
23
0x000001
0x000003
0x000005
0x000007
INTERRUPT AND TRAP VECTORS
Instruction Width
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
4.2
Data Address Space
The CPU has a separate 16-bit-wide data memory space.
The data space is accessed using separate Address
Generation Units (AGUs) for read and write operations.
The data memory maps is shown in Figure 4-3.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA<15> = 0) is used for
implemented memory addresses, while the upper half
(EA<15> = 1) is reserved for the Program Space
Visibility area (see Section 4.6.3 “Reading Data from
Program Memory Using Program Space Visibility”).
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices implement
up to 9 Kbytes of data memory. Should an EA point to
a location outside of this area, an all-zero word or byte
will be returned.
4.2.1
DATA SPACE WIDTH
The data memory space is organized in byte
addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® MCU
devices and improve data space memory usage
efficiency, the instruction set supports both word and
byte operations. As a consequence of byte accessibility, all Effective Address calculations are internally
scaled to step through word-aligned memory. For
example, the core recognizes that Post-Modified
Register Indirect Addressing mode [Ws++] that results
in a value of Ws + 1 for byte operations and Ws + 2 for
word operations.
Data byte reads will read the complete word that
contains the byte, using the LSB of any EA to
determine which byte to select. The selected byte is
placed onto the LSB of the data path. That is, data
memory and registers are organized as two parallel
byte-wide entities with shared (word) address decode
but separate write lines. Data byte writes only write to
the corresponding side of the array or register that
matches the byte address.
 2009-2014 Microchip Technology Inc.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed. If the error occurred
on a write, the instruction is executed but the write does
not occur. In either case, a trap is then executed,
allowing the system and/or user application to examine
the machine state prior to execution of the address
Fault.
All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte is not
modified.
A Sign-Extend (SE) instruction is provided to allow user
applications to translate 8-bit signed data to 16-bit
signed values. Alternatively, for 16-bit unsigned data,
user applications can clear the MSB of any W register
by executing a Zero-Extend (ZE) instruction on the
appropriate address.
4.2.3
SFR SPACE
The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the core and
peripheral modules for controlling the operation of the
device.
SFRs are distributed among the modules that they
control and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’.
Note:
4.2.4
The actual set of peripheral features and
interrupts varies by the device. Refer to the
corresponding device tables and pinout
diagrams for device-specific information.
NEAR DATA SPACE
The 8-Kbyte area between 0x0000 and 0x1FFF is
referred to as the Near Data Space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a Working
register as an Address Pointer.
DS7000591F-page 47
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 4-3:
DATA MEMORY MAP FOR DEVICES WITH 4-KBYTE RAM
MSB
Address
MSb
2-Kbyte
SFR Space
LSb
0x0000
0x0001
SFR Space
0x07FF
0x0801
0x0FFF
0x1001
0x07FE
0x0800
X Data RAM (X)
Y Data RAM (Y)
0x0FFE
0x1000
0x17FF
0x1801
0x17FE
0x1800
0x8001
0x8000
6-Kbyte
Near Data
Space
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
DS7000591F-page 48
LSB
Address
16 Bits
0xFFFE
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 4-4:
DATA MEMORY MAP FOR DEVICES WITH 8-KBYTE RAM
MSB
Address
MSb
2-Kbyte
SFR Space
LSB
Address
16 Bits
LSb
0x0000
0x0001
SFR Space
0x07FF
0x0801
0x07FE
0x0800
X Data RAM (X)
0x17FF
0x1801
0x17FE
0x1800
8-Kbyte
Near Data
Space
Y Data RAM (Y)
0x1FFF
0x2001
0x1FFE
0x27FF
0x2801
0x27FE
0x2800
0x8001
0x8000
0x2000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
 2009-2014 Microchip Technology Inc.
0xFFFE
DS7000591F-page 49
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 4-5:
DATA MEMORY MAP FOR DEVICES WITH 9-KBYTE RAM
MSB
Address
MSb
2-Kbyte
SFR Space
LSB
Address
16 Bits
LSb
0x0000
0x0001
SFR Space
0x07FF
0x0801
0x07FE
0x0800
X Data RAM (X)
0x17FF
0x1801
0x17FE
0x1800
8-Kbyte
Near Data
Space
Y Data RAM (Y)
0x1FFF
0x2001
0x1FFE
0x27FF
0x2801
0x27FE
0x2800
0x2000
DMA RAM
0x2BFF
0x2C01
0x2BFE
0x2C00
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
DS7000591F-page 50
0xFFFE
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
4.2.5
X AND Y DATA SPACES
The core has two data spaces, X and Y. These data
spaces can be considered either separate (for some
DSP instructions), or as one unified linear address
range (for MCU instructions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms
such as Finite Impulse Response (FIR) filtering and
Fast Fourier Transform (FFT).
The X data space is used by all instructions and
supports all addressing modes. X data space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
data space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MAC class).
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED, EDAC,
MAC, MOVSAC, MPY, MPY.N and MSC) to provide two
concurrent data read paths.
Both the X and Y data spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for writes to X data space.
 2009-2014 Microchip Technology Inc.
All data memory writes, including in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent and is not user-programmable.
All Effective Addresses (EAs) are 16 bits wide and point
to bytes within the data space. Therefore, the data
space address range is 64 Kbytes, or 32K words,
though the implemented memory locations vary by
device.
4.2.6
DMA RAM
Some devices contain 1 Kbyte of dual ported DMA
RAM, which is located at the end of Y data space.
Memory locations that are part of Y data RAM and are in
the DMA RAM space are accessible simultaneously by
the CPU and the DMA Controller module. DMA RAM is
utilized by the DMA Controller to store data to be
transferred to various peripherals using DMA, as well as
data transferred from various peripherals using DMA.
The DMA RAM can be accessed by the DMA Controller
without having to steal cycles from the CPU.
When the CPU and the DMA Controller attempt to
concurrently write to the same DMA RAM location, the
hardware ensures that the CPU is given precedence in
accessing the DMA RAM location. Therefore, the DMA
RAM provides a reliable means of transferring DMA
data without ever having to stall the CPU.
DS7000591F-page 51
File
Name
SFR
Addr
CPU CORE REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
WREG0
0000
Working Register 0
0000
WREG1
0002
Working Register 1
0000
WREG2
0004
Working Register 2
0000
WREG3
0006
Working Register 3
0000
WREG4
0008
Working Register 4
0000
WREG5
000A
Working Register 5
0000
WREG6
000C
Working Register 6
0000
WREG7
000E
Working Register 7
0000
WREG8
0010
Working Register 8
0000
WREG9
0012
Working Register 9
0000
WREG10
0014
Working Register 10
0000
WREG11
0016
Working Register 11
0000
 2009-2014 Microchip Technology Inc.
WREG12
0018
Working Register 12
0000
WREG13
001A
Working Register 13
0000
WREG14
001C
Working Register 14
0000
WREG15
001E
Working Register 15
0800
SPLIM
0020
Stack Pointer Limit Register
xxxx
ACCAL
0022
ACCAL
xxxx
ACCAH
0024
ACCAH
ACCAU
0026
ACCBL
0028
ACCBL
ACCBH
002A
ACCBH
ACCBU
002C
PCL
002E
PCH
0030
—
—
—
—
—
—
—
—
TBLPAG
0032
—
—
—
—
—
—
—
PSVPAG
0034
—
—
—
—
—
—
—
RCOUNT
0036
REPEAT Loop Counter Register
DCOUNT
0038
DCOUNT<15:0>
DOSTARTL
003A
ACCA<39>
ACCB<39>
ACCA<39>
ACCB<39>
ACCA<39>
ACCB<39>
ACCA<39>
ACCB<39>
ACCA<39>
ACCB<39>
ACCA<39>
ACCB<39>
xxxx
ACCA<39> ACCA<39>
ACCAU
xxxx
xxxx
ACCB<39> ACCB<39>
ACCBU
xxxx
Program Counter High Byte Register
0000
—
Table Page Address Pointer Register
0000
—
Program Memory Visibility Page Address Pointer Register
0000
Program Counter Low Byte Register
0000
xxxx
xxxx
DOSTARTL<15:1>
DOSTARTH
003C
DOENDL
003E
DOENDH
0040
—
—
—
—
—
—
—
—
—
—
SR
0042
OA
OB
SA
SB
OAB
SAB
DA
DC
IPL2
IPL1
Legend:
xxxx
—
—
—
—
—
—
—
—
—
—
xxxx
0
xxxx
DOSTARTH<5:0>
00xx
DOENDL<15:1>
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0
DOENDH
IPL0
RA
N
00xx
OV
Z
C
0000
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 52
TABLE 4-1:
File
Name
SFR
Addr
CORCON
0044
MODCON
0046
CPU CORE REGISTER MAP (CONTINUED)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
—
—
—
US
EDT
DL2
DL1
DL0
XMODEN
YMODEN
—
—
BWM3
BWM2
BWM1
BWM0
Bit 7
Bit 6
Bit 5
Bit 4
SATA
SATB
SATDW
ACCSAT
YWM3 YWM2
YWM1
YWM0
Bit 3
Bit 2
Bit 1
Bit 0
IPL3
PSV
RND
IF
XWM3 XWM2 XWM1 XWM0
All
Resets
0000
0000
XMODSRT
0048
XS<15:1>
0
xxxx
XMODEND
004A
XE<15:1>
1
xxxx
YMODSRT
004C
YS<15:1>
0
xxxx
YMODEND
004E
YE<15:1>
1
xxxx
XBREV
0050
BREN
XB14
DISICNT
0052
—
—
Legend:
XB13
XB12
XB11
XB10
XB9
XB8
XB7
XB6
Disable Interrupts Counter Register
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
XB5
XB4
XB3
XB2
XB1
XB0
xxxx
xxxx
DS7000591F-page 53
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-1:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32GS608/610 AND dsPIC33FJ64GS608/610 DEVICES
File
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
CNEN1
0060
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CNEN2
0062
—
—
—
—
—
—
—
—
CN23IE
CN22IE
CN21IE
CN20IE
CN19IE
CN18IE
CNPU1
0068
CN8PUE
CN7PUE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CNPU2
006A
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-3:
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE
—
—
—
—
—
—
—
—
Bit 0
All
Resets
CN1IE
CN0IE
0000
CN17IE
CN16IE
0000
CN0PUE
0000
CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES
File
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
CNEN1
0060
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
CNEN2
0062
—
—
—
—
—
—
—
—
CNPU1
0068
CN8PUE
CN7PUE
CNPU2
006A
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE
—
—
—
—
—
—
—
—
Bit 7
Bit 0
All
Resets
CN1IE
CN0IE
0000
CN17IE
CN16IE
0000
CN0PUE
0000
CN18PUE CN17PUE CN16PUE
0000
Bit 6
Bit 5
Bit 4
Bit 3
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN23IE
CN22IE
—
—
—
CN18IE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
—
—
—
CN23PUE CN22PUE
Bit 2
Bit 1
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 54
TABLE 4-2:
File
Name
SFR
Addr
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS610 DEVICES
Bit 15
Bit 14
Bit 13
INTCON1 0080 NSTDIS
OVAERR
OVBERR
INTCON2 0082 ALTIVT
DISI
—
—
—
DMA1IF
ADIF
U1TXIF
U2RXIF
INT2IF
—
Bit 12
Bit 11
Bit 6
Bit 4
OSCFAIL
—
0000
INT1EP
INT0EP
0000
OC1IF
IC1IF
INT0IF
0000
CNIF
AC1IF
MI2C1IF
SI2C1IF
0000
Bit 8
OVATE
OVBTE
COVTE
—
—
—
—
—
—
INT4EP
INT3EP
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
OC2IF
IC2IF
DMA0IF
T5IF
T4IF
OC4IF
OC3IF
DMA2IF
—
—
—
SFTACERR DIV0ERR
Bit 5
All
Resets
Bit 9
COVAERR COVBERR
Bit 7
Bit 0
Bit 10
Bit 3
Bit 2
Bit 1
STKERR
INT2EP
T1IF
INT1IF
DMACERR MATHERR ADDRERR
DS7000591F-page 55
IFS0
0084
IFS1
0086 U2TXIF
IFS2
0088
—
—
—
—
—
—
—
—
—
IC4IF
IC3IF
DMA3IF
C1IF
C1RXIF
SPI2IF
SPI2EIF
0000
IFS3
008A
—
—
—
—
—
QEI1IF
PSEMIF
—
—
INT4IF
INT3IF
—
—
MI2C2IF
SI2C2IF
—
0000
IFS4
008C
—
—
—
—
QEI2IF
—
PSESMIF
—
—
C1TXIF
—
—
—
U2EIF
U1EIF
—
0000
IFS5
008E PWM2IF
PWM1IF
ADCP12IF
—
—
—
—
—
—
—
—
ADCP11IF
ADCP10IF
ADCP9IF
ADCP8IF
—
0000
IFS6
0090 ADCP1IF ADCP0IF
—
—
—
—
AC4IF
AC3IF
AC2IF
PWM9IF
PWM8IF
PWM7IF
PWM6IF
PWM5IF
PWM4IF
PWM3IF
0000
IFS7
0092
—
—
—
—
—
—
—
—
—
—
ADCP7IF
ADCP6IF
ADCP5IF
ADCP4IF
ADCP3IF
ADCP2IF
0000
IEC0
0094
—
DMA1IE
ADIE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
DMA0IE
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0096 U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
DMA2IE
—
—
—
INT1IE
CNIE
AC1IE
MI2C1IE
SI2C1IE
0000
IEC2
0098
—
—
—
—
—
—
—
—
—
IC4IE
IC3IE
DMA3IE
C1IE
C1RXIE
SPI2IE
SPI2EIE
0000
IEC3
009A
—
—
—
—
—
QEI1IE
PSEMIE
—
—
INT4IE
INT3IE
—
—
MI2C2IE
SI2C2IE
—
0000
IEC4
009C
—
—
—
—
QEI2IE
—
PSESMIE
—
—
C1TXIE
—
—
—
U2EIE
U1EIE
—
0000
IEC5
009E PWM2IE
PWM1IE
ADCP12IE
—
—
—
—
—
—
—
—
ADCP11IE
ADCP10IE
ADCP9IE
ADCP8IE
—
0000
IEC6
00A0 ADCP1IE ADCP0IE
—
—
—
—
AC4IE
AC3IE
AC2IE
PWM9IE
PWM8IE
PWM7IE
PWM6IE
PWM5IE
PWM4IE
PWM3IE
0000
IEC7
00A2
—
—
—
—
—
—
—
—
—
—
ADCP7IE
ADCP6IE
ADCP5IE
ADCP4IE
ADCP3IE
ADCP2IE
0000
IPC0
00A4
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP1
INT0IP0
4444
IPC1
00A6
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
DMA0IP2
DMA0IP1
DMA0IP0
4444
IPC2
00A8
—
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPI1EIP2
SPI1EIP1
SPI1EIP0
—
T3IP2
T3IP1
T3IP0
0444
IPC3
00AA
—
—
—
—
—
DMA1IP2 DMA1IP1 DMA1IP0
—
ADIP2
ADIP1
ADIP0
—
U1TXIP2
U1TXIP1
U1TXIP0
0044
IPC4
00AC
—
CNIP2
CNIP1
CNIP0
—
AC1IP2
AC1IP1
AC1IP0
—
MI2C1IP2
MI2C1IP1
MI2C1IP0
—
SI2C1IP2
SI2C1IP1
SI2C1IP0
4444
IPC5
00AE
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP2
INT1IP1
INT1IP0
0004
IPC6
00B0
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
—
OC3IP2
OC3IP1
OC3IP0
—
DMA2IP2
DMA2IP1
DMA2IP0
4444
IPC7
00B2
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2
T5IP1
T5IP0
4444
IPC8
00B4
—
C1IP2
C1IP1
C1IP0
—
C1RXIP2
C1RXIP1
C1RXIP0
—
SPI2IP2
SPI2IP1
SPI2IP0
—
SPI2EIP2
SPI2EIP1
SPI2EIP0
4444
IPC9
00B6
—
—
—
—
—
IC4IP2
IC4IP1
IC4IP0
—
IC3IP2
IC3IP1
IC3IP0
—
DMA3IP2
DMA3IP1
DMA3IP0
0444
IPC12
00BC
—
—
—
—
—
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
—
—
—
0440
IPC13
00BE
—
—
—
—
—
—
INT3IP2
INT3IP1
INT3IP0
—
—
—
—
0440
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
MI2C2IP2 MI2C2IP1 MI2C2IP0
INT4IP2
INT4IP1
INT4IP0
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-4:
File
Name
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS610 DEVICES (CONTINUED)
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
IPC14
00C0
—
—
—
—
—
QEI1IP2
QEI1IP1
QEI1IP0
—
PSEMIP2
PSEMIP1
PSEMIP0
—
—
—
—
0440
IPC16
00C4
—
—
—
—
—
U2EIP2
U2EIP1
U2EIP0
—
U1EIP2
U1EIP1
U1EIP0
—
—
—
—
0440
IPC17
00C6
—
—
—
—
—
C1TXIP2
C1TXIP1
C1TXIP0
—
—
—
—
—
—
—
—
0400
IPC18
00C8
—
QEI2IP2
QEI2IP1
QEI2IP0
—
—
—
—
—
PSESMIP2 PSESMIP1 PSESMIP0
—
—
—
—
4040
IPC20
00CC
—
—
ADCP8IP2 ADCP8IP1
ADCP8IP0
—
—
—
—
4440
IPC21
00CE
—
—
—
—
—
—
ADCP12IP2 ADCP12IP1 ADCP12IP0
—
IPC23
00D2
—
PWM2IP2
PWM2IP1
PWM2IP0
—
PWM1IP2 PWM1IP1 PWM1IP0
—
—
—
—
—
—
—
—
4400
IPC24
00D4
—
PWM6IP2
PWM6IP1
PWM6IP0
—
PWM5IP2 PWM5IP1 PWM5IP0
—
PWM4IP2
PWM4IP1
PWM4IP0
—
PWM3IP2
PWM3IP1
PWM3IP0
4444
IPC25
00D6
—
AC2IP2
AC2IP1
AC2IP0
—
PWM9IP2 PWM9IP1 PWM9IP0
—
PWM8IP2
PWM8IP1
PWM8IP0
—
PWM7IP2
PWM7IP1
PWM7IP0
4444
IPC26
00D8
—
—
—
—
—
—
AC4IP2
AC4IP1
AC4IP0
—
AC3IP2
AC3IP1
AC3IP0
0044
IPC27
00DA
—
ADCP1IP2 ADCP1IP1 ADCP1IP0
—
ADCP0IP2 ADCP0IP1 ADCP0IP0
—
—
—
—
—
—
—
—
4400
IPC28
00DC
—
ADCP5IP2 ADCP5IP1 ADCP5IP0
—
ADCP4IP2 ADCP4IP1 ADCP4IP0
—
ADCP3IP2 ADCP3IP1
ADCP3IP0
—
ADCP2IP2 ADCP2IP1
ADCP2IP0
4444
IPC29
00DE
—
—
—
—
—
—
—
—
—
ADCP7IP2 ADCP7IP1
ADCP7IP0
—
ADCP6IP2 ADCP6IP1
ADCP6IP0
0044
INTTREG 00E0
—
—
—
—
ILR3
ILR2
ILR1
ILR0
—
VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
Legend:
ADCP10IP2 ADCP10IP1 ADCP10IP0
—
ADCP9IP2 ADCP9IP1 ADCP9IP0
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ADCP11IP2 ADCP11IP1 ADCP11IP0
0044
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 56
TABLE 4-4:
File
Name
SFR
Addr
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS608 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
INTCON1 0080
NSTDIS
OVAERR
OVBERR
INTCON2 0082
ALTIVT
DISI
—
—
—
COVAERR COVBERR
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
OVATE
OVBTE
COVTE
—
—
—
—
—
—
INT4EP
INT3EP
INT2EP
SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR
Bit 0
All
Resets
OSCFAIL
—
0000
INT1EP
INT0EP
0000
Bit 1
DS7000591F-page 57
IFS0
0084
—
DMA1IF
ADIF
U1TXIF
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
OC2IF
IC2IF
DMA0IF
T1IF
OC1IF
IC1IF
INT0IF
0000
IFS1
0086
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
DMA2IF
—
—
—
INT1IF
CNIF
AC1IF
MI2C1IF
SI2C1IF
0000
IFS2
0088
—
—
—
—
—
—
—
—
—
IC4IF
IC3IF
DMA3IF
C1IF
C1RXIF
SPI2IF
SPI2EIF
0000
IFS3
008A
—
—
—
—
—
QEI1IF
PSEMIF
—
—
INT4IF
INT3IF
—
—
MI2C2IF
SI2C2IF
—
0000
IFS4
008C
—
—
—
—
QEI2IF
—
PSESMIF
—
—
C1TXIF
—
—
—
U2EIF
U1EIF
—
0000
IFS5
008E PWM2IF
PWM1IF
ADCP12IF
—
—
—
—
—
—
—
—
—
—
—
ADCP8IF
—
0000
IFS6
0090 ADCP1IF ADCP0IF
—
—
—
—
AC4IF
AC3IF
AC2IF
—
PWM8IF
PWM7IF
PWM6IF
PWM5IF
PWM4IF
PWM3IF
0000
IFS7
0092
—
—
—
—
—
—
—
—
—
—
ADCP7IF
ADCP6IF
ADCP5IF
ADCP4IF ADCP3IF ADCP2IF
0000
IEC0
0094
—
DMA1IE
ADIE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
DMA0IE
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0096
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
DMA2IE
—
—
—
INT1IE
CNIE
AC1IE
MI2C1IE
SI2C1IE
0000
IEC2
0098
—
—
—
—
—
—
—
—
—
IC4IE
IC3IE
DMA3IE
C1IE
C1RXIE
SPI2IE
SPI2EIE
0000
IEC3
009A
—
—
—
—
—
QEI1IE
PSEMIE
—
—
INT4IE
INT3IE
—
—
MI2C2IE
SI2C2IE
—
0000
IEC4
009C
—
—
—
—
QEI2IE
—
PSESMIE
—
—
C1TXIE
—
—
—
U2EIE
U1EIE
—
0000
IEC5
009E PWM2IE
PWM1IE
ADCP12IE
—
—
—
—
—
—
—
—
—
—
—
ADCP8IE
—
0000
IEC6
00A0 ADCP1IE ADCP0IE
—
—
—
—
AC4IE
AC3IE
AC2IE
—
PWM8IE
PWM7IE
PWM6IE
PWM5IE
PWM4IE
PWM3IE
0000
IEC7
00A2
—
—
—
—
—
—
—
—
—
—
ADCP7IE
ADCP6IE
ADCP5IE
ADCP4IE ADCP3IE ADCP2IE
0000
IPC0
00A4
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP0
4444
IPC1
00A6
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
DMA0IP2 DMA0IP1 DMA0IP0
4444
IPC2
00A8
—
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPI1EIP2
SPI1EIP1
SPI1EIP0
—
T3IP2
T3IP1
T3IP0
4444
IPC3
00AA
—
—
—
—
—
DMA1IP2
DMA1IP1
DMA1IP0
—
ADIP2
ADIP1
ADIP0
—
U1TXIP2
U1TXIP1
U1TXIP0
4444
IPC4
00AC
—
CNIP2
CNIP1
CNIP0
—
AC1IP2
AC1IP1
AC1IP0
—
MI2C1IP2
MI2C1IP1
MI2C1IP0
—
SI2C1IP2 SI2C1IP1 SI2C1IP0
4444
IPC5
00AE
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP2
INT1IP0
0004
IPC6
00B0
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
—
OC3IP2
OC3IP1
OC3IP0
—
DMA2IP2 DMA2IP1 DMA2IP0
4444
IPC7
00B2
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
—
INT2IP2
INT2IP1
INT2IP0
—
IPC8
00B4
—
C1IP2
C1IP1
C1IP0
—
C1RXIP2
C1RXIP1
C1RXIP0
—
SPI2IP2
SPI2IP1
SPI2IP0
—
SPI2EIP2 SPI2EIP1 SPI2EIP0
4444
IPC9
00B6
—
—
—
—
—
IC4IP2
IC4IP1
IC4IP0
—
IC3IP2
IC3IP1
IC3IP0
—
DMA3IP2 DMA3IP1 DMA3IP0
0444
IPC12
00BC
—
—
—
—
—
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
—
—
—
0440
IPC13
00BE
—
—
—
—
—
INT4IP2
INT4IP1
INT4IP0
—
INT3IP2
INT3IP1
INT3IP0
—
—
—
—
0440
IPC14
00C0
—
—
—
—
—
QEI1IP2
QEI1IP0
QEI1IP0
—
PSEMIP2
PSEMIP1
PSEMIP0
—
—
—
—
0440
IPC16
00C4
—
—
—
—
—
U2EIP2
U2EIP1
U2EIP0
—
U1EIP2
U1EIP1
U1EIP0
—
—
—
—
0440
IPC17
00C6
—
—
—
—
—
C1TXIP2
C1TXIP1
C1TXIP0
—
—
—
—
—
—
—
—
0400
IPC18
00C8
—
QEI2IP2
QEI2IP1
QEI2IP0
—
—
—
—
—
—
—
—
—
4040
Legend:
MI2C2IP2 MI2C2IP1 MI2C2IP0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PSESMIP2 PSESMIP1 PSESMIP0
T5IP2
INT0IP1
INT1IP1
T5IP1
T5IP0
4444
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-5:
File
Name
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS608 DEVICES (CONTINUED)
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
IPC20
00CC
—
—
—
—
—
—
—
—
—
IPC21
00CE
—
—
—
—
—
—
—
—
—
IPC23
00D2
—
PWM2IP2
PWM2IP1
PWM2IP0
—
PWM1IP2 PWM1IP1 PWM1IP0
—
—
—
IPC24
00D4
—
PWM6IP2
PWM6IP2
PWM6IP2
—
PWM5IP2 PWM5IP1 PWM5IP0
—
PWM4IP2
IPC25
00D6
—
AC2IP2
AC2IP1
AC2IP0
—
—
—
—
—
IPC26
00D8
—
—
—
—
—
—
—
—
IPC27
00DA
—
ADCP1IP2 ADCP1IP1
ADCP1IP0
—
IPC28
00DC
—
ADCP5IP2 ADCP5IP1
ADCP5IP0
—
IPC29
00DE
—
—
—
—
—
—
—
—
INTTREG 00E0
—
—
—
—
ILR3
ILR2
ILR1
ILR0
Legend:
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ADCP8IP2 ADCP8IP1 ADCP8IP0
—
—
—
—
0040
ADCP12IP2 ADCP12IP1 ADCP12IP0
—
—
—
—
0040
—
—
—
—
—
4400
PWM4IP1
PWM4IP0
—
PWM3IP2 PWM3IP1 PWM3IP0
4444
PWM8IP2
PWM8IP1
PWM8IP0
—
PWM7IP2 PWM7IP1 PWM7IP0
4044
—
AC4IP2
AC4IP1
AC4IP0
—
AC3IP2
AC3IP1
AC3IP0
0044
ADCP0IP2 ADCP0IP1 ADCP0IP0
—
—
—
—
—
—
—
—
4400
ADCP4IP2 ADCP4IP1 ADCP4IP0
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 6
Bit 5
Bit 4
ADCP3IP2 ADCP3IP1 ADCP3IP0
—
ADCP2IP2 ADCP2IP1 ADCP2IP0 4444
—
ADCP7IP2 ADCP7IP1 ADCP7IP0
—
ADCP6IP2 ADCP6IP1 ADCP6IP0 0044
—
VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 58
TABLE 4-5:
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS606 DEVICES
File
Name
SFR
Addr
Bit 15
Bit 14
DS7000591F-page 59
Bit 0
All
Resets
INTCON1
0080
NSTDIS
OVAERR
INTCON2
0082
ALTIVT
DISI
—
—
—
OSCFAIL
—
0000
INT1EP
INT0EP
IFS0
0084
—
DMA1IF
ADIF
U1TXIF
0000
OC1IF
IC1IF
INT0IF
IFS1
0086
U2TXIF
U2RXIF
INT2IF
0000
CNIF
AC1IF
MI2C1IF
SI2C1IF
IFS2
0088
—
—
0000
DMA3IF
C1IF
C1RXIF
SPI2IF
SPI2EIF
IFS3
008A
—
0000
INT3IF
—
—
MI2C2IF
SI2C2IF
—
IFS4
008C
—
0000
C1TXIF
—
—
—
U2EIF
U1EIF
—
IFS5
008E PWM2IF
0000
—
—
—
—
—
—
—
—
IFS6
0090 ADCP1IF ADCP0IF
0000
AC3IF
AC2IF
PWM9IF
PWM8IF
PWM7IF
PWM6IF
PWM5IF
PWM4IF
PWM3IF
IFS7
0092
—
0000
—
—
—
—
ADCP7IF
ADCP6IF
ADCP5IF
ADCP4IF ADCP3IF ADCP2IF
IEC0
0094
0000
SPI1IE
SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
DMA0IE
T1IE
OC1IE
IC1IE
INT0IE
IEC1
0000
T4IE
OC4IE
OC3IE
DMA2IE
—
—
—
INT1IE
CNIE
AC1IE
MI2C1IE
SI2C1IE
0000
—
—
—
—
—
—
IC4IE
IC3IE
DMA3IE
C1IE
C1RXIE
SPI2IE
SPI2EIE
0000
—
—
—
QEI1IE
PSEMIE
—
—
INT4IE
INT3IE
—
—
MI2C2IE
SI2C2IE
—
0000
—
—
QEI2IE
—
PSESMIE
—
—
C1TXIE
—
—
—
U2EIE
U1EIE
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
AC4IE
AC3IE
AC2IE
—
—
—
PWM6IE
PWM5IE
PWM4IE
PWM3IE
0000
—
—
—
—
—
—
—
—
—
ADCP7IE
ADCP6IE
ADCP5IE
ADCP4IE ADCP3IE ADCP2IE
0000
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP0
4444
00A6
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
DMA0IP2 DMA0IP1 DMA0IP0
4444
IPC2
00A8
—
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPI1EIP2
SPI1EIP1
SPI1EIP0
—
T3IP2
T3IP1
T3IP0
4444
IPC3
00AA
—
—
—
—
—
DMA1IP2
DMA1IP1 DMA1IP0
—
ADIP2
ADIP1
ADIP0
—
U1TXIP2
U1TXIP1
U1TXIP0
4444
IPC4
00AC
—
CNIP2
CNIP1
CNIP0
—
AC1IP2
AC1IP1
AC1IP0
—
MI2C1IP2
MI2C1IP2
MI2C1IP2
—
SI2C1IP2 SI2C1IP1 SI2C1IP0
4444
IPC5
00AE
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP2
INT1IP0
0004
IPC6
00B0
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
—
OC3IP2
OC3IP1
OC3IP0
—
DMA2IP2 DMA2IP1 DMA2IP0
4444
IPC7
00B2
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
—
INT2IP2
INT2IP1
INT2IP0
—
IPC8
00B4
—
C1IP2
C1IP1
C1IP0
—
C1RXIP2
C1RXIP1
C1RXIP0
—
SPI2IP2
SPI2IP1
SPI2IP0
—
SPI2EIP2 SPI2EIP1 SPI2EIP0
4444
IPC9
00B6
—
—
—
—
—
IC4IP2
IC4IP1
IC4IP0
—
IC3IP2
IC3IP1
IC3IP0
—
DMA3IP2 DMA3IP1 DMA3IP0
0444
IPC12
00BC
—
—
—
—
—
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
—
—
—
0440
IPC13
00BE
—
—
—
—
—
INT4IP2
INT4IP1
INT4IP0
—
INT3IP2
INT3IP1
INT3IP0
—
—
—
—
0440
IPC14
00C0
—
—
—
—
—
QEI1IP2
QEI1IP1
QEI1IP0
—
PSEMIP2
PSEMIP1
PSEMIP0
—
—
—
—
0440
IPC16
00C4
—
—
—
—
—
U2EIP2
U2EIP1
U2EIP0
—
U1EIP2
U1EIP1
U1EIP0
—
—
—
—
0440
IPC17
00C6
—
—
—
—
—
C1TXIP2
C1TXIP1
C1TXIP0
—
—
—
—
—
—
—
—
0400
IPC18
00C8
—
QEI2IP2
QEI2IP1
QEI2IP0
—
—
—
—
—
—
—
—
—
4040
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
OVATE
OVBTE
COVTE
SFTACERR
DIV0ERR
DMACERR
—
—
—
—
—
—
INT4EP
INT3EP
INT2EP
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
OC2IF
IC2IF
DMA0IF
T1IF
T5IF
T4IF
OC4IF
OC3IF
DMA2IF
—
—
—
INT1IF
—
—
—
—
—
—
—
IC4IF
IC3IF
—
—
—
—
QEI1IF
PSEMIF
—
—
INT4IF
—
—
—
QEI2IF
—
PSESMIF
—
—
—
—
—
—
—
—
—
—
—
AC4IF
—
—
—
—
—
—
DMA1IE
ADIE
U1TXIE
U1RXIE
0096
U2TXIE
U2RXIE
INT2IE
T5IE
IEC2
0098
—
—
—
IEC3
009A
—
—
IEC4
009C
—
—
IEC5
009E PWM2IE
IEC6
00A0 ADCP1IE ADCP0IE
IEC7
00A2
—
IPC0
00A4
IPC1
OVBERR COVAERR COVBERR
PWM1IF ADCP12IF
PWM1IE ADCP12IE
MI2C2IP2 MI2C2IP1 MI2C2IP0
Bit 4
Bit 3
Bit 2
MATHERR ADDRERR STKERR
PSESMIP2 PSESMIP1 PSESMIP0
T5IP2
Bit 1
INT0IP1
INT1IP1
T5IP1
T5IP0
4444
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-6:
File
Name
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS606 DEVICES (CONTINUED)
SFR
Addr
Bit 15
IPC21
00CE
—
IPC23
00D2
—
PWM2IP2 PWM2IP1 PWM2IP0
—
PWM1IP2 PWM1IP1 PWM1IP0
—
—
—
—
IPC24
00D4
—
PWM6IP2 PWM6IP1 PWM6IP0
—
PWM5IP2 PWM5IP1 PWM5IP0
—
PWM4IP2
PWM4IP1
PWM4IP0
—
PWM3IP2 PWM3IP1 PWM3IP0
4444
IPC25
00D6
—
AC2IP2
AC2IP1
AC2IP0
—
PWM9IP2 PWM9IP1 PWM9IP0
—
PWM8IP2
PWM8IP1
PWM8IP0
—
PWM7IP2 PWM7IP1 PWM7IP0
4000
IPC26
00D8
—
—
—
—
—
—
AC4IP2
AC4IP1
AC4IP0
—
AC3IP2
AC3IP1
AC3IP0
0044
IPC27
00DA
—
ADCP1IP2 ADCP1IP1 ADCP1IP0
—
ADCP0IP2 ADCP0IP1 ADCP0IP0
—
—
—
—
—
—
—
—
4400
IPC28
00DC
—
ADCP5IP2 ADCP5IP1 ADCP5IP0
—
ADCP4IP2 ADCP4IP1 ADCP4IP0
—
ADCP3IP2
ADCP3IP1
ADCP3IP0
—
ADCP2IP2 ADCP2IP1 ADCP2IP0
4444
IPC29
00DE
—
—
—
—
—
—
—
—
—
ADCP7IP2
ADCP7IP1
ADCP7IP0
—
ADCP6IP2 ADCP6IP1 ADCP6IP0
0004
INTTREG 00E0
—
—
—
—
ILR3
ILR2
ILR1
ILR0
—
VECNUM6
VECNUM5
VECNUM4
VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
Legend:
Bit 14
Bit 13
Bit 12
Bit 11
—
—
—
—
Bit 10
Bit 9
Bit 8
Bit 7
—
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 6
Bit 5
Bit 4
ADCP12IP2 ADCP12IP1 ADCP12IP0
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
—
—
0040
—
—
—
—
4400
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 60
TABLE 4-6:
File
Name
SFR
Addr
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
INTCON1 0080
NSTDIS
OVAERR
INTCON2 0082
ALTIVT
DISI
—
—
—
OVBERR COVAERR COVBERR
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
OVATE
OVBTE
COVTE
—
—
—
—
—
—
INT4EP
INT3EP
INT2EP
SFTACERR DIV0ERR
Bit 5
—
Bit 4
Bit 3
Bit 2
MATHERR ADDRERR STKERR
Bit 0
All
Resets
OSCFAIL
—
0000
INT1EP
INT0EP
0000
Bit 1
DS7000591F-page 61
IFS0
0084
—
—
ADIF
U1TXIF
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
OC2IF
IC2IF
—
T1IF
OC1IF
IC1IF
INT0IF
0000
IFS1
0086
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
—
—
—
—
INT1IF
CNIF
—
MI2C1IF
SI2C1IF
0000
IFS2
0088
—
—
—
—
—
—
—
—
—
IC4IF
IC3IF
—
—
—
SPI2IF
SPI2EIF
0000
IFS3
008A
—
—
—
—
—
QEI1IF
PSEMIF
—
—
INT4IF
INT3IF
—
—
MI2C2IF
SI2C2IF
—
0000
IFS4
008C
—
—
—
—
—
—
PSESMIF
—
—
—
—
—
—
U2EIF
U1EIF
—
0000
IFS5
008E
PWM2IF
PWM1IF ADCP12IF
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IFS6
0090 ADCP1IF
ADCP0IF
—
—
—
—
—
—
—
—
—
—
PWM6IF
PWM5IF
PWM4IF
PWM3IF
0000
IFS7
0092
—
—
—
—
—
—
—
—
—
—
ADCP7IF
ADCP6IF
ADCP5IF
ADCP4IF
ADCP3IF
ADCP2IF
0000
IEC0
0094
—
—
ADIE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
—
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0096
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
—
—
—
—
INT1IE
CNIE
—
MI2C1IE
SI2C1IE
0000
IEC2
0098
—
—
—
—
—
—
—
—
—
IC4IE
IC3IE
—
—
—
SPI2IE
SPI2EIE
0000
IEC3
009A
—
—
—
—
—
QEI1IE
PSEMIE
—
—
INT4IE
INT3IE
—
—
MI2C2IE
SI2C2IE
—
0000
IEC4
009C
—
—
—
—
—
—
PSESMIE
—
—
—
—
—
—
U2EIE
U1EIE
—
0000
IEC5
009E
PWM2IE
PWM1IE ADCP12IE
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IEC6
00A0
—
ADCP0IE
—
—
—
—
—
—
—
—
—
—
PWM6IE
PWM5IE
PWM4IE
PWM3IE
0000
IEC7
00A2
—
—
—
—
—
—
—
—
—
ADCP7IE
ADCP6IE
ADCP5IE
ADCP4IE
ADCP3IE
ADCP2IE
0000
IPC0
00A4
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP1
INT0IP0
4444
IPC1
00A6
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
—
—
—
4440
IPC2
00A8
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPI1EIP2
SPI1EIP1
SPI1EIP0
—
T3IP2
T3IP1
T3IP0
4444
IPC3
00AA
—
—
—
—
—
—
—
—
ADIP2
ADIP1
ADIP0
—
U1TXIP2
U1TXIP1
U1TXIP0
0044
IPC4
00AC
—
CNIP2
CNIP1
CNIP0
—
—
—
—
—
—
SI2C1IP2
SI2C1IP1
SI2C1IP0
4444
IPC5
00AE
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP2
INT1IP1
INT1IP0
0004
IPC6
00B0
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
—
OC3IP2
OC3IP1
OC3IP0
—
—
—
—
4440
IPC7
00B2
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2
T5IP1
T5IP0
4444
IPC8
00B4
—
—
—
—
—
—
—
—
—
SPI2IP2
SPI2IP1
SPI2IP0
—
SPI2EIP0
0044
IPC9
00B6
—
—
—
—
—
IC4IP2
IC4IP1
IC4IP0
—
IC3IP2
IC3IP1
IC3IP0
—
—
—
—
0440
IPC12
00BC
—
—
—
—
—
MI2C2IP2
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
—
—
—
0440
IPC13
00BE
—
—
—
—
—
INT4IP2
INT4IP1
INT4IP0
—
INT3IP2
INT3IP1
INT3IP0
—
—
—
—
0440
IPC14
00C0
—
—
—
—
—
QEI1IP2
QEI1IP1
QEI1IP0
—
PSEMIP2
PSEMIP1
PSEMIP0
—
—
—
—
0440
IPC16
00C4
—
—
—
—
—
U2EIP2
U2EIP1
U2EIP0
—
U1EIP2
U1EIP1
U1EIP0
—
—
—
—
0440
IPC18
00C8
—
—
—
—
—
—
—
—
—
—
—
—
—
0040
IPC23
00D2
—
—
PWM1IP2
—
—
—
—
4400
Legend:
PWM2IP2 PWM2IP1 PWM2IP0
MI2C2IP1 MI2C2IP0
PWM1IP1 PWM1IP0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
MI2C1IP2 MI2C1IP1 MI2C1IP0
PSESMIP2 PSESMIP1 PSESMIP0
—
—
—
SPI2EIP2 SPI2EIP1
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-7:
File
Name
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES (CONTINUED)
All
Resets
SFR
Addr
Bit 15
IPC24
00D4
—
PWM6IP2 PWM6IP1 PWM6IP0
—
PWM5IP2
PWM5IP1 PWM5IP0
—
IPC27
00DA
—
ADCP1IP2 ADCP1IP1 ADCP1IP0
—
ADCP0IP2 ADCP0IP1 ADCP0IP0
—
IPC28
00DC
—
ADCP5IP2 ADCP5IP1 ADCP5IP0
—
ADCP4IP2 ADCP4IP1 ADCP4IP0
—
ADCP3IP2 ADCP3IP1 ADCP3IP0
—
ADCP2IP2 ADCP2IP1 ADCP2IP0
4444
IPC29
00DE
—
—
—
—
—
—
—
—
—
ADCP7IP2 ADCP7IP1 ADCP7IP0
—
ADCP6IP2 ADCP6IP1 ADCP6IP0
0004
INTTREG 00E0
—
—
—
—
ILR3
ILR2
ILR1
ILR0
—
VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
Legend:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 7
Bit 6
Bit 5
Bit 4
PWM4IP2 PWM4IP1 PWM4IP0
—
—
—
Bit 3
—
—
Bit 2
Bit 1
Bit 0
PWM3IP2 PWM3IP1 PWM3IP0
—
—
—
4444
4400
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 62
TABLE 4-7:
File
Name
SFR
Addr
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS610 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
INTCON1 0080
NSTDIS
OVAERR
OVBERR
INTCON2 0082
ALTIVT
DISI
—
—
—
COVAERR COVBERR
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
OVATE
OVBTE
COVTE
—
—
—
—
—
—
INT4EP
INT3EP
SFTACERR DIV0ERR
Bit 5
—
Bit 4
Bit 3
MATHERR ADDRERR
Bit 0
All
Resets
OSCFAIL
—
0000
INT1EP
INT0EP
0000
Bit 2
Bit 1
STKERR
INT2EP
DS7000591F-page 63
IFS0
0084
—
—
ADIF
U1TXIF
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
OC2IF
IC2IF
—
T1IF
OC1IF
IC1IF
INT0IF
0000
IFS1
0086
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
—
—
—
—
INT1IF
CNIF
AC1IF
MI2C1IF
SI2C1IF
0000
IFS2
0088
—
—
—
—
—
—
—
—
—
IC4IF
IC3IF
—
—
—
SPI2IF
SPI2EIF
0000
IFS3
008A
—
—
—
—
—
QEI1IF
PSEMIF
—
—
INT4IF
INT3IF
—
—
MI2C2IF
SI2C2IF
—
0000
IFS4
008C
—
—
—
—
QEI2IF
—
PSESMIF
—
—
—
—
—
—
U2EIF
U1EIF
—
0000
IFS5
008E PWM2IF
PWM1IF
ADCP12IF
—
—
—
—
—
—
—
—
ADCP9IF
ADCP8IF
—
0000
IFS6
0090 ADCP1IF ADCP0IF
—
—
—
—
AC4IF
AC3IF
AC2IF
PWM9IF
PWM8IF
PWM7IF
PWM6IF
PWM5IF
PWM4IF
PWM3IF
0000
IFS7
0092
—
—
—
—
—
—
—
—
—
—
ADCP7IF
ADCP6IF
ADCP5IF
ADCP4IF
ADCP3IF
ADCP2IF
0000
IEC0
0094
—
—
ADIE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
—
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0096
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
—
—
—
—
INT1IE
CNIE
AC1IE
MI2C1IE
SI2C1IE
0000
IEC2
0098
—
—
—
—
—
—
—
—
—
IC4IE
IC3IE
—
—
—
SPI2IE
SPI2EIE
0000
IEC3
009A
—
—
—
—
—
QEI1IE
PSEMIE
—
—
INT4IE
INT3IE
—
—
MI2C2IE
SI2C2IE
—
0000
IEC4
009C
—
—
—
—
QEI2IE
—
PSESMIE
—
—
—
—
—
—
U2EIE
U1EIE
—
0000
IEC5
009E PWM2IE
PWM1IE
ADCP12IE
—
—
—
—
—
—
—
—
ADCP8IE
—
0000
IEC6
00A0 ADCP1IE ADCP0IE
—
—
—
—
AC4IE
AC3IE
AC2IE
PWM9IE
PWM8IE
PWM7IE
PWM6IE
PWM5IE
PWM4IE
PWM3IE
0000
IEC7
00A2
—
—
—
—
—
—
—
—
—
—
ADCP7IE
ADCP6IE
ADCP5IE
ADCP4IE
ADCP3IE
ADCP2IE
0000
IPC0
00A4
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP1
INT0IP0
4444
IPC1
00A6
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
—
—
—
4440
IPC2
00A8
—
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPI1EIP2
SPI1EIP1
SPI1EIP0
—
T3IP2
T3IP1
T3IP0
4444
IPC3
00AA
—
—
—
—
—
—
—
—
—
ADIP2
ADIP1
ADIP0
—
U1TXIP2
U1TXIP1
U1TXIP0
0044
IPC4
00AC
—
CNIP2
CNIP1
CNIP0
—
AC1IP2
AC1IP1
AC1IP0
—
MI2C1IP2
MI2C1IP1
MI2C1IP0
—
SI2C1IP2
SI2C1IP1
SI2C1IP0
4444
IPC5
00AE
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP2
INT1IP1
INT1IP0
0004
IPC6
00B0
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
—
OC3IP2
OC3IP1
OC3IP0
—
—
—
—
4440
IPC7
00B2
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2
T5IP1
T5IP0
4444
IPC8
00B4
—
—
—
—
—
—
—
—
—
SPI2IP2
SPI2IP1
SPI2IP0
—
SPI2EIP2
SPI2EIP1
SPI2EIP0
0044
IPC9
00B6
—
—
—
—
—
IC4IP2
IC4IP1
IC4IP0
—
IC3IP2
IC3IP1
IC3IP0
—
—
—
—
0440
IPC12
00BC
—
—
—
—
—
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
—
—
—
0440
IPC13
00BE
—
—
—
—
—
INT4IP2
INT4IP1
INT4IP0
—
INT3IP2
INT3IP1
INT3IP0
—
—
—
—
0440
IPC14
00C0
—
—
—
—
—
QEI1IP2
QEI1IP1
QEI1IP0
—
PSEMIP2
PSEMIP1
PSEMIP0
—
—
—
—
0440
IPC16
00C4
—
—
—
—
—
U2EIP2
U2EIP1
U2EIP0
—
U1EIP2
U1EIP1
U1EIP0
—
—
—
—
0440
IPC18
00C8
—
QEI2IP2
QEI2IP1
QEI2IP0
—
—
—
—
—
PSESMIP2 PSESMIP1 PSESMIP0
—
—
—
—
4040
IPC20
00CC
—
—
ADCP8IP2 ADCP8IP1 ADCP8IP0
—
—
—
—
4440
Legend:
ADCP10IP2 ADCP10IP1 ADCP10IP0
—
MI2C2IP2 MI2C2IP1 MI2C2IP0
ADCP9IP2 ADCP9IP1 ADCP9IP0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ADCP11IF ADCP10IF
ADCP11IE ADCP10IE ADCP9IE
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-8:
File
Name
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS610 DEVICES (CONTINUED)
SFR
Addr
Bit 15
IPC21
00CE
—
—
IPC23
00D2
—
PWM2IP2
IPC24
00D4
—
PWM6IP2
IPC25
00D6
—
IPC26
00D8
—
IPC27
00DA
—
ADCP1IP2 ADCP1IP1 ADCP1IP0
—
IPC28
00DC
—
ADCP5IP2 ADCP5IP1 ADCP5IP0
—
IPC29
00DE
—
—
—
—
—
—
—
INTTREG 00E0
—
—
—
—
ILR3
ILR2
ILR1
Legend:
Bit 14
Bit 13
Bit 10
Bit 9
Bit 8
Bit 7
—
—
—
—
Bit 11
—
—
—
PWM2IP1
PWM2IP0
—
PWM1IP2 PWM1IP1 PWM1IP0
—
—
—
—
—
—
—
—
4400
PWM6IP1
PWM6IP0
—
PWM5IP2 PWM5IP1 PWM5IP0
—
PWM4IP2
PWM4IP1
PWM4IP0
—
PWM3IP2
PWM3IP1
PWM3IP0
4444
AC2IP2
AC2IP1
AC2IP0
—
PWM9IP2 PWM9IP1 PWM9IP0
—
PWM8IP2
PWM8IP1
PWM8IP0
—
PWM7IP2
PWM7IP1
PWM7IP0
4444
—
—
—
—
—
AC4IP2
AC4IP1
AC4IP0
—
AC3IP2
AC3IP1
AC3IP0
0044
ADCP0IP2 ADCP0IP1 ADCP0IP0
—
—
—
—
—
—
—
—
4400
ADCP4IP2 ADCP4IP1 ADCP4IP0
—
ADCP3IP2 ADCP3IP1 ADCP3IP0
—
ADCP2IP2 ADCP2IP1 ADCP2IP0
4444
—
—
ADCP7IP2 ADCP7IP1 ADCP7IP0
—
ADCP6IP2 ADCP6IP1 ADCP6IP0
0044
ILR0
—
VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 6
Bit 5
Bit 4
ADCP12IP2 ADCP12IP1 ADCP12IP0
Bit 3
—
Bit 2
Bit 1
Bit 0
All
Resets
Bit 12
ADCP11IP2 ADCP11IP1 ADCP11IP0 0044
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 64
TABLE 4-8:
File
Name
SFR
Addr
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS608
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
INTCON1 0080
NSTDIS
OVAERR
INTCON2 0082
ALTIVT
DISI
—
—
—
OVBERR COVAERR COVBERR
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
OVATE
OVBTE
COVTE
—
—
—
—
—
—
INT4EP
INT3EP
INT2EP
SFTACERR DIV0ERR
Bit 5
—
Bit 4
Bit 3
Bit 2
MATHERR ADDRERR STKERR
Bit 0
All
Resets
OSCFAIL
—
0000
INT1EP
INT0EP
0000
Bit 1
DS7000591F-page 65
IFS0
0084
—
—
ADIF
U1TXIF
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
OC2IF
IC2IF
—
T1IF
OC1IF
IC1IF
INT0IF
0000
IFS1
0086
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
—
—
—
—
INT1IF
CNIF
AC1IF
MI2C1IF
SI2C1IF
0000
IFS2
0088
—
—
—
—
—
—
—
—
—
IC4IF
IC3IF
—
—
—
SPI2IF
SPI2EIF
0000
IFS3
008A
—
—
—
—
—
QEI1IF
PSEMIF
—
—
INT4IF
INT3IF
—
—
MI2C2IF
SI2C2IF
—
0000
IFS4
008C
—
—
—
—
QEI2IF
—
PSESMIF
—
—
—
—
—
—
U2EIF
U1EIF
—
0000
IFS5
008E PWM2IF
PWM1IF
ADCP12IF
—
—
—
—
—
—
—
—
—
—
—
ADCP8IF
—
0000
IFS6
0090 ADCP1IF ADCP0IF
—
—
—
—
AC4IF
AC3IF
AC2IF
—
PWM8IF
PWM7IF
PWM6IF
PWM5IF
PWM4IF
PWM3IF
0000
IFS7
0092
—
—
—
—
—
—
—
—
—
—
ADCP7IF
ADCP6IF
ADCP5IF
ADCP4IF ADCP3IF ADCP2IF
0000
IEC0
0094
—
—
ADIE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
—
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0096
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
—
—
—
—
INT1IE
CNIE
—
MI2C1IE
SI2C1IE
0000
IEC2
0098
—
—
—
—
—
—
—
—
—
IC4IE
IC3IE
—
—
—
SPI2IE
SPI2EIE
0000
IEC3
009A
—
—
—
—
—
QEI1IE
PSEMIE
—
—
INT4IE
INT3IE
—
—
MI2C2IE
SI2C2IE
—
0000
IEC4
009C
—
—
—
—
QEI2IE
—
PSESMIE
—
—
—
—
—
—
U2EIE
U1EIE
—
0000
IEC5
009E PWM2IE
—
—
—
—
—
—
—
—
—
—
—
ADCP8IE
—
0000
IEC6
00A0 ADCP1IE ADCP0IE
—
—
—
—
AC4IE
AC3IE
AC2IE
—
PWM8IE
PWM7IE
PWM6IE
PWM5IE
PWM4IE
PWM3IE
0000
IEC7
00A2
—
—
—
—
—
—
—
—
—
—
ADCP7IE
ADCP6IE
ADCP5IE
ADCP4IE ADCP3IE ADCP2IE
0000
IPC0
00A4
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP1
INT0IP0
4444
IPC1
00A6
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
—
—
—
4440
IPC2
00A8
—
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPI1EIP2
SPI1EIP1
SPI1EIP0
—
T3IP2
T3IP1
T3IP0
4444
IPC3
00AA
—
—
—
—
—
—
—
—
—
ADIP2
ADIP1
ADIP0
—
U1TXIP2
U1TXIP1
U1TXIP0
0044
IPC4
00AC
—
CNIP2
CNIP1
CNIP0
—
AC1IP2
AC1IP1
AC1IP0
—
MI2C1IP2
MI2C1IP1
MI2C1IP0
—
SI2C1IP2 SI2C1IP1 SI2C1IP0
4444
IPC5
00AE
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP2
INT1IP1
INT1IP0
0004
IPC6
00B0
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
—
OC3IP2
OC3IP1
OC3IP0
—
—
—
—
4440
IPC7
00B2
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2
T5IP1
T5IP0
4444
IPC8
00B4
—
—
—
—
—
—
—
—
—
SPI2IP2
SPI2IP1
SPI2IP0
—
IPC9
00B6
—
—
—
—
—
IC4IP2
IC4IP1
IC4IP0
—
IC3IP2
IC3IP1
IC3IP0
—
—
—
—
0440
IPC12
00BC
—
—
—
—
—
MI2C2IP0
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
—
—
—
0440
IPC13
00BE
—
—
—
—
—
INT4IP2
INT4IP1
INT4IP0
—
INT3IP2
INT3IP1
INT3IP0
—
—
—
—
0440
IPC14
00C0
—
—
—
—
—
QEI1IP2
QEI1IP1
QEI1IP0
—
PSEMIP2
PSEMIP1
PSEMIP0
—
—
—
—
0440
IPC16
00C4
—
—
—
—
—
U2EIP2
U2EIP1
U2EIP0
—
U1EIP2
U1EIP1
U1EIP0
—
—
—
—
0440
IPC18
00C8
—
QEI2IP2
QEI2IP1
QEI2IP0
—
—
—
—
—
PSESMIP2 PSESMIP1 PSESMIP0
—
—
—
—
4040
IPC20
00CC
—
—
—
—
—
—
—
—
—
ADCP8IP2 ADCP8IP1 ADCP8IP0
—
—
—
—
0040
Legend:
PWM1IE ADCP12IE
MI2C2IP2 MI2C2IP1
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SPI2EIP2 SPI2EIP1 SPI2EIP0
0044
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-9:
File
Name
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS608 (CONTINUED)
SFR
Addr
Bit 15
IPC21
00CE
—
IPC23
00D2
—
PWM2IP2 PWM2IP1
IPC24
00D4
—
PWM6IP2 PWM6IP1
IPC25
00D6
—
AC2IP2
IPC26
00D8
—
—
IPC27
00DA
—
ADCP1IP2 ADCP1IP1 ADCP1IP0
—
IPC28
00DC
—
ADCP5IP2 ADCP5IP1 ADCP5IP0
—
IPC29
00DE
—
—
—
—
—
—
—
INTTREG 00E0
—
—
—
—
ILR3
ILR2
ILR1
Legend:
Bit 14
Bit 13
Bit 12
Bit 11
—
—
Bit 10
Bit 9
—
—
PWM2IP0
—
PWM1IP2 PWM1IP1
—
—
PWM6IP0
—
PWM5IP2 PWM5IP1
AC2IP1
AC2IP0
—
—
—
—
—
—
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
All
Resets
—
—
—
—
0040
—
—
—
—
4400
Bit 7
—
—
PWM1IP0
—
—
—
—
PWM5IP0
—
PWM4IP2
PWM4IP1
PWM4IP0
—
PWM3IP2 PWM3IP1 PWM3IP0
4444
—
—
—
PWM8IP2
PWM8IP1
PWM8IP0
—
PWM7IP2 PWM7IP1 PWM7IP0
4044
—
—
—
AC4IP2
AC4IP1
AC4IP0
—
AC3IP2
AC3IP1
AC3IP0
0044
ADCP0IP2 ADCP0IP1 ADCP0IP0
—
—
—
—
—
—
—
—
4400
ADCP4IP2 ADCP4IP1 ADCP4IP0
—
ADCP3IP2 ADCP3IP1 ADCP3IP0
—
ADCP2IP2 ADCP2IP1 ADCP2IP0
4444
—
—
ADCP7IP2 ADCP7IP1 ADCP7IP0
—
ADCP6IP2 ADCP6IP1 ADCP6IP0
0044
ILR0
—
VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 6
Bit 3
Bit 8
ADCP12IP2 ADCP12IP1 ADCP12IP1
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 66
TABLE 4-9:
File
Name
SFR
Addr
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS606 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
OVAERR OVBERR COVAERR COVBERR
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
SFTACERR DIV0ERR
Bit 5
—
Bit 4
Bit 3
MATHERR ADDRERR
Bit 2
Bit 1
Bit 0
All
Resets
INTCON1 0080
NSTDIS
OVATE
OVBTE
COVTE
STKERR
OSCFAIL
—
0000
INTCON2 0082
ALTIVT
DISI
—
—
—
—
—
—
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
DS7000591F-page 67
IFS0
0084
—
—
ADIF
U1TXIF
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
OC2IF
IC2IF
—
T1IF
OC1IF
IC1IF
INT0IF
0000
IFS1
0086
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
—
—
—
—
INT1IF
CNIF
AC1IF
MI2C1IF
SI2C1IF
0000
IFS2
0088
—
—
—
—
—
—
—
—
—
IC4IF
IC3IF
—
—
—
SPI2IF
SPI2EIF
0000
IFS3
008A
—
—
—
—
—
QEI1IF
PSEMIF
—
—
INT4IF
INT3IF
—
—
MI2C2IF
SI2C2IF
—
0000
IFS4
008C
—
—
—
—
QEI2IF
—
PSESMIF
—
—
—
—
—
—
U2EIF
U1EIF
—
0000
IFS5
008E PWM2IF
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IFS6
0090 ADCP1IF ADCP0IF
—
—
—
—
AC4IF
AC3IF
AC2IF
—
—
—
PWM6IF
PWM5IF
PWM4IF
PWM3IF
0000
IFS7
0092
—
—
—
—
—
—
—
—
—
—
ADCP7IF
ADCP6IF
ADCP5IF
ADCP4IF
ADCP3IF
ADCP2IF
0000
IEC0
0094
—
—
ADIE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
—
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0096
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
—
—
—
—
INT1IE
CNIE
AC1IE
MI2C1IE
SI2C1IE
0000
IEC2
0098
—
—
—
—
—
—
—
—
—
IC4IE
IC3IE
—
—
—
SPI2IE
SPI2EIE
0000
IEC3
009A
—
—
—
—
—
QEI1IE
PSEMIE
—
—
INT4IE
INT3IE
—
—
MI2C2IE
SI2C2IE
—
0000
IEC4
009C
—
—
—
—
QEI2IE
—
PSESMIE
—
—
—
—
—
—
U2EIE
U1EIE
—
0000
IEC5
009E PWM2IE PWM1IE ADCP12IE
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IEC6
00A0 ADCP1IE ADCP0IE
—
—
—
—
AC4IE
AC3IE
AC2IE
—
—
—
PWM6IE
PWM5IE
PWM4IE
PWM3IE
0000
IEC7
00A2
—
—
—
—
—
—
—
—
—
—
ADCP7IE
ADCP6IE
ADCP5IE
ADCP4IE ADCP3IE ADCP2IE
0000
IPC0
00A4
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP1
INT0IP0
4444
IPC1
00A6
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
—
—
—
4440
IPC2
00A8
—
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPI1EIP2
SPI1EIP1
SPI1EIP0
—
T3IP2
T3IP1
T3IP0
4444
IPC3
00AA
—
—
—
—
—
—
—
—
—
ADIP2
ADIP1
ADIP0
—
U1TXIP2
U1TXIP1
U1TXIP0
0044
IPC4
00AC
—
CNIP2
CNIP1
CNIP0
—
AC1IP2
AC1IP1
AC1IP0
—
MI2C1IP2
MI2C1IP1
MI2C1IP0
—
SI2C1IP2 SI2C1IP1 SI2C1IP0
4444
IPC5
00AE
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP2
INT1IP1
INT1IP0
0004
IPC6
00B0
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
—
OC3IP2
OC3IP1
OC3IP0
—
—
—
—
4440
IPC7
00B2
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2
T5IP1
T5IP0
4444
IPC8
00B4
—
—
—
—
—
—
—
—
—
SPI2IP2
SPI2IP1
SPI2IP0
—
IPC9
00B6
—
—
—
—
—
IC4IP2
IC4IP1
IC4IP0
—
IC3IP2
IC3IP1
IC3IP0
—
—
—
—
0440
IPC12
00BC
—
—
—
—
—
MI2C2IP2
MI2C2IP1
MI2C2IP0
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
—
—
—
0440
IPC13
00BE
—
—
—
—
—
INT4IP2
INT4IP1
INT4IP0
—
INT3IP2
INT3IP1
INT3IP0
—
—
—
—
0440
IPC14
00C0
—
—
—
—
—
QEI1IP2
QEI1IP1
QEI1IP0
—
PSEMIP2
PSEMIP1
PSEMIP0
—
—
—
—
0440
IPC16
00C4
—
—
—
—
—
U2EIP2
U2EIP1
U2EIP0
—
U1EIP2
U1EIP1
U1EIP0
—
—
—
—
0440
IPC18
00C8
—
QEI2IP2
QEI2IP1
QEI2IP0
—
—
—
—
—
PSESMIP2 PSESMIP1 PSESMIP0
—
—
—
—
4040
IPC21
00CE
—
—
—
—
—
—
—
—
—
ADCP12IP2 ADCP12IP1 ADCP12IP0
—
—
—
—
0040
Legend:
PWM1IF ADCP12IF
U1RXIP2 U1RXIP1
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SPI2EIP2 SPI2EIP1 SPI2EIP0
0044
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-10:
File
Name
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS606 DEVICES (CONTINUED)
SFR
Addr
Bit 15
IPC23
00D2
—
IPC24
00D4
—
IPC25
00D6
—
AC2IP2
AC2IP1
IPC26
00D8
—
—
—
IPC27
00DA
—
ADCP1IP2 ADCP1IP1 ADCP1IP0
—
IPC28
00DC
—
ADCP5IP2 ADCP5IP1 ADCP5IP0
—
IPC29
00DE
—
—
—
—
—
—
—
INTTREG 00E0
—
—
—
—
ILR3
ILR2
ILR1
Legend:
Bit 14
Bit 13
Bit 12
Bit 9
Bit 8
Bit 6
Bit 5
Bit 1
Bit 0
All
Resets
—
—
—
4400
Bit 10
PWM2IP2 PWM2IP1 PWM2IP0
—
PWM1IP2
PWM1IP1 PWM1IP0
—
—
PWM6IP2 PWM6IP1 PWM6IP0
—
PWM5IP2
PWM5IP1 PWM5IP0
—
PWM4IP2
AC2IP0
—
—
—
—
—
—
—
—
—
—
—
—
ADCP0IP2 ADCP0IP1 ADCP0IP0
—
ADCP4IP2 ADCP4IP1 ADCP4IP0
—
ADCP3IP2 ADCP3IP1 ADCP3IP0
—
ADCP2IP2 ADCP2IP1 ADCP2IP0
4444
—
—
ADCP7IP2 ADCP7IP1 ADCP7IP0
—
ADCP6IP2 ADCP6IP1 ADCP6IP0
0004
ILR0
—
VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 7
Bit 2
Bit 11
Bit 4
Bit 3
—
—
—
PWM4IP1
PWM4IP0
—
—
—
—
—
—
—
4000
AC4IP2
AC4IP1
AC4IP0
—
AC3IP2
AC3IP1
AC3IP0
0044
—
—
—
—
—
—
—
4400
PWM3IP2 PWM3IP1 PWM3IP0
4444
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 68
TABLE 4-10:
File
Name
SFR
Addr
TIMERS REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TMR1
0100
Timer1 Register
PR1
0102
Period Register 1
T1CON
0104
TMR2
0106
Timer2 Register
TMR3HLD
0108
Timer3 Holding Register (for 32-bit timer operations only)
xxxx
TMR3
010A
Timer3 Register
0000
PR2
010C
Period Register 2
FFFF
PR3
010E
Period Register 3
T2CON
0110
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1 TCKPS0
T32
—
TCS
—
T3CON
0112
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1 TCKPS0
—
—
TCS
—
TMR4
0114
Timer4 Register
TMR5HLD
0116
Timer5 Holding Register (for 32-bit timer operations only)
xxxx
TMR5
0118
Timer5 Register
0000
PR4
011A
Period Register 4
FFFF
PR5
011C
Period Register 5
T4CON
011E
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1 TCKPS0
T32
—
TCS
—
0000
T5CON
0120
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1 TCKPS0
—
—
TCS
—
0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
Legend:
—
TSIDL
—
—
—
—
—
—
FFFF
TGATE
TCKPS1 TCKPS0
—
TSYNC
TCS
—
0000
0000
FFFF
0000
0000
0000
FFFF
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-12:
File
Name
TON
0000
SFR
Addr
IC1BUF
0140
IC1CON
0142
IC2BUF
0144
IC2CON
0146
INPUT CAPTURE REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
—
—
ICSIDL
—
—
—
—
Bit 8
Input 1 Capture Register
—
ICTMR
xxxx
Input 2 Capture Register
DS7000591F-page 69
—
—
ICSIDL
—
—
—
—
—
—
ICSIDL
—
—
—
—
—
—
ICSIDL
—
—
—
—
—
ICTMR
IC3BUF
0148
IC3CON
014A
IC4BUF
014C
IC4CON
014E
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
xxxx
Input 3 Capture Register
—
ICTMR
xxxx
Input 4 Capture Register
—
ICTMR
xxxx
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-11:
File
Name
SFR
Addr
OUTPUT COMPARE REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
OC1RS
0180
Output Compare 1 Secondary Register
OC1R
0182
Output Compare 1 Register
OC1CON
0184
OC2RS
0186
Output Compare 2 Secondary Register
OC2R
0188
Output Compare 2 Register
OC2CON
018A
OC3RS
018C
Output Compare 3 Secondary Register
OC3R
018E
Output Compare 3 Register
OC3CON
0190
—
—
—
OCSIDL
—
—
OCSIDL
—
OCSIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OC4CON
0196
Legend:
—
—
—
All
Resets
—
OCFLT
OCTSEL
OCM2
OCM1
OCM0
0000
—
OCFLT
OCTSEL
OCM2
OCM1
OCM0
0000
xxxx
Output Compare 4 Register
—
Bit 0
xxxx
—
Output Compare 4 Secondary Register
—
Bit 1
xxxx
0192
—
Bit 2
xxxx
—
0194
OCSIDL
Bit 3
xxxx
OC4R
—
Bit 4
xxxx
—
OC4RS
—
Bit 5
—
OCFLT
OCTSEL
OCM2
OCM1
OCM0
0000
xxxx
xxxx
—
—
OCFLT
OCTSEL
OCM2
OCM1
OCM0
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-14:
File
Name
QEI1 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
QEI1CON
01E0
CNTERR
—
QEISIDL
INDX
UPDN
QEIM2 QEIM1 QEIM0
DFLT1CON
01E2
—
—
—
—
—
IMV1
Bit 9
IMV0
Bit 8
CEID
All
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SWPAB
PCDOUT
TQGATE
TQCKPS1
TQCKPS0
POSRES
TQCS
UPDN_SRC
0000
QEOUT
QECK2
QECK1
QECK0
—
—
—
—
0000
POS1CNT
01E4
Position Counter<15:0>
0000
MAX1CNT
01E6
Maximum Count<15:0>
FFFF
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
 2009-2014 Microchip Technology Inc.
TABLE 4-15:
File
Name
QEI2CON
QEI2 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
01F0
CNTERR
—
QEISIDL
INDX
UPDN
QEIM2 QEIM1 QEIM0
—
—
—
—
—
DFLT2CON 01F2
IMV1
Bit 9
IMV0
Bit 8
CEID
All
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SWPAB
PCDOUT
TQGATE
TQCKPS1
TQCKPS0
POSRES
TQCS
UPDN_SRC
0000
QEOUT
QECK2
QECK1
QECK0
—
—
—
—
0000
POS2CNT
01F4
Position Counter<15:0>
0000
MAX2CNT
01F6
Maximum Count<15:0>
FFFF
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 70
TABLE 4-13:
File
Name
HIGH-SPEED PWM REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
PTCON
0400
PTEN
—
PTSIDL
SESTAT
SEIEN
EIPU
SYNCPOL
SYNCOEN
SYNCEN
PTCON2
0402
—
—
—
—
—
—
—
—
—
PTPER
0404
SEVTCMP
0406
MDC
040A
STCON
040E
—
—
—
SESTAT
SEIEN
EIPU
SYNCPOL
SYNCOEN
SYNCEN
STCON2
0410
—
—
—
—
—
—
—
—
—
STPER
0412
Legend:
Bit 4
SYNCSRC2 SYNCSRC1 SYNCSRC0
—
—
—
Bit 3
SEVTPS3
Bit 2
Bit 0
All
Resets
SEVTPS0
0000
Bit 1
SEVTPS2 SEVTPS1
—
PCLKDIV<2:0>
0000
FFF8
SEVTCMP<12:0>
—
—
—
MDC<15:0>
—
—
—
SEVTPS3
SEVTPS2 SEVTPS1 SEVTPS0
0000
—
PCLKDIV<2:0>
0000
FFF8
SSEVTCMP<15:3>
—
—
—
—
—
0000
0000
SYNCSRC2 SYNCSRC1 SYNCSRC0
STPER<15:0>
041A CHPCLKEN
CHOPCLK6 CHOPCLK5 CHOPCLK4 CHOPCLK3 CHOPCLK2 CHOPCLK1 CHOPCLK0
—
—
—
0000
—
—
—
0000
Bit 0
All
Resets
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-17:
File
Name
Bit 5
PTPER<15:0>
SSEVTCMP 0414
CHOP
Bit 6
SFR
Addr
HIGH-SPEED PWM GENERATOR 1 REGISTER MAP
Bit 11
Bit 10
PWMCON1 0420 FLTSTAT CLSTAT TRGSTAT FLTIEN
CLIEN
TRGIEN
ITB
MDCS
—
IOCON1
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0 FLTDAT1
FLTDAT0
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC1
FLTSRC0
0422
Bit 15
PENH
Bit 14
PENL
Bit 13
POLH
Bit 12
POLL
FCLCON1 0424 IFLTMOD CLSRC4 CLSRC3 CLSRC2
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
DTC1
DTC0
DTCP
FLTSRC2
Bit 4
Bit 3
Bit 2
Bit 1
MTBS
CAM
XPRES
IUE
0000
CLDAT1
CLDAT0
SWAP
OSYNC
0000
FLTPOL
FLTMOD1
FLTMOD0
0000
PDC1
0426
PDC1<15:0>
0000
PHASE1
0428
PHASE1<15:0>
0000
DTR1
042A
—
—
DTR1<13:0>
0000
ALTDTR1
042C
—
—
ALTDTR1<13:0>
0000
SDC1
042E
SDC1<15:0>
SPHASE1 0430
TRIG1
0432
0000
TRGCMP<12:0>
TRGCON1 0434 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG1
0000
SPHASE1<15:0>
—
—
—
—
—
DTM
—
—
—
0000
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000
DS7000591F-page 71
0436
STRGCMP<12:0>
—
—
—
0000
PWMCAP1 0438
PWMCAP<12:0>
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
CHOPLEN
0000
LEBCON1 043A
LEBDLY1
043C
PHR
PHF
PLR
PLF
—
—
—
—
—
—
AUXCON1 043E HRPDIS HRDDIS
Legend:
FLTLEBEN
CLLEBEN
—
—
—
—
LEB<8:0>
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
BCH
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-16:
File
Name
SFR
Addr
HIGH-SPEED PWM GENERATOR 2 REGISTER MAP
Bit 15
Bit 14
Bit 13
PWMCON2 0440 FLTSTAT CLSTAT TRGSTAT
PENH
PENL
POLH
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
Bit 0
All
Resets
XPRES
IUE
0000
SWAP
OSYNC
0000
FLTMOD1
FLTMOD0
0000
Bit 2
Bit 1
MTBS
CAM
CLDAT1
CLDAT0
FLTPOL
IOCON2
0442
FCLCON2
0444 IFLTMOD CLSRC4 CLSRC3 CLSRC2
PDC2
0446
PDC2<15:0>
0000
PHASE2
0448
PHASE2<15:0>
0000
DTR2
044A
—
—
DTR2<13:0>
0000
ALTDTR2
044C
—
—
ALTDTR2<13:0>
0000
SDC2
044E
SDC2<15:0>
SPHASE2
0450
SPHASE2<15:0>
TRIG2
0452
TRGCON2
0454 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG2
0456
STRGCMP<12:0>
—
—
—
0000
PWMCAP2 0458
PWMCAP<12:0>
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
0000
TRGCMP<12:0>
LEBCON2
045A
PHR
PHF
PLR
PLF
LEBDLY2
045C
—
—
—
—
AUXCON2
045E HRPDIS
HRDDIS
—
—
Legend:
0000
—
FLTLEBEN
—
CLLEBEN
—
—
—
—
DTM
—
—
—
—
LEB<8:0>
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
BCH
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
0000
0000
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 72
TABLE 4-18:
File
Name
SFR
Addr
HIGH-SPEED PWM GENERATOR 3 REGISTER MAP
Bit 15
Bit 14
Bit 13
PWMCON3 0460 FLTSTAT CLSTAT TRGSTAT
PENL
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
MTBS
CAM
XPRES
IUE
0000
POLH
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
0000
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
0000
IOCON3
0462
FCLCON3
0464 IFLTMOD CLSRC4
PDC3
0466
PDC3<15:0>
0000
PHASE3
0468
PHASE3<15:0>
0000
DTR3
046C
—
—
DTR3<13:0>
0000
ALTDTR3
046C
—
—
ALTDTR3<13:0>
0000
SDC3
046E
SDC3<15:0>
SPHASE3
0470
SPHASE3<15:0>
TRIG3
0472
TRGCON3
0474 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG3
0476
STRGCMP<12:0>
—
—
—
0000
PWMCAP3
0478
PWMCAP<12:0>
—
—
—
0000
LEBCON3
047A
PHR
PHF
PLR
PLF
BPHL
BPLH
BPLL
0000
LEBDLY3
047C
—
—
—
—
—
—
—
0000
AUXCON3
047E
HRPDIS
HRDDIS
—
—
Legend:
PENH
Bit 12
FLTSRC3
0000
0000
TRGCMP<12:0>
—
FLTLEBEN
—
CLLEBEN
—
—
—
—
—
DTM
—
—
—
LEB<8:0>
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
—
0000
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000
BCH
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
DS7000591F-page 73
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-19:
File
Name
SFR
Addr
HIGH-SPEED PWM GENERATOR 4 REGISTER MAP
Bit 15
PWMCON4 0480 FLTSTAT
PENH
Bit 14
Bit 13
CLSTAT TRGSTAT
PENL
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
MTBS
CAM
XPRES
IUE
0000
POLH
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
0000
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
0000
IOCON4
0482
FCLCON4
0484 IFLTMOD CLSRC4
PDC4
0486
PDC4<15:0>
0000
PHASE4
0488
PHASE4<15:0>
0000
DTR4
048A
—
—
DTR4<13:0>
0000
ALTDTR4
048A
—
—
ALTDTR4<13:0>
0000
SDC4
048E
SDC4<15:0>
SPHASE4
0490
SPHASE4<15:0>
TRIG4
0492
TRGCON4
0494 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG4
0496
STRGCMP<12:0>
—
—
—
0000
PWMCAP4 0498
PWMCAP<12:0>
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
0000
0000
TRGCMP<12:0>
—
FLTLEBEN
—
CLLEBEN
—
—
—
—
LEBCON4
049A
PHR
PHF
PLR
PLF
LEBDLY4
049C
—
—
—
—
AUXCON4
049E
HRPDIS
HRDDIS
—
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DTM
—
—
—
—
LEB<8:0>
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
—
—
—
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
BCH
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
0000
0000
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 74
TABLE 4-20:
File
Name
SFR
Addr
HIGH-SPEED PWM GENERATOR 5 REGISTER MAP
Bit 15
PWMCON5 04A0 FLTSTAT
PENH
Bit 14
Bit 13
Bit 12
CLSTAT TRGSTAT FLTIEN
PENL
POLH
POLL
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
MTBS
CAM
XPRES
IUE
0000
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
0000
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
0000
IOCON5
04A2
FCLCON5
04A4 IFLTMOD CLSRC4 CLSRC3 CLSRC2
PDC5
04A6
PDC5<15:0>
0000
PHASE5
04A8
PHASE5<15:0>
0000
DTR5
04AA
—
—
DTR5<13:0>
0000
ALTDTR5
04AA
—
—
ALTDTR5<13:0>
0000
SDC5
04AE
SDC5<15:0>
SPHASE5
04B0
SPHASE5<15:0>
TRIG5
04B2
0000
TRGCMP<12:0>
TRGCON5 04B4 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG5
0000
—
—
—
—
—
DTM
—
—
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
0000
0000
04B6
STRGCMP<12:0>
—
—
—
0000
PWMCAP5 04B8
PWMCAP<12:0>
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
LEBCON5
04BA
PHR
PHF
PLR
PLF
LEBDLY5
04BC
—
—
—
—
HRDDIS
—
—
AUXCON5 04BE HRPDIS
Legend:
FLTLEBEN
CLLEBEN
—
—
—
—
LEB<8:0>
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
BCH
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
DS7000591F-page 75
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-21:
File
Name
SFR
Addr
HIGH-SPEED PWM GENERATOR 6 REGISTER MAP
Bit 15
PWMCON6 04C0 FLTSTAT
PENH
Bit 14
Bit 13
CLSTAT TRGSTAT
PENL
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
MTBS
CAM
XPRES
IUE
0000
POLH
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
0000
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
0000
IOCON6
04C2
FCLCON6
04C4 IFLTMOD CLSRC4
PDC6
04C6
PDC6<15:0>
0000
PHASE6
04C8
PHASE6<15:0>
0000
DTR6
04CA
—
—
DTR6<13:0>
0000
ALTDTR6
04CA
—
—
ALTDTR6<13:0>
0000
SDC6
04CE
SDC6<15:0>
SPHASE6
04D0
SPHASE6<15:0>
TRIG6
04D2
TRGCON6
04D4 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG6
04D6
STRGCMP<12:0>
—
—
—
0000
PWMCAP6 04D8
PWMCAP<12:0>
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
CHOPLEN
0000
0000
0000
TRGCMP<12:0>
—
FLTLEBEN
—
CLLEBEN
—
—
—
—
LEBCON6
04DA
PHR
PHF
PLR
PLF
LEBDLY6
04DC
—
—
—
—
AUXCON6
04DE HRPDIS
HRDDIS
—
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DTM
—
—
—
—
LEB<8:0>
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
—
—
—
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
BCH
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN
0000
0000
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 76
TABLE 4-22:
File
Name
SFR
Addr
HIGH-SPEED PWM GENERATOR 7 REGISTER MAP (EXCLUDES dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES)
Bit 15
PWMCON7 04E0 FLTSTAT
PENH
Bit 14
Bit 13
CLSTAT TRGSTAT
PENL
POLH
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
Bit 0
All
Resets
XPRES
IUE
0000
SWAP
OSYNC
0000
FLTMOD1
FLTMOD0
0000
Bit 2
Bit 1
MTBS
CAM
CLDAT1
CLDAT0
FLTPOL
IOCON7
04E2
FCLCON7
04E4 IFLTMOD CLSRC4
PDC7
04E6
PDC7<15:0>
0000
PHASE7
04E8
PHASE7<15:0>
0000
DTR7
04EA
—
—
DTR7<13:0>
0000
ALTDTR7
04EA
—
—
ALTDTR7<13:0>
0000
SDC7
04EE
SDC7<15:0>
SPHASE7
04F0
SPHASE7<15:0>
TRIG7
04F2
TRGCON7
04F4 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG7
04F6
STRGCMP<12:0>
—
—
—
0000
PWMCAP7 04F8
PWMCAP<12:0>
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
CHOPLEN
0000
CLSRC3 CLSRC2
0000
0000
TRGCMP<12:0>
—
FLTLEBEN
—
CLLEBEN
—
—
—
—
LEBCON7
04FA
PHR
PHF
PLR
PLF
LEBDLY7
04FC
—
—
—
—
AUXCON7
04FE HRPDIS
HRDDIS
—
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DTM
—
—
—
—
LEB<8:0>
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
—
—
—
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
BCH
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN
0000
0000
DS7000591F-page 77
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-23:
File
Name
SFR
Addr
HIGH-SPEED PWM GENERATOR 8 REGISTER MAP (EXCLUDES dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES)
Bit 15
Bit 14
Bit 13
PWMCON8 0500 FLTSTAT CLSTAT TRGSTAT
PENH
PENL
POLH
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
Bit 0
All
Resets
XPRES
IUE
0000
SWAP
OSYNC
0000
FLTMOD1
FLTMOD0
0000
Bit 2
Bit 1
MTBS
CAM
CLDAT1
CLDAT0
FLTPOL
IOCON8
0502
FCLCON8
0504 IFLTMOD CLSRC4 CLSRC3
PDC8
0506
PDC8<15:0>
0000
PHASE8
0508
PHASE8<15:0>
0000
DTR8
050A
—
—
DTR8<13:0>
0000
ALTDTR8
050A
—
—
ALTDTR8<13:0>
0000
SDC8
050E
SDC8<15:0>
SPHASE8
0510
SPHASE8<15:0>
TRIG8
0512
TRGCON8
0514 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG8
0516
STRGCMP<12:0>
—
—
—
0000
PWMCAP8 0518
PWMCAP<12:0>
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
CHOPLEN
0000
0000
0000
TRGCMP<12:0>
—
FLTLEBEN
—
CLLEBEN
—
—
—
—
LEBCON8
051A
PHR
PHF
PLR
PLF
LEBDLY8
051C
—
—
—
—
AUXCON8
051E HRPDIS HRDDIS
—
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DTM
—
—
—
—
LEB<8:0>
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
—
—
—
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
BCH
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN
0000
0000
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 78
TABLE 4-24:
File
Name
SFR
Addr
HIGH-SPEED PWM GENERATOR 9 REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES
Bit 15
PWMCON9 0520 FLTSTAT
PENH
Bit 14
Bit 13
CLSTAT TRGSTAT
PENL
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
MTBS
CAM
XPRES
IUE
0000
POLH
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
0000
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
0000
IOCON9
0522
FCLCON9
0524 IFLTMOD CLSRC4
PDC9
0526
PDC9<15:0>
0000
PHASE9
0528
PHASE9<15:0>
0000
DTR9
052A
—
—
DTR9<13:0>
0000
ALTDTR9
052A
—
—
ALTDTR9<13:0>
0000
SDC9
052E
SDC9<15:0>
0000
SPHASE9
0530
SPHASE9<15:0>
0000
TRIG9
0532
TRGCMP<15:0>
TRGCON9
0534 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG9
0536
—
—
—
—
DTM
0000
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
STRGCMP<15:0>
PWMCAP9 0538
0000
PWMCAP<12:0>
LEBCON9
053A
PHR
PHF
PLR
PLF
FLTLEBEN
CLLEBEN
—
—
LEBDLY9
053C
—
—
—
—
AUXCON9
053E HRPDIS
HRDDIS
—
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
LEB<8:0>
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
—
0000
—
BCH
BCL
BPHH
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
DS7000591F-page 79
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-25:
I2C1 REGISTER MAP
File
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
I2C1RCV
0200
—
—
—
—
—
—
—
—
I2C1 Receive Register
0000
I2C1TRN
0202
—
—
—
—
—
—
—
—
I2C1 Transmit Register
00FF
I2C1BRG
0204
—
—
—
—
—
—
—
I2C1CON
0206
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
I2C1STAT 0208 ACKSTAT TRSTAT
GCSTAT
ADD10
IWCOL
I2COV
I2C1ADD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Baud Rate Generator Register
All
Resets
0000
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
D_A
P
S
R_W
RBF
TBF
0000
—
—
—
BCL
020A
—
—
—
—
—
—
I2C1 Address Register
0000
I2C1MSK 020C
—
—
—
—
—
—
I2C1 Address Mask Register
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-27:
File
Name
I2C2 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
I2C2RCV
0210
—
—
—
—
—
—
—
—
I2C2 Receive Register
I2C2TRN
0212
—
—
—
—
—
—
—
—
I2C2 Transmit Register
I2C2BRG
0214
—
—
—
—
—
—
—
I2C2CON
0216
I2CEN
—
Bit 2
Bit 1
Bit 0
All
Resets
0000
00FF
Baud Rate Generator Register
0000
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
I2C2STAT 0218 ACKSTAT TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
I2C2ADD
1000
0000
021A
—
—
—
—
—
—
I2C2 Address Register
0000
I2C2MSK
021C
—
—
—
—
—
—
I2C2 Address Mask Register
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 80
TABLE 4-26:
File Name
SFR
Addr.
UART1 REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
—
USIDL
IREN
Bit 11
Bit 10
RTSMD
—
Bit 9
Bit 8
UEN1
UEN0
UTXBF
TRMT
Bit 7
Bit 6
WAKE
LPBACK
Bit 0
All
Resets
PDSEL0
STSEL
0000
OERR
URXDA
0110
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ABAUD
URXINV
BRGH
PDSEL1
ADDEN
RIDLE
PERR
FERR
U1MODE
0220
UARTEN
U1STA
0222
UTXISEL1 UTXINV UTXISEL0
U1TXREG
0224
—
—
—
—
—
—
—
UART1 Transmit Register
xxxx
U1RXREG
0226
—
—
—
—
—
—
—
UART1 Receive Register
0000
U1BRG
0228
Legend:
UTXBRK UTXEN
Baud Rate Generator Prescaler
0000
SFR
Addr
UART2 REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
U2MODE
0230
UARTEN
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
U2STA
0232
UTXISEL1
UTXINV
UTXISEL0
—
UTXBRK
UTXEN
UTXBF
TRMT
U2TXREG
0234
—
—
—
—
—
—
—
U2RXREG
0236
—
—
—
—
—
—
—
U2BRG
0238
Legend:
URXISEL1 URXISEL0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-29:
File
Name
—
Bit 7
Bit 6
WAKE
LPBACK
URXISEL1 URXISEL0
Baud Rate Generator Prescaler
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 0
All
Resets
PDSEL0
STSEL
0000
OERR
URXDA
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ABAUD
URXINV
BRGH
PDSEL1
ADDEN
RIDLE
PERR
FERR
0110
UART2 Transmit Register
xxxx
UART2 Receive Register
0000
0000
DS7000591F-page 81
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-28:
File Name
SPI1 REGISTER MAP
SFR
Addr.
Bit 15
Bit 14
Bit 13
SPI1STAT
0240
SPIEN
—
SPISIDL
SPI1CON1
0242
—
—
—
SPI1CON2
0244
FRMEN
SPIFSD
FRMPOL
SPI1BUF
0248
Legend:
—
—
—
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
—
—
SPIROV
—
—
—
—
SPITBF
SPIRBF
0000
MODE16
SMP
CKE
SSEN
CKP
MSTEN
SPRE2
SPRE1
SPRE0
PPRE1
PPRE0
0000
—
—
—
—
—
—
—
—
FRMDLY
—
0000
—
0000
SPI2 REGISTER MAP
Bit 15
Bit 14
Bit 13
SPI2STAT
0260
SPIEN
—
SPISIDL
SPI2CON1
0262
—
—
—
SPI2CON2
0264
FRMEN
SPIFSD
FRMPOL
Legend:
—
DISSCK DISSDO
Bit 10
SPI1 Transmit and Receive Buffer Register
SFR
Addr.
SPI2BUF
Bit 11
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-31:
File Name
Bit 12
0268
Bit 12
Bit 11
Bit 10
—
—
—
DISSCK DISSDO MODE16
—
—
—
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000
—
—
—
SPIROV
—
—
—
—
SPITBF
SPIRBF
SMP
CKE
SSEN
CKP
MSTEN
SPRE2
SPRE1
SPRE0
PPRE1
PPRE0
0000
—
—
—
—
—
—
—
—
FRMDLY
—
0000
SPI2 Transmit and Receive Buffer Register
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 82
TABLE 4-30:
File
Name
HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES ONLY
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
ADCON
0300
ADON
—
ADSIDL
SLOWCLK
—
GSWTRG
—
FORM
EIE
ADPCFG
0302
ADPCFG2
0304
—
—
—
—
—
—
—
—
ADSTAT
0306
—
—
—
P12RDY
P11RDY
P10RDY
P9RDY
P8RDY
ADBASE
0308
ADCPC0
030A
IRQEN1
PEND1
SWTRG1
TRGSRC14
TRGSRC13
TRGSRC12
TRGSRC11
TRGSRC10
IRQEN0
PEND0
SWTRG0
TRGSRC04
TRGSRC03
TRGSRC02
ADCPC1
030C IRQEN3
PEND3
SWTRG3
TRGSRC34
TRGSRC33
TRGSRC32
TRGSRC31
TRGSRC30
IRQEN2
PEND2
SWTRG2
TRGSRC24
TRGSRC23
ADCPC2
030E
IRQEN5
PEND5
SWTRG5
TRGSRC54
TRGSRC53
TRGSRC52
TRGSRC51
TRGSRC50
IRQEN4
PEND4
SWTRG4
TRGSRC44
ADCPC3
0310
IRQEN7
PEND7
SWTRG7
TRGSRC74
TRGSRC73
TRGSRC72
TRGSRC71
TRGSRC70
IRQEN6
PEND6
SWTRG6
ADCPC4
0312
IRQEN9
PEND9
SWTRG9
TRGSRC94
TRGSRC93
TRGSRC92
TRGSRC94
TRGSRC90
IRQEN8
PEND8
SWTRG8
Bit 6
Bit 5
Bit 4
ORDER SEQSAMP ASYNCSAMP
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
ADCS2
ADCS1
ADCS0
0003
PCFG<15:0>
0000
PCFG<23:16>
P6RDY
P5RDY
P4RDY
P3RDY
0000
DS7000591F-page 83
P0RDY
0000
—
0000
TRGSRC01
TRGSRC00
0000
TRGSRC22
TRGSRC21
TRGSRC20
0000
TRGSRC43
TRGSRC42
TRGSRC41
TRGSRC40
0000
TRGSRC64
TRGSRC63
TRGSRC62
TRGSRC61 TRGSRC640
0000
TRGSRC84
TRGSRC83
TRGSRC82
TRGSRC81
TRGSRC80
0000
ADCPC5
0314 IRQEN11 PEND11 SWTRG11 TRGSRC114 TRGSRC113 TRGSRC112 TRGSRC111 TRGSRC110 IRQEN10 PEND10 SWTRG10 TRGSRC104 TRGSRC103 TRGSRC102 TRGSRC101 TRGSRC100
0000
ADCPC6
0316
0000
ADCBUF0
0340
ADC Data Buffer 0
xxxx
ADCBUF1
0342
ADC Data Buffer 1
xxxx
ADCBUF2
0344
ADC Data Buffer 2
xxxx
ADCBUF3
0346
ADC Data Buffer 3
xxxx
ADCBUF4
0348
ADC Data Buffer 4
xxxx
ADCBUF5
034A
ADC Data Buffer 5
xxxx
ADCBUF6
034C
ADC Data Buffer 6
xxxx
ADCBUF7
034E
ADC Data Buffer 7
xxxx
ADCBUF8
0350
ADC Data Buffer 8
xxxx
ADCBUF9
0352
ADC Data Buffer 9
xxxx
ADCBUF10 0354
ADC Data Buffer 10
xxxx
ADCBUF11 0356
ADC Data Buffer 11
xxxx
ADCBUF12 0358
ADC Data Buffer 12
xxxx
ADCBUF13 035A
ADC Data Buffer 13
xxxx
ADCBUF14 035C
ADC Data Buffer 14
xxxx
ADCBUF15 035E
ADC Data Buffer 15
xxxx
ADCBUF16 0360
ADC Data Buffer 16
xxxx
ADCBUF17 0362
ADC Data Buffer 17
xxxx
ADCBUF18 0364
ADC Data Buffer 18
xxxx
ADCBUF19 0366
ADC Data Buffer 19
xxxx
ADCBUF20 0368
ADC Data Buffer 20
xxxx
ADCBUF21 036A
ADC Data Buffer 21
xxxx
Legend:
P7RDY
P2RDY
P1RDY
ADBASE<15:1>
—
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
IRQEN12 PEND12 SWTRG12 TRGSRC124 TRGSRC123 TRGSRC122 TRGSRC121 TRGSRC120
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-32:
File
Name
SFR
Addr
HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES ONLY (CONTINUED)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ADCBUF22 036C
ADC Data Buffer 22
xxxx
ADCBUF23 036E
ADC Data Buffer 23
xxxx
ADCBUF24 0370
ADC Data Buffer 24
xxxx
ADCBUF25 0372
ADC Data Buffer 25
xxxx
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 84
TABLE 4-32:
File
Name
HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES
DS7000591F-page 85
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
ADCON
0300
ADON
—
ADSIDL
SLOWCLK
—
GSWTRG
—
FORM
ADPCFG
0302
ADPCFG2
0304
—
—
—
—
—
—
—
—
—
—
ADSTAT
0306
—
—
—
P12RDY
—
—
—
P8RDY
P7RDY
P6RDY
ADBASE
0308
ADCPC0
030A
IRQEN1
PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10
IRQEN0
PEND0
SWTRG0
TRGSRC04
TRGSRC03
TRGSRC02
ADCPC1
030C
IRQEN3
PEND3 SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30
IRQEN2
PEND2
SWTRG2
TRGSRC24
TRGSRC23
ADCPC2
030E
IRQEN5
PEND5 SWTRG5 TRGSRC54 TRGSRC53 TRGSRC52 TRGSRC51 TRGSRC50
IRQEN4
PEND4
SWTRG4
TRGSRC44
ADCPC3
0310
IRQEN7
PEND7 SWTRG7 TRGSRC74 TRGSRC73 TRGSRC72 TRGSRC71 TRGSRC70
IRQEN6
PEND6
SWTRG6
ADCPC4
0312
—
—
—
—
—
—
—
—
IRQEN8
PEND8
ADCPC6
0316
—
—
—
—
—
—
—
—
ADCBUF0
0340
ADC Data Buffer 0
xxxx
ADCBUF1
0342
ADC Data Buffer 1
xxxx
ADCBUF2
0344
ADC Data Buffer 2
xxxx
ADCBUF3
0346
ADC Data Buffer 3
xxxx
ADCBUF4
0348
ADC Data Buffer 4
xxxx
ADCBUF5
034A
ADC Data Buffer 5
xxxx
ADCBUF6
034C
ADC Data Buffer 6
xxxx
ADCBUF7
034E
ADC Data Buffer 7
xxxx
ADCBUF8
0350
ADC Data Buffer 8
xxxx
ADCBUF9
0352
ADC Data Buffer 9
xxxx
ADCBUF10
0354
ADC Data Buffer 10
xxxx
ADCBUF11
0356
ADC Data Buffer 11
xxxx
ADCBUF12
0358
ADC Data Buffer 12
xxxx
ADCBUF13
035A
ADC Data Buffer 13
xxxx
ADCBUF14
035C
ADC Data Buffer 14
xxxx
ADCBUF15
035E
ADC Data Buffer 15
xxxx
ADCBUF16
0360
ADC Data Buffer 16
xxxx
ADCBUF17
0362
ADC Data Buffer 17
xxxx
ADCBUF24
0370
ADC Data Buffer 24
xxxx
ADCBUF25
0372
ADC Data Buffer 25
xxxx
Legend:
Bit 7
EIE
Bit 6
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ASYNCSAMP
—
ADCS2
ADCS1
ADCS0
0003
—
—
—
—
P5RDY
P4RDY
P3RDY
P2RDY
Bit 5
ORDER SEQSAMP
PCFG<15:0>
0000
PCFG<17:16>
P1RDY
0000
—
0000
TRGSRC01
TRGSRC00
0000
TRGSRC22
TRGSRC21
TRGSRC20
0000
TRGSRC43
TRGSRC42
TRGSRC41
TRGSRC40
0000
TRGSRC64
TRGSRC63
TRGSRC62
TRGSRC61 TRGSRC640
0000
SWTRG8
TRGSRC84
TRGSRC83
TRGSRC82
TRGSRC81
TRGSRC80
0000
IRQEN12 PEND12 SWTRG12
TRGSRC124
TRGSRC123 TRGSRC122 TRGSRC121 TRGSRC120
0000
ADBASE<15:1>
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
P0RDY
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-33:
File
Name
HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS606 AND dsPIC33FJ64GS606 DEVICES
 2009-2014 Microchip Technology Inc.
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
ADCON
0300
ADON
—
ADSIDL
SLOWCLK
—
GSWTRG
—
FORM
ADPCFG
0302
ADSTAT
0306
ADBASE
0308
ADCPC0
030A
IRQEN1
PEND1
SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0
PEND0
SWTRG0
TRGSRC04
TRGSRC03
TRGSRC02
ADCPC1
030C
IRQEN3
PEND3
SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30 IRQEN2
PEND2
SWTRG2
TRGSRC24
TRGSRC23
ADCPC2
030E
IRQEN5
PEND5
SWTRG5 TRGSRC54 TRGSRC53 TRGSRC52 TRGSRC51 TRGSRC50 IRQEN4
PEND4
SWTRG4
TRGSRC44
ADCPC3
0310
IRQEN7
PEND7
SWTRG7 TRGSRC74 TRGSRC73 TRGSRC72 TRGSRC71 TRGSRC70 IRQEN6
PEND6
SWTRG6
TRGSRC64
ADCPC6
0316
—
—
IRQEN12 PEND12
SWTRG12
ADCBUF0
0340
ADC Data Buffer 0
xxxx
ADCBUF1
0342
ADC Data Buffer 1
xxxx
ADCBUF2
0344
ADC Data Buffer 2
xxxx
ADCBUF3
0346
ADC Data Buffer 3
xxxx
ADCBUF4
0348
ADC Data Buffer 4
xxxx
ADCBUF5
034A
ADC Data Buffer 5
xxxx
ADCBUF6
034C
ADC Data Buffer 6
xxxx
ADCBUF7
034E
ADC Data Buffer 7
xxxx
ADCBUF8
0350
ADC Data Buffer 8
xxxx
ADCBUF9
0352
ADC Data Buffer 9
xxxx
ADCBUF10
0354
ADC Data Buffer 10
xxxx
ADCBUF11
0356
ADC Data Buffer 11
xxxx
ADCBUF12
0358
ADC Data Buffer 12
xxxx
ADCBUF13 035A
ADC Data Buffer 13
xxxx
ADCBUF14 035C
ADC Data Buffer 14
xxxx
ADCBUF15 035E
ADC Data Buffer 15
xxxx
ADCBUF24
0370
ADC Data Buffer 24
xxxx
ADCBUF25
0372
ADC Data Buffer 25
xxxx
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 7
Bit 6
EIE
ORDER
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
ADCS2
ADCS1
ADCS0
0003
P3RDY
P2RDY
P1RDY
P0RDY
0000
—
0000
TRGSRC01
TRGSRC00
0000
TRGSRC22
TRGSRC21
TRGSRC20
0000
TRGSRC43
TRGSRC42
TRGSRC41
TRGSRC40
0000
TRGSRC63
TRGSRC62
TRGSRC61 TRGSRC640
0000
TRGSRC124 TRGSRC123 TRGSRC122 TRGSRC121 TRGSRC120
0000
Bit 4
SEQSAMP ASYNCSAMP
PCFG<15:0>
—
—
—
P12RDY
—
—
—
—
P7RDY
0000
P6RDY
P5RDY
P4RDY
ADBASE<15:1>
—
—
—
—
—
—
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 86
TABLE 4-34:
File
Name
HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
ADCON
0300
ADON
—
ADSIDL
SLOWCLK
—
GSWTRG
—
FORM
ADPCFG
0302
ADSTAT
0306
ADBASE
0308
ADCPC0
030A
IRQEN1
PEND1
SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0
PEND0
SWTRG0
TRGSRC04
TRGSRC03 TRGSRC02
ADCPC1
030C
IRQEN3
PEND3
SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30 IRQEN2
PEND2
SWTRG2
TRGSRC24
ADCPC2
030E
IRQEN5
PEND5
SWTRG5 TRGSRC54 TRGSRC53 TRGSRC52 TRGSRC51 TRGSRC50 IRQEN4
PEND4
SWTRG4
ADCPC3
0310
IRQEN7
PEND7
SWTRG7 TRGSRC74 TRGSRC73 TRGSRC72 TRGSRC71 TRGSRC70 IRQEN6
PEND6
SWTRG6
ADCBUF0
0340
ADC Data Buffer 0
xxxx
ADCBUF1
0342
ADC Data Buffer 1
xxxx
ADCBUF2
0344
ADC Data Buffer 2
xxxx
ADCBUF3
0346
ADC Data Buffer 3
xxxx
ADCBUF4
0348
ADC Data Buffer 4
xxxx
ADCBUF5
034A
ADC Data Buffer 5
xxxx
ADCBUF6
034C
ADC Data Buffer 6
xxxx
ADCBUF7
034E
ADC Data Buffer 7
xxxx
ADCBUF8
0350
ADC Data Buffer 8
xxxx
ADCBUF9
0352
ADC Data Buffer 9
xxxx
ADCBUF10
0354
ADC Data Buffer 10
xxxx
ADCBUF11
0356
ADC Data Buffer 11
xxxx
ADCBUF12
0358
ADC Data Buffer 12
xxxx
ADCBUF13
035A
ADC Data Buffer 13
xxxx
ADCBUF14
035C
ADC Data Buffer 14
xxxx
ADCBUF15
035E
ADC Data Buffer 15
xxxx
Legend:
Bit 7
EIE
Bit 6
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
ADCS2
ADCS1
ADCS0
0003
P3RDY
P2RDY
P1RDY
P0RDY
0000
—
0000
TRGSRC01
TRGSRC00
0000
TRGSRC23 TRGSRC22
TRGSRC21
TRGSRC20
0000
TRGSRC44
TRGSRC43 TRGSRC42
TRGSRC41
TRGSRC40
0000
TRGSRC64
TRGSRC63 TRGSRC62
TRGSRC61 TRGSRC640
0000
Bit 4
ORDER SEQSAMP ASYNCSAMP
PCFG<15:0>
—
—
—
P12RDY
—
—
—
—
P7RDY
0000
P6RDY
P5RDY
P4RDY
ADBASE<15:1>
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS7000591F-page 87
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-35:
File
Name
SFR
Addr
DMA REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
DMA0CON 0380
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
DMA0REQ 0382
FORCE
—
—
—
—
—
—
—
Bit 4
Bit 3
Bit 2
—
—
AMODE1
AMODE0
—
—
—
IRQSEL6
IRQSEL5
IRQSEL4
IRQSEL3
IRQSEL2
Bit 0
All
Resets
MODE1
MODE0
0000
IRQSEL1
IRQSEL0
007F
Bit 1
DMA0STA
0384
STA<15:0>
0000
DMA0STB
0386
STB<15:0>
0000
DMA0PAD
0388
PAD<15:0>
0000
DMA0CNT 038A
—
—
—
—
—
—
DMA1CON 038C
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
—
AMODE1
AMODE0
—
—
MODE1
MODE0
0000
—
—
—
—
—
—
—
—
IRQSEL6
IRQSEL5
IRQSEL4
IRQSEL3
IRQSEL2
IRQSEL1
IRQSEL0
007F
DMA1REQ 038E FORCE
CNT<9:0>
0000
DMA1STA
0390
STA<15:0>
0000
DMA1STB
0392
STB<15:0>
0000
DMA1PAD
0394
PAD<15:0>
DMA1CNT
0396
DMA2CON 0398
0000
—
—
—
—
—
—
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
—
AMODE1
AMODE0
—
—
MODE1
MODE0
0000
—
—
—
—
—
—
—
—
IRQSEL6
IRQSEL5
IRQSEL4
IRQSEL3
IRQSEL2
IRQSEL1
IRQSEL0
007F
DMA2REQ 039A FORCE
CNT<9:0>
0000
DMA2STA
039C
STA<15:0>
0000
DMA2STB
039E
STB<15:0>
0000
DMA2PAD
03A0
PAD<15:0>
0000
DMA2CNT 03A2
—
—
—
—
—
—
DMA3CON 03A4
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
—
AMODE1
AMODE0
—
—
MODE1
MODE0
0000
—
—
—
—
—
—
—
—
IRQSEL6
IRQSEL5
IRQSEL4
IRQSEL3
IRQSEL2
IRQSEL1
IRQSEL0
007F
DMA3REQ 03A6 FORCE
DMA3STA
CNT<9:0>
0000
03A8
STA<15:0>
0000
DMA3STB 03AA
STB<15:0>
0000
DMA3PAD 03AC
PAD<15:0>
 2009-2014 Microchip Technology Inc.
—
—
—
—
DMACS0
03E0
—
—
—
—
PWCOL3 PWCOL2 PWCOL1 PWCOL0
—
—
—
—
XWCOL3
XWCOL2
XWCOL1
XWCOL0
0000
DMACS1
03E2
—
—
—
—
LSTCH3
—
—
—
—
PPST3
PPST2
PPST1
PPST0
0F00
DSADR
03E4
Legend:
—
0000
DMA3CNT 03AE
—
LSTCH2
CNT<9:0>
LSTCH1
LSTCH0
DSADR<15:0>
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
0000
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 88
TABLE 4-36:
ECAN1 REGISTER MAP WHEN WIN (C1CTRL1<0>) = 0 OR 1
Bit 2
Bit 1
Bit 0
All
Resets
—
—
WIN
0480
ICODE2
ICODE1
ICODE0
0000
FSA3
FSA2
FSA1
FSA0
0000
FNRB4
FNRB3
FNRB2
FNRB1
FNRB0
0000
ERRIF
—
FIFOIF
RBOVIF
RBIF
TBIF
0000
ERRIE
—
FIFOIE
RBOVIE
RBIE
TBIE
0000
File
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
C1CTRL1
0600
—
—
CSIDL
ABAT
—
REQOP2
REQOP1
REQOP0
C1CTRL2
0602
—
—
—
—
—
—
—
—
—
—
—
C1VEC
0604
—
—
—
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
—
ICODE6
ICODE5
ICODE4
ICODE3
C1FCTRL
0606
DMABS2
DMABS1
DMABS0
—
—
—
—
—
—
—
—
FSA4
C1FIFO
0608
—
—
FBP5
FBP4
FBP3
FBP2
FBP1
FBP0
—
—
FNRB5
C1INTF
060A
—
—
TXBO
TXBP
RXBP
TXWAR
RXWAR
EWARN
IVRIF
WAKIF
C1INTE
060C
—
—
—
—
—
—
—
—
IVRIE
WAKIE
C1EC
060E TERRCNT7 TERRCNT6 TERRCNT5 TERRCNT4 TERRCNT3 TERRCNT2 TERRCNT1 TERRCNT0 RERRCNT7 RERRCNT6 RERRCNT5 RERRCNT4 RERRCNT3 RERRCNT2 RERRCNT1 RERRCNT0
0000
C1CFG1
0610
—
—
—
—
—
—
—
C1CFG2
0612
—
WAKFIL
—
—
—
SEG2PH2
SEG2PH1
C1FEN1
0614
—
Bit 7
Bit 6
Bit 5
OPMODE2 OPMODE1 OPMODE0
SJW1
SEG2PH0 SEG2PHTS
Bit 4
Bit 3
—
CANCAP
DNCNT<4:0>
0000
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
0000
SAM
SEG1PH2
SEG1PH1
SEG1PH0
PRSEG2
PRSEG1
PRSEG0
0000
FLTEN<15:0>
FFFF
C1FMSKSEL1 0618
F7MSK1
F7MSK0
F6MSK1
F6MSK0
F5MSK1
F5MSK0
F4MSK1
F4MSK0
F3MSK1
F3MSK0
F2MSK1
F2MSK0
F1MSK1
F1MSK0
F0MSK1
F0MSK0
0000
C1FMSKSEL2 061A
F15MSK1
F15MSK0
F14MSK1
F14MSK0
F13MSK1
F13MSK0
F12MSK1
F12MSK1
F11MSK1
F11MSK0
F10MSK1
F10MSK0
F9MSK1
F9MSK0
F8MSK1
F8MSK0
0000
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
All
Resets
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-38:
File
Name
SFR
Addr
ECAN1 REGISTER MAP WHEN WIN (C1CTRL1<0>) = 0
Bit 15
0600061E
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 4
Bit 3
See definition when WIN = x
C1RXFUL1
0620
RXFUL<15:0>
0000
C1RXFUL2
0622
RXFUL<31:16>
0000
C1RXOVF1
0628
RXOVF<15:0>
0000
C1RXOVF2
062A
RXOVF<31:16>
0000
C1TR01CON 0630
TXEN1
TXABT1 TXLARB1 TXERR1 TXREQ1 RTREN1 TX1PRI1 TX1PRI0
TXEN0
TXABT0 TXLARB0 TXERR0 TXREQ0 RTREN0 TX0PRI1 TX0PRI0
0000
C1TR23CON 0632
TXEN3
TXABT3 TXLARB3 TXERR3 TXREQ3 RTREN3 TX3PRI1 TX3PRI0
TXEN2
TXABT2 TXLARB2 TXERR2 TXREQ2 RTREN2 TX2PRI1 TX2PRI0
0000
C1TR45CON 0634
TXEN5
TXABT5 TXLARB5 TXERR5 TXREQ5 RTREN5 TX5PRI1 TX5PRI0
TXEN4
TXABT4 TXLARB4 TXERR4 TXREQ4 RTREN4 TX4PRI1 TX4PRI0
0000
C1TR67CON 0636
TXEN7
TXABT7 TXLARB7 TXERR7 TXREQ7 RTREN7 TX7PRI1 TX7PRI0
TXEN6
TXABT6 TXLARB6 TXERR6 TXREQ6 RTREN6 TX6PRI1 TX6PRI0
0000
DS7000591F-page 89
C1RXD
0640
ECAN1 Received Data Word Register
xxxx
C1TXD
0642
ECAN1 Transmit Data Word Register
xxxx
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-37:
File
Name
SFR
Addr
ECAN1 REGISTER MAP WHEN WIN (C1CTRL1<0>) = 1
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
0600061E
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
See definition when WIN = x
C1BUFPNT1
0620
F3BP3
F3BP2
F3BP1
F3BP0
F2BP3
F2BP2
F2BP1
F2BP0
F1BP3
F1BP2
F1BP1
F1BP0
F0BP3
F0BP2
F0BP1
F0BP0
0000
C1BUFPNT2
0622
F7BP3
F7BP2
F7BP1
F7BP0
F6BP3
F6BP2
F6BP1
F6BP0
F5BP3
F5BP2
F5BP1
F5BP0
F4BP3
F4BP2
F4BP1
F4BP0
0000
 2009-2014 Microchip Technology Inc.
C1BUFPNT3
0624
F11BP3
F11BP2
F11BP1
F11BP0
F10BP3
F10BP2
F10BP1
F10BP0
F9BP3
F9BP2
F9BP1
F9BP0
F8BP3
F8BP2
F8BP1
F8BP0
0000
C1BUFPNT4
0626
F15BP3
F15BP2
F15BP1
F15BP0
F14BP3
F14BP2
F14BP1
F14BP0
F13BP3
F13BP2
F13BP1
F13BP0
F12BP3
F12BP2
F12BP1 F12BP0
0000
C1RXM0SID
0630
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
SID1
SID0
—
MIDE
—
EID17
EID16
xxxx
C1RXM0EID
0632
C1RXM1SID
0634
SID1
SID0
—
MIDE
—
EID17
EID16
xxxx
C1RXM1EID
0636
C1RXM2SID
0638
SID1
SID0
—
MIDE
—
EID17
EID16
xxxx
C1RXM2EID
063A
C1RXF0SID
0640
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
C1RXF0EID
0642
C1RXF1SID
0644
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
C1RXF1EID
0646
C1RXF2SID
0648
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
C1RXF2EID
064A
C1RXF3SID
064C
C1RXF3EID
064E
C1RXF4SID
0650
C1RXF4EID
0652
C1RXF5SID
0654
C1RXF5EID
0656
C1RXF6SID
0658
C1RXF6EID
065A
C1RXF7SID
065C
C1RXF7EID
065E
C1RXF8SID
0660
C1RXF8EID
0662
C1RXF9SID
0664
C1RXF9EID
0666
C1RXF10SID
0668
C1RXF10EID
066A
C1RXF11SID
066C
Legend:
EID<15:0>
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
xxxx
EID<15:0>
SID2
xxxx
EID<15:0>
SID2
xxxx
EID<15:0>
SID2
xxxx
EID<15:0>
SID2
xxxx
EID<15:0>
SID2
xxxx
EID<15:0>
SID2
xxxx
EID<15:0>
SID2
xxxx
EID<15:0>
SID2
xxxx
EID<15:0>
SID2
xxxx
EID<15:0>
SID2
xxxx
EID<15:0>
SID2
xxxx
EID<15:0>
SID2
xxxx
EID<15:0>
SID2
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
xxxx
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 90
TABLE 4-39:
File
Name
SFR
Addr
C1RXF11EID
066E
C1RXF12SID
0670
C1RXF12EID
0672
C1RXF13SID
0674
C1RXF13EID
0676
C1RXF14SID
0678
C1RXF14EID
067A
C1RXF15SID
067C
C1RXF15EID
067E
Legend:
ECAN1 REGISTER MAP WHEN WIN (C1CTRL1<0>) = 1 (CONTINUED)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
Bit 7
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
EID<15:0>
SID2
xxxx
EID<15:0>
SID2
xxxx
EID<15:0>
SID2
xxxx
EID<15:0>
SID2
xxxx
EID<15:0>
xxxx
ANALOG COMPARATOR CONTROL REGISTER MAP
File
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
—
DACOE
CMPCON1
0540
CMPON
—
CMPSIDL
—
—
—
CMPDAC1
0542
—
—
-
—
—
—
CMPCON2
0544
CMPON
—
CMPSIDL
—
—
—
CMPDAC2
0546
—
—
-
—
—
—
CMPCON3
0548
CMPON
—
CMPSIDL
—
—
—
CMPDAC3
054A
—
—
-
—
—
—
CMPCON4
054C
CMPON
—
CMPSIDL
—
—
—
054E
—
—
—
—
—
—
Legend:
Bit 5
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-40:
CMPDAC4
Bit 6
Bit 7
Bit 6
INSEL1 INSEL0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
EXTREF
—
CMPSTAT
—
CMPPOL
RANGE
0000
CMPSTAT
—
CMPPOL
RANGE
0000
CMPSTAT
—
CMPPOL
RANGE
0000
CMPSTAT
—
CMPPOL
RANGE
0000
CMREF<9:0>
—
DACOE
INSEL1 INSEL0
EXTREF
—
DACOE
INSEL1 INSEL0
EXTREF
—
DACOE
INSEL1 INSEL0
EXTREF
—
0000
CMREF<9:0>
—
0000
CMREF<9:0>
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
CMREF<9:0>
0000
0000
DS7000591F-page 91
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-39:
File
Name
SFR
Addr
TRISA
02C0
PORTA
02C2
LATA
ODCA
Legend:
Bit 15
Bit 14
Bit 10
Bit 9
Bit 8
Bit 7
Bit 12
Bit 11
TRISA<15:14>
—
—
—
TRISA<10:9>
—
TRISA<7:0>
C6FF
RA<15:14>
—
—
—
RA<10:9>
—
RA<7:0>
xxxx
02C4
LATA<15:14>
—
—
—
LATA<10:9>
—
LATA<7:0>
02C6
ODCA<15:14>
—
—
—
ODCA<10:9>
—
—
Bit 6
—
Bit 5
Bit 4
ODCA<5:4>
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
Bit 13
0000
—
—
ODCA<1:0>
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-42:
File
Name
PORTA REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES
SFR
Addr
PORTA REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISA
02C0
TRISA<15:14>
—
—
—
TRISA<10:9>
—
—
—
—
—
—
—
—
—
C600
PORTA
02C2
RA<15:14>
—
—
—
RA<10:9>
—
—
—
—
—
—
—
—
—
xxxx
LATA
02C4
LATA<15:14>
—
—
—
LATA<10:9>
—
—
—
—
—
—
—
—
—
0000
ODCA
02C6
ODCA<15:14>
—
—
—
ODCA<10:9>
—
—
—
—
—
—
—
—
—
0000
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-43:
File
Name
SFR
Addr
PORTB REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
TRISB
02C8
TRISB<15:0>
PORTB
02CA
RB<15:0>
xxxx
LATB
02CC
LATB<15:0>
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
 2009-2014 Microchip Technology Inc.
TABLE 4-44:
File
Name
SFR
Addr
FFFF
PORTC REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISC
02D0
TRISC<15:12>
—
—
—
—
—
—
—
TRISC<4:1>
—
F01E
PORTC
02D2
RC<15:12>
—
—
—
—
—
—
—
RC<4:1>
—
xxxx
LATC
02D4
LATC<15:12>
—
—
—
—
—
—
—
LATC<4:1>
—
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 92
TABLE 4-41:
File
Name
SFR
Addr
PORTC REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISC
02D0
TRISC<15:12>
—
—
—
—
—
—
—
—
—
TRISC<2:1>
—
F006
PORTC
02D2
RC<15:12>
—
—
—
—
—
—
—
—
—
RC<2:1>
—
xxxx
LATC
02D4
LATC<15:12>
—
—
—
—
—
—
—
—
—
LATC<2:1>
—
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-46:
File
Name
SFR
Addr
PORTC REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISC
02D0
TRISC<15:12>
—
—
—
—
—
—
—
—
—
—
—
—
F000
PORTC
02D2
RC<15:12>
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
LATC
02D4
LATC<15:12>
—
—
—
—
—
—
—
—
—
—
—
—
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 2
Bit 1
Bit 0
All
Resets
TABLE 4-47:
File
Name
SFR
Addr
PORTD REGISTER MAP FOR dsPIC33FJ32GS608/610 AND dsPIC33FJ64GS608/610 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
TRISD
02D8
TRISD<15:0>
FFFF
PORTD
02DA
RD<15:0>
xxxx
LATD
02DC
LATD<15:0>
0000
ODCD
02DE
ODCD<15:0>
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-48:
File
Name
PORTD REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES
DS7000591F-page 93
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
TRISD
02D8
—
—
—
—
TRISD<11:0>
0FFF
PORTD
02DA
—
—
—
—
RD<11:0>
xxxx
LATD
02DC
—
—
—
—
LATD<11:0>
0000
ODCD
02DE
—
—
—
—
ODCD<11:0>
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-45:
File
Name
PORTE REGISTER MAP FOR dsPIC33FJ32GS608/610 AND dsPIC33FJ64GS608/610 DEVICES
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
TRISE
02E0
—
—
—
—
—
—
TRISE<9:0>
03FF
PORTE
02E2
—
—
—
—
—
—
RE<9:0>
xxxx
LATE
02E4
—
—
—
—
—
—
LATE<9:0>
ODCE
02E6
—
—
—
—
—
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-50:
File
Name
Bit 9
—
Bit 8
Bit 7
Bit 6
Bit 5
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000
ODCE<7:0>
0000
PORTE REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TRISE
02E0
—
—
—
—
—
—
—
—
TRISE<7:0>
00FF
PORTE
02E2
—
—
—
—
—
—
—
—
RE<7:0>
xxxx
LATE
02E4
—
—
—
—
—
—
—
—
LATE<7:0>
0000
ODCE
02E6
—
—
—
—
—
—
—
—
ODCE<7:0>
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-51:
File
Name
Bit 7
 2009-2014 Microchip Technology Inc.
Bit 15
Bit 14
TRISF
02E8
—
—
PORTF
02EA
—
—
LATF
02EC
—
ODCF
02EE
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
PORTF REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES
SFR
Addr
TABLE 4-52:
Bit 6
Bit 13
Bit 12
Bit 8
Bit 7
Bit 6
Bit 10
Bit 9
TRISF<13:12>
—
—
—
TRISF<8:0>
30FF
RF<13:12>
—
—
—
RF<8:0>
xxxx
—
LATF<13:12>
—
—
—
LATF<8:0>
—
ODCF<13:12>
—
—
—
ODCF<8:6>
Bit 5
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
Bit 11
0000
—
ODCF<3:1>
—
0000
Bit 0
All
Resets
PORTF REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
TRISF
02E8
—
—
—
—
—
—
—
TRISF<8:0>
01FF
PORTF
02EA
—
—
—
—
—
—
—
RF<8:0>
xxxx
LATF
02EC
—
—
—
—
—
—
—
LATF<8:0>
ODCF
02EE
—
—
—
—
—
—
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 8
Bit 7
ODCF<8:6>
Bit 6
Bit 5
—
Bit 4
—
Bit 3
Bit 2
Bit 1
0000
ODCF<3:1>
—
0000
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 94
TABLE 4-49:
File
Name
PORTF REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
TRISF
02E8
—
—
—
—
—
—
—
—
—
TRISF<6:0>
007F
PORTF
02EA
—
—
—
—
—
—
—
—
—
RF<6:0>
xxxx
LATF
02EC
—
—
—
—
—
—
—
—
—
LATF<6:0>
ODCF
02EE
—
—
—
—
—
—
—
—
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-54:
File
Name
SFR
Addr
Bit 6
ODCF6
Bit 5
Bit 4
—
Bit 3
Bit 2
—
Bit 1
Bit 0
All
Resets
0000
ODCF<3:1>
—
0000
Bit 0
All
Resets
PORTG REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TRISG
02F0
TRISG<15:12
—
—
TRISG<9:6>
—
—
TRISG<3:0>
F3CF
PORTG
02F2
RG<15:12>
—
—
RG<9:6>
—
—
RG<3:0>
xxxx
LATG
02F4
LATG<15:12>
—
—
LATG<9:6>
—
—
LATG<3:0>
0000
ODCG
02F6
ODCG<15:12>
—
—
ODCG<9:6>
—
—
ODCG<3:0>
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-55:
File
Name
PORTG REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
TRISG
02F0
—
—
—
—
—
—
PORTG
02F2
—
—
—
—
—
—
LATG
02F4
—
—
—
—
—
ODCG
02F6
—
—
—
—
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-56:
File
Name
Bit 9
Bit 8
Bit 7
Bit 6
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
Bit 5
Bit 4
TRISG<9:6>
—
—
TRISG<3:0>
03CF
RG<9:6>
—
—
RG<3:0>
xxxx
—
LATG<9:6>
—
—
LATG<3:0>
0000
—
ODCG<9:6>
—
—
ODCG<3:0>
0000
PORTG REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES
DS7000591F-page 95
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
TRISG
02F0
—
—
—
—
—
—
PORTG
02F2
—
—
—
—
—
—
LATG
02F4
—
—
—
—
—
ODCG
02F6
—
—
—
—
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 9
Bit 8
Bit 7
Bit 6
Bit 1
Bit 0
All
Resets
TRISG<3:2>
—
—
03CC
RG<3:2>
—
—
xxxx
—
LATG<3:2>
—
—
0000
—
ODCG<3:2>
—
—
0000
Bit 5
Bit 4
TRISG<9:6>
—
—
RG<9:6>
—
—
—
LATG<9:6>
—
—
ODCG<9:6>
—
Bit 3
Bit 2
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-53:
File
Name
SFR
Addr
SYSTEM CONTROL REGISTER MAP
Bit 15
Bit 14
TRAPR IOPUWR
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
—
—
—
VREGS
EXTR
SWR
SWDTEN
WDTO
SLEEP
IDLE
BOR
POR
xxxx(1)
—
NOSC2
NOSC1
NOSC0
CLKLOCK
—
LOCK
—
CF
—
—
OSWEN
0300(2)
FRCDIV0
RCON
0740
OSCCON
0742
—
COSC2
COSC1
COSC0
CLKDIV
0744
ROI
DOZE2
DOZE1
DOZE0 DOZEN
FRCDIV2
FRCDIV1
PLLFBD
0746
—
—
—
—
—
—
—
OSCTUN
0748
—
—
—
—
—
—
—
—
—
—
ROON
—
RODIV2
RODIV1
RODIV0
—
—
—
—
—
—
—
—
0000
FRCSEL
—
—
—
—
—
—
2300
Bit 2
Bit 1
REFOCON 074E
ROSSLP ROSEL RODIV3
ACLKCON 0750 ENAPLL APLLCK SELACLK
Legend:
Note 1:
2:
—
—
PLLPOST1 PLLPOST0
—
PLLPRE4 PLLPRE3 PLLPRE2 PLLPRE1 PLLPRE0 0040
PLLDIV<8:0>
APSTSCLR2 APSTSCLR1 APSTSCLR0 ASRCSEL
0030
TUN<5:0>
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
The RCON register Reset values are dependent on the type of Reset.
The OSCCON register Reset values are dependent on the FOSCx Configuration bits and on the type of Reset.
TABLE 4-58:
NVM REGISTER MAP
File
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
NVMCON
0760
WR
WREN
WRERR
—
—
—
—
—
—
ERASE
—
—
NVMKEY
0766
—
—
—
—
—
—
—
—
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
The Reset value shown is for POR only. The value on other Reset states is dependent on the state of the memory write or erase operations at the time of Reset.
TABLE 4-59:
Bit 3
Bit 0
NVMOP3 NVMOP2 NVMOP1 NVMOP0
NVMKEY<7:0>
All
Resets
0000(1)
0000
PMD REGISTER MAP FOR dsPIC33FJ64GS610 DEVICES
File
SFR
Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
 2009-2014 Microchip Technology Inc.
PMD1 0770
T5MD
T4MD
T3MD
T2MD
T1MD
QEI1MD
PWMMD
—
I2C1MD
U2MD
U1MD
SPI2MD
SPI1MD
—
C1MD
ADCMD
0000
PMD2 0772
—
—
—
—
IC4MD
IC3MD
IC2MD
IC1MD
—
—
—
—
OC4MD
OC3MD
OC2MD
OC1MD
0000
PMD3 0774
—
—
—
—
—
CMPMD
—
—
—
—
QEI2MD
—
—
—
I2C2MD
—
0000
PMD4 0776
—
—
—
—
—
—
—
—
—
—
—
—
REFOMD
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
PWM9MD
0000
PMD6 077A
PMD7 077C
Legend:
PWM8MD PWM7MD PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD
—
—
—
—
CMP4MD
CMP3MD
CMP2MD
CMP1MD
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 96
TABLE 4-57:
PMD REGISTER MAP FOR dsPIC33FJ32GS610 DEVICES
File
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
PMD1
0770
T5MD
T4MD
T3MD
PMD2
0772
—
—
—
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
T2MD
T1MD
QEI1MD
—
IC4MD
IC3MD
PWMMD
—
I2C1MD
U2MD
U1MD
SPI2MD
SPI1MD
IC2MD
IC1MD
—
—
—
—
OC4MD
All
Resets
Bit 2
Bit 1
Bit 0
—
—
ADCMD
0000
OC1MD
0000
OC3MD OC2MD
PMD3
0774
—
—
—
—
—
CMPMD
—
—
—
—
QEI2MD
—
—
—
I2C2MD
—
0000
PMD4
0776
—
—
—
—
—
—
—
—
—
—
—
—
REFOMD
—
—
—
0000
PMD6
077A PWM8MD PWM7MD PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD
—
—
—
—
—
—
—
—
0000
PMD7
077C
—
—
—
—
—
—
—
PWM9MD
0000
Bit 2
Bit 1
Bit 0
All
Resets
—
C1MD
ADCMD
0000
Legend:
—
—
—
—
CMP4MD
CMP3MD
CMP2MD
CMP1MD
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-61:
PMD REGISTER MAP FOR dsPIC33FJ64GS608 DEVICES
File
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
PMD1
0770
T5MD
T4MD
T3MD
PMD2
0772
—
—
—
PMD3
0774
—
—
PMD4
0776
—
—
PMD6
077A PWM8MD PWM7MD PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD
PMD7
077C
Legend:
—
Bit 10
Bit 9
T2MD
T1MD
QEI1MD
—
IC4MD
IC3MD
—
—
—
—
—
—
—
—
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PWMMD
—
I2C1MD
U2MD
U1MD
SPI2MD
SPI1MD
IC2MD
IC1MD
—
—
—
—
OC4MD
CMPMD
—
—
—
—
QEI2MD
—
—
—
—
—
—
—
—
—
—
REFOMD
—
—
—
—
—
—
—
—
—
—
CMP3MD
CMP2MD
CMP1MD
OC3MD OC2MD
OC1MD
0000
I2C2MD
—
0000
—
—
—
0000
—
—
—
0000
—
—
—
0000
PMD REGISTER MAP FOR dsPIC33FJ32GS608 DEVICES
DS7000591F-page 97
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
PMD1
0770
T5MD
T4MD
T3MD
PMD2
0772
—
—
—
PMD3
0774
—
—
PMD4
0776
—
—
PMD6
PMD7
Legend:
CMP4MD
Bit 8
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-62:
File
Name
—
Bit 11
Bit 9
T2MD
T1MD
QEI1MD
—
IC4MD
IC3MD
—
—
—
—
—
—
Bit 0
All
Resets
—
—
ADCMD
0000
OC3MD
OC2MD
OC1MD
0000
—
I2C2MD
—
0000
REFOMD
—
—
—
0000
—
—
—
—
—
0000
—
—
—
—
—
0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PWMMD
—
I2C1MD
U2MD
U1MD
SPI2MD
SPI1MD
IC2MD
IC1MD
—
—
—
—
OC4MD
CMPMD
—
—
—
—
QEI2MD
—
—
—
—
—
—
—
—
—
077A PWM8MD PWM7MD PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD
—
—
—
077C
—
—
—
—
Bit 10
Bit 1
Bit 8
—
Bit 11
—
—
CMP4MD
CMP3MD
CMP2MD
CMP1MD
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 2
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
TABLE 4-60:
File
Name
PMD REGISTER MAP FOR dsPIC33FJ64GS606 DEVICES
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
PMD1
0770
T5MD
T4MD
T3MD
PMD2
0772
—
—
—
PMD3
0774
—
—
PMD4
0776
—
—
PMD6
077A
—
—
PMD7
077C
—
—
Legend:
Bit 10
Bit 9
T2MD
T1MD
QEI1MD
—
IC4MD
IC3MD
—
—
—
—
—
—
—
CMP4MD
Bit 1
Bit 0
All
Resets
—
C1MD
ADCMD
0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PWMMD
—
I2C1MD
U2MD
U1MD
SPI2MD
SPI1MD
IC2MD
IC1MD
—
—
—
—
OC4MD
CMPMD
—
—
—
—
QEI2MD
—
—
—
—
—
—
—
—
—
—
REFOMD
—
—
—
—
—
—
—
—
—
—
PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD
—
Bit 2
Bit 8
CMP3MD
CMP2MD
CMP1MD
OC3MD OC2MD
OC1MD
0000
I2C2MD
—
0000
—
—
—
0000
—
—
—
0000
—
—
—
0000
Bit 2
Bit 1
Bit 0
All
Resets
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-64:
File
Name
Bit 11
PMD REGISTER MAP FOR dsPIC33FJ32GS606 DEVICES
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
PMD1
0770
T5MD
T4MD
T3MD
PMD2
0772
—
—
—
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
T2MD
T1MD
QEI1MD
—
IC4MD
IC3MD
PWMMD
—
I2C1MD
U2MD
U1MD
SPI2MD
SPI1MD
—
—
ADCMD
0000
IC2MD
IC1MD
—
—
—
—
OC4MD
OC3MD
OC2MD
OC1MD
0000
PMD3
0774
—
—
—
—
—
CMPMD
—
—
—
—
QEI2MD
—
—
—
I2C2MD
—
0000
PMD4
0776
—
—
—
—
—
—
—
—
—
—
—
—
REFOMD
—
—
—
0000
PMD6
077A
—
—
—
—
—
—
—
—
—
—
0000
PMD7
077C
—
—
—
—
—
—
—
—
—
—
0000
Bit 2
Bit 1
Bit 0
All
Resets
Legend:
—
—
CMP4MD
CMP3MD CMP2MD
CMP1MD
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-65:
File
Name
PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD
PMD REGISTER MAP FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES
 2009-2014 Microchip Technology Inc.
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
PMD1
0770
T5MD
T4MD
T3MD
PMD2
0772
—
—
—
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
T2MD
T1MD
QEI1MD
—
IC4MD
IC3MD
PWMMD
—
I2C1MD
U2MD
U1MD
SPI2MD
SPI1MD
—
—
ADCMD
0000
IC2MD
IC1MD
—
—
—
—
OC4MD
OC3MD
OC2MD
OC1MD
0000
PMD3
0774
—
—
—
—
—
—
—
—
—
—
QEI2MD
—
—
—
I2C2MD
—
0000
PMD4
0776
—
—
—
—
—
—
—
—
—
—
—
—
REFOMD
—
—
—
0000
PMD6
077A
—
—
—
—
—
—
—
—
—
—
0000
Legend:
PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 98
TABLE 4-63:
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
4.2.7
SOFTWARE STACK
4.3
In addition to its use as a Working register, the W15
register in the dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610 devices is also used
as a Software Stack Pointer. The Stack Pointer always
points to the first available free word and grows from
lower to higher addresses. It predecrements for stack
pops and post-increments for stack pushes, as shown
in Figure 4-6. For a PC push during any CALL instruction, the MSb of the PC is zero-extended before the
push, ensuring that the MSb is always clear.
Note:
A PC push during exception processing
concatenates the SRL register to the MSb
of the PC prior to the push.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. As is the
case for the Stack Pointer, SPLIM<0> is forced to ‘0’
because all stack operations must be word-aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is
compared with the value in SPLIM. If the contents of
the Stack Pointer (W15) and the SPLIM register are
equal and a push operation is performed, a stack error
trap will not occur. The stack error trap will occur on a
subsequent push operation. For example, to cause a
stack error trap when the stack grows beyond address
0x1800 in RAM, initialize the SPLIM with the value,
0x17FE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-6:
Stack Grows Toward
Higher Address
0x0000
CALL STACK FRAME
15
Instruction Addressing Modes
The addressing modes shown in Table 4-66 form the
basis of the addressing modes optimized to support the
specific features of individual instructions. The
addressing modes provided in the MAC class of
instructions differ from those in the other instruction
types.
4.3.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first
8192 bytes of data memory (Near Data Space). Most
file register instructions employ a Working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
4.3.2
MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where Operand 1 is always a Working register (that is,
the addressing mode can only be register direct), which
is referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or a data memory
location. The following addressing modes are
supported by MCU instructions:
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
5-Bit or 10-Bit Literal
Note:
Not all instructions support all the
addressing modes given above. Individual
instructions can support different subsets
of these addressing modes.
0
PC<15:0>
000000000 PC<22:16>
<Free Word>
W15 (before CALL)
W15 (after CALL)
POP : [--W15]
PUSH : [W15++]
 2009-2014 Microchip Technology Inc.
DS7000591F-page 99
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 4-66:
FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
Description
File Register Direct
The address of the file register is specified explicitly.
Register Direct
The contents of a register are accessed directly.
Register Indirect
The contents of Wn forms the Effective Address (EA).
Register Indirect Post-Modified
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
(Register Indexed)
Register Indirect with Literal Offset
4.3.3
The sum of Wn and a literal forms the EA.
MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing modes supported by most MCU
instructions, move and accumulator instructions also
support Register Indirect with Register Offset
Addressing mode, also referred to as Register Indexed
mode.
Note:
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA. However, the 4-bit Wb (Register Offset) field is
shared by both source and destination
(but typically only used by one).
4.3.4
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred
to as MAC instructions, use a simplified set of addressing
modes to allow the user application to effectively
manipulate the Data Pointers through Register Indirect
tables.
The two-source operand, prefetch registers must be
members of the set: {W8, W9, W10, W11}. For data
reads, W8 and W9 are always directed to the X RAGU,
and W10 and W11 are always directed to the Y AGU.
The Effective Addresses generated (before and after
modification) must, therefore, be valid addresses within
X data space for W8 and W9 and Y data space for W10
and W11.
Note:
In summary, the following addressing modes are
supported by move and accumulator instructions:
•
•
•
•
•
•
•
•
MAC INSTRUCTIONS
Register Indirect with Register Offset
Addressing mode is available only for W9
(in X space) and W11 (in Y space).
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-Bit Literal
16-Bit Literal
In summary, the following addressing modes are
supported by the MAC class of instructions:
Note:
4.3.5
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
DS7000591F-page 100
•
•
•
•
•
Register Indirect
Register Indirect Post-Modified by 2
Register Indirect Post-Modified by 4
Register Indirect Post-Modified by 6
Register Indirect with Register Offset (Indexed)
OTHER INSTRUCTIONS
Besides the addressing modes outlined previously, some
instructions use literal constants of various sizes. For
example, BRA (branch) instructions use 16-bit signed
literals to specify the branch destination directly, whereas
the DISI instruction uses a 14-bit unsigned literal field. In
some instructions, such as ADD Acc, the source of an
operand or result is implied by the opcode itself. Certain
operations, such as NOP, do not have any operands.
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
4.4
4.4.1
Modulo Addressing
Modulo Addressing mode is a method used to provide
an automated means to support circular data buffers
using hardware. The objective is to remove the need
for software to perform data address boundary checks
when executing tightly looped code, as is typical in
many DSP algorithms.
Modulo Addressing can operate in either data or program
space (since the Data Pointer mechanism is essentially
the same for both). One circular buffer can be supported
in each of the X (which also provides the pointers into
program space) and Y data spaces. Modulo Addressing
can operate on any W Register Pointer. However, it is not
advisable to use W14 or W15 for Modulo Addressing
since these two registers are used as the Stack Frame
Pointer and Stack Pointer, respectively.
In general, any particular circular buffer can be
configured to operate in only one direction as there are
certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing
buffers), based upon the direction of the buffer.
The only exception to the usage restrictions is for
buffers that have a power-of-two length. As these
buffers satisfy the start and end address criteria, they
can operate in a bidirectional mode (that is, address
boundary checks are performed on both the lower and
upper address boundaries).
START AND END ADDRESS
The Modulo Addressing scheme requires that a
starting and ending address be specified and loaded
into the 16-bit Modulo Buffer Address registers:
XMODSRT, XMODEND, YMODSRT and YMODEND
(see Table 4-1).
Note:
Y Space Modulo Addressing EA
calculations assume word-sized data
(LSb of every EA is always clear).
The length of a circular buffer is not directly specified. It is
determined by the difference between the corresponding
start and end addresses. The maximum possible length
of the circular buffer is 32K words (64 Kbytes).
4.4.2
W ADDRESS REGISTER
SELECTION
The Modulo and Bit-Reversed Addressing Control
register, MODCON<15:0>, contains enable flags as
well as a W register field to specify the W Address
registers. The XWM and YWM fields select the
registers that will operate with Modulo Addressing:
• If XWM = 15, X RAGU and X WAGU Modulo
Addressing is disabled.
• If YWM = 15, Y AGU Modulo Addressing is disabled.
The X Address Space Pointer W register (XWM), to
which Modulo Addressing is to be applied, is stored in
MODCON<3:0> (see Table 4-1). Modulo Addressing is
enabled for X data space when XWM is set to any value
other than ‘15’ and the XMODEN bit is set at
MODCON<15>.
The Y Address Space Pointer W register (YWM) to
which Modulo Addressing is to be applied is stored in
MODCON<7:4>. Modulo Addressing is enabled for Y
data space when YWM is set to any value other than
‘15’ and the YMODEN bit is set at MODCON<14>.
FIGURE 4-7:
MODULO ADDRESSING OPERATION EXAMPLE
Byte
Address
0x1100
0x1163
MOV
MOV
MOV
MOV
MOV
MOV
#0x1100, W0
W0, XMODSRT
#0x1163, W0
W0, MODEND
#0x8001, W0
W0, MODCON
MOV
#0x0000, W0
;W0 holds buffer fill value
MOV
#0x1110, W1
;point W1 to buffer
DO
AGAIN, #0x31
MOV
W0, [W1++]
AGAIN: INC W0, W0
;set modulo start address
;set modulo end address
;enable W1, X AGU for modulo
;fill the 50 buffer locations
;fill the next location
;increment the fill value
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 Words
 2009-2014 Microchip Technology Inc.
DS7000591F-page 101
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
4.4.3
MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register. Address boundaries check for addresses
equal to:
• Upper boundary addresses for incrementing buffers
• Lower boundary addresses for decrementing buffers
It is important to realize that the address boundaries
check for addresses less than or greater than the upper
(for incrementing buffers) and lower (for decrementing
buffers) boundary addresses (not just equal to).
Address changes can, therefore, jump beyond
boundaries and still be adjusted correctly.
Note:
4.5
The modulo corrected Effective Address
is written back to the register only when
Pre-Modify or Post-Modify Addressing
mode is used to compute the Effective
Address. When an address offset (such
as [W7 + W2]) is used, Modulo Addressing
correction is performed but the contents of
the register remain unchanged.
Bit-Reversed Addressing
Bit-Reversed Addressing mode is intended to simplify
data re-ordering for radix-2 FFT algorithms. It is
supported by the X AGU for data writes only.
The modifier, which can be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order.
Thus, the only operand requiring reversal is the modifier.
4.5.1
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing mode is enabled in any of
these situations:
• BWMx bits (W register selection) in the MODCON
register are any value other than ‘15’ (the stack
cannot be accessed using Bit-Reversed
Addressing)
• The BREN bit is set in the XBREV register
• The addressing mode used is Register Indirect
with Pre-Increment or Post-Increment
If the length of a bit-reversed buffer is M = 2N bytes,
the last ‘N’ bits of the data buffer start address must
be zeros.
XB<14:0> is the Bit-Reversed Addressing modifier, or
‘pivot point,’ which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
Note:
All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
When enabled, Bit-Reversed Addressing is executed
only for Register Indirect with Pre-Increment or PostIncrement Addressing and word-sized data writes. It
will not function for any other addressing mode or for
byte-sized data and normal addresses are generated
instead. When Bit-Reversed Addressing is active, the
W Address Pointer is always added to the address
modifier (XB) and the offset associated with the Register Indirect Addressing mode is ignored. In addition, as
word-sized data is a requirement, the LSb of the EA is
ignored (and always clear).
Note:
Modulo Addressing and Bit-Reversed
Addressing should not be enabled
together. If an application attempts to do
so, Bit-Reversed Addressing will assume
priority when active for the X WAGU and X
WAGU, and Modulo Addressing will be
disabled. However, Modulo Addressing will
continue to function in the X RAGU.
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the Bit-Reversed Pointer.
DS7000591F-page 102
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 4-8:
BIT-REVERSED ADDRESS EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4
0
Bit-Reversed Address
Pivot Point
XB = 0x0008 for a 16-Word Bit-Reversed Buffer
TABLE 4-67:
BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
Normal Address
Bit-Reversed Address
A3
A2
A1
A0
Decimal
A3
A2
A1
A0
Decimal
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
8
0
0
1
0
2
0
1
0
0
4
0
0
1
1
3
1
1
0
0
12
0
1
0
0
4
0
0
1
0
2
0
1
0
1
5
1
0
1
0
10
0
1
1
0
6
0
1
1
0
6
0
1
1
1
7
1
1
1
0
14
1
0
0
0
8
0
0
0
1
1
1
0
0
1
9
1
0
0
1
9
1
0
1
0
10
0
1
0
1
5
1
0
1
1
11
1
1
0
1
13
1
1
0
0
12
0
0
1
1
3
1
1
0
1
13
1
0
1
1
11
1
1
1
0
14
0
1
1
1
7
1
1
1
1
15
1
1
1
1
15
 2009-2014 Microchip Technology Inc.
DS7000591F-page 103
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
4.6
4.6.1
Interfacing Program and Data
Memory Spaces
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices’ architecture
uses a 24-bit-wide program space and a 16-bit-wide
data space. The architecture is also a modified Harvard
scheme, meaning that data can also be present in the
program space. To use this data successfully, it must
be accessed in a way that preserves the alignment of
information in both spaces.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to define a 32K word region within
the program space. This is concatenated with a 16-bit
EA to arrive at a full 24-bit program space address. In
this format, the Most Significant bit of TBLPAG is used
to determine if the operation occurs in the user memory
(TBLPAG<7> = 0) or the configuration memory
(TBLPAG<7> = 1).
Aside from normal execution, the dsPIC33FJ32GS406/
606/608/610 and dsPIC33FJ64GS406/606/608/610
architecture provides two methods by which program
space can be accessed during operation:
For remapping operations, the 8-bit Program Space
Visibility register (PSVPAG) is used to define a
16K word page in the program space. When the Most
Significant bit of the EA is ‘1’, PSVPAG is concatenated
with the lower 15 bits of the EA to form a 23-bit program
space address. Unlike table operations, this limits
remapping operations strictly to the user memory area.
• Using table instructions to access individual bytes
or words anywhere in the program space
• Remapping a portion of the program space into
the data space (Program Space Visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated periodically. It also allows access
to all bytes of the program word. The remapping
method allows an application to access a large block of
data on a read-only basis, which is ideal for look-ups
from a large table of static data. The application can
only access the least significant word of the program
word.
TABLE 4-68:
ADDRESSING PROGRAM SPACE
Table 4-68 and Figure 4-9 show how the program EA is
created for table operations and remapping accesses
from the data EA. Here, P<23:0> refers to a program
space word and D<15:0> refers to a data space word.
PROGRAM SPACE ADDRESS CONSTRUCTION
Access
Space
Access Type
Program Space Address
<23>
<22:16>
Instruction Access
(Code Execution)
User
TBLRD/TBLWT
(Byte/Word Read/Write)
User
TBLPAG<7:0>
Configuration
TBLPAG<7:0>
<15>
PC<22:1>
0
0xx
xxxx
xxxx
0xxx xxxx
1xxx xxxx
Program Space Visibility
(Block Remap/Read)
Note 1:
User
<14:1>
0
PSVPAG<7:0>
0
xxxx xxxx
xxxx
<0>
0
xxxx
xxx0
Data EA<15:0>
xxxx xxxx xxxx xxxx
Data EA<15:0>
xxxx xxxx xxxx xxxx
Data EA<14:0>(1)
xxx xxxx xxxx xxxx
Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG<0>.
DS7000591F-page 104
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 4-9:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter
0
0
23 Bits
EA
Table Operations(2)
1/0
1/0
TBLPAG
8 Bits
16 Bits
24 Bits
Select
Space Visibility(1)
Program
(Remapping)
0
EA
1
0
PSVPAG
8 Bits
15 Bits
23 Bits
User/Configuration
Space Select
Note 1:
2:
Byte Select
The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word
alignment of data in the program and data spaces.
Table operations are not required to be word-aligned. Table Read operations are permitted in the
configuration memory space.
 2009-2014 Microchip Technology Inc.
DS7000591F-page 105
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
4.6.2
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going
through data space. The TBLRDH and TBLWTH
instructions are the only method to read or write the
upper 8 bits of a program space word as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit-wide
word address spaces, residing side by side, each with
the same address range. TBLRDL and TBLWTL access
the space that contains the least significant data word.
TBLRDH and TBLWTH access the space that contains the
upper data byte.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.
• TBLRDL (Table Read Low):
- In Word mode, this instruction maps the
lower word of the program space location
(P<15:0>) to a data address (D<15:0>).
FIGURE 4-10:
- In Byte mode, either the upper or lower byte
of the lower program word is mapped to the
lower byte of a data address. The upper byte
is selected when Byte Select is ‘1’; the lower
byte is selected when it is ‘0’.
• TBLRDH (Table Read High):
- In Word mode, this instruction maps the entire
upper word of a program address (P<23:16>)
to a data address. Note that D<15:8>, the
‘phantom byte’, will always be ‘0’.
- In Byte mode, this instruction maps the upper
or lower byte of the program word to D<7:0>
of the data address, in the TBLRDL
instruction. The data is always ‘0’ when
the upper ‘phantom’ byte is selected
(Byte Select = 1).
Similarly, two table instructions, TBLWTH and TBLWTL,
are used to write individual bytes or words to a program
space address. The details of their operation are
explained in Section 5.0 “Flash Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPAG). TBLPAG covers the entire program
memory space of the device, including user and
configuration spaces. When TBLPAG<7> = 0, the table
page is located in the user memory space. When
TBLPAG<7> = 1, the page is located in configuration
space.
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
TBLPAG
02
23
15
0
0x000000
23
16
8
0
00000000
00000000
0x020000
00000000
0x030000
00000000
‘Phantom’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
0x800000
DS7000591F-page 106
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
4.6.3
READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This option provides transparent access to stored
constant data from the data space without the need to
use special instructions (such as TBLRDL/H).
Program space access through the data space occurs
if the Most Significant bit of the data space EA is ‘1’ and
program space visibility is enabled by setting the PSV
bit in the Core Control register (CORCON<2>). The
location of the program memory space to be mapped
into the data space is determined by the Program
Space Visibility Page register (PSVPAG). This 8-bit
register defines any one of 256 possible pages of
16K words in program space. In effect, PSVPAG
functions as the upper 8 bits of the program memory
address, with the 15 bits of the EA functioning as the
lower bits. By incrementing the PC by 2 for each
program memory word, the lower 15 bits of data space
addresses directly map to the lower 15 bits in the
corresponding program space addresses.
Data reads to this area add a cycle to the instruction
being executed, since two program memory fetches
are required.
Although each data space address 8000h and higher
maps directly into a corresponding program memory
address (see Figure 4-11), only the lower 16 bits of the
FIGURE 4-11:
24-bit program word are used to contain the data. The
upper 8 bits of any program space location used as
data should be programmed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
Note:
PSV access is temporarily disabled during
Table Reads/Writes.
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions require
one instruction cycle in addition to the specified
execution time. All other instructions require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV and are executed inside a
REPEAT loop, these instances require two instruction
cycles in addition to the specified execution time of the
instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow the
instruction using PSV to access data, to execute in a
single cycle.
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> = 1 and EA<15> = 1:
Program Space
PSVPAG
02
23
15
Data Space
0
0x000000
0x0000
Data EA<14:0>
0x010000
0x018000
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space...
0x8000
PSV Area
0xFFFF
0x800000
 2009-2014 Microchip Technology Inc.
...while the lower 15 bits
of the EA specify an
exact address within
the PSV area. This
corresponds exactly to
the same lower 15 bits
of the actual program
space address.
DS7000591F-page 107
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS7000591F-page 108
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
5.0
FLASH PROGRAM MEMORY
pin pairs: PGEC1/PGED1, PGEC2/PGED2 or PGEC3/
PGED3), and three other lines for power (VDD), ground
(VSS) and Master Clear (MCLR). This allows customers
to manufacture boards with unprogrammed devices
and then program the Digital Signal Controller (DSC)
just before shipping the product. This also allows the
most recent firmware or a custom firmware to be
programmed.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to “Flash Programming” (DS70191) in the “dsPIC33/PIC24
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com). The information in
this data sheet supersedes the
information in the FRM.
RTSP is accomplished using TBLRD (Table Read) and
TBLWT (Table Write) instructions. With RTSP, the user
application can write program memory data, either in
blocks or ‘rows’ of 64 instructions (192 bytes) at a time,
or a single program memory word, and erase program
memory in blocks or ‘pages’ of 512 instructions
(1536 bytes) at a time.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
5.1
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices contain
internal Flash program memory for storing and executing application code. The memory is readable, writable
and erasable during normal operation over the entire
VDD range.
Flash memory can be programmed in two ways:
• In-Circuit Serial Programming™ (ICSP™)
• Run-Time Self-Programming (RTSP)
ICSP allows a dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610 device to be serially
programmed while in the end application circuit. This is
done with two lines for programming clock and
programming data (one of the alternate programming
FIGURE 5-1:
Table Instructions and Flash
Programming
Regardless of the method used, all programming of
Flash memory is done with the Table Read and Table
Write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using bits<7:0> of the TBLPAG register and the
Effective Address (EA) from a W register specified in
the table instruction, as shown in Figure 5-1.
The TBLRDL and the TBLWTL instructions are used to
read or write to bits<15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
both Word and Byte modes.
The TBLRDH and TBLWTH instructions are used to read
or write to bits<23:16> of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
ADDRESSING FOR TABLE REGISTERS
24 Bits
Using
Program Counter
Program Counter
0
0
Working Reg EA
Using
Table Instruction
1/0
TBLPAG Reg
8 Bits
User/Configuration
Space Select
 2009-2014 Microchip Technology Inc.
16 Bits
24-Bit EA
Byte
Select
DS70000591F-page 109
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
5.2
RTSP Operation
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 Flash program
memory array is organized into rows of 64 instructions or
192 bytes. RTSP allows the user application to erase a
page of memory, which consists of eight rows
(512 instructions) at a time, and to program one row or
one word at a time. Table 27-12 shows typical erase and
programming times. The 8-row erase pages and single
row write rows are edge-aligned from the beginning of
program memory, on boundaries of 1536 bytes and
192 bytes, respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers sequentially. The
instruction words loaded must always be from a group
of 64 boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
All of the Table Write operations are single-word writes
(two instruction cycles) because only the buffers are written. A programming cycle is required for programming
each row.
5.3
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the
programming operation is finished.
For example, if the device is operating at +125°C, the
FRC accuracy will be ±2%. If the TUN<5:0> bits (see
Register 9-4) are set to ‘b000000, the minimum row
write time is equal to Equation 5-2.
EQUATION 5-2:
TRW =
MINIMUM ROW WRITE
TIME
11064 Cycles
= 1.473 ms
7.37 MHz  (1 + 0.02)  (1 – 0.000938)
The maximum row write time is equal to Equation 5-3.
EQUATION 5-3:
TRW =
MAXIMUM ROW WRITE
TIME
11064 Cycles
= 1.533 ms
7.37 MHz  (1 – 0.02)  (1 – 0.000938)
Setting the WR bit (NVMCON<15>) starts the
operation and the WR bit is automatically cleared
when the operation is finished.
5.4
Control Registers
Two SFRs are used to read and write the program
Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user application must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 5.3
“Programming Operations” for further details.
The programming time depends on the FRC accuracy
(see Table 27-20) and the value of the FRC Oscillator
Tuning register (see Register 9-4). Use the following
formula to calculate the minimum and maximum values
for the Row Write Time, Page Erase Time and Word
Write Cycle Time parameters (see Table 27-12).
EQUATION 5-1:
PROGRAMMING TIME
T
-------------------------------------------------------------------------------------------------------------------------7.37 MHz   FRC Accuracy %   FRC Tuning %
DS70000591F-page 110
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 5-1:
NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0(1)
R/W-0(1)
R/W-0(1)
U-0
U-0
U-0
U-0
U-0
WR
WREN
WRERR
—
—
—
—
—
bit 15
bit 8
R/W-0(1)
U-0
—
U-0
ERASE
—
U-0
R/W-0(1)
R/W-0(1)
R/W-0(1)
R/W-0(1)
—
NVMOP3(2)
NVMOP2(2)
NVMOP1(2)
NVMOP0(2)
bit 7
bit 0
Legend:
SO = Settable Only bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
WR: Write Control bit(1)
1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is
cleared by hardware once operation is complete
0 = Program or erase operation is complete and inactive
bit 14
WREN: Write Enable bit(1)
1 = Enables Flash program/erase operations
0 = Inhibits Flash program/erase operations
bit 13
WRERR: Write Sequence Error Flag bit(1)
1 = An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12-7
Unimplemented: Read as ‘0’
bit 6
ERASE: Erase/Program Enable bit(1)
1 = Performs the erase operation specified by the NVMOP<3:0> bits on the next WR command
0 = Performs the program operation specified by the NVMOP<3:0> bits on the next WR command
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
NVMOP<3:0>: NVM Operation Select bits(1,2)
If ERASE = 1:
1111 = Memory bulk erase operation
1101 = Erases General Segment (GS)
0011 = No operation
0010 = Memory page erase operation
0001 = No operation
0000 = Erases a single Configuration register byte
If ERASE = 0:
1111 = No operation
1101 = No operation
0011 = Memory word program operation
0010 = No operation
0001 = Memory row program operation
0000 = Programs a single Configuration register byte
Note 1:
2:
These bits can only be reset on a Power-on Reset.
All other combinations of NVMOP<3:0> are unimplemented.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 111
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 5-2:
NVMKEY: NONVOLATILE MEMORY KEY REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
NVMKEY<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
Unimplemented: Read as ‘0’
bit 7-0
NVMKEY<7:0>: Key Register bits (write-only)
DS70000591F-page 112
x = Bit is unknown
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
5.4.1
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
4.
5.
One row of program Flash memory can be
programmed at a time. To achieve this, it is necessary
to erase the 8-row erase page that contains the desired
row. The general process is:
1.
2.
3.
Read eight rows of program memory
(512 instructions) and store in data RAM.
Update the program data in RAM with the
desired new data.
Erase the block (see Example 5-1):
a) Set the NVMOPx bits (NVMCON<3:0>) to
‘0010’ to configure for block erase. Set the
ERASE (NVMCON<6>) and WREN
(NVMCON<14>) bits.
b) Write the starting address of the page to be
erased into the TBLPAG and W registers.
c) Write 0x55 to NVMKEY.
d) Write 0xAA to NVMKEY.
e) Set the WR bit (NVMCON<15>). The erase
cycle begins and the CPU stalls for the
duration of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
EXAMPLE 5-1:
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
application must wait for the programming time until
programming is complete. The two instructions
following the start of the programming sequence
should be NOPs, as shown in Example 5-3.
ERASING A PROGRAM MEMORY PAGE
; Set up NVMCON for block erase operation
MOV
#0x4042, W0
MOV
W0, NVMCON
; Init pointer to row to be ERASED
MOV
#tblpage(PROG_ADDR), W0
MOV
W0, TBLPAG
MOV
#tbloffset(PROG_ADDR), W0
TBLWTL W0, [W0]
DISI
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
6.
Write the first 64 instructions from data RAM into
the program memory buffers (see Example 5-2).
Write the program block to Flash memory:
a) Set the NVMOPx bits to ‘0001’ to configure
for row programming. Clear the ERASE bit
and set the WREN bit.
b) Write 0x55 to NVMKEY.
c) Write 0xAA to NVMKEY.
d) Set the WR bit. The programming cycle
begins and the CPU stalls for the duration of
the write cycle. When the write to Flash
memory is done, the WR bit is cleared
automatically.
Repeat Steps 4 and 5, using the next available
64 instructions from the block in data RAM by
incrementing the value in TBLPAG, until all
512 instructions are written back to Flash memory.
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
 2009-2014 Microchip Technology Inc.
;
; Initialize NVMCON
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PM Page Boundary SFR
Initialize in-page EA[15:0] pointer
Set base address of erase block
Block all interrupts with priority <7
for next 5 instructions
Write the 55 key
Write the AA key
Start the erase sequence
Insert two NOPs after the erase
command is asserted
DS70000591F-page 113
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
EXAMPLE 5-2:
LOADING THE WRITE BUFFERS
; Set up NVMCON for row programming operations
MOV
#0x4001, W0
;
MOV
W0, NVMCON
; Initialize NVMCON
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV
#0x0000, W0
;
MOV
W0, TBLPAG
; Initialize PM Page Boundary SFR
MOV
#0x6000, W0
; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV
#LOW_WORD_0, W2
;
MOV
#HIGH_BYTE_0, W3
;
TBLWTL W2, [W0]
; Write PM low word into program latch
TBLWTH W3, [W0++]
; Write PM high byte into program latch
; 1st_program_word
MOV
#LOW_WORD_1, W2
;
MOV
#HIGH_BYTE_1, W3
;
TBLWTL W2, [W0]
; Write PM low word into program latch
TBLWTH W3, [W0++]
; Write PM high byte into program latch
; 2nd_program_word
MOV
#LOW_WORD_2, W2
;
MOV
#HIGH_BYTE_2, W3
;
TBLWTL W2, [W0]
; Write PM low word into program latch
TBLWTH W3, [W0++]
; Write PM high byte into program latch
•
•
•
; 63rd_program_word
MOV
#LOW_WORD_31, W2
;
MOV
#HIGH_BYTE_31, W3
;
TBLWTL W2, [W0]
; Write PM low word into program latch
TBLWTH W3, [W0++]
; Write PM high byte into program latch
EXAMPLE 5-3:
INITIATING A PROGRAMMING SEQUENCE
DISI
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
DS70000591F-page 114
; Block all interrupts with priority <7
; for next 5 instructions
;
;
;
;
;
;
Write the 55 key
Write the AA key
Start the erase sequence
Insert two NOPs after the
erase command is asserted
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
6.0
RESETS
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Reset” (DS70192) in
the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
The information in this data sheet
supersedes the information in the FRM.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
•
•
•
•
•
•
•
POR: Power-on Reset
BOR: Brown-out Reset
MCLR: Master Clear Pin Reset
SWR: Software RESET Instruction
WDTO: Watchdog Timer Reset
TRAPR: Trap Conflict Reset
IOPUWR: Illegal Condition Device Reset
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
Any active source of Reset will make the SYSRST
signal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state and some are unaffected.
Note:
Refer to the specific peripheral section or
Section 3.0 “CPU” of this data sheet for
register Reset states.
All types of device Reset sets a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 6-1).
A POR clears all the bits, except for the POR bit
(RCON<0>), that are set. The user application can set
or clear any bit at any time during code execution. The
RCON bits only serve as status bits. Setting a particular
Reset status bit in software does not cause a device
Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset is meaningful.
A simplified block diagram of the Reset module is
shown in Figure 6-1.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 115
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 6-1:
RESET SYSTEM BLOCK DIAGRAM
RESET Instruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
BOR
Internal
Regulator
SYSRST
VDD
VDD Rise
Detect
POR
Trap Conflict
Illegal Opcode
Uninitialized W Register
DS70000591F-page 116
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
RCON: RESET CONTROL REGISTER(1)
REGISTER 6-1:
R/W-0
TRAPR
bit 15
R/W-0
IOPUWR
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
VREGS
bit 8
R/W-0
EXTR
bit 7
R/W-0
SWR
R/W-0
SWDTEN(2)
R/W-0
WDTO
R/W-0
SLEEP
R/W-0
IDLE
R/W-1
BOR
R/W-1
POR
bit 0
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-9
bit 8
bit 7
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or Uninitialized W register used as an
Address Pointer caused a Reset
0 = An Illegal Opcode or Uninitialized W Reset has not occurred
Unimplemented: Read as ‘0’
VREGS: Voltage Regulator Standby During Sleep bit
1 = Voltage regulator is active during Sleep
0 = Voltage regulator goes into Standby mode during Sleep
EXTR: External Reset Pin (MCLR) bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
SWR: Software Reset Flag (Instruction) bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
SWDTEN: Software Enable/Disable of WDT bit(2)
1 = WDT is enabled
0 = WDT is disabled
WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
SLEEP: Wake-up from Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
IDLE: Wake-up from Idle Flag bit
1 = Device has been in Idle mode
0 = Device has not been in Idle mode
BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset has occurred
0 = A Brown-out Reset has not occurred
POR: Power-on Reset Flag bit
1 = A Power-on Reset has occurred
0 = A Power-on Reset has not occurred
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 117
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
6.1
System Reset
A Warm Reset is the result of all the other Reset
sources, including the RESET instruction. On Warm
Reset, the device will continue to operate from the
current clock source as indicated by the Current
Oscillator Selection (COSC<2:0>) bits in the Oscillator
Control (OSCCON<14:12>) register.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 families of devices
have two types of Reset:
• Cold Reset
• Warm Reset
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The sequence in
which this occurs is described in Figure 6-2.
A Cold Reset is the result of a Power-on Reset (POR)
or a Brown-out Reset (BOR). On a Cold Reset, the
FNOSCx Configuration bits in the FOSC Configuration
register select the device clock source.
TABLE 6-1:
OSCILLATOR DELAY
Oscillator Mode
Oscillator
Start-up Delay
Oscillator
Start-up Timer
PLL Lock Time
Total Delay
FRC, FRCDIV16, FRCDIVN
TOSCD(1)
—
—
TOSCD(1)
FRCPLL
TOSCD(1)
—
TLOCK(3)
TOSCD + TLOCK(1,3)
XT
TOST(2)
—
TOSCD + TOST(1,2)
HS
TOSCD(1)
TOSCD(1)
TOST(2)
—
TOSCD + TOST(1,2)
EC
—
—
—
—
TOST(2)
TOST(2)
TLOCK(3)
TLOCK(3)
TOSCD + TOST + TLOCK(1,2,3)
HSPLL
TOSCD(1)
TOSCD(1)
ECPLL
—
—
TLOCK(3)
TLOCK(3)
LPRC
TOSCD(1)
—
—
TOSCD(1)
XTPLL
Note 1:
2:
3:
TOSCD + TOST + TLOCK(1,2,3)
TOSCD = Oscillator start-up delay (1.1 s max. for FRC, 70 s max. for LPRC). Crystal oscillator start-up
times vary with the crystal characteristics, load capacitance, etc.
TOST = Oscillator Start-up Timer (OST) delay (1024 oscillator clock period). For example, TOST = 102.4 s
for a 10 MHz crystal and TOST = 32 ms for a 32 kHz crystal.
TLOCK = PLL lock time (1.5 ms nominal) if PLL is enabled.
DS70000591F-page 118
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 6-2:
SYSTEM RESET TIMING
VBOR
VPOR
VDD
TPOR
1
POR
TBOR
2
BOR
3
TPWRT
SYSRST
4
Oscillator Clock
TOSCD
TOST
TLOCK
6
TFSCM
FSCM
5
Reset
Device Status
Run
Time
Note 1:
2:
3:
4:
5:
6:
TABLE 6-2:
Symbol
POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until
VDD crosses the VPOR threshold and the delay, TPOR, has elapsed.
BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR
threshold and the delay, TBOR, has elapsed. The delay, TBOR, ensures the voltage regulator output becomes stable.
PWRT Timer: The programmable Power-up Timer (PWRT) continues to hold the processor in Reset for a
specific period of time (TPWRT) after a BOR. The delay, TPWRT, ensures that the system power supplies have
stabilized at the appropriate level for full-speed operation. After the delay, TPWRT has elapsed and the SYSRST
becomes inactive, which in turn, enables the selected oscillator to start generating clock cycles.
Oscillator Delay: The total delay for the clock to be ready for various clock source selections is given in
Table 6-1. Refer to Section 9.0 “Oscillator Configuration” for more information.
When the oscillator clock is ready, the processor begins execution from location, 0x000000. The user application
programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up
routine.
If the Fail-Safe Clock Monitor (FSCM) is enabled, it begins to monitor the system clock when the system clock is
ready and the delay, TFSCM, has elapsed.
OSCILLATOR DELAY
Parameter
Value
VPOR
POR Threshold
1.8V nominal
TPOR
POR Extension Time
30 s maximum
VBOR
BOR Threshold
2.5V nominal
TBOR
BOR Extension Time
100 s maximum
TPWRT
Programmable
Power-up Time Delay
0-128 ms nominal
TFSCM
Fail-Safe Clock Monitor 900 s maximum
Delay
 2009-2014 Microchip Technology Inc.
Note:
When the device exits the Reset
condition (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges; otherwise,
the device may not function correctly.
The user application must ensure that
the delay between the time power is first
applied, and the time SYSRST becomes
inactive, is long enough to get all
operating parameters within specification.
DS70000591F-page 119
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
6.2
Power-on Reset (POR)
A Power-on Reset (POR) circuit ensures the device is
reset from power-on. The POR circuit is active until
VDD crosses the VPOR threshold and the delay, TPOR,
has elapsed. The delay, TPOR, ensures the internal
device bias circuits become stable.
The device supply voltage characteristics must meet
the specified starting voltage and rise rate
requirements to generate the POR. Refer to
Section 27.0 “Electrical Characteristics” for details.
The Power-on Reset (POR) status bit in the Reset
Control (RCON<0>) register is set to indicate the
Power-on Reset.
6.3
Brown-out Reset (BOR) and
Power-up Timer (PWRT)
The on-chip regulator has a Brown-out Reset (BOR)
circuit that resets the device when the VDD is too low
(VDD < VBOR) for proper device operation. The BOR
circuit keeps the device in Reset until VDD crosses the
FIGURE 6-3:
VBOR threshold and the delay, TBOR, has elapsed. The
delay, TBOR, ensures the voltage regulator output
becomes stable.
The Brown-out Reset (BOR) status bit in the Reset
Control (RCON<1>) register is set to indicate the
Brown-out Reset.
The device will not run at full speed after a BOR as the
VDD should rise to acceptable levels for full-speed
operation. The PWRT provides a Power-up Time Delay
(TPWRT) to ensure that the system power supplies have
stabilized at the appropriate levels for full-speed
operation before the SYSRST is released.
The Power-up Timer delay (TPWRT) is programmed by
the
Power-on
Reset
Timer
Value
Select
(FPWRT<2:0>) bits in the FPOR Configuration
(FPOR<2:0>) register, which provides eight settings
(from 0 ms to 128 ms). Refer to Section 24.0 “Special
Features” for further details.
Figure 6-3 shows the typical brown-out scenarios. The
Reset delay (TBOR + TPWRT) is initiated each time VDD
rises above the VBOR trip point
BROWN-OUT SITUATIONS
VDD
VBOR
TBOR + TPWRT
SYSRST
VDD
VBOR
TBOR + TPWRT
SYSRST
VDD Dips Before PWRT Expires
VDD
VBOR
TBOR + TPWRT
SYSRST
DS70000591F-page 120
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
6.4
External Reset (EXTR)
The External Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt Trigger input with
an additional glitch filter. Reset pulses that are longer
than the minimum pulse width will generate a Reset.
Refer to Section 27.0 “Electrical Characteristics” for
minimum pulse width specifications. The External
Reset (MCLR) pin (EXTR) bit in the Reset Control
(RCON) register is set to indicate the MCLR Reset.
6.4.1
EXTERNAL SUPERVISORY
CIRCUIT
Many systems have external supervisory circuits that
generate Reset signals to reset multiple devices in the
system. This external Reset signal can be directly
connected to the MCLR pin to reset the device when
the rest of system is reset.
6.4.2
INTERNAL SUPERVISORY CIRCUIT
When using the internal power supervisory circuit to
reset the device, the External Reset pin (MCLR) should
be tied directly or resistively to VDD. In this case, the
MCLR pin will not be used to generate a Reset. The
External Reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
6.7
Trap Conflict Reset
If a lower priority hard trap occurs while a higher
priority trap is being processed, a hard Trap Conflict
Reset occurs. The hard traps include exceptions of
Priority Level 13 through Level 15, inclusive. The
address error (Level 13) and oscillator error (Level 14)
traps fall into this category.
The Trap Reset (TRAPR) flag in the Reset Control
(RCON<15>) register is set to indicate the Trap Conflict
Reset. Refer to Section 7.0 “Interrupt Controller” for
more information on Trap Conflict Resets.
6.8
Illegal Condition Device Reset
An illegal condition device Reset occurs due to the
following sources:
• Illegal Opcode Reset
• Uninitialized W Register Reset
• Security Reset
The Illegal Opcode or Uninitialized W Access Reset
(IOPUWR) flag in the Reset Control (RCON<14>) register
is set to indicate the illegal condition device Reset.
6.8.1
ILLEGAL OPCODE RESET
Software RESET Instruction (SWR)
A device Reset is generated if the device attempts to
execute an illegal opcode value that is fetched from
program memory.
Whenever the RESET instruction is executed, the
device will assert SYSRST, placing the device in a
special Reset state. This Reset state will not
re-initialize the clock. The clock source in effect prior to
the RESET instruction will remain. SYSRST is released
at the next instruction cycle and the Reset vector fetch
will commence.
The Illegal Opcode Reset function can prevent the
device from executing program memory sections that
are used to store constant data. To take advantage of
the Illegal Opcode Reset, use only the lower 16 bits of
each program memory section to store the data values.
The upper 8 bits should be programmed with 3Fh,
which is an illegal opcode value.
The Software Reset (SWR) flag (instruction) in the
Reset Control (RCON<6>) register is set to indicate
the Software Reset.
6.8.2
6.5
6.6
Watchdog Timer Time-out Reset
(WDTO)
Whenever a Watchdog Timer Time-out Reset occurs,
the device will asynchronously assert SYSRST. The
clock source will remain unchanged. A WDT time-out
during Sleep or Idle mode will wake-up the processor,
but will not reset the processor.
The Watchdog Timer Time-out (WDTO) flag in the
Reset Control (RCON<4>) register is set to indicate
the Watchdog Timer Reset. Refer to Section 24.4
“Watchdog Timer (WDT)” for more information on
the Watchdog Timer Reset.
UNINITIALIZED W REGISTER RESET
Any attempt to use the Uninitialized W register as an
Address Pointer will reset the device. The W register
array (with the exception of W15) is cleared during all
Resets and is considered uninitialized until written to.
6.8.3
SECURITY RESET
If a Program Flow Change (PFC) or Vector Flow
Change (VFC) targets a restricted location in a
protected segment (Boot and Secure Segment), that
operation will cause a Security Reset.
The PFC occurs when the Program Counter is reloaded
as a result of a call, jump, computed jump, return, return
from subroutine or other form of branch instruction.
The VFC occurs when the Program Counter is
reloaded with an interrupt or trap vector.
Refer to Section 24.8 “Code Protection and
CodeGuard™ Security” for more information on
Security Reset.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 121
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
6.9
Using the RCON Status Bits
The user application can read the Reset Control
(RCON) register after any device Reset to determine
the cause of the Reset.
Note:
Table 6-3 provides a summary of the Reset flag bit
operation.
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
TABLE 6-3:
RESET FLAG BIT OPERATION
Flag Bit
Set by:
Cleared by:
TRAPR (RCON<15>)
Trap Conflict Event
POR, BOR
IOPWR (RCON<14>)
Illegal Opcode or Uninitialized W register
Access or Security Reset
POR, BOR
EXTR (RCON<7>)
MCLR Reset
POR
SWR (RCON<6>)
RESET Instruction
POR, BOR
WDTO (RCON<4>)
WDT Time-out
PWRSAV Instruction, CLRWDT Instruction,
POR, BOR
SLEEP (RCON<3>)
PWRSAV #SLEEP Instruction
POR, BOR
IDLE (RCON<2>)
PWRSAV #IDLE Instruction
POR, BOR
BOR (RCON<1>)
POR, BOR
—
POR (RCON<0>)
POR
—
Note:
All Reset flag bits can be set or cleared by user software.
DS70000591F-page 122
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
7.0
INTERRUPT CONTROLLER
Note 1: This data sheet summarizes the features of
the
dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Interrupts (Part V)”
(DS70597) in the “dsPIC33/PIC24 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com). The information
in this data sheet supersedes the
information in the FRM.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 interrupt controller
reduces the numerous peripheral interrupt request
signals to a single interrupt request signal to
the
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 CPU. It has the
following features:
• Up to Eight Processor Exceptions and Software
Traps
• Seven User-Selectable Priority Levels
• Interrupt Vector Table (IVT) with up to 118 Vectors
• A Unique Vector for each Interrupt or Exception
Source
• Fixed Priority within a Specified User Priority Level
• Alternate Interrupt Vector Table (AIVT) for Debug
Support
• Fixed Interrupt Entry and Return Latencies
7.1
Interrupt Vector Table
The Interrupt Vector Table (IVT) is shown in Figure 7-1.
The IVT resides in program memory, starting at location
000004h. The IVT contains 126 vectors, consisting of
eight nonmaskable trap vectors, plus up to 118 sources
of interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit-wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
 2009-2014 Microchip Technology Inc.
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with Vector 0 will take priority over interrupts at any
other vector address.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices implement
up to 71 unique interrupts and five non-maskable traps.
These are summarized in Table 7-1.
7.1.1
ALTERNATE INTERRUPT VECTOR
TABLE
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 7-1. Access to the
AIVT is provided by the ALTIVT control bit
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports debugging by providing a means to
switch between an application and a support environment without requiring the interrupt vectors to be
reprogrammed. This feature also enables switching
between applications for evaluation of different software algorithms at run time. If the AIVT is not needed,
the AIVT should be programmed with the same
addresses used in the IVT.
7.2
Reset Sequence
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset
process. The dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610 devices clear their
registers in response to a Reset, which forces the PC to
zero. The Digital Signal Controller (DSC) then begins
program execution at location, 0x000000. A GOTO
instruction at the Reset address can redirect program
execution to the appropriate start-up routine.
Note:
Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
DS70000591F-page 123
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 7-1:
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
INTERRUPT VECTOR TABLE
Decreasing Natural Order Priority
Reset – GOTO Instruction
Reset – GOTO Address
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
DMA Error Trap Vector
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
~
~
~
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
~
~
~
Interrupt Vector 116
Interrupt Vector 117
Reserved
Reserved
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
DMA Error Trap Vector
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
~
~
~
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
~
~
~
Interrupt Vector 116
Interrupt Vector 117
Start of Code
Note 1:
0x000000
0x000002
0x000004
0x000014
0x00007C
0x00007E
0x000080
Interrupt Vector Table (IVT)(1)
0x0000FC
0x0000FE
0x000100
0x000102
0x000114
Alternate Interrupt Vector Table (AIVT)(1)
0x00017C
0x00017E
0x000180
0x0001FE
0x000200
See Table 7-1 for the list of implemented interrupt vectors.
DS70000591F-page 124
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 7-1:
INTERRUPT VECTORS
Vector
Number
Interrupt
Request (IQR)
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29-31
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21-23
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47-56
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39-48
57
58
59-60
49
50
51-52
61
62
53
54
IVT Address
AIVT Address
Interrupt Source
Highest Natural Order Priority
0x000014
0x000114
INT0 – External Interrupt 0
0x000016
0x000116
IC1 – Input Capture 1
0x000018
0x000118
OC1 – Output Compare 1
0x00001A
0x00011A
T1 – Timer1
0x00001C
0x00011C
DMA0 – DMA Channel 0
0x00001E
0x00011E
IC2 – Input Capture 2
0x000020
0x000120
OC2 – Output Compare 2
0x000022
0x000122
T2 – Timer2
0x000024
0x000124
T3 – Timer3
0x000026
0x000126
SPI1E – SPI1 Fault
0x000028
0x000128
SPI1 – SPI1 Transfer Done
0x00002A
0x00012A
U1RX – UART1 Receiver
0x00002C
0x00012C
U1TX – UART1 Transmitter
0x00002E
0x00012E
ADC – ADC Group Convert Done
0x000030
0x000130
DMA1 – DMA Channel 1
0x000032
0x000132
Reserved
0x000034
0x000134
SI2C1 – I2C1 Slave Event
0x000036
0x000136
MI2C1 – I2C1 Master Event
0x000038
0x000138
CMP1 – Analog Comparator 1 Interrupt
0x00003A
0x00013A
CN – Input Change Notification Interrupt
0x00003C
0x00013C
INT1 – External Interrupt 1
0x00003E0x00013EReserved
0x000042
0x000142
0x000044
0x000144
DMA2 – DMA Channel 2
0x000046
0x000146
OC3 – Output Compare 3
0x000048
0x000148
OC4 – Output Compare 4
0x00004A
0x00014A
T4 – Timer4
0x00004C
0x00014C
T5 – Timer5
0x00004E
0x00014E
INT2 – External Interrupt 2
0x000050
0x000150
U2RX – UART2 Receiver
0x000052
0x000152
U2TX – UART2 Transmitter
0x000054
0x000154
SPI2E – SPI2 Error
0x000056
0x000156
SPI2 – SPI2 Transfer Done
0x000058
0x000158
C1RX – ECAN1 Receive Data Ready
0x00005A
0x00015A
C1 – ECAN1 Event
0x00005C
0x00015C
DMA3 – DMA Channel 3
0x00005E
0x00015E
IC3 – Input Capture 3
0x000060
0x000160
IC4 – Input Capture 4
0x0000620x000162Reserved
0x000074
0x000174
0x000076
0x000176
SI2C2 – I2C2 Slave Events
0x000078
0x000178
MI2C2 – I2C2 Master Events
0x00007A0x00017AReserved
0x00007C
0x00017C
0x00007E
0x00017E
INT3 – External Interrupt 3
0x000080
0x000180
INT4 – External Interrupt 4
 2009-2014 Microchip Technology Inc.
DS70000591F-page 125
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 7-1:
INTERRUPT VECTORS (CONTINUED)
Vector
Number
Interrupt
Request (IQR)
63-64
55-56
65
66
67-72
57
58
59-64
73
74
75-77
65
66
67-69
78
79
80
81
82
83
84-88
70
71
72
73
74
75
76-80
89
90
91
92
93
94-101
81
82
83
84
85
86-93
102
103
104
105
106
107
108
109
110
111
112
113
114-117
94
95
96
97
98
99
100
101
102
103
104
105
106-109
118
119
120
121
122
123
124
125
110
111
112
113
114
115
116
117
DS70000591F-page 126
IVT Address
AIVT Address
Interrupt Source
0x0000820x000182Reserved
0x000084
0x000184
0x000086
0x000186
PWM PSEM Special Event Match
0x000088
0x000188
QEI1 – Position Counter Compare
0x00008A0x00018AReserved
0x000094
0x000194
0x000096
0x000196
U1E – UART1 Error Interrupt
0x000098
0x000198
U2E – UART2 Error Interrupt
0x00009A0x00019AReserved
0x00009E
0x00019E
0x0000A0
0x0001A0
C1TX – ECAN1 Transmit Data Request
0x0000A2
0x0001A2
Reserved
0x0000A4
0x0001A4
Reserved
0x0000A6
0x0001A6
PWM Secondary Special Event Match
0x0000A8
0x0001A8
Reserved
0x0000AA
0x0001AA
QEI2 – Position Counter Compare
0x0000AC0x0001ACReserved
0x0000B4
0x0001B4
0x0000B6
0x0001B6
ADC Pair 8 Conversion Done
0x0000B8
0x0001B8
ADC Pair 9 Conversion Done
0x0000BA
0x0001BA
ADC Pair 10 Conversion Done
0x0000BC
0x0001BC
ADC Pair 11 Conversion Done
0x0000BE
0x0001BE
ADC Pair 12 Conversion Done
0x0000C00x0001C0Reserved
0x0000CE
0x0001CE
0x0000D0
0x0001D0
PWM1 – PWM1 Interrupt
0x0000D2
0x0001D2
PWM2 – PWM2 Interrupt
0x0000D4
0x0001D4
PWM3 – PWM3 Interrupt
0x0000D6
0x0001D6
PWM4 – PWM4 Interrupt
0x0000D8
0x0001D8
PWM5 – PWM5 Interrupt
0x0000DA
0x0001DA
PWM6 – PWM6 Interrupt
0x0000DC
0x0001DC
PWM7– PWM7 Interrupt
0x0000DE
0x0001DE
PWM8 – PWM8 Interrupt
0x0000E0
0x0001E0
PWM9 – PWM9 Interrupt
0x0000E2
0x00001E2
CMP2 – Analog Comparator 2
0x0000E4
0x0001E4
CMP3 – Analog Comparator 3
0x0000E6
0x0001E6
CMP4 – Analog Comparator 4
0x0000E80x0001E8Reserved
0x0000EE
0x0001EE
0x0000F0
0x0001F0
ADC Pair 0 Convert Done
0x0000F2
0x0001F2
ADC Pair 1 Convert Done
0x0000F4
0x0001F4
ADC Pair 2 Convert Done
0x0000F6
0x0001F6
ADC Pair 3 Convert Done
0x0000F8
0x0001F8
ADC Pair 4 Convert Done
0x0000FA
0x0001FA
ADC Pair 5 Convert Done
0x0000FC
0x0001FC
ADC Pair 6 Convert Done
0x0000FE
0x0001FE
ADC Pair 7 Convert Done
Lowest Natural Order Priority
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
7.3
Interrupt Control and Status
Registers
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices implement
44 registers for the interrupt controller:
•
•
•
•
•
•
INTCON1
INTCON2
IFSx
IECx
IPCx
INTTREG
7.3.1
INTCON1 AND INTCON2
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the
Interrupt Nesting Disable (NSTDIS) bit as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.
7.3.2
IFSx
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.
7.3.3
IECx
The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
7.3.4
7.3.5
INTTREG
The INTTREG register contains the associated
interrupt vector number and the new CPU Interrupt
Priority Level, which are latched into the Vector Number (VECNUM<6:0>) and Interrupt Level (ILR<3:0>) bit
fields in the INTTREG register. The new Interrupt
Priority Level is the priority of the pending interrupt.
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence that they are
listed in Table 7-1. For example, the INT0 (External
Interrupt 0) is shown as having vector number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit is found in IEC0<0> and the
INT0IP bits are found in the first position of IPC0
(IPC0<2:0>).
7.3.6
STATUS/CONTROL REGISTERS
Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers
contain bits that control interrupt functionality.
• The CPU STATUS Register, SR, contains the
IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU Interrupt Priority Level. The user can
change the current CPU Priority Level by writing
to the IPLx bits.
• The CORCON register contains the IPL3 bit,
which together with IPL<2:0>, indicates the
current CPU Priority Level. IPL3 is a read-only bit
so that trap events cannot be masked by the user
software.
All Interrupt registers are described in Register 7-1
through Register 7-46 in the following pages.
IPCx
The IPCx registers are used to set the Interrupt Priority
Level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 127
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
SR: CPU STATUS REGISTER(1)
REGISTER 7-1:
R-0
R-0
R/C-0
R/C-0
R-0
R/C-0
R-0
R/W-0
OA
OB
SA
SB
OAB
SAB
DA
DC
bit 15
bit 8
R/W-0(3)
IPL2
R/W-0(3)
(2)
IPL1
(2)
R/W-0(3)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
IPL0(2)
RA
N
OV
Z
C
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)
111 = CPU Interrupt Priority Level is 7 (15), user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 7-5
Note 1:
2:
3:
For complete register details, see Register 3-1.
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
CORCON: CORE CONTROL REGISTER(1)
REGISTER 7-2:
U-0
U-0
U-0
R/W-0
R/W-0
R-0
R-0
R-0
—
—
—
US
EDT
DL2
DL1
DL0
bit 15
bit 8
R/W-0
R/W-0
SATA
SATB
R/W-1
SATDW
R/W-0
R/C-0
R/W-0
R/W-0
R/W-0
ACCSAT
IPL3(2)
PSV
RND
IF
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
-n = Value at POR
0’ = Bit is cleared
‘x = Bit is unknown
U = Unimplemented bit, read as ‘0’
bit 3
Note 1:
2:
‘1’ = Bit is set
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
For complete register details, see Register 3-2.
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
DS70000591F-page 128
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-3:
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NSTDIS
OVAERR
OVBERR
COVAERR
COVBERR
OVATE
OVBTE
COVTE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
SFTACERR
DIV0ERR
DMACERR
MATHERR
ADDRERR
STKERR
OSCFAIL
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
NSTDIS: Interrupt Nesting Disable bit
1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
bit 14
OVAERR: Accumulator A Overflow Trap Flag bit
1 = Trap was caused by an overflow of Accumulator A
0 = Trap was not caused by an overflow of Accumulator A
bit 13
OVBERR: Accumulator B Overflow Trap Flag bit
1 = Trap was caused by an overflow of Accumulator B
0 = Trap was not caused by an overflow of Accumulator B
bit 12
COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit
1 = Trap was caused by a catastrophic overflow of Accumulator A
0 = Trap was not caused by a catastrophic overflow of Accumulator A
bit 11
COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit
1 = Trap was caused by a catastrophic overflow of Accumulator B
0 = Trap was not caused by a catastrophic overflow of Accumulator B
bit 10
OVATE: Accumulator A Overflow Trap Enable bit
1 = Trap overflow of Accumulator A
0 = Trap is disabled
bit 9
OVBTE: Accumulator B Overflow Trap Enable bit
1 = Trap overflow of Accumulator B
0 = Trap is disabled
bit 8
COVTE: Catastrophic Overflow Trap Enable bit
1 = Trap on a catastrophic overflow of Accumulator A or B is enabled
0 = Trap is disabled
bit 7
SFTACERR: Shift Accumulator Error Status bit
1 = Math error trap was caused by an invalid accumulator shift
0 = Math error trap was not caused by an invalid accumulator shift
bit 6
DIV0ERR: Arithmetic Error Status bit
1 = Math error trap was caused by a divide-by-zero
0 = Math error trap was not caused by a divide-by-zero
bit 5
DMACERR: DMA Controller Error Status bit
1 = DMA Controller error trap has occurred
0 = DMA Controller error trap has not occurred
bit 4
MATHERR: Arithmetic Error Status bit
1 = Math error trap has occurred
0 = Math error trap has not occurred
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 129
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-3:
INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)
bit 3
ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred
bit 2
STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred
0 = Stack error trap has not occurred
bit 1
OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred
bit 0
Unimplemented: Read as ‘0’
DS70000591F-page 130
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-4:
R/W-0
ALTIVT
INTCON2: INTERRUPT CONTROL REGISTER 2
R-0
U-0
U-0
U-0
U-0
U-0
U-0
DISI
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
ALTIVT: Enable Alternate Interrupt Vector Table bit
1 = Uses Alternate Interrupt Vector Table
0 = Uses standard (default) Interrupt Vector Table
bit 14
DISI: DISI Instruction Status bit
1 = DISI instruction is active
0 = DISI instruction is not active
bit 13-5
Unimplemented: Read as ‘0’
bit 4
INT4EP: External Interrupt 4 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 3
INT3EP: External Interrupt 3 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 2
INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 1
INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 0
INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 131
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
DMA1IF
ADIF
U1TXIF
U1RXIF
SPI1IF
SPI1EIF
T3IF
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T2IF
OC2IF
IC2IF
DMA0IF
T1IF
OC1IF
IC1IF
INT0IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14
DMA1IF: DMA Channel 1 Data Transfer Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13
ADIF: ADC Group Conversion Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12
U1TXIF: UART1 Transmitter Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 11
U1RXIF: UART1 Receiver Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10
SPI1IF: SPI1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 9
SPI1EIF: SPI1 Fault Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8
T3IF: Timer3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7
T2IF: Timer2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6
OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5
IC2IF: Input Capture Channel 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4
DMA0IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3
T1IF: Timer1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
DS70000591F-page 132
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)
bit 2
OC1IF: Output Compare Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1
IC1IF: Input Capture Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
INT0IF: External Interrupt 0 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
 2009-2014 Microchip Technology Inc.
DS70000591F-page 133
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-6:
IFS1: INTERRUPT FLAG STATUS REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
DMA2IF
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
INT1IF
CNIF
AC1IF
MI2C1IF
SI2C1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 12
U2TXIF: UART2 Transmitter Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 11
U2RXIF: UART2 Receiver Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13
INT2IF: External Interrupt 2 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12
T5IF: Timer5 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 11
T4IF: Timer4 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10
OC4IF: Output Compare Channel 4 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 9
OC3IF: Output Compare Channel 3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8
DMA2IF: DMA Channel 2 Data Transfer Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7-5
Unimplemented: Read as ‘0’
bit 4
INT1IF: External Interrupt 1 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3
CNIF: Input Change Notification Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2
AC1IF: Analog Comparator 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
DS70000591F-page 134
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-6:
IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED)
bit 1
MI2C1IF: I2C1 Master Events Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
 2009-2014 Microchip Technology Inc.
DS70000591F-page 135
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-7:
IFS2: INTERRUPT FLAG STATUS REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
IC4IF
IC3IF
DMA3IF
C1IF(1)
C1RXIF(1)
SPI2IF
SPI2EIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-7
Unimplemented: Read as ‘0’
bit 6
IC4IF: Input Capture Channel 4 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5
IC3IF: Input Capture Channel 3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4
DMA3IF: DMA Channel 3 Data Transfer Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3
C1IF: ECAN1 Event Interrupt Flag Status bit(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2
C1RXIF: ECAN1 External Event Interrupt Flag Status bit(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1
SPI2IF: SPI2 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
SPI2EIF: SPI2 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
Note 1:
Interrupts are disabled on devices without ECAN™ modules.
DS70000591F-page 136
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-8:
IFS3: INTERRUPT FLAG STATUS REGISTER 3
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
U-0
—
—
—
—
—
QEI1IF
PSEMIF
—
bit 15
bit 8
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
U-0
—
INT4IF
INT3IF
—
—
MI2C2IF
SI2C2IF
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10
QEI1IF: QEI1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 9
PSEMIF: PWM Special Event Match Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8-7
Unimplemented: Read as ‘0’
bit 6
INT4IF: External Interrupt 4 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5
INT3IF: External Interrupt 3 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4-3
Unimplemented: Read as ‘0’
bit 2
MI2C2IF: I2C2 Master Events Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1
SI2C2IF: I2C2 Slave Events Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
Unimplemented: Read as ‘0’
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 137
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-9:
IFS4: INTERRUPT FLAG STATUS REGISTER 4
U-0
U-0
U-0
U-0
R/W-0
U-0
R/W-0
U-0
—
—
—
—
QEI2IF
—
PSESMIF
—
bit 15
bit 8
U-0
R/W-0
—
C1TXIF
(1)
U-0
U-0
U-0
R/W-0
R/W-0
U-0
—
—
—
U2EIF
U1EIF
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
Unimplemented: Read as ‘0’
bit 11
QEI2IF: QEI2 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10
Unimplemented: Read as ‘0’
bit 9
PSESMIF: PWM Special Event Secondary Match Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8-7
Unimplemented: Read as ‘0’
bit 6
C1TXIF: ECAN1 Transmit Data Request Interrupt Flag Status bit(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5-3
Unimplemented: Read as ‘0’
bit 2
U2EIF: UART2 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1
U1EIF: UART1 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
Unimplemented: Read as ‘0’
Note 1:
Interrupts are disabled on devices without ECAN™ modules.
DS70000591F-page 138
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-10:
R/W-0
IFS5: INTERRUPT FLAG STATUS REGISTER 5
R/W-0
PWM2IF
PWM1IF
R/W-0
U-0
U-0
U-0
U-0
U-0
ADCP12IF
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
—
—
ADCP11IF
ADCP10IF
ADCP9IF
ADCP8IF
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
PWM2IF: PWM2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 14
PWM1IF: PWM1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13
ADCP12IF: ADC Pair 12 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12-5
Unimplemented: Read as ‘0’
bit 4
ADCP11IF: ADC Pair 11 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3
ADCP10IF: ADC Pair 10 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2
ADCP9IF: ADC Pair 9 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1
ADCP8IF: ADC Pair 8 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
Unimplemented: Read as ‘0’
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 139
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-11:
R/W-0
ADCP1IF
IFS6: INTERRUPT FLAG STATUS REGISTER 6
R/W-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
ADCP0IF
—
—
—
—
AC4IF
AC3IF
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AC2IF
PWM9IF
PWM8IF
PWM7IF
PWM6IF
PWM5IF
PWM4IF
PWM3IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
ADCP1IF: ADC Pair 1 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 14
ADCP0IF: ADC Pair 0 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13-10
Unimplemented: Read as ‘0’
bit 9
AC4IF: Analog Comparator 4 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8
AC3IF: Analog Comparator 3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7
AC2IF: Analog Comparator 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6
PWM9IF: PWM9 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5
PWM8IF: PWM8 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4
PWM7IF: PWM7 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3
PWM6IF: PWM6 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2
PWM5IF: PWM5 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1
PWM4IF: PWM4 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
PWM3IF: PWM3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
DS70000591F-page 140
x = Bit is unknown
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-12:
IFS7: INTERRUPT FLAG STATUS REGISTER 7
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
ADCP7IF
ADCP6IF
ADCP5IF
ADCP4IF
ADCP3IF
ADCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-6
Unimplemented: Read as ‘0’
bit 5
ADCP7IF: ADC Pair 7 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4
ADCP6IF: ADC Pair 6 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3
ADCP5IF: ADC Pair 5 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2
ADCP4IF: ADC Pair 4 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1
ADCP3IF: ADC Pair 3 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
ADCP2IF: ADC Pair 2 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 141
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-13:
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
DMA1IE
ADIE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T2IE
OC2IE
IC2IE
DMA0IE
T1IE
OC1IE
IC1IE
INT0IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14
DMA1IE: DMA Channel 1 Data Transfer Complete Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 13
ADIE: ADC1 Conversion Complete Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 12
U1TXIE: UART1 Transmitter Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 11
U1RXIE: UART1 Receiver Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 10
SPI1IE: SPI1 Event Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 9
SPI1EIE: SPI1 Event Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 8
T3IE: Timer3 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 7
T2IE: Timer2 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 6
OC2IE: Output Compare Channel 2 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 5
IC2IE: Input Capture Channel 2 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 4
DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 3
T1IE: Timer1 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
DS70000591F-page 142
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-13:
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)
bit 2
OC1IE: Output Compare Channel 1 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1
IC1IE: Input Capture Channel 1 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0
INT0IE: External Interrupt 0 Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
 2009-2014 Microchip Technology Inc.
DS70000591F-page 143
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-14:
IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
DMA2IE
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
INT1IE
CNIE
AC1IE
MI2C1IE
SI2C1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 12
U2TXIE: UART2 Transmitter Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 11
U2RXIE: UART2 Receiver Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 13
INT2IE: External Interrupt 2 Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 12
T5IE: Timer5 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 11
T4IE: Timer4 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 10
OC4IE: Output Compare Channel 4 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 9
OC3IE: Output Compare Channel 3 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 8
DMA2IE: DMA Channel 2 Data Transfer Complete Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 7-5
Unimplemented: Read as ‘0’
bit 4
INT1IE: External Interrupt 1 Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 3
CNIE: Input Change Notification Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 2
AC1IE: Analog Comparator 1 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
DS70000591F-page 144
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-14:
IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED)
bit 1
MI2C1IE: I2C1 Master Events Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0
SI2C1IE: I2C1 Slave Events Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
 2009-2014 Microchip Technology Inc.
DS70000591F-page 145
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-15:
IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
IC4IE
IC3IE
DMA3IE
C1IE(1)
C1RXIE(1)
SPI2IE
SPI2EIE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-7
Unimplemented: Read as ‘0’
bit 6
IC4IE: Input Capture Channel 4 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 5
IC3IE: Input Capture Channel 3 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 4
DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 3
C1IE: ECAN1 Event Interrupt Enable bit(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 2
C1RXIE: ECAN1 Receive Data Ready Interrupt Enable bit(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1
SPI2IE: SPI2 Event Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0
SPI2EIE: SPI2 Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
Note 1:
Interrupts are disabled on devices without ECAN™ modules.
DS70000591F-page 146
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-16:
IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
U-0
—
—
—
—
—
QEI1IE
PSEMIE
—
bit 15
bit 8
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
U-0
—
INT4IE
INT3IE
—
—
MI2C2IE
SI2C2IE
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10
QEI1IE: QEI1 Event Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 9
PSEMIE: PWM Special Event Match Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 8-7
Unimplemented: Read as ‘0’
bit 6
INT4IE: External Interrupt 4 Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 6
INT3IE: External Interrupt 3 Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 4-3
Unimplemented: Read as ‘0’
bit 2
MI2C2IE: I2C2 Master Events Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1
SI2C2IE: I2C2 Slave Events Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0
Unimplemented: Read as ‘0’
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 147
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-17:
IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
U-0
U-0
U-0
U-0
R/W-0
U-0
R/W-0
U-0
—
—
—
—
QEI2IE
—
PSESMIE
—
bit 15
bit 8
U-0
R/W-0
—
C1TXIE
(1)
U-0
U-0
U-0
R/W-0
R/W-0
U-0
—
—
—
U2EIE
U1EIE
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
Unimplemented: Read as ‘0’
bit 11
QEI2IE: QEI2 Event Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 10
Unimplemented: Read as ‘0’
bit 9
PSESMIE: PWM Special Event Secondary Match Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 8-7
Unimplemented: Read as ‘0’
bit 6
C1TXIE: ECAN1 Transmit Data Request Interrupt Enable bit(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5-3
Unimplemented: Read as ‘0’
bit 2
U2EIE: UART2 Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1
U1EIE: UART1 Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0
Unimplemented: Read as ‘0’
Note 1:
Interrupts are disabled on devices without ECAN™ modules.
DS70000591F-page 148
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-18:
R/W-0
IEC5: INTERRUPT ENABLE CONTROL REGISTER 5
R/W-0
PWM2IE
PWM1IE
R/W-0
U-0
U-0
U-0
U-0
U-0
ADCP12IE
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
PWM2IE: PWM2 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 14
PWM1IE: PWM1 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 13
ADCP12IE: ADC Pair 12 Conversion Done Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 12-0
Unimplemented: Read as ‘0’
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 149
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-19:
R/W-0
ADCP1IE
IEC6: INTERRUPT ENABLE CONTROL REGISTER 6
R/W-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
ADCP0IE
—
—
—
—
AC4IE
AC3IE
bit 15
bit 8
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
AC2IE
—
—
—
PWM6IE
PWM5IE
PWM4IE
PWM3IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
ADCP1IE: ADC Pair 1 Conversion Done Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 14
ADCP0IE: ADC Pair 0 Conversion Done Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 13-10
Unimplemented: Read as ‘0’
bit 9
AC4IE: Analog Comparator 4 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 8
AC3IE: Analog Comparator 3 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 7
AC2IE: Analog Comparator 2 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 6-4
Unimplemented: Read as ‘0’
bit 3
PWM6IE: PWM6 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 2
PWM5IE: PWM5 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1
PWM4IE: PWM4 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0
PWM3IE: PWM3 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
DS70000591F-page 150
x = Bit is unknown
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-20:
IEC7: INTERRUPT ENABLE CONTROL REGISTER 7
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
ADCP7IE
ADCP6IE
ADCP5IE
ADCP4IE
ADCP3IE
ADCP2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-6
Unimplemented: Read as ‘0’
bit 5
ADCP7IE: ADC Pair 7 Conversion Done Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 4
ADCP6IE: ADC Pair 6 Conversion Done Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 3
ADCP5IE: ADC Pair 5 Conversion Done Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 2
ADCP4IE: ADC Pair 4 Conversion Done Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1
ADCP3IE: ADC Pair 3 Conversion Done Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0
ADCP2IE: ADC Pair 2 Conversion Done Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 151
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-21:
IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP1
INT0IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
T1IP<2:0>: Timer1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT0IP<2:0>: External Interrupt 0 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
DS70000591F-page 152
x = Bit is unknown
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-22:
IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
IC2IP2
IC2IP1
IC2IP0
—
DMA0IP2
DMA0IP1
DMA0IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
T2IP<2:0>: Timer2 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
 2009-2014 Microchip Technology Inc.
DS70000591F-page 153
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-23:
IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
SPI1EIP2
SPI1EIP1
SPI1EIP0
—
T3IP2
T3IP1
T3IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
SPI1IP<2:0>: SPI1 Event Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T3IP<2:0>: Timer3 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
DS70000591F-page 154
x = Bit is unknown
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-24:
IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
DMA1IP2
DMA1IP1
DMA1IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
ADIP2
ADIP1
ADIP0
—
U1TXIP2
U1TXIP1
U1TXIP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
DMA1IP<2:0>: DMA Channel 1 Data Transfer Complete Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
ADIP<2:0>: ADC1 Conversion Complete Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
 2009-2014 Microchip Technology Inc.
DS70000591F-page 155
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-25:
IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
CNIP2
CNIP1
CNIP0
—
AC1IP2
AC1IP1
AC1IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
MI2C1IP2
MI2C1IP1
MI2C1IP0
—
SI2C1IP2
SI2C1IP1
SI2C1IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
CNIP<2:0>: Change Notification Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
AC1IP<2:0>: Analog Comparator 1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
DS70000591F-page 156
x = Bit is unknown
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-26:
IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
INT1IP2
INT1IP1
INT1IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-3
Unimplemented: Read as ‘0’
bit 2-0
INT1IP<2:0>: External Interrupt 1 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 157
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-27:
IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
OC3IP2
OC3IP1
OC3IP0
—
DMA2IP2
DMA2IP1
DMA2IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
T4IP<2:0>: Timer4 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DMA2IP<2:0>: DMA Channel 2 Data Transfer Complete Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
DS70000591F-page 158
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-28:
IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2
T5IP1
T5IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
INT2IP<2:0>: External Interrupt 2 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T5IP<2:0>: Timer5 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 159
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-29:
IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
C1IP2(1)
C1IP1(1)
C1IP0(1)
—
C1RXIP2(1)
C1RXIP1(1)
C1RXIP0(1)
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
SPI2IP2
SPI2IP1
SPI2IP0
—
SPI2EIP2
SPI2EIP1
SPI2EIP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
C1IP<2:0>: ECAN1 Event Interrupt Priority bits(1)
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
C1RXIP<2:0>: ECAN1 Receive Data Ready Interrupt Priority bits(1)
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SPI2IP<2:0>: SPI2 Event Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SPI2EIP<2:0>: SPI2 Error Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
Note 1:
Interrupts are disabled on devices without ECAN™ modules.
DS70000591F-page 160
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-30:
IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
IC4IP2
IC4IP1
IC4IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
IC3IP2
IC3IP1
IC3IP0
—
DMA3IP2
DMA3IP1
DMA3IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
IC4IP<2:0>: Input Capture Channel 4 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC3IP<2:0>: Input Capture Channel 3 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
 2009-2014 Microchip Technology Inc.
DS70000591F-page 161
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-31:
IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
MI2C2IP2
MI2C2IP1
MI2C2IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
MI2C2IP<2:0>: I2C2 Master Events Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SI2C2IP<2:0>: I2C2 Slave Events Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS70000591F-page 162
x = Bit is unknown
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-32:
IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
INT4IP2
INT4IP1
INT4IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
INT3IP2
INT3IP1
INT3IP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
INT4IP<2:0>: External Interrupt 4 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
INT3IP<2:0>: External Interrupt 3 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 163
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-33:
IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
QEI1IP2
QEI1IP1
QEI1IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
PSEMIP2
PSEMIP1
PSEMIP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
QEI1IP<2:0>: QEI1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
PSEMIP<2:0>: PWM Special Event Match Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS70000591F-page 164
x = Bit is unknown
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-34:
IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
U2EIP2
U2EIP1
U2EIP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
U1EIP2
U1EIP1
U1EIP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
U2EIP<2:0>: UART2 Error Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
U1EIP<2:0>: UART1 Error Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 165
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-35:
IPC17: INTERRUPT PRIORITY CONTROL REGISTER 17
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
C1TXIP2(1)
C1TXIP1(1)
C1TXIP0(1)
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
C1TXIP<2:0>: ECAN1 Transmit Data Request Interrupt Priority bits(1)
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7-0
Unimplemented: Read as ‘0’
Note 1:
Interrupts are disabled on devices without ECAN™ modules.
DS70000591F-page 166
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-36:
IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
QEI2IP2
QEI2IP1
QEI2IP0
—
—
—
—
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
PSESMIP2
PSESMIP1
PSESMIP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
QEI2IP<2:0>: QEI2 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11-7
Unimplemented: Read as ‘0’
bit 6-4
PSESMIP<2:0>: PWM Special Event Secondary Match Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
 2009-2014 Microchip Technology Inc.
DS70000591F-page 167
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-37:
IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20
U-0
R/W-1
—
ADCP10IP2
R/W-0
R/W-0
ADCP10IP1 ADCP10IP0
U-0
R/W-1
R/W-0
R/W-0
—
ADCP9IP2
ADCP9IP1
ADCP9IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
ADCP8IP2
ADCP8IP1
ADCP8IP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
ADCP10IP<2:0>: ADC Pair 10 Conversion Done Interrupt 1 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
ADCP9IP<2:0>: ADC Pair 9 Conversion Done Interrupt 1 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
ADCP8IP<2:0>: ADC Pair 8 Conversion Done Interrupt 1 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS70000591F-page 168
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-38:
IPC21: INTERRUPT PRIORITY CONTROL REGISTER 21
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-1
—
ADCP12IP2
R/W-0
R/W-0
ADCP12IP1 ADCP12IP0
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
ADCP12IP<2:0>: ADC Pair 12 Conversion Done Interrupt 1 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 169
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-39:
IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
PWM2IP2
PWM2IP1
PWM2IP0
—
PWM1IP2
PWM1IP1
PWM1IP0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
PWM2IP<2:0>: PWM2 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
PWM1IP<2:0>: PWM1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7-0
Unimplemented: Read as ‘0’
DS70000591F-page 170
x = Bit is unknown
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-40:
IPC24: INTERRUPT PRIORITY CONTROL REGISTER 24
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
PWM6IP2
PWM6IP1
PWM6IP0
—
PWM5IP2
PWM5IP1
PWM5IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
PWM4IP2
PWM4IP1
PWM4IP0
—
PWM3IP2
PWM3IP1
PWM3IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
PWM6IP<2:0>: PWM6 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
PWM5IP<2:0>: PWM5 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
PWM4IP<2:0>: PWM4 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
PWM3IP<2:0>: PWM3 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 171
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-41:
IPC25: INTERRUPT PRIORITY CONTROL REGISTER 25
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
AC2IP2
AC2IP1
AC2IP0
—
PWM9IP2
PWM9IP1
PWM9IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
PWM8IP2
PWM8IP1
PWM8IP0
—
PWM7IP2
PWM7IP1
PWM7IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
AC2IP<2:0>: Analog Comparator 2 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
PWM9IP<2:0>: PWM9 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
PWM8IP<2:0>: PWM8 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
PWM7IP<2:0>: PWM7 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
DS70000591F-page 172
x = Bit is unknown
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-42:
IPC26: INTERRUPT PRIORITY CONTROL REGISTER 26
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
AC4IP2
AC4IP1
AC4IP0
—
AC3IP2
AC3IP1
AC3IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
AC4IP<2:0>: Analog Comparator 4 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
AC3IP<2:0>: Analog Comparator 3 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 173
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-43:
IPC27: INTERRUPT PRIORITY CONTROL REGISTER 27
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
ADCP1IP2
ADCP1IP1
ADCP1IP0
—
ADCP0IP2
ADCP0IP1
ADCP0IP0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
ADCP1IP<2:0>: ADC Pair 1 Conversion Done Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
ADCP0IP<2:0>: ADC Pair 0 Conversion Done Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7-0
Unimplemented: Read as ‘0’
DS70000591F-page 174
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-44:
IPC28: INTERRUPT PRIORITY CONTROL REGISTER 28
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
ADCP5IP2
ADCP5IP1
ADCP5IP0
—
ADCP4IP2
ADCP4IP1
ADCP4IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
ADCP3IP2
ADCP3IP1
ADCP3IP0
—
ADCP2IP2
ADCP2IP1
ADCP2IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
ADCP5IP<2:0>: ADC Pair 5 Conversion Done Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
ADCP4IP<2:0>: ADC Pair 4 Conversion Done Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
ADCP3IP<2:0>: ADC Pair 3 Conversion Done Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
ADCP2IP<2:0>: ADC Pair 2 Conversion Done Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 175
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-45:
IPC29: INTERRUPT PRIORITY CONTROL REGISTER 29
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
ADCP7IP2
ADCP7IP1
ADCP7IP0
—
ADCP6IP2
ADCP6IP1
ADCP6IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
ADCP7IP<2:0>: ADC Pair 7 Conversion Done Interrupt 1 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
ADCP6IP<2:0>: ADC Pair 6 Conversion Done Interrupt 1 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
DS70000591F-page 176
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-46:
INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
—
—
—
—
ILR3
ILR2
ILR1
ILR0
bit 15
bit 8
U-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
—
VECNUM6
VECNUM5
VECNUM4
VECNUM3
VECNUM2
VECNUM1
VECNUM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
Unimplemented: Read as ‘0’
bit 11-8
ILR<3:0>: New CPU Interrupt Priority Level bits
1111 = CPU Interrupt Priority Level is 15
•
•
•
0001 = CPU Interrupt Priority Level is 1
0000 = CPU Interrupt Priority Level is 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
VECNUM<6:0>: Vector Number of Pending Interrupt bits
0111111 = Interrupt vector pending is Number 135
•
•
•
0000001 = Interrupt vector pending is Number 9
0000000 = Interrupt vector pending is Number 8
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 177
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
7.4
7.4.3
Interrupt Setup Procedures
7.4.1
INITIALIZATION
Complete the following steps to configure an interrupt
source at initialization:
1.
2.
Set the NSTDIS bit (INTCON1<15>) if nested
interrupts are not desired.
Select the user-assigned priority level for the
interrupt source by writing the control bits in the
appropriate IPCx register. The priority level will
depend on the specific application and type of
interrupt source. If multiple priority levels are not
desired, the IPCx register control bits for all
enabled interrupt sources can be programmed
to the same non-zero value.
Note:
3.
4.
At a device Reset, the IPCx registers are
initialized such that all user interrupt
sources are assigned to Priority Level 4.
Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
Enable the interrupt source by setting the
interrupt enable control bit associated with the
source in the appropriate IECx register.
7.4.2
TRAP SERVICE ROUTINE
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
7.4.4
INTERRUPT DISABLE
The following steps outline the procedure to disable all
user interrupts:
1.
2.
Push the current SR value onto the software
stack using the PUSH instruction.
Force the CPU to Priority Level 7 by inclusive
ORing the value, EOh, with SRL.
To enable user interrupts, the POP instruction can be
used to restore the previous SR value.
Note:
Only user interrupts with a priority level of
7 or lower can be disabled. Trap sources
(Level 8-Level 15) cannot be disabled.
The DISI instruction provides a convenient way to
disable interrupts of Priority Levels 1-6 for a fixed
period of time. Level 7 interrupt sources are not
disabled by the DISI instruction.
INTERRUPT SERVICE ROUTINE
The method used to declare an ISR and initialize
IVT with the correct vector address depends on
programming language (C or assembler) and
language development toolsuite used to develop
application.
the
the
the
the
In general, the user application must clear the interrupt
flag in the appropriate IFSx register for the source of
interrupt that the ISR handles. Otherwise, program will
re-enter the ISR immediately after exiting the routine. If
the ISR is coded in assembly language, it must be
terminated using a RETFIE instruction to unstack the
saved PC value, SRL value and old CPU priority level.
DS70000591F-page 178
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
8.0
DIRECT MEMORY ACCESS
(DMA)
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information
in this data sheet, refer to “Direct
Memory Access (DMA)” (DS70182) in
the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
The information in this data sheet
supersedes the information in the FRM.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
TABLE 8-1:
Direct Memory Access (DMA) is a very efficient
mechanism of copying data between peripheral SFRs
(e.g., the UART Receive register and Input Capture 1
buffer) and buffers, or variables stored in RAM, with
minimal CPU intervention. The DMA Controller
(DMAC) can automatically copy entire blocks of data
without requiring the user software to read or write the
peripheral Special Function Registers (SFRs) every
time a peripheral interrupt occurs. The DMA Controller
uses a dedicated bus for data transfers and, therefore,
does not steal cycles from the code execution flow of
the CPU. To exploit the DMA capability, the
corresponding user buffers or variables must be
located in DMA RAM.
Note:
The DMA module is not available on
dsIPC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406 devices.
The peripherals that can utilize DMA are listed in
Table 8-1 along with their associated Interrupt Request
(IRQ) numbers.
DMA CONTROLLER CHANNEL TO PERIPHERAL ASSOCIATIONS
Peripheral to DMA Association
DMAxREQ Register
IRQSEL<6:0> Bits
DMAxPAD Register
Values to Read from
Peripheral
DMAxPAD Register
Values to Write to
Peripheral
INT0 – External Interrupt 0
IC1 – Input Capture 1
IC2 – Input Capture 2
IC3 – Input Capture 3
IC4 – Input Capture 4
OC1 – Output Compare 1 Data
OC1 – Output Compare 1 Secondary Data
OC2 – Output Compare 2 Data
OC2 – Output Compare 2 Secondary Data
OC3 – Output Compare 3 Data
OC3 – Output Compare 3 Secondary Data
OC4 – Output Compare 4 Data
OC4 – Output Compare 4 Secondary Data
TMR2 – Timer2
TMR3 – Timer3
TMR4 – Timer4
TMR5 – Timer5
SPI1 – Transfer Done
SPI2 – Transfer Done
UART1RX – UART1 Receiver
UART1TX – UART1 Transmitter
UART2RX – UART2 Receiver
UART2TX – UART2 Transmitter
ECAN1 – RX Data Ready
ECAN1 – TX Data Request
0000000
0000001
0000101
0100101
0100110
0000010
0000010
0000110
0000110
0011001
0011001
0011010
0011010
0000111
0001000
0011011
0011100
0001010
0100001
0001011
0001100
0011110
0011111
0100010
1000110
—
0x0140 (IC1BUF)
0x0144 (IC2BUF)
0x0148 (IC3BUF)
0x014C (IC4BUF)
—
—
—
—
—
—
—
—
—
—
—
—
0x0248 (SPI1BUF)
0x0268 (SPI2BUF)
0x0226 (U1RXREG)
—
0x0236 (U2RXREG)
—
0x0640 (C1RXD)
—
—
—
—
—
—
0x0182 (OC1R)
0x0180 (OC1RS)
0x0188 (OC2R)
0x0186 (OC2RS)
0x018E (OC3R)
0x018C (OC3RS)
0x0194 (OC4R)
0x0192 (OC4RS)
—
—
—
—
0x0248 (SPI1BUF)
0x0268 (SPI2BUF)
—
0x0224 (U1TXREG)
—
0x0234 (U2TXREG)
—
0x0642 (C1TXD)
 2009-2014 Microchip Technology Inc.
DS70000591F-page 179
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
8.1
The DMA Controller features four identical data
transfer channels. Each channel has its own set of
control and status registers. Each DMA channel can be
configured to copy data either from buffers stored in
dual port DMA RAM to peripheral SFRs or from
peripheral SFRs to buffers in DMA RAM.
DMAC Registers
Each DMAC Channel x (x = 0, 1, 2 or 3) contains the
following registers:
• A 16-Bit DMA Channel Control Register
(DMAxCON)
• A 16-Bit DMA Channel IRQ Select Register
(DMAxREQ)
• A 16-Bit DMA RAM Primary Start Address Offset
Register (DMAxSTA)
• A 16-Bit DMA RAM Secondary Start Address
Offset Register (DMAxSTB)
• A 16-Bit DMA Peripheral Address Register
(DMAxPAD)
• A 10-Bit DMA Transfer Count Register (DMAxCNT)
The DMA Controller supports the following features:
• Word or byte-sized data transfers.
• Transfers from peripheral to DMA RAM or DMA
RAM to peripheral
• Indirect Addressing of DMA RAM locations with or
without automatic post-increment
• Peripheral Indirect Addressing – In some
peripherals, the DMA RAM read/write addresses
may be partially derived from the peripheral
• One-Shot Block Transfers – Terminating a DMA
transfer after one block transfer
• Continuous Block Transfers – Reloading the DMA
RAM buffer start address after every block
transfer is complete
• Ping-Pong Mode – Switching between two DMA
RAM start addresses between successive block
transfers, thereby filling two buffers alternately
• Automatic or manual initiation of block transfers
An additional pair of status registers, DMACS0 and
DMACS1, are common to all DMAC channels.
For each DMA channel, a DMA interrupt request is
generated when a block transfer is complete.
Alternatively, an interrupt can be generated when half of
the block has been filled.
FIGURE 8-1:
TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS
Peripheral Indirect Address
DMA
Control
DMA Controller
DMA RAM
SRAM
0
DMA
Channels
1
2
DMA
Ready
Peripheral 3
3
PORT 1 PORT 2
SRAM X-Bus
CPU
DMA
DMA DS Bus
CPU Peripheral DS Bus
CPU
CPU
Non-DMA
Ready
Peripheral
DMA
DMA
Ready
Peripheral 1
CPU
DMA
DMA
Ready
Peripheral 2
Note: For clarity, CPU and DMA address buses are not shown.
DS70000591F-page 180
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 8-1:
DMAxCON: DMA CHANNEL x CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
—
—
AMODE1
AMODE0
—
—
MODE1
MODE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CHEN: DMA Channel Enable bit
1 = Channel is enabled
0 = Channel is disabled
bit 14
SIZE: Data Transfer Size bit
1 = Byte
0 = Word
bit 13
DIR: Transfer Direction bit (source/destination bus select)
1 = Reads from DMA RAM address; writes to peripheral address
0 = Reads from peripheral address; writes to DMA RAM address
bit 12
HALF: Early Block Transfer Complete Interrupt Select bit
1 = Initiates block transfer complete interrupt when half of the data has been moved
0 = Initiates block transfer complete interrupt when all of the data has been moved
bit 11
NULLW: Null Data Peripheral Write Mode Select bit
1 = Null data write to peripheral in addition to DMA RAM write (DIR bit must also be clear)
0 = Normal operation
bit 10-6
Unimplemented: Read as ‘0’
bit 5-4
AMODE<1:0>: DMA Channel Operating Mode Select bits
11 = Reserved
10 = Peripheral Indirect Addressing mode
01 = Register Indirect without Post-Increment mode
00 = Register Indirect with Post-Increment mode
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
MODE<1:0>: DMA Channel Operating Mode Select bits
11 = One-Shot, Ping-Pong modes are enabled (one block transfer from/to each DMA RAM buffer)
10 = Continuous, Ping-Pong modes are enabled
01 = One-Shot, Ping-Pong modes are disabled
00 = Continuous, Ping-Pong modes are disabled
 2009-2014 Microchip Technology Inc.
DS70000591F-page 181
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 8-2:
DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
FORCE(1)
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-1
R/W-1
—
IRQSEL6(2)
IRQSEL5(2)
R/W-1
R/W-1
IRQSEL4(2) IRQSEL3(2)
R/W-1
R/W-1
R/W-1
IRQSEL2(2)
IRQSEL1(2)
IRQSEL0(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
FORCE: Force DMA Transfer bit(1)
1 = Forces a single DMA transfer (Manual mode)
0 = Automatic DMA transfer initiation by DMA request
bit 14-7
Unimplemented: Read as ‘0’
bit 6-0
IRQSEL<6:0>: DMA Peripheral IRQ Number Select bits(2)
0000000-1111111 = DMAIRQ0-DMAIRQ127 are selected to be Channel DMAREQ
Note 1:
2:
The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced
DMA transfer is complete.
See Table 8-1 for a complete listing of IRQ numbers for all interrupt sources.
REGISTER 8-3:
R/W-0
DMAxSTA: DMA CHANNEL x RAM START ADDRESS OFFSET REGISTER A
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STA<15:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STA<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
STA<15:0>: Primary DMA RAM Start Address bits (source or destination)
DS70000591F-page 182
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 8-4:
R/W-0
DMAxSTB: DMA CHANNEL x RAM START ADDRESS OFFSET REGISTER B
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STB<15:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STB<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
STB<15:0>: Secondary DMA RAM Start Address bits (source or destination)
REGISTER 8-5:
R/W-0
DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PAD<15:8>(2)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PAD<7:0>(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
x = Bit is unknown
PAD<15:0>: Peripheral Address Register bits(2)
If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
See Table 8-1 for a complete list of peripheral addresses.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 183
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER(1)
REGISTER 8-6:
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
CNT<9:8>(2)
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 15
CNT<7:0>
R/W-0
R/W-0
(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-10
Unimplemented: Read as ‘0’
bit 9-0
CNT<9:0>: DMA Transfer Count Register bits(2)
Note 1:
2:
x = Bit is unknown
If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
Number of DMA transfers = CNT<9:0> + 1.
DS70000591F-page 184
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 8-7:
DMACS0: DMA CONTROLLER STATUS REGISTER 0
U-0
U-0
U-0
U-0
R/C-0
R/C-0
R/C-0
R/C-0
—
—
—
—
PWCOL3
PWCOL2
PWCOL1
PWCOL0
bit 15
bit 8
U-0
U-0
U-0
U-0
R/C-0
R/C-0
R/C-0
R/C-0
—
—
—
—
XWCOL3
XWCOL2
XWCOL1
XWCOL0
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
Unimplemented: Read as ‘0’
bit 11
PWCOL3: Channel 3 Peripheral Write Collision Flag bit
1 = Write collision is detected
0 = No write collision is detected
bit 10
PWCOL2: Channel 2 Peripheral Write Collision Flag bit
1 = Write collision is detected
0 = No write collision is detected
bit 9
PWCOL1: Channel 1 Peripheral Write Collision Flag bit
1 = Write collision is detected
0 = No write collision is detected
bit 8
PWCOL0: Channel 0 Peripheral Write Collision Flag bit
1 = Write collision is detected
0 = No write collision is detected
bit 7-4
Unimplemented: Read as ‘0’
bit 3
XWCOL3: Channel 3 DMA RAM Write Collision Flag bit
1 = Write collision is detected
0 = No write collision is detected
bit 2
XWCOL2: Channel 2 DMA RAM Write Collision Flag bit
1 = Write collision is detected
0 = No write collision is detected
bit 1
XWCOL1: Channel 1 DMA RAM Write Collision Flag bit
1 = Write collision is detected
0 = No write collision is detected
bit 0
XWCOL0: Channel 0 DMA RAM Write Collision Flag bit
1 = Write collision is detected
0 = No write collision is detected
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 185
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 8-8:
DMACS1: DMA CONTROLLER STATUS REGISTER 1
U-0
U-0
U-0
U-0
R-1
R-1
R-1
R-1
—
—
—
—
LSTCH3
LSTCH2
LSTCH1
LSTCH0
bit 15
bit 8
U-0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
—
—
—
—
PPST3
PPST2
PPST1
PPST0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
Unimplemented: Read as ‘0’
bit 11-8
LSTCH<3:0>: Last DMA Channel Active bits
1111 = No DMA transfer has occurred since system Reset
1110 = Reserved
•
•
•
0100 = Reserved
0011 = Last data transfer was by DMA Channel 3
0010 = Last data transfer was by DMA Channel 2
0001 = Last data transfer was by DMA Channel 1
0000 = Last data transfer was by DMA Channel 0
bit 7-4
Unimplemented: Read as ‘0’
bit 3
PPST3: Channel 3 Ping-Pong Mode Status Flag bit
1 = DMA3STB register is selected
0 = DMA3STA register is selected
bit 2
PPST2: Channel 2 Ping-Pong Mode Status Flag bit
1 = DMA2STB register is selected
0 = DMA2STA register is selected
bit 1
PPST1: Channel 1 Ping-Pong Mode Status Flag bit
1 = DMA1STB register is selected
0 = DMA1STA register is selected
bit 0
PPST0: Channel 0 Ping-Pong Mode Status Flag bit
1 = DMA0STB register is selected
0 = DMA0STA register is selected
DS70000591F-page 186
x = Bit is unknown
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 8-9:
R-0
DSADR: MOST RECENT DMA RAM ADDRESS REGISTER
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DSADR<15:8>
bit 15
bit 8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DSADR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits
 2009-2014 Microchip Technology Inc.
DS70000591F-page 187
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS70000591F-page 188
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
9.0
OSCILLATOR
CONFIGURATION
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to “Oscillator (Part IV)”
(DS70307) in the “dsPIC33/PIC24
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com). The information
in this data sheet supersedes the
information in the FRM.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
 2009-2014 Microchip Technology Inc.
The oscillator system provides:
• External and Internal Oscillator Options as Clock
Sources
• An On-Chip Phase-Locked Loop (PLL) to Scale
the Internal Operating frequency to the Required
System Clock Frequency
• An Internal FRC Oscillator that can also be used
with the PLL, thereby allowing Full-Speed Operation
without any External Clock Generation Hardware
• Clock Switching Between Various Clock Sources
• Programmable Clock Postscaler for System
Power Savings
• A Fail-Safe Clock Monitor (FSCM) that Detects
Clock Failure and takes Fail-Safe Measures
• A Clock Control Register (OSCCON)
• Nonvolatile Configuration bits for Main Oscillator
Selection
• Auxiliary PLL for ADC and PWM
A simplified diagram of the oscillator system is shown
in Figure 9-1.
DS70000591F-page 189
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
OSC1
OSCILLATOR SYSTEM DIAGRAM
Primary Oscillator (POSC)
POSCCLK
R(2)
DOZE<2:0>
XT, HS, EC
XTPLL, HSPLL,
ECPLL, FRCPLL
S3
PLL(1)
S1
FVCO(1)
POSCMD<1:0>
S1/S3
To ADC and
Auxiliary Clock
Generator
FRC
Oscillator
FRCDIV
OSC2
S2
DOZE
FIGURE 9-1:
TUN<5:0>
÷ 16
FCY(4)
FP(4)
FRCDIVN
÷2
S7
FOSC
FRCDIV<2:0>
FRCDIV16
FRC
LPRC
LPRC
Oscillator
Secondary Oscillator (SOSC)
SOSC
SOSCO
S6
S0
S5
S4
LPOSCEN
SOSCI
Clock Fail
Clock Switch
Reset
S7
NOSC<2:0>
FNOSC<2:0>
Reference Clock Generation
POSCCLK
Timer 1
÷N
FOSC
WDT, PWRT,
FSCM
REFCLKO(3)
ROSEL RODIV<3:0>
Auxiliary Clock Generation
FRCCLK
ASRCSEL
Note
1:
2:
3:
4:
FVCO(1)
APLL(1)
x16
POSCCLK
FRCSEL
÷N
ENAPLL
SELACLK
ACLK
To PWM/ADC(1)
APSTSCLR<2:0>
See Section 9.1.3 “PLL Configuration” and Section 9.2 “Auxiliary Clock Generation” for configuration restrictions.
If the oscillator is used with XT or HS modes, an external parallel resistor with the value of 1 M must be connected.
REFCLKO functionality is not available if the primary oscillator is used.
The term, FP, refers to the clock source for all the peripherals, while FCY refers to the clock source for the CPU. Throughout this
document, FP and FCY are used interchangeably, except in the case of Doze mode. FP and FCY will be different when Doze mode
is used in any ratio other than 1:1, which is the default.
DS70000591F-page 190
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
9.1
CPU Clocking System
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices provide six
system clock options:
•
•
•
•
•
•
•
Fast RC (FRC) Oscillator
FRC Oscillator with PLL
Primary (XT, HS, or EC) Oscillator
Primary Oscillator with PLL
Low-Power RC (LPRC) Oscillator
FRC Oscillator with Postscaler
Secondary (LP) Oscillator
9.1.1
The clock signals generated by the FRC and primary
oscillators can be optionally applied to an on-chip PhaseLocked Loop (PLL) to provide a wide range of output
frequencies for device operation. PLL configuration is
described in Section 9.1.3 “PLL Configuration”.
The FRC frequency depends on the FRC accuracy
(see Table 27-20) and the value of the FRC Oscillator
Tuning register (see Register 9-4).
9.1.2
SYSTEM CLOCK SOURCES
The Fast RC (FRC) internal oscillator runs at a nominal
frequency of 7.37 MHz. User software can tune the
FRC frequency. User software can optionally specify a
factor (ranging from 1:2 to 1:256) by which the FRC
clock frequency is divided. This factor is selected using
the FRCDIV<2:0> (CLKDIV<10:8>) bits.
The primary oscillator can use one of the following as
its clock source:
• XT (Crystal): Crystals and ceramic resonators in
the range of 3 MHz to 10 MHz. The crystal is
connected to the OSC1 and OSC2 pins
• HS (High-Speed Crystal): Crystals in the range of
10 MHz to 50 MHz. The crystal is connected to
the OSC1 and OSC2 pins
• EC (External Clock): The external clock signal is
directly applied to the OSC1 pin
SYSTEM CLOCK SELECTION
The oscillator source used at a device Power-on Reset
event is selected using Configuration bit settings. The
Oscillator Configuration bit settings are located in the
Configuration registers in the program memory. (Refer to
Section 24.1 “Configuration Bits” for further details.)
The Initial Oscillator Selection Configuration bits,
FNOSC<2:0> (FOSCSEL<2:0>), and the Primary Oscillator Mode Select Configuration bits, POSCMD<1:0>
(FOSC<1:0>), select the oscillator source that is used at
a Power-on Reset. The FRC primary oscillator is the
default (unprogrammed) selection.
The Configuration bits allow users to choose among
12 different clock modes, shown in Table 9-1.
The output of the oscillator (or the output of the PLL if
a PLL mode has been selected), FOSC, is divided by 2
to generate the device instruction clock (FCY) and the
peripheral clock time base (FP). FCY defines the
operating speed of the device and speeds up to
50 MIPS are supported by the device architecture.
The secondary (LP) oscillator is designed for low power
and uses a 32.768 kHz crystal or ceramic resonator.
The LP oscillator uses the SOSCI and SOSCO pins.
Instruction execution speed or device operating
frequency, FCY, is given by Equation 9-1.
EQUATION 9-1:
The LPRC internal oscillator runs at a nominal
frequency of 32.768 kHz. It is also used as a reference
clock by the Watchdog Timer (WDT) and Fail-Safe
Clock Monitor (FSCM).
TABLE 9-1:
DEVICE OPERATING
FREQUENCY
FCY = FOSC/2
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode
Oscillator Source POSCMD<1:0> FNOSC<2:0> See Notes
Fast RC Oscillator with Divide-by-N (FRCDIVN)
Internal
xx
Fast RC Oscillator with Divide-by-16 (FRCDIV16)
Internal
xx
Low-Power RC Oscillator (LPRC)
Internal
xx
Secondary Oscillator (SOSC)
Secondary
xx
Primary Oscillator (HS) with PLL (HSPLL)
Primary
10
Primary Oscillator (XT) with PLL (XTPLL)
Primary
01
Primary Oscillator (EC) with PLL (ECPLL)
Primary
00
Primary Oscillator (HS)
Primary
10
Primary Oscillator (XT)
Primary
01
Primary Oscillator (EC)
Primary
00
Fast RC Oscillator with PLL (FRCPLL)
Internal
xx
Fast RC Oscillator (FRC)
Internal
xx
Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
 2009-2014 Microchip Technology Inc.
111
110
101
100
011
011
011
010
010
010
001
000
1, 2
1
1
—
—
—
1
—
—
1
1
1
DS70000591F-page 191
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
9.1.3
PLL CONFIGURATION
For a primary oscillator or FRC oscillator, output ‘FIN’,
the PLL output ‘FOSC’ is given by Equation 9-2.
The primary oscillator and internal FRC oscillator can
optionally use an on-chip PLL to obtain higher speeds
of operation. The PLL provides significant flexibility in
selecting the device operating speed. A block diagram
of the PLL is shown in Figure 9-2.
EQUATION 9-2:
FOSC = FIN *
The output of the primary oscillator or FRC, denoted as
‘FIN’, is divided down by a prescale factor (N1) of 2,
3, ... or 33 before being provided to the PLL’s Voltage
Controlled Oscillator (VCO). The input to the VCO must
be selected in the range of 0.8 MHz to 8 MHz. The
prescale factor ‘N1’ is selected using the
PLLPRE<4:0> bits (CLKDIV<4:0>).
( N1M* N2 )
For example, suppose a 10 MHz crystal is being used
with the selected oscillator mode of XT with PLL (see
Equation 9-3).
The PLL Feedback Divisor, selected using the
PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor, ‘M’,
by which the input to the VCO is multiplied. This factor
must be selected such that the resulting VCO output
frequency is in the range of 100 MHz to 200 MHz.
The VCO output is further divided by a postscale factor,
‘N2’. This factor is selected using the PLLPOST<1:0>
bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and
must be selected such that the PLL output frequency
(FOSC) is in the range of 12.5 MHz to 100 MHz, which
generates device operating speeds of 6.25-50 MIPS.
FIGURE 9-2:
FOSC CALCULATION
• If PLLPRE<4:0> = 0000, then N1 = 2. This yields
a VCO input of 10/2 = 5 MHz, which is within the
acceptable range of 0.8-8 MHz.
• If PLLDIV<8:0> = 0x26, then M = 40. This yields a
VCO output of 5 x 40 = 200 MHz, which is within
the 100-200 MHz ranged needed.
• If PLLPOST<1:0> = 00, then N2 = 2. This provides a FOSC of 200/2 = 100 MHz. The resultant
device operating speed is 100/2 = 40 MIPS.
EQUATION 9-3:
FCY =
XT WITH PLL MODE
EXAMPLE
FOSC
1
=
2
2
* 40
( 10000000
) = 50 MIPS
2*2
PLL BLOCK DIAGRAM
FVCO
100-200 MHz
Here(1)
0.8-8.0 MHz
Here(1)
Source (Crystal, External Clock
or Internal RC)
PLLPRE
X
VCO
PLLPOST
12.5-100 MHz
Here(1,2)
FOSC
PLLDIV
N1
Divide by
2-33
Note 1:
2:
M
Divide by
2-513
N2
Divide by
2, 4, 8
This frequency range must be met at all times.
This frequency range is not supported for all devices.
DS70000591F-page 192
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
9.2
Auxiliary Clock Generation
The auxiliary clock generation is used for a peripherals
that need to operate at a frequency unrelated to the
system clock such as a PWM or ADC.
The primary oscillator and internal FRC oscillator
sources can be used with an auxiliary PLL to obtain the
auxiliary clock. The auxiliary PLL has a fixed 16x
multiplication factor.
9.3
Reference Clock Generation
The reference clock output logic provides the user with
the ability to output a clock signal based on the system
clock or the crystal oscillator on a device pin. The user
application can specify a wide range of clock scaling
prior to outputting the reference clock.
The auxiliary clock has the following configuration
restrictions:
• For proper PWM operation, auxiliary clock
generation must be configured for 120 MHz (see
Parameter OS56 in Table 27-18 in Section 27.0
“Electrical Characteristics”). If a slower frequency
is desired, the PWM Input Clock Prescaler (Divider)
Select bits (PCLKDIV<2:0>) should be used.
• To achieve 1.04 ns PWM resolution, the auxiliary
clock must use the 16x auxiliary PLL (APLL). All
other clock sources will have a minimum PWM
resolution of 8 ns.
• If the primary PLL is used as a source for the
auxiliary clock, the primary PLL should be configured up to a maximum operation of 30 MIPS or
less.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 193
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
9.4
Oscillator Control Registers
OSCCON: OSCILLATOR CONTROL REGISTER(1)
REGISTER 9-1:
U-0
R-y
R-y
R-y
U-0
R/W-y
R/W-y
R/W-y
—
COSC2
COSC1
COSC0
—
NOSC2(2)
NOSC1(2)
NOSC0(2)
bit 15
bit 8
R/W-0
U-0
R-0
U-0
R/C-0
U-0
U-0
R/W-0
CLKLOCK
—
LOCK
—
CF
—
—
OSWEN
bit 7
bit 0
Legend:
C = Clearable bit
y = Value set from Configuration bits on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
COSC<2:0>: Current Oscillator Selection bits (read-only)
111 = Fast RC Oscillator (FRC) with Divide-by-n
110 = Fast RC Oscillator (FRC) with Divide-by-16
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator (XT, HS, EC) with PLL
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator (FRC) with PLL
000 = Fast RC Oscillator (FRC)
bit 11
Unimplemented: Read as ‘0’
bit 10-8
NOSC<2:0>: New Oscillator Selection bits(2)
111 = Fast RC Oscillator (FRC) with Divide-by-n
110 = Fast RC Oscillator (FRC) with Divide-by-16
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator (XT, HS, EC) with PLL
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator (FRC) with PLL
000 = Fast RC Oscillator (FRC)
bit 7
CLKLOCK: Clock Lock Enable bit
If Clock Switching is Enabled and FSCM is Disabled (FCKSM<1:0> (FOSC<7:6>) = 0b01):
1 = Clock switching is disabled, system clock source is locked
0 = Clock switching is enabled, system clock source can be modified by clock switching
bit 6
Unimplemented: Read as ‘0’
bit 5
LOCK: PLL Lock Status bit (read-only)
1 = Indicates that PLL is in lock or PLL start-up timer is satisfied
0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
bit 4
Unimplemented: Read as ‘0’
Note 1:
2:
Writes to this register require an unlock sequence. Refer to “Oscillator (Part IV)” (DS70307) in the
“dsPIC33/PIC24 Family Reference Manual” for details.
Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transition clock source between the two PLL modes.
DS70000591F-page 194
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 9-1:
OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED)
bit 3
CF: Clock Fail Detect bit (read/clear by application)
1 = FSCM has detected clock failure
0 = FSCM has not detected clock failure
bit 2-1
Unimplemented: Read as ‘0’
bit 0
OSWEN: Oscillator Switch Enable bit
1 = Requests oscillator switch to the selection specified by the NOSC<2:0> bits
0 = Oscillator switch is complete
Note 1:
2:
Writes to this register require an unlock sequence. Refer to “Oscillator (Part IV)” (DS70307) in the
“dsPIC33/PIC24 Family Reference Manual” for details.
Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transition clock source between the two PLL modes.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 195
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 9-2:
CLKDIV: CLOCK DIVISOR REGISTER
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
ROI
DOZE2
DOZE1
DOZE0
DOZEN(1)
FRCDIV2
FRCDIV1
FRCDIV0
bit 15
bit 8
R/W-0
R/W-1
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PLLPOST1
PLLPOST0
—
PLLPRE4
PLLPRE3
PLLPRE2
PLLPRE1
PLLPRE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ROI: Recover on Interrupt bit
1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1
0 = Interrupts have no effect on the DOZEN bit
bit 14-12
DOZE<2:0>: Processor Clock Reduction Select bits
111 = FCY/128
110 = FCY/64
101 = FCY/32
100 = FCY/16
011 = FCY/8 (default)
010 = FCY/4
001 = FCY/2
000 = FCY/1
bit 11
DOZEN: Doze Mode Enable bit(1)
1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0 = Processor clock/peripheral clock ratio forced to 1:1
bit 10-8
FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
111 = FRC divide-by-256
110 = FRC divide-by-64
101 = FRC divide-by-32
100 = FRC divide-by-16
011 = FRC divide-by-8
010 = FRC divide-by-4
001 = FRC divide-by-2
000 = FRC divide-by-1 (default)
bit 7-6
PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
11 = Output/8
10 = Reserved
01 = Output/4 (default)
00 = Output/2
bit 5
Unimplemented: Read as ‘0’
bit 4-0
PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler)
00000 = Input/2 (default)
00001 = Input/3
•
•
•
11111 = Input/33
Note 1:
This bit is cleared when the ROI bit is set and an interrupt occurs.
DS70000591F-page 196
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 9-3:
PLLFBD: PLL FEEDBACK DIVISOR REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
PLLDIV8
bit 15
bit 8
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
PLLDIV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
Unimplemented: Read as ‘0’
bit 8-0
PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)
000000000 = 2
000000001 = 3
000000010 = 4
•
•
•
000110000 = 50 (default)
•
•
•
111111111 = 513
 2009-2014 Microchip Technology Inc.
DS70000591F-page 197
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 9-4:
OSCTUN: OSCILLATOR TUNING REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TUN<5:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-6
Unimplemented: Read as ‘0’
bit 5-0
TUN<5:0>: FRC Oscillator Tuning bits(1)
011111 = Center Frequency + 2.91% (7.584 MHz)
011110 = Center Frequency + 2.81% (7.577 MHz)
•
•
•
000001 = Center Frequency + 0.0938% (7.377 MHz)
000000 = Center Frequency (7.37 MHz nominal)
111111 = Center Frequency – 0.0938% (7.363 MHz)
•
•
•
100001 = Center Frequency – 2.91% (7.156 MHz)
100000 = Center Frequency – 3% (7.149 MHz)
Note 1:
x = Bit is unknown
OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step-size is an approximation and is neither
characterized nor tested.
DS70000591F-page 198
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 9-5:
ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER
R/W-0
R-0
ENAPLL
APLLCK
R/W-1
U-0
U-0
SELACLK
—
—
R/W-1
R/W-1
R/W-1
APSTSCLR2 APSTSCLR1 APSTSCLR0
bit 15
bit 8
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
ASRCSEL
FRCSEL
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ENAPLL: Auxiliary PLL Enable bit
1 = APLL is enabled
0 = APLL is disabled
bit 14
APLLCK: APLL Locked Status bit (read-only)
1 = Indicates that auxiliary PLL is in lock
0 = Indicates that auxiliary PLL is not in lock
bit 13
SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider bit
1 = Auxiliary oscillators provide the source clock for the auxiliary clock divider
0 = Primary PLL (FVCO) provides the source clock for the auxiliary clock divider
bit 12-11
Unimplemented: Read as ‘0’
bit 10-8
APSTSCLR<2:0>: Auxiliary Clock Output Divider bits
111 = Divided by 1
110 = Divided by 2
101 = Divided by 4
100 = Divided by 8
011 = Divided by 16
010 = Divided by 32
001 = Divided by 64
000 = Divided by 256
bit 7
ASRCSEL: Select Reference Clock Source for Auxiliary Clock bit
1 = Primary oscillator is the clock source
0 = No clock input is selected
bit 6
FRCSEL: Select Reference Clock Source for Auxiliary PLL bit
1 = Selects FRC clock for auxiliary PLL
0 = Input clock source is determined by the ASRCSEL bit setting
bit 5-0
Unimplemented: Read as ‘0’
 2009-2014 Microchip Technology Inc.
DS70000591F-page 199
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 9-6:
REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ROON
—
ROSSLP
ROSEL
RODIV3(1)
RODIV2(1)
RODIV1(1)
RODIV0(1)
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
ROON: Reference Oscillator Output Enable bit
1 = Reference oscillator output is enabled on the REFCLK0 pin
0 = Reference oscillator output is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
ROSSLP: Reference Oscillator Run in Sleep bit
1 = Reference oscillator output continues to run in Sleep mode
0 = Reference oscillator output is disabled in Sleep mode
bit 12
ROSEL: Reference Oscillator Source Select bit
1 = Oscillator crystal is used as the reference clock
0 = System clock is used as the reference clock
bit 11-8
RODIV<3:0>: Reference Oscillator Divider bits(1)
1111 = Reference clock divided by 32,768
1110 = Reference clock divided by 16,384
1101 = Reference clock divided by 8,192
1100 = Reference clock divided by 4,096
1011 = Reference clock divided by 2,048
1010 = Reference clock divided by 1,024
1001 = Reference clock divided by 512
1000 = Reference clock divided by 256
0111 = Reference clock divided by 128
0110 = Reference clock divided by 64
0101 = Reference clock divided by 32
0100 = Reference clock divided by 16
0011 = Reference clock divided by 8
0010 = Reference clock divided by 4
0001 = Reference clock divided by 2
0000 = Reference clock
bit 7-0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
The reference oscillator output must be disabled (ROON = 0) before writing to these bits.
DS70000591F-page 200
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
9.5
Clock Switching Operation
Applications are free to switch among any of the four
clock sources (primary, LP, FRC and LPRC) under
software control at any time. To limit the possible side
effects of this flexibility, dsPIC33FJ32GS406/606/608/
610 and dsPIC33FJ64GS406/606/608/610 devices
have a safeguard lock built into the switch process.
Note:
9.5.1
Primary oscillator mode has three different
submodes (XT, HS and EC), which are
determined by the POSCMD<1:0> Configuration bits. While an application can
switch to and from primary oscillator
mode in software, it cannot switch among
the different primary submodes without
reprogramming the device.
2.
If a valid clock switch has been initiated, the LOCK
(OSCCON<5>) and the CF (OSCCON<3>) status
bits are cleared.
The new oscillator is turned on by the hardware if
it is not currently running. If a crystal oscillator
must be turned on, the hardware waits until the
Oscillator Start-up Timer (OST) expires. If the new
source is using the PLL, the hardware waits until a
PLL lock is detected (LOCK = 1).
The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the NOSCx
bit values are transferred to the COSCx status bits.
The old clock source is turned off at this time, with
the exception of LPRC (if WDT or FSCM are
enabled) or LP (if LPOSCEN remains set).
3.
4.
5.
6.
ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSM1 Configuration bit
in the FOSC Configuration register must be programmed
to ‘0’. (Refer to Section 24.1 “Configuration Bits” for
further details.) If the FCKSM1 Configuration bit is unprogrammed (‘1’), the clock switching function and Fail-Safe
Clock Monitor function are disabled; this is the default
setting.
Note 1: The processor continues to execute code
throughout the clock switching sequence.
Timing-sensitive code should not be
executed during this time.
2: Direct clock switches between any primary oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direction. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL modes.
3: Refer to “Oscillator (Part IV)” (DS70307)
in the “dsPIC33/PIC24 Family Reference
Manual” for details.
The NOSC control bits (OSCCON<10:8>) do not
control the clock selection when clock switching is
disabled. However, the COSC bits (OSCCON<14:12>)
reflect the clock source selected by the FNOSC<2:0>
Configuration bits.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled; it is held at ‘0’ at all
times.
9.5.2
OSCILLATOR SWITCHING SEQUENCE
To perform a clock switch, the following basic sequence
is required:
1.
2.
3.
4.
5.
If desired, read the COSCx bits (OSCCON<14:12>)
to determine the current oscillator source.
Perform the unlock sequence to allow a write to
the OSCCON register high byte.
Write the appropriate value to the NOSCx control
bits (OSCCON<10:8>) for the new oscillator
source.
Perform the unlock sequence to allow a write to
the OSCCON register low byte.
Set the OSWEN bit (OSCCON<0>) to initiate the
oscillator switch.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
1.
The clock switching hardware compares the
COSCx status bits with the new value of the
NOSCx control bits. If they are the same, the clock
switch is a redundant operation. In this case, the
OSWEN bit is cleared automatically and the clock
switch is aborted.
 2009-2014 Microchip Technology Inc.
9.6
Fail-Safe Clock Monitor (FSCM)
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the Watchdog Timer.
In the event of an oscillator failure, the FSCM
generates a clock failure trap event and switches the
system clock over to the FRC oscillator. Then, the
application program can either attempt to restart the
oscillator or execute a controlled shutdown. The trap
can be treated as a Warm Reset by simply loading the
Reset address into the oscillator fail trap vector.
If the PLL multiplier is used to scale the system clock,
the internal FRC is also multiplied by the same factor
on clock failure. Essentially, the device switches to
FRC with PLL on a clock failure.
DS70000591F-page 201
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS70000591F-page 202
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
10.0
POWER-SAVING FEATURES
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Watchdog Timer and
Power-Saving Modes” (DS70196) in the
“dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip
web site (www.microchip.com). The information in this data sheet supersedes the
information in the FRM.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices provide
the ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked constitutes lower
consumed power. Devices can manage power
consumption in four different ways:
•
•
•
•
Clock Frequency
Instruction-Based Sleep and Idle modes
Software Controlled Doze mode
Selective Peripheral Control in Software
Combinations of these methods can be used to
selectively tailor an application’s power consumption
while still maintaining critical application features, such
as timing-sensitive communications.
10.1
Clock Frequency and Clock
Switching
The devices allow a wide range of clock frequencies to
be selected under application control. If the system
clock configuration is not locked, users can choose
low-power or high-precision oscillators by simply
changing the NOSCx bits (OSCCON<10:8>). The
process of changing a system clock during operation, as
well as limitations to the process, are discussed in more
detail in Section 9.0 “Oscillator Configuration”.
EXAMPLE 10-1:
10.2
Instruction-Based Power-Saving
Modes
The devices have two special power-saving modes that
are entered through the execution of a special PWRSAV
instruction. Sleep mode stops clock operation and halts all
code execution. Idle mode halts the CPU and code
execution, but allows peripheral modules to continue
operation. The assembler syntax of the PWRSAV
instruction is shown in Example 10-1.
Note:
SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to wake-up.
10.2.1
SLEEP MODE
The following occurs in Sleep mode:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption is reduced to a
minimum, provided that no I/O pin is sourcing
current.
• The Fail-Safe Clock Monitor does not operate,
since the system clock source is disabled.
• The LPRC clock continues to run in Sleep mode if
the WDT is enabled.
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
• Some device features or peripherals may continue
to operate. This includes the items such as the
Input Change Notification on the I/O ports or
peripherals that use an external clock input.
• Any peripheral that requires the system clock
source for its operation is disabled.
The device will wake-up from Sleep mode on any of
these events:
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
On wake-up from Sleep mode, the processor restarts
with the same clock source that was active when Sleep
mode was entered.
PWRSAV INSTRUCTION SYNTAX
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
; Put the device into SLEEP mode
; Put the device into IDLE mode
 2009-2014 Microchip Technology Inc.
DS70000591F-page 203
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
10.2.2
IDLE MODE
The following occur in Idle mode:
• The CPU stops executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 10.5
“Peripheral Module Disable”).
• If the WDT or FSCM is enabled, the LPRC also
remains active.
The device will wake-up from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle mode, the clock is reapplied to
the CPU and instruction execution will begin (2-4 clock
cycles later), starting with the instruction following the
PWRSAV instruction, or the first instruction in the ISR.
10.2.3
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of a
PWRSAV instruction is held off until entry into Sleep or
Idle mode has completed. The device then wakes up
from Sleep or Idle mode.
10.3
Doze Mode
The preferred strategies for reducing power
consumption are changing clock speed and invoking
one of the power-saving modes. In some circumstances,
this may not be practical. For example, it may be necessary for an application to maintain uninterrupted
synchronous communication, even while it is doing nothing else. Reducing system clock speed can introduce
communication errors, while using a power-saving mode
can stop communications completely.
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock
continues to operate from the same source and at the
same speed. Peripheral modules continue to be
clocked at the same speed, while the CPU clock speed
is reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
DS70000591F-page 204
Doze mode is enabled by setting the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core
clock speed is determined by the DOZE<2:0> bits
(CLKDIV<14:12>). There are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default
setting.
Programs can use Doze mode to selectively reduce
power consumption in event-driven applications. This
allows clock-sensitive functions, such as synchronous
communications, to continue without interruption while
the CPU idles, waiting for something to invoke an
interrupt routine. An automatic return to full-speed CPU
operation on interrupts can be enabled by setting the
ROI bit (CLKDIV<15>). By default, interrupt events
have no effect on Doze mode operation.
For example, suppose the device is operating at
20 MIPS and the ECAN module has been configured
for 500 kbps based on this device operating speed. If
the device is placed in Doze mode with a clock
frequency ratio of 1:4, the ECAN module continues to
communicate at the required bit rate of 500 kbps, but
the CPU now starts executing instructions at a
frequency of 5 MIPS.
10.4
PWM Power-Saving Features
Typically, many applications need either a highresolution duty cycle or phase offset (for fixed
frequency operation) or a high-resolution PWM period
for variable frequency modes of operation (such as
Resonant mode). Very few applications require both
high-resolution modes simultaneously.
The HRPDIS and the HRDDIS bits in the AUXCONx
registers permit the user to disable the circuitry associated with the high-resolution duty cycle and PWM
period to reduce the operating current of the device.
If the HRDDIS bit is set, the circuitry associated with
the high-resolution duty cycle, phase offset and dead
time for the respective PWM generator, is disabled. If
the HRPDIS bit is set, the circuitry associated with the
high-resolution PWM period for the respective PWM
generator is disabled.
When the HRPDIS bit is set, the smallest unit of
measure for the PWM period is 8.32 ns.
If the HRDDIS bit is set, the smallest unit of measure
for the PWM duty cycle, phase offset and dead time is
8.32 ns.
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
10.5
Peripheral Module Disable
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers will have no effect and read
values will be invalid.
Note:
If a PMD bit is set, the corresponding
module is disabled after a delay of one
instruction cycle. Similarly, if a PMD bit is
cleared, the corresponding module is
enabled after a delay of one instruction
cycle (assuming the module control registers are already configured to enable
module operation).
A peripheral module is enabled only if both the
associated bit in the PMD register is cleared and the
peripheral is supported by the specific dsPIC® DSC
variant. If the peripheral is present in the device, it is
enabled in the PMD register by default.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 205
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 10-1:
PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
T5MD
T4MD
T3MD
T2MD
T1MD
QEI1MD
PWMMD(1)
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
I2C1MD
U2MD
U1MD
SPI2MD
SPI1MD
—
C1MD
ADCMD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
T5MD: Timer5 Module Disable bit
1 = Timer5 module is disabled
0 = Timer5 module is enabled
bit 14
T4MD: Timer4 Module Disable bit
1 = Timer4 module is disabled
0 = Timer4 module is enabled
bit 13
T3MD: Timer3 Module Disable bit
1 = Timer3 module is disabled
0 = Timer3 module is enabled
bit 12
T2MD: Timer2 Module Disable bit
1 = Timer2 module is disabled
0 = Timer2 module is enabled
bit 11
T1MD: Timer1 Module Disable bit
1 = Timer1 module is disabled
0 = Timer1 module is enabled
bit 10
QEI1MD: QEI1 Module Disable bit
1 = QEI1 module is disabled
0 = QEI1 module is enabled
bit 9
PWMMD: PWM Module Disable bit(1)
1 = PWM module is disabled
0 = PWM module is enabled
bit 8
Unimplemented: Read as ‘0’
bit 7
I2C1MD: I2C1 Module Disable bit
1 = I2C1 module is disabled
0 = I2C1 module is enabled
bit 6
U2MD: UART2 Module Disable bit
1 = UART2 module is disabled
0 = UART2 module is enabled
bit 5
U1MD: UART1 Module Disable bit
1 = UART1 module is disabled
0 = UART1 module is enabled
bit 4
SPI2MD: SPI2 Module Disable bit
1 = SPI2 module is disabled
0 = SPI2 module is enabled
Note 1:
x = Bit is unknown
Once the PWM module is re-enabled (PWMMD is set to ‘1’ and then set to ‘0’), all PWM registers must be
re-initialized.
DS70000591F-page 206
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 10-1:
PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED)
bit 3
SPI1MD: SPI1 Module Disable bit
1 = SPI1 module is disabled
0 = SPI1 module is enabled
bit 2
Unimplemented: Read as ‘0’
bit 1
C1MD: ECAN1 Module Disable bit
1 = ECAN1 module is disabled
0 = ECAN1 module is enabled
bit 0
ADCMD: ADC Module Disable bit
1 = ADC module is disabled
0 = ADC module is enabled
Note 1:
Once the PWM module is re-enabled (PWMMD is set to ‘1’ and then set to ‘0’), all PWM registers must be
re-initialized.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 207
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 10-2:
PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
IC4MD
IC3MD
IC2MD
IC1MD
bit 15
bit 8
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
OC4MD
OC3MD
OC2MD
OC1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
Unimplemented: Read as ‘0’
bit 11
IC4MD: Input Capture 4 Module Disable bit
1 = Input Capture 4 module is disabled
0 = Input Capture 4 module is enabled
bit 19
IC3MD: Input Capture 3 Module Disable bit
1 = Input Capture 3 module is disabled
0 = Input Capture 3 module is enabled
bit 9
IC2MD: Input Capture 2 Module Disable bit
1 = Input Capture 2 module is disabled
0 = Input Capture 2 module is enabled
bit 8
IC1MD: Input Capture 1 Module Disable bit
1 = Input Capture 1 module is disabled
0 = Input Capture 1 module is enabled
bit 7-4
Unimplemented: Read as ‘0’
bit 3
OC4MD: Output Compare 4 Module Disable bit
1 = Output Compare 4 module is disabled
0 = Output Compare 4 module is enabled
bit 2
OC3MD: Output Compare 3 Module Disable bit
1 = Output Compare 3 module is disabled
0 = Output Compare 3 module is enabled
bit 1
OC2MD: Output Compare 2 Module Disable bit
1 = Output Compare 2 module is disabled
0 = Output Compare 2 module is enabled
bit 0
OC1MD: Output Compare 1 Module Disable bit
1 = Output Compare 1 module is disabled
0 = Output Compare 1 module is enabled
DS70000591F-page 208
x = Bit is unknown
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 10-3:
PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
U-0
—
—
—
—
—
CMPMD
—
—
bit 15
bit 8
U-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
U-0
—
—
QEI2MD
—
—
—
I2C2MD
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10
CMPMD: Analog Comparator Module Disable bit
1 = Analog comparator module is disabled
0 = Analog comparator module is enabled
bit 9-6
Unimplemented: Read as ‘0’
bit 5
QEI2MD: QEI2 Module Disable bit
1 = QEI2 module is disabled
0 = QEI2 module is enabled
bit 4-2
Unimplemented: Read as ‘0’
bit 1
I2C2MD: I2C2 Module Disable bit
1 = I2C2 module is disabled
0 = I2C2 module is enabled
bit 0
Unimplemented: Read as ‘0’
REGISTER 10-4:
x = Bit is unknown
PMD4: PERIPHERAL MODULE DISABLE CONTROL REGISTER 4
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
—
—
—
—
REFOMD
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-4
Unimplemented: Read as ‘0’
bit 3
REFOMD: Reference Clock Generator Module Disable bit
1 = Reference clock generator module is disabled
0 = Reference clock generator module is enabled
bit 2-0
Unimplemented: Read as ‘0’
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 209
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 10-5:
PMD6: PERIPHERAL MODULE DISABLE CONTROL REGISTER 6
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PWM8MD
PWM7MD
PWM6MD
PWM5MD
PWM4MD
PWM3MD
PWM2MD
PWM1MD
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
PWM8MD: PWM Generator 8 Module Disable bit
1 = PWM Generator 8 module is disabled
0 = PWM Generator 8 module is enabled
bit 14
PWM7MD: PWM Generator 7 Module Disable bit
1 = PWM Generator 7 module is disabled
0 = PWM Generator 7 module is enabled
bit 13
PWM6MD: PWM Generator 6 Module Disable bit
1 = PWM Generator 6 module is disabled
0 = PWM Generator 6 module is enabled
bit 12
PWM5MD: PWM Generator 5 Module Disable bit
1 = PWM Generator 5 module is disabled
0 = PWM Generator 5 module is enabled
bit 11
PWM4MD: PWM Generator 4 Module Disable bit
1 = PWM Generator 4 module is disabled
0 = PWM Generator 4 module is enabled
bit 10
PWM3MD: PWM Generator 3 Module Disable bit
1 = PWM Generator 3 module is disabled
0 = PWM Generator 3 module is enabled
bit 9
PWM2MD: PWM Generator 2 Module Disable bit
1 = PWM Generator 2 module is disabled
0 = PWM Generator 2 module is enabled
bit 8
PWM1MD: PWM Generator 1 Module Disable bit
1 = PWM Generator 1 module is disabled
0 = PWM Generator 1 module is enabled
bit 7-0
Unimplemented: Read as ‘0’
DS70000591F-page 210
x = Bit is unknown
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 10-6:
PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
CMP4MD
CMP3MD
CMP2MD
CMP1MD
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
PWM9MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
Unimplemented: Read as ‘0’
bit 11
CMP4MD: Analog Comparator 4 Module Disable bit
1 = Analog Comparator 4 module is disabled
0 = Analog Comparator 4 module is enabled
bit 10
CMP3MD: Analog Comparator 3 Module Disable bit
1 = Analog Comparator 3 module is disabled
0 = Analog Comparator 3 module is enabled
bit 9
CMP2MD: Analog Comparator 2 Module Disable bit
1 = Analog Comparator 2 module is disabled
0 = Analog Comparator 2 module is enabled
bit 8
CMP1MD: Analog Comparator 1 Module Disable bit
1 = Analog Comparator 1 module is disabled
0 = Analog Comparator 1 module is enabled
bit 7-1
Unimplemented: Read as ‘0’
bit 0
PWM9MD: PWM Generator 9 Module Disable bit
1 = PWM Generator 9 module is disabled
0 = PWM Generator 9 module is enabled
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 211
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS70000591F-page 212
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
11.0
I/O PORTS
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “I/O Ports” (DS70193) in
the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the Microchip web site (www.microchip.com). The
information in this data sheet supersedes
the information in the FRM.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
All of the device pins (except VDD, VSS, MCLR and
OSC1/CLKI) are shared among the peripherals and the
parallel I/O ports. All I/O input ports feature Schmitt
Trigger inputs for improved noise immunity.
11.1
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
can be read, but the output driver for the parallel port bit
is disabled. If a peripheral is enabled, but the peripheral
is not actively driving a pin, that pin can be driven by a
port.
All port pins have three registers directly associated
with their operation as digital I/O. The Data Direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx) read the latch.
Writes to the latch write the latch. Reads from the port
(PORTx) read the port pins, while writes to the port pins
write the latch.
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers and the port pin will read as zeros.
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs.
Parallel I/O (PIO) Ports
Generally a parallel I/O port that shares a pin with a
peripheral is subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through”, in
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 11-1 shows
how ports are shared with other peripherals and the
associated I/O pin to which they are connected.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 213
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 11-1:
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Module
Output Multiplexers
Peripheral Input Data
Peripheral Module Enable
I/O
Peripheral Output Enable
Peripheral Output Data
PIO Module
WR TRIS
Output Enable
0
1
Output Data
0
Read TRIS
Data Bus
1
D
Q
I/O Pin
CK
TRIS Latch
D
WR LAT +
WR PORT
Q
CK
Data Latch
Read LAT
Input Data
Read PORT
DS70000591F-page 214
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
11.2
Open-Drain Configuration
In addition to the PORTx, LATx and TRISx registers for
data control, some digital only port pins can also be
individually configured for either digital or open-drain
output. This is controlled by the Open-Drain Control
register, ODCx, associated with each port. Setting any
of the bits configures the corresponding pin to act as an
open-drain output.
The open-drain feature allows the generation of
outputs higher than VDD (for example, 5V) on any
desired 5V tolerant pins by using external pull-up
resistors. The maximum open-drain voltage allowed is
the same as the maximum VIH specification.
Refer to “Pin Diagrams” for the available pins and
their functionality.
11.3
Configuring Analog Port Pins
The ADPCFG and TRISx registers control the
operation of the Analog-to-Digital port pins. The port
pins that are to function as analog inputs must have
their corresponding TRISx bit set (input). If the TRISx
bit is cleared (output), the digital output level (VOH or
VOL) will be converted.
The ADPCFG and ADPCFG2 registers have a default
value of 0x000; therefore, all pins that share ANx
functions are analog (not digital) by default.
When the PORTx register is read, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin defined as a
digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
EQUATION 11-1:
MOV
MOV
NOP
BTSS
0xFF00, W0
W0, TRISBB
PORTB, #13
11.4
I/O Port Write/Read Timing
One instruction cycle is required between a port direction
change or port write operation and a read operation of
the same port. Typically, this instruction would be a NOP.
An example is shown in Example 11-1.
11.5
Input Change Notification (ICN)
The Input Change Notification function of the I/O
ports allows the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610 devices to generate interrupt requests to the processor in response to
a Change-of-State (COS) on selected input pins. This
feature can detect input Change-of-States even in
Sleep mode, when the clocks are disabled. Depending
on the device pin count, up to 30 external signals (CNx
pin) can be selected (enabled) for generating an
interrupt request on a Change-of-State.
Four control registers are associated with the Change
Notification (CN) module. The CNEN1 and CNEN2
registers contain the interrupt enable control bits for
each of the CN input pins. Setting any of these bits
enables an CN interrupt for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source connected to the
pin and eliminate the need for external resistors when
the push button or keypad devices are connected. The
pull-ups are enabled separately using the CNPU1 and
CNPU2 registers, which contain the control bits for
each of the CN pins. Setting any of the control bits
enables the weak pull-ups for the corresponding pins.
Note:
Pull-ups on Change Notification pins
should always be disabled when the port
pin is configured as a digital output.
PORT WRITE/READ EXAMPLE
;
;
;
;
 2009-2014 Microchip Technology Inc.
Configure PORTB<15:8> as inputs
and PORTB<7:0> as outputs
Delay 1 cycle
Next Instruction
DS70000591F-page 215
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS70000591F-page 216
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
12.0
TIMER1
The unique features of Timer1 allow it to be used for
Real-Time Clock (RTC) applications. A block diagram
of Timer1 is shown in Figure 12-1.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Timers” (DS70205) in the
“dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip
web site (www.microchip.com). The information in this data sheet supersedes the
information in the FRM.
The Timer1 module can operate in one of the following
modes:
•
•
•
•
In Timer and Gated Timer modes, the input clock is
derived from the internal instruction cycle clock (FCY).
In Synchronous and Asynchronous Counter modes,
the input clock is derived from the external clock input
at the T1CK pin.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Timer modes are determined by the following bits:
• Timer Clock Source Control bit: TCS (T1CON<1>)
• Timer Synchronization Control bit: TSYNC
(T1CON<2>)
• Timer Gate Control bit: TGATE (T1CON<6>)
The Timer1 module is a 16-bit timer, which can serve
as a time counter for the Real-Time Clock (RTC), or
operate as a free-running interval timer/counter.
The timer control bit settings for different operating
modes are given in the Table 12-1.
The Timer1 module has the following unique features
over other timers:
TABLE 12-1:
TIMER MODE SETTINGS
Mode
• Can be operated from the low-power 32.767 kHz
crystal oscillator available on the device.
• Can be operated in Asynchronous Counter mode
from an external clock source.
• The external clock input (T1CK) can optionally be
synchronized to the internal device clock and the
clock synchronization is performed after the
prescaler.
FIGURE 12-1:
Timer mode
Gated Timer mode
Synchronous Counter mode
Asynchronous Counter mode
TCS
TGATE
TSYNC
0
0
1
0
1
x
x
x
1
1
x
0
Timer
Gated Timer
Synchronous
Counter
Asynchronous
Counter
16-BIT TIMER1 MODULE BLOCK DIAGRAM
Falling Edge
Detect
Gate
Sync
1
Set T1IF Flag
0
FCY
10
Prescaler
(/n)
00
TMR1
Reset
TGATE
TCKPS<1:0>
0
x1
T1CK
Prescaler
(/n)
Sync
TSYNC
TCKPS<1:0>
 2009-2014 Microchip Technology Inc.
Comparator
1
Equal
TGATE
TCS
PR1
DS70000591F-page 217
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 12-1:
T1CON: TIMER1 CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
TON
—
TSIDL
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
U-0
—
TGATE
TCKPS1
TCKPS0
—
TSYNC
TCS
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
TON: Timer1 On bit
1 = Starts 16-bit Timer1
0 = Stops 16-bit Timer1
bit 14
Unimplemented: Read as ‘0’
bit 13
TSIDL: Timer1 Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7
Unimplemented: Read as ‘0’
bit 6
TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4
TCKPS<1:0>:Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3
Unimplemented: Read as ‘0’
bit 2
TSYNC: Timer1 External Clock Input Synchronization Select bit
When TCS = 1:
1 = Synchronizes external clock input
0 = Does not synchronize external clock input
When TCS = 0:
This bit is ignored.
bit 1
TCS: Timer1 Clock Source Select bit
1 = External clock from T1CK pin (on the rising edge)
0 = Internal clock (FCY)
bit 0
Unimplemented: Read as ‘0’
DS70000591F-page 218
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
13.0
TIMER2/3/4/5 FEATURES
Timer2 and Timer4 are Type B timers that offer the
following major features:
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Timers” (DS70205) in the
“dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip
web site (www.microchip.com). The information in this data sheet supersedes the
information in the FRM.
• A Type B Timer can be Concatenated with a
Type C Timer to form a 32-Bit Timer
• At Least One Type B Timer Has the Ability to
Trigger an Analog-to-Digital Conversion
• External Clock Input (TxCK) is Always Synchronized
to the Internal Device Clock and the Clock
Synchronization is Performed after the Prescaler
Figure 13-1 shows a block diagram of the Type B timer.
Timer3 and Timer5 are Type C timers that offer the
following major features:
• A Type C Timer can be Concatenated with a
Type B Timer to form a 32-Bit Timer
• External Clock Input (TxCK) is Always Synchronized
to the Internal Device Clock and the Clock
Synchronization is Performed before the Prescaler
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
A block diagram of the Type C timer is shown in
Figure 13-2.
Note:
FIGURE 13-1:
Timer3 is not available on all devices.
TYPE B TIMER BLOCK DIAGRAM (x = 2, 4)
Gate
Sync
FCY
Falling Edge
Detect
Set TxIF Flag
0
10
Prescaler
(/n)
TMRx
00
TCKPS<1:0>
Prescaler
(/n)
1
x1
Sync
Comparator
Reset
TGATE
Equal
ADC SOC Trigger
TxCK
TCKPS<1:0>
TGATE
PRx
TCS
FIGURE 13-2:
TYPE C TIMER BLOCK DIAGRAM (x = 3, 5)
Gate
Sync
Falling Edge
Detect
Prescaler
(/n)
FCY
1
Set TxIF Flag
0
10
00
Reset
TMRx
TGATE
TCKPS<1:0>
Prescaler
(/n)
Sync
x1
Comparator
Equal
TxCK
TCKPS<1:0>
TGATE
PRx
TCS
 2009-2014 Microchip Technology Inc.
DS70000591F-page 219
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
The Timer2/3/4/5 modules can operate in one of the
following modes:
• Timer mode
• Gated Timer mode
• Synchronous Counter mode
In Timer and Gated Timer modes, the input clock is
derived from the internal instruction cycle clock (FCY).
In Synchronous Counter mode, the input clock is
derived from the external clock input at the TxCK pin.
When configured for 32-bit operation, only the Type B
Timerx Control (TxCON) register bits are required for
setup and control while the Type C Timer Control
register bits are ignored (except the TSIDL bit).
For interrupt control, the combined 32-bit timer uses
the interrupt enable, interrupt flag and interrupt priority
control bits of the Type C timer. The interrupt control
and status bits for the Type B timer are ignored
during 32-bit timer operation.
The timer modes are determined by the following bits:
The timers that can be combined to form a 32-bit timer
are listed in Table 13-2.
• TCS (TxCON<1>): Timer Clock Source Control bit
• TGATE (TxCON<6>): Timer Gate Control bit
TABLE 13-2:
Timer control bit settings for different operating modes
are given in the Table 13-1.
TABLE 13-1:
TIMER MODE SETTINGS
Mode
TCS
TGATE
Timer
0
0
Gated Timer
0
1
Synchronous Counter
1
x
13.1
16-Bit Operation
1.
2.
3.
4.
5.
6.
13.2
Type C Timer (msw)
Timer2
Timer3
TImer4
Timer5
To configure the timer features for 32-bit operation:
1.
2.
3.
Type B Timer (lsw)
A block diagram representation of the 32-bit timer
module is shown in Figure 13-3. The 32-timer module
can operate in one of the following modes:
• Timer mode
• Gated Timer mode
• Synchronous Counter mode
To configure any of the timers for individual 16-bit
operation:
Clear the T32 bit corresponding to that timer.
Select the timer prescaler ratio using the
TCKPS<1:0> bits.
Set the Clock and Gating modes using the TCS
and TGATE bits.
Load the timer period value into the PRx
register.
If interrupts are required, set the interrupt enable
bit, TxIE. Use the priority bits, TxIP<2:0>, to set
the interrupt priority.
Set the TON bit.
32-BIT TIMER
4.
5.
6.
Set the T32 control bit.
Select the prescaler ratio for Timer2 using the
TCKPS<1:0> bits.
Set the Clock and Gating modes using the
corresponding TCS and TGATE bits.
Load the timer period value. PR3 contains the
most significant word of the value, while PR2
contains the least significant word.
If interrupts are required, set the interrupt enable
bit, T3IE. Use the priority bits, T3IP<2:0>, to set
the interrupt priority. While Timer2 controls the
timer, the interrupt appears as a Timer3
interrupt.
Set the corresponding TON bit.
32-Bit Operation
A 32-bit timer module can be formed by combining a
Type B and a Type C 16-bit timer module. For 32-bit
timer operation, the T32 control bit in the Type B Timer
Control (TxCON<3>) register must be set. The Type C
timer holds the most significant word (msw) and the
Type B timer holds the least significant word (lsw)
for 32-bit operation.
DS70000591F-page 220
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 13-3:
32-BIT TIMER BLOCK DIAGRAM
Gate
Sync
Falling Edge
Detect
1
PRx
Set TyIF
Flag
PRy
0
Equal
Comparator
Prescaler
(/n)
FCY
10
lsw
00
TCKPS<1:0>
Prescaler
(/n)
TGATE
Sync
TMRx(1)
msw
TMRy(2)
Reset
x1
TxCK
TCKPS<1:0>
TGATE
TMRyHLD
TCS
Data Bus <15:0>
Note 1:
Timerx is a Type B Timer (x = 2, 4).
2:
Timery is a Type C Timer (y = 3, 5).
 2009-2014 Microchip Technology Inc.
DS70000591F-page 221
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 13-1:
TxCON: TIMERx CONTROL REGISTER (x = 2, 4)
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
TON
—
TSIDL
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
—
TGATE
TCKPS1
TCKPS0
T32
—
TCS
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
TON: Timerx On bit
When T32 = 1 (in 32-Bit Timer mode):
1 = Starts 32-bit TMRx:TMRy timer pair
0 = Stops 32-bit TMRx:TMRy timer pair
When T32 = 0 (in 16-Bit Timer mode):
1 = Starts 16-bit timer
0 = Stops 16-bit timer
bit 14
Unimplemented: Read as ‘0’
bit 13
TSIDL: Timerx Stop in Idle Mode bit
1 = Discontinues timer operation when device enters Idle mode
0 = Continues timer operation in Idle mode
bit 12-7
Unimplemented: Read as ‘0’
bit 6
TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4
TCKPS<1:0>: Timerx Input Clock Prescale Select bits
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
bit 3
T32: 32-Bit Timerx Mode Select bit
1 = TMRx and TMRy form a 32-bit timer
0 = TMRx and TMRy form a separate 16-bit timer
bit 2
Unimplemented: Read as ‘0’
bit 1
TCS: Timerx Clock Source Select bit
1 = External clock from TxCK pin
0 = Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
DS70000591F-page 222
x = Bit is unknown
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 13-2:
R/W-0
TON
(2)
TyCON: TIMERy CONTROL REGISTER (y = 3, 5)
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
TSIDL(1)
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
—
TGATE(2)
TCKPS1(2)
TCKPS0(2)
U-0
—
U-0
R/W-0
U-0
—
TCS(2)
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
TON: Timery On bit(2)
1 = Starts 16-bit Timery
0 = Stops 16-bit Timery
bit 14
Unimplemented: Read as ‘0’
bit 13
TSIDL: Timery Stop in Idle Mode bit(1)
1 = Discontinues timer operation when device enters Idle mode
0 = Continues timer operation in Idle mode
bit 12-7
Unimplemented: Read as ‘0’
bit 6
TGATE: Timery Gated Time Accumulation Enable bit(2)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4
TCKPS<1:0>: Timery Input Clock Prescale Select bits(2)
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
bit 3-2
Unimplemented: Read as ‘0’
bit 1
TCS: Timery Clock Source Select bit(2)
1 = External clock from TxCK pin
0 = Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
Note 1:
2:
x = Bit is unknown
When 32-bit timer operation is enabled (T32 = 1) in the Timerx Control register (TxCON<3>), the TSIDL
bit must be cleared to operate the 32-bit timer in Idle mode.
When the 32-bit timer operation is enabled (T32 = 1) in the Timerx Control register (TxCON<3>), these
bits have no effect.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 223
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS70000591F-page 224
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
14.0
INPUT CAPTURE
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Input Capture” (DS70198)
in the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the Microchip web site (www.microchip.com). The
information in this data sheet supersedes
the information in the FRM.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices support up
to two input capture channels.
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
FIGURE 14-1:
• Simple Capture Event modes:
- Capture timer value on every falling edge of
input at ICx pin
- Capture timer value on every rising edge of
input at ICx pin
• Capture Timer Value on Every Edge (rising and
falling)
• Prescaler Capture Event modes:
- Capture timer value on every 4th rising edge
of input at ICx pin
- Capture timer value on every 16th rising
edge of input at ICx pin
Each input capture channel can select one of the
two 16-bit timers (Timer2 or Timer3) for the time
base. The selected timer can use either an internal
or external clock.
Other operational features include:
• Device Wake-up from Capture Pin during CPU
Sleep and Idle modes
• Interrupt on Input Capture Event
• 4-Word FIFO Buffer for Capture Values
- Interrupt optionally generated after 1, 2, 3 or
4 buffer locations are filled
• Use of Input Capture to provide Additional
Sources of External Interrupts
INPUT CAPTURE x BLOCK DIAGRAM
From 16-Bit Timers
TMR2 TMR3
16
16
1
ICx Pin
ICM<2:0> (ICxCON<2:0>)
Mode Select
ICTMR
(ICxCON<7>)
FIFO
3
0
FIFO
R/W
Logic
Edge Detection Logic
and
Clock Synchronizer
Prescaler
Counter
(1, 4, 16)
ICOV, ICBNE (ICxCON<4:3>)
ICxBUF
ICI<1:0>
ICxCON
Interrupt
Logic
System Bus
Set Flag ICxIF
(in IFSx Register)
Note 1: An ‘x’ in a signal, register or bit name denotes the number of the input capture channel.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 225
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
14.1
Input Capture Registers
REGISTER 14-1:
ICxCON: INPUT CAPTURE x CONTROL REGISTER (x = 1 TO 4)
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
ICSIDL
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R-0, HC
R-0, HC
R/W-0
R/W-0
R/W-0
ICTMR
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13
ICSIDL: Input Capture x Stop in Idle Control bit
1 = Input capture module halts in CPU Idle mode
0 = Input capture module continues to operate in CPU Idle mode
bit 12-8
Unimplemented: Read as ‘0’
bit 7
ICTMR: Input Capture x Timer Select bit
1 = TMR2 contents are captured on capture event
0 = TMR3 contents are captured on capture event
bit 6-5
ICI<1:0>: Select Number of Captures per Interrupt bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4
ICOV: Input Capture x Overflow Status Flag bit (read-only)
1 = Input capture overflow occurred
0 = No input capture overflow occurred
bit 3
ICBNE: Input Capture x Buffer Empty Status bit (read-only)
1 = Input capture buffer is not empty, at least one more capture value can be read
0 = Input capture buffer is empty
bit 2-0
ICM<2:0>: Input Capture x Mode Select bits
111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode; rising edge
detect only, all other control bits are not applicable
110 = Unused (module disabled)
101 = Capture mode, every 16th rising edge
100 = Capture mode, every 4th rising edge
011 = Capture mode, every rising edge
010 = Capture mode, every falling edge
001 = Capture mode, every edge (rising and falling); ICI<1:0> bits do not control interrupt generation
for this mode
000 = Input capture module is turned off
DS70000591F-page 226
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
15.0
OUTPUT COMPARE
The output compare module can select either Timer2 or
Timer3 for its time base. The module compares the
value of the timer with the value of one or two Compare
registers depending on the operating mode selected.
The state of the output pin changes when the timer
value matches the Compare register value. The output
compare module generates either a single output
pulse, or a sequence of output pulses, by changing the
state of the output pin on the compare match events.
The output compare module can also generate
interrupts on compare match events.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Output Compare”
(DS70005157) in the “dsPIC33/PIC24
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com). The information
in this data sheet supersedes the
information in the FRM.
The output compare module has multiple operating
modes:
•
•
•
•
•
•
•
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 15-1:
Active-Low One-Shot mode
Active-High One-Shot mode
Toggle mode
Delayed One-Shot mode
Continuous Pulse mode
PWM mode without Fault Protection
PWM mode with Fault Protection
OUTPUT COMPARE x MODULE BLOCK DIAGRAM
Set Flag bit
OCxIF
OCxRS
Output
Logic
OCxR
3
16
1
Q
OCx
Output Enable
OCM<2:0>
Mode Select
Comparator
0
S
R
OCTSEL
0
OCFA
1
16
TMR2 TMR3
TMR2
TMR3
Rollover Rollover
Note: An ‘x’ in a signal, register or bit name denotes the number of the output compare channels.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 227
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
15.1
Output Compare Modes
Configure the Output Compare modes by setting the
appropriate Output Compare Mode (OCM<2:0>) bits in
the Output Compare Control (OCxCON<2:0>) register.
Table 15-1 lists the different bit settings for the Output
Compare modes. Figure 15-2 illustrates the output
compare operation for various modes. The user
TABLE 15-1:
application must disable the associated timer when
writing to the Output Compare Control registers to
avoid malfunctions.
Note:
See “Output Compare” (DS70005157)
in the “dsPIC33/PIC24 Family Reference
Manual” for OCxR and OCxRS register
restrictions.
OUTPUT COMPARE MODES
OCM<2:0>
Mode
000
001
010
011
100
101
110
Module Disabled
Active-Low One-Shot
Active-High One-Shot
Toggle
Delayed One-Shot
Continuous Pulse
PWM without Fault Protection
111
PWM with Fault Protection
FIGURE 15-2:
OCx Pin Initial State
OCx Interrupt Generation
Controlled by GPIO register
0
1
Current output is maintained
0
0
‘0’ if OCxR is zero,
‘1’ if OCxR is non-zero
‘0’ if OCxR is zero,
‘1’ if OCxR is non-zero
—
OCx rising edge
OCx falling edge
OCx rising and falling edge
OCx falling edge
OCx falling edge
No interrupt
OCFA falling edge for OC1 to OC4
OUTPUT COMPARE x OPERATION
Output Compare
Mode Enabled
Timer is Reset on
Period Match
OCxRS
TMRy
OCxR
Active-Low One-Shot
(OCM = 001)
Active-High One-Shot
(OCM = 010)
Toggle
(OCM = 011)
Delayed One-Shot
(OCM = 100)
Continuous Pulse
(OCM = 101)
PWM
(OCM = 110 or 111)
DS70000591F-page 228
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 15-1:
OCxCON: OUTPUT COMPARE x CONTROL REGISTER (x = 1 TO 4)
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
OCSIDL
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
R-0, HC
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
OCFLT
OCTSEL
OCM2
OCM1
OCM0
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13
OCSIDL: Output Compare x Stop in Idle Mode Control bit
1 = Output Compare x halts in CPU Idle mode
0 = Output Compare x continues to operate in CPU Idle mode
bit 12-5
Unimplemented: Read as ‘0’
bit 4
OCFLT: PWM Fault Condition Status bit
1 = PWM Fault condition has occurred (cleared in hardware only)
0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)
bit 3
OCTSEL: Output Compare x Timer Select bit
1 = Timer3 is the clock source for Output Compare x
0 = Timer2 is the clock source for Output Compare x
bit 2-0
OCM<2:0>: Output Compare x Mode Select bits
111 = PWM mode on OCx, Fault pin is enabled
110 = PWM mode on OCx, Fault pin is disabled
101 = Initializes OCx pin low, generates continuous output pulses on OCx pin
100 = Initializes OCx pin low, generates single output pulse on OCx pin
011 = Compare event toggles OCx pin
010 = Initializes OCx pin high, compare event forces OCx pin low
001 = Initializes OCx pin low, compare event forces OCx pin high
000 = Output compare channel is disabled
 2009-2014 Microchip Technology Inc.
DS70000591F-page 229
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS70000591F-page 230
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
16.0
HIGH-SPEED PWM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “High-Speed PWM”
(DS70000323) in the “dsPIC33/PIC24
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com). The information
in this data sheet supersedes the
information in the FRM.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The
high-speed
PWM
module
on
the
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices supports a
wide variety of PWM modes and output formats. This
PWM module is ideal for power conversion
applications, such as:
•
•
•
•
•
•
•
AC/DC Converters
DC/DC Converters
Power Factor Correction
Uninterruptible Power Supply (UPS)
Inverters
Battery Chargers
Digital Lighting
16.1
Features Overview
The high-speed PWM module incorporates the
following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
Two Master Time Base modules
Up to Nine PWM Generators with up to 18 Outputs
Two PWM Outputs per PWM Generator
Individual Time Base and Duty Cycle for each
PWM Output
Duty Cycle, Dead Time, Phase Shift and
Frequency Resolution of 1.04 ns
Independent Fault and Current-Limit Inputs for
Eight PWM Outputs
Redundant Output
True Independent Output
Center-Aligned PWM mode
Output Override Control
Chop mode (also known as Gated mode)
Special Event Trigger
Prescaler for Input Clock
 2009-2014 Microchip Technology Inc.
• Dual Trigger from PWM to Analog-to-Digital
Converter (ADC) per PWM Period
• PWMxL and PWMxH Output Pin Swapping
• Independent PWM Frequency, Duty Cycle and
Phase-Shift Changes
• Current Compensation
• Enhanced Leading-Edge Blanking (LEB) Functionality
• PWM Capture Functionality
Note:
Duty cycle, dead-time, phase shift and
frequency resolution is 8.32 ns in
Center-Aligned PWM mode.
Figure 16-1 conceptualizes the PWM module in a
simplified block diagram. Figure 16-2 illustrates how
the module hardware is partitioned for each PWM
output pair for the Complementary PWM mode.
The PWM module contains nine PWM generators. The
module has up to 18 PWM output pins: PWM1H/
PWM1L through PWM9H/PWM9L. For complementary
outputs, these 18 I/O pins are grouped into high/low
pairs.
16.2
Feature Description
The PWM module is designed for applications that
require:
• High-resolution at high PWM frequencies
• The ability to drive Standard, Edge-Aligned,
Center-Aligned Complementary mode and
Push-Pull mode outputs
• The ability to create multiphase PWM outputs
For Center-Aligned mode, the duty cycle, period phase
and dead-time resolutions will be 8.32 ns.
Two common, medium power converter topologies are
push-pull and half-bridge. These designs require the
PWM output signal to be switched between alternate
pins, as provided by the Push-Pull PWM mode.
Phase-shifted PWM describes the situation where
each PWM generator provides outputs, but the phase
relationship between the generator outputs is
specifiable and changeable.
Multiphase PWM is often used to improve DC/DC Converter load transient response, and reduce the size of
output filter capacitors and inductors. Multiple DC/DC
Converters are often operated in parallel, but
phase-shifted in time. A single PWM output, operating at
250 kHz, has a period of 4 s, but an array of four PWM
channels, staggered by 1 s each, yields an effective
switching frequency of 1 MHz. Multiphase PWM
applications typically use a fixed-phase relationship.
Variable phase PWM is useful in Zero Voltage
Transition (ZVT) power converters. Here, the PWM
duty cycle is always 50% and the power flow is
controlled by varying the relative phase shift between
the two PWM generators.
DS70000591F-page 231
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 16-1:
HIGH-SPEED PWMx MODULE ARCHITECTURAL DIAGRAM
SYNCIx
Data Bus
Primary and Secondary
Master Time Base
SYNCOx
Synchronization Signal
PWM1 Interrupt
PWM1H
PWM
Generator 1
PWM1L
Fault, Current-Limit
and Dead-Time Compensation
Synchronization Signal
PWM2 Interrupt
PWM2H
PWM
Generator 2
PWM2L
Fault, Current-Limit
and Dead-Time Compensation
CPU
PWM3 through PWM7
Synchronization Signal
PWM8 Interrupt
PWM8H
PWM
Generator 8
PWM8L
Fault, Current-Limit
and Dead-Time Compensation
Synchronization Signal
PWM9H
PWM9 Interrupt
PWM
Generator 9
PWM9L
Primary Trigger
Secondary Trigger
ADC Module
Special Event Trigger
DS70000591F-page 232
Fault and
Current-Limit
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 16-2:
SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF THE HIGH-SPEED PWMx
PTCON, PTCON2
SYNCI1
Module Control and Timing
PTPER
SEVTCMP
Comparator
Comparator
SYNCI4
•••
STCON, STCON2
SYNCO1
Special Event Compare Trigger
Special Event
Postscaler
Special Event Trigger
Master Time Base Counter
Clock
Prescaler
PMTMR
STPER
SEVTCMP
Comparator
Comparator
Primary Master Time Base
SYNCO2
Special Event Compare Trigger
Special Event
Postscaler
Special Event Trigger
Master Time Base Counter
Clock
Prescaler
SMTMR
Master Duty Cycle
Master Duty Cycle Register
PWM Generator 1
PDCx
MUX
Master Period
16-Bit Data Bus
Synchronization
MDC
Secondary Master Time Base
PWM Output Mode
Control Logic
Comparator
PWMCAPx
ADC Trigger
User Override Logic
PTMRx
Comparator
Current-Limit
Override Logic
TRIGx
Fault Override Logic
PHASEx
SDCx
DeadTime
Logic
Pin
Control
Logic
PWM1H
PWM1L
Secondary PWM
MUX
Comparator
Interrupt
Logic
Fault and
Current-Limit
Logic
FLTn(1)
Master Period
Master Duty Cycle
Synchronization
ADC Trigger
STMRx
Comparator
SPHASEx
STRIGx
PWMCONx
TRGCONx
FCLCONx
IOCONx
LEBCONx
ALTDTRx
DTRx
PWMxH
PWM Generator 2 – PWM Generator 9
PWMxL
FLTn(1)
DTCMPx
Note 1:
n = 1 through 23.
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16.3
Control Registers
The following registers control the operation of the
high-speed PWM module.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PTCON: PWM Time Base Control Register
PTCON2: PWM Clock Divider Select Register 2
PTPER: PWM Primary Master Time Base Period Register(1,2)
SEVTCMP: PWM Special Event Compare Register(1)
STCON: PWM Secondary Master Time Base Control Register
STCON2: PWM Secondary Clock Divider Select Register 2
STPER: PWM Secondary Master Time Base Period Register
SSEVTCMP: PWM Secondary Special Event Compare Register
CHOP: PWM Chop Clock Generator Register(1)
MDC: PWM Master Duty Cycle Register(1,2)
PWMCONx: PWM Control x Register
PDCx: PWM Generator Duty Cycle x Register(1,2,3)
PHASEx: PWM Primary Phase-Shift x Register(1,2)
DTRx: PWM Dead-Time x Register
ALTDTRx: PWM Alternate Dead-Time x Register
SDCx: PWM Secondary Duty Cycle x Register(1,2,3)
SPHASEx: PWM Secondary Phase-Shift x Register(1,2)
TRGCONx: PWM Trigger Control x Register
IOCONx: PWM I/O Control x Register
FCLCONx: PWM Fault Current-Limit Control x Register
TRIGx: PWM Primary Trigger x Compare Value Register
STRIGx: PWM Secondary Trigger x Compare Value Register(1)
LEBCONx: Leading-Edge Blanking Control x Register
LEBDLYx: Leading-Edge Blanking Delay x Register
AUXCONx: PWM Auxiliary Control x Register
PWMCAPx: Primary PWM Time Base Capture x Register
DS70000591F-page 234
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-1:
R/W-0
PTCON: PWM TIME BASE CONTROL REGISTER
U-0
—
PTEN
R/W-0
HS/HC-0
PTSIDL
SESTAT
R/W-0
R/W-0
R/W-0
R/W-0
SEIEN
EIPU(1)
SYNCPOL(1)
SYNCOEN(1)
bit 15
bit 8
R/W-0
(1)
SYNCEN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SYNCSRC2(1)
SYNCSRC1(1)
SYNCSRC0(1)
SEVTPS3(1)
SEVTPS2(1)
SEVTPS1(1)
SEVTPS0(1)
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
PTEN: PWM Module Enable bit
1 = PWM module is enabled
0 = PWM module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
PTSIDL: PWM Time Base Stop in Idle Mode bit
1 = PWM time base halts in CPU Idle mode
0 = PWM time base runs in CPU Idle mode
bit 12
SESTAT: Special Event Interrupt Status bit
1 = Special event interrupt is pending
0 = Special event interrupt is not pending
bit 11
SEIEN: Special Event Interrupt Enable bit
1 = Special event interrupt is enabled
0 = Special event interrupt is disabled
bit 10
EIPU: Enable Immediate Period Updates bit(1)
1 = Active Period register is updated immediately
0 = Active Period register updates occur on PWM cycle boundaries
bit 9
SYNCPOL: Synchronize Input and Output Polarity bit(1)
1 = SYNCIx/SYNCO1 polarity is inverted (active-low)
0 = SYNCIx/SYNCO1 is active-high
bit 8
SYNCOEN: Primary Time Base Synchronization Enable bit(1)
1 = SYNCO1 output is enabled
0 = SYNCO1 output is disabled
bit 7
SYNCEN: External Time Base Synchronization Enable bit(1)
1 = External synchronization of primary time base is enabled
0 = External synchronization of primary time base is disabled
bit 6-4
SYNCSRC<2:0>: Synchronous Source Selection bits(1)
111 = Reserved
101 = Reserved
100 = Reserved
011 = SYNCI4
010 = SYNCI3
001 = SYNCI2
000 = SYNCI1
Note 1:
x = Bit is unknown
These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user
application must program the Period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
 2009-2014 Microchip Technology Inc.
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-1:
bit 3-0
Note 1:
PTCON: PWM TIME BASE CONTROL REGISTER (CONTINUED)
SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits(1)
1111 = 1:16 Postscaler generates Special Event Trigger on every sixteenth compare match event
•
•
•
0001 = 1:2 Postscaler generates Special Event Trigger on every second compare match event
0000 = 1:1 Postscaler generates Special Event Trigger on every compare match event
These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user
application must program the Period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
DS70000591F-page 236
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-2:
PTCON2: PWM CLOCK DIVIDER SELECT REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
PCLKDIV<2:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-3
Unimplemented: Read as ‘0’
bit 2-0
PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1)
111 = Reserved
110 = Divide-by-64, maximum PWM timing resolution
101 = Divide-by-32, maximum PWM timing resolution
100 = Divide-by-16, maximum PWM timing resolution
011 = Divide-by-8, maximum PWM timing resolution
010 = Divide-by-4, maximum PWM timing resolution
001 = Divide-by-2, maximum PWM timing resolution
000 = Divide-by-1, maximum PWM timing resolution (power-on default)
Note 1:
These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
REGISTER 16-3:
R/W-1
PTPER: PWM PRIMARY MASTER TIME BASE PERIOD REGISTER(1,2)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
PTPER<15:8>
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
PTPER<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
x = Bit is unknown
PTPER<15:0>: Primary Master Time Base (PMTMR) Period Value bits
The PWM time base has a minimum value of 0x0010 and a maximum value of 0xFFF8.
Any period value that is less than 0x0028 must have the Least Significant 3 bits set to ‘0’, thus yielding a
period resolution at 8.32 ns (at fastest auxiliary clock rate).
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REGISTER 16-4:
R/W-0
SEVTCMP: PWM SPECIAL EVENT COMPARE REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEVTCMP<12:5>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEVTCMP<4:0>
U-0
U-0
U-0
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-3
SEVTCMP<12:0>: Special Event Compare Count Value bits
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
One LSB = 1.04 ns (at fastest auxiliary clock rate); therefore, the minimum SEVTCMP resolution is 8.32 ns.
DS70000591F-page 238
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-5:
U-0
STCON: PWM SECONDARY MASTER TIME BASE CONTROL REGISTER
U-0
—
—
U-0
—
HS/HC-0
SESTAT
R/W-0
R/W-0
R/W-0
R/W-0
SEIEN
EIPU(1)
SYNCPOL
SYNCOEN
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SYNCEN
SYNCSRC2
SYNCSRC1
SYNCSRC0
SEVTPS3
SEVTPS2
SEVTPS1
SEVTPS0
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12
SESTAT: Special Event Interrupt Status bit
1 = Secondary special event interrupt is pending
0 = Secondary special event interrupt is not pending
bit 11
SEIEN: Special Event Interrupt Enable bit
1 = Secondary special event interrupt is enabled
0 = Secondary special event interrupt is disabled
bit 10
EIPU: Enable Immediate Period Updates bit(1)
1 = Active Secondary Period register is updated immediately
0 = Active Secondary Period register updates occur on PWM cycle boundaries
bit 9
SYNCPOL: Synchronize Input and Output Polarity bit
1 = SYNCIx/SYNCO2 polarity is inverted (active-low)
0 = SYNCIx/SYNCO2 polarity is active-high
bit 8
SYNCOEN: Secondary Master Time Base Synchronization Enable bit
1 = SYNCO2 output is enabled.
0 = SYNCO2 output is disabled
bit 7
SYNCEN: External Secondary Master Time Base Synchronization Enable bit
1 = External synchronization of secondary time base is enabled
0 = External synchronization of secondary time base is disabled
bit 6-4
SYNCSRC<2:0>: PWM Secondary Time Base Synchronization Source Selection bits
111 = Reserved
101 = Reserved
100 = Reserved
011 = SYNCI4
010 = SYNCI3
001 = SYNCI2
000 = SYNCI1
bit 3-0
SEVTPS<3:0>: PWM Secondary Special Event Trigger Output Postscaler Select bits
1111 = 1:16 Postcale
0001 = 1:2 Postcale
•
•
•
0000 = 1:1 Postscale
Note 1:
This bit only applies to the secondary master time base period.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 239
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-6:
STCON2: PWM SECONDARY CLOCK DIVIDER SELECT REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
PCLKDIV2(1) PCLKDIV1(1) PCLKDIV0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-3
Unimplemented: Read as ‘0’
bit 2-0
PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1)
111 = Reserved
110 = Divide-by-64, maximum PWM timing resolution
101 = Divide-by-32, maximum PWM timing resolution
100 = Divide-by-16, maximum PWM timing resolution
011 = Divide-by-8, maximum PWM timing resolution
010 = Divide-by-4, maximum PWM timing resolution
001 = Divide-by-2, maximum PWM timing resolution
000 = Divide-by-1, maximum PWM timing resolution (power-on default)
Note 1:
These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
REGISTER 16-7:
R/W-1
STPER: PWM SECONDARY MASTER TIME BASE PERIOD REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
STPER<15:8>
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
STPER<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
STPER<15:0>: Secondary Master Time Base (SMTMR) Period Value bits
DS70000591F-page 240
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-8:
R/W-0
SSEVTCMP: PWM SECONDARY SPECIAL EVENT COMPARE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSEVTCMP<12:5>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSEVTCMP<4:0>
U-0
U-0
U-0
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-3
SSEVTCMP<12:0>: Special Event Compare Count Value bits
bit 2-0
Unimplemented: Read as ‘0’
REGISTER 16-9:
x = Bit is unknown
CHOP: PWM CHOP CLOCK GENERATOR REGISTER(1)
R/W-0
U-0
U-0
U-0
U-0
U-0
CHPCLKEN
—
—
—
—
—
R/W-0
R/W-0
CHOPCLK6 CHOPCLK5
bit 15
bit 8
R/W-0
R/W-0
CHOPCLK4
R/W-0
R/W-0
R/W-0
CHOPCLK3 CHOPCLK2 CHOPCLK1 CHOPCLK0
U-0
U-0
U-0
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CHPCLKEN: Enable Chop Clock Generator bit
1 = Chop clock generator is enabled
0 = Chop clock generator is disabled
bit 14-10
Unimplemented: Read as ‘0’
bit 9-3
CHOPCLK<6:0>: Chop Clock Divider bits
Value in 8.32 ns increments. The frequency of the chop clock signal is given by the following
expression:
Chop Frequency = 1/(16.64 * (CHOPCLK<6:0> + 1) * Primary Master PWM Input Clock Period)
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
The chop clock generator operates with the primary PWM clock prescaler (PCLKDIV<2:0>) in the
PTCON2 register (Register 16-2).
 2009-2014 Microchip Technology Inc.
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-10: MDC: PWM MASTER DUTY CYCLE REGISTER(1,2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MDC<15:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MDC<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
x = Bit is unknown
MDC<15:0>: PWM Master Duty Cycle Value bits
The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0009,
while the maximum pulse width generated corresponds to a value of Period – 0x0009.
As the duty cycle gets closer to 0% or 100% of the PWM period (0 to 40 ns, depending on the mode of
operation), the PWM duty cycle resolution will increase from 1 to 3 LSBs.
DS70000591F-page 242
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-11: PWMCONx: PWM CONTROL x REGISTER
HS/HC-0
FLTSTAT
(1)
HS/HC-0
CLSTAT(1)
HS/HC-0
TRGSTAT
R/W-0
FLTIEN
R/W-0
CLIEN
R/W-0
R/W-0
R/W-0
TRGIEN
ITB(3)
MDCS(3)
bit 15
bit 8
R/W-0
R/W-0
DTC1
DTC0
R/W-0
DTCP
(4)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
MTBS
CAM(2,3,5)
XPRES(6)
IUE
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
FLTSTAT: Fault Interrupt Status bit(1)
1 = Fault interrupt is pending
0 = No Fault interrupt is pending
This bit is cleared by setting FLTIEN = 0.
bit 14
CLSTAT: Current-Limit Interrupt Status bit(1)
1 = Current-limit interrupt is pending
0 = No current-limit interrupt is pending
This bit is cleared by setting CLIEN = 0.
bit 13
TRGSTAT: Trigger Interrupt Status bit
1 = Trigger interrupt is pending
0 = No trigger interrupt is pending
This bit is cleared by setting TRGIEN = 0.
bit 12
FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt is enabled
0 = Fault interrupt is disabled and FLTSTAT bit is cleared
bit 11
CLIEN: Current-Limit Interrupt Enable bit
1 = Current-limit interrupt is enabled
0 = Current-limit interrupt is disabled and CLSTAT bit is cleared
bit 10
TRGIEN: Trigger Interrupt Enable bit
1 = A trigger event generates an interrupt request
0 = Trigger event interrupts are disabled and TRGSTAT bit is cleared
bit 9
ITB: Independent Time Base Mode bit(3)
1 = PHASEx/SPHASEx registers provide time base period for this PWM generator
0 = PTPER register provides timing for this PWM generator
bit 8
MDCS: Master Duty Cycle Register Select bit(3)
1 = MDC register provides duty cycle information for this PWM generator
0 = PDCx and SDCx registers provide duty cycle information for this PWM generator
Note 1:
2:
3:
4:
5:
6:
Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
These bits should not be changed after the PWM is enabled by setting PTEN (PTCON<15>) = 1.
For DTCP to be effective, DTC<1:0> must be set to ‘11’; otherwise, DTCP is ignored.
Center-Aligned mode ignores the Least Significant 3 bits of the Duty Cycle, Phase and Dead-Time
registers. The highest Center-Aligned mode resolution available is 8.32 ns with the clock prescaler set to
the fastest clock.
Configure CLMOD (FCLCONX<8>) = 0 and ITB (PWMCONx<9>) = 1 to operate in External Period
Reset mode.
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-11: PWMCONx: PWM CONTROL x REGISTER (CONTINUED)
bit 7-6
DTC<1:0>: Dead-Time Control bits
11 = Dead-Time Compensation mode
10 = Dead-time function is disabled
01 = Negative dead time is actively applied for Complementary Output mode
00 = Positive dead time is actively applied for all output modes
bit 5
DTCP: Dead-Time Compensation Polarity bit(4)
1 = If DTCMPx = 0, PWMxL is shortened and PWMxH is lengthened;
If DTCMPx = 1, PWMxH is shortened and PWMxL is lengthened
0 = If DTCMPx = 0, PWMxH is shortened and PWMLx is lengthened;
If DTCMPx = 1, PWMxL is shortened and PWMxH is lengthened
bit 4
Unimplemented: Read as ‘0’
bit 3
MTBS: Master Time Base Select bit
1 = PWM generator uses the secondary master time base for synchronization and the clock source for
the PWM generation logic (if secondary time base is available)
0 = PWM generator uses the primary master time base for synchronization and the clock source for
the PWM generation logic
bit 2
CAM: Center-Aligned Mode Enable bit(2,3,5)
1 = Center-Aligned mode is enabled
0 = Edge-Aligned mode is enabled
bit 1
XPRES: External PWM Reset Control bit(6)
1 = Current-limit source resets the time base for this PWM generator if it is in Independent Time
Base mode
0 = External pins do not affect PWM time base
bit 0
IUE: Immediate Update Enable bit
1 = Updates to the active MDC/PDCx/SDCx registers are immediate
0 = Updates to the active PDCx registers are synchronized to the PWM time base
Note 1:
2:
3:
4:
5:
6:
Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
These bits should not be changed after the PWM is enabled by setting PTEN (PTCON<15>) = 1.
For DTCP to be effective, DTC<1:0> must be set to ‘11’; otherwise, DTCP is ignored.
Center-Aligned mode ignores the Least Significant 3 bits of the Duty Cycle, Phase and Dead-Time
registers. The highest Center-Aligned mode resolution available is 8.32 ns with the clock prescaler set to
the fastest clock.
Configure CLMOD (FCLCONX<8>) = 0 and ITB (PWMCONx<9>) = 1 to operate in External Period
Reset mode.
DS70000591F-page 244
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-12: PDCx: PWM GENERATOR DUTY CYCLE x REGISTER(1,2,3)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PDCx<15:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PDCx<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
3:
x = Bit is unknown
PDCx<15:0>: PWM Generator # Duty Cycle Value bits
In Independent PWM mode, the PDCx register controls the PWMxH duty cycle only. In the Complementary,
Redundant and Push-Pull PWM modes, the PDCx register controls the duty cycle of both the PWMxH and
PWMxL.
The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0009,
while the maximum pulse width generated corresponds to a value of Period – 0x0009.
As the duty cycle gets closer to 0% or 100% of the PWM period (0 to 40 ns, depending on the mode of
operation), PWM duty cycle resolution will increase from 1 to 3 LSBs.
REGISTER 16-13: SDCx: PWM SECONDARY DUTY CYCLE x REGISTER(1,2,3)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDCx<15:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDCx<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
3:
x = Bit is unknown
SDCx<15:0>: Secondary Duty Cycle bits for PWMxL Output Pin
The SDCx register is used in Independent PWM mode only. When used in Independent PWM mode, the
SDCx register controls the PWMxL duty cycle.
The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0009,
while the maximum pulse width generated corresponds to a value of Period – 0x0009.
As the duty cycle gets closer to 0% or 100% of the PWM period (0 to 40 ns, depending on the mode of
operation), PWM duty cycle resolution will increase from 1 to 3 LSBs.
 2009-2014 Microchip Technology Inc.
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-14: PHASEx: PWM PRIMARY PHASE-SHIFT x REGISTER(1,2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PHASEx<15:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PHASEx<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
x = Bit is unknown
PHASEx<15:0>: PWM Phase-Shift Value or Independent Time Base Period for the PWM Generator bits
If PWMCONx<9> = 0, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (IOCONx<10:8> = 00, 01 or 10),
PHASEx<15:0> = Phase-Shift Value for PWMxH and PWMxL outputs.
• True Independent Output mode (IOCONx<10:8> = 11), PHASEx<15:0> = Phase-Shift Value for
PWMxH only.
• The PHASEx/SPHASEx registers provide the phase shift with respect to the master time base;
therefore, the valid range is 0x0000 through period.
If PWMCONx<9> = 1, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (IOCONx<10:8> = 00, 01 or 10),
PHASEx<15:0> = Independent Time Base Period Value for PWMxH and PWMxL.
• True Independent Output mode (IOCONx<10:8> = 11). PHASEx<15:0> = Independent Time Base
Period Value for PWMxH only.
• When the PHASEx/SPHASEx registers provide the local period, the valid range is 0x0000 through
0xFFF8.
DS70000591F-page 246
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-15: SPHASEx: PWM SECONDARY PHASE-SHIFT x REGISTER(1,2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SPHASEx<15:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SPHASEx<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
x = Bit is unknown
SPHASEx<15:0>: Secondary Phase Offset bits for PWMxL Output Pin bits (used in Independent
PWM mode only)
If PWMCONx<9> = 0, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (IOCONx<10:8> = 00, 01 or 10),
SPHASEx<15:0> = Not Used.
• True Independent Output mode (IOCONx<10:8> = 11), PHASEx<15:0> = Phase-Shift Value for
PWMxL only.
• The PHASEx/SPHASEx registers provide the phase shift with respect to the master time base;
therefore, the valid range is 0x0000 through period.
If PWMCONx<9> = 1, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (IOCONx<10:8> = 00, 01 or 10),
SPHASEx<15:0> = Not Used.
• True Independent Output mode (IOCONx<10:8> = 11). PHASEx<15:0> = Independent Time Base
Period Value for PWMxL only.
• When the PHASEx/SPHASEx registers provide the local period, the valid range of values is
0x0010-0xFFF8.
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-16: DTRx: PWM DEAD-TIME x REGISTER
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DTRx<13:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DTRx<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-0
DTRx<13:0>: Unsigned 14-Bit Value for PWMx Dead-Time Unit bits
REGISTER 16-17: ALTDTRx: PWM ALTERNATE DEAD-TIME x REGISTER
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALTDTRx<13:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALTDTRx<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-0
ALTDTRx<13:0>: Unsigned 14-Bit Value for PWMx Dead-Time Unit bits
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-18: TRGCONx: PWM TRIGGER CONTROL x REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
TRGDIV3
TRGDIV2
TRGDIV1
TRGDIV0
—
—
—
—
bit 15
bit 8
R/W-0
(1)
DTM
U-0
R/W-0
—
TRGSTRT5
R/W-0
R/W-0
TRGSTRT4 TRGSTRT3
R/W-0
R/W-0
R/W-0
TRGSTRT2
TRGSTRT1
TRGSTRT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
TRGDIV<3:0>: Trigger # Output Divider bits
1111 = Trigger output for every 16th trigger event
1110 = Trigger output for every 15th trigger event
1101 = Trigger output for every 14th trigger event
1100 = Trigger output for every 13th trigger event
1011 = Trigger output for every 12th trigger event
1010 = Trigger output for every 11th trigger event
1001 = Trigger output for every 10th trigger event
1000 = Trigger output for every 9th trigger event
0111 = Trigger output for every 8th trigger event
0110 = Trigger output for every 7th trigger event
0101 = Trigger output for every 6th trigger event
0100 = Trigger output for every 5th trigger event
0011 = Trigger output for every 4th trigger event
0010 = Trigger output for every 3rd trigger event
0001 = Trigger output for every 2nd trigger event
0000 = Trigger output for every trigger event
bit 11-8
Unimplemented: Read as ‘0’
bit 7
DTM: Dual Trigger Mode bit(1)
1 = Secondary trigger event is combined with the primary trigger event to create the PWM trigger
0 = Secondary trigger event is not combined with the primary trigger event to create the PWM trigger;
two separate PWM triggers are generated
bit 6
Unimplemented: Read as ‘0’
bit 5-0
TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits
111111 = Waits 63 PWM cycles before generating the first trigger event after the module is enabled
•
•
•
000010 = Waits 2 PWM cycles before generating the first trigger event after the module is enabled
000001 = Waits 1 PWM cycle before generating the first trigger event after the module is enabled
000000 = Waits 0 PWM cycles before generating the first trigger event after the module is enabled
Note 1:
The secondary PWM generator cannot generate PWM trigger interrupts.
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
aa
REGISTER 16-19: IOCONx: PWM I/O CONTROL x REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PENH
PENL
POLH
POLL
PMOD1(1)
PMOD0(1)
OVRENH
OVRENL
bit 15
bit 8
R/W-0
R/W-0
OVRDAT1
OVRDAT0
R/W-0
FLTDAT1
R/W-0
(2)
R/W-0
(2)
FLTDAT0
(2)
CLDAT1
R/W-0
CLDAT0
(2)
R/W-0
R/W-0
SWAP
OSYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
PENH: PWMxH Output Pin Ownership bit
1 = PWM module controls PWMxH pin
0 = GPIO module controls PWMxH pin
bit 14
PENL: PWMxL Output Pin Ownership bit
1 = PWM module controls PWMxL pin
0 = GPIO module controls PWMxL pin
bit 13
POLH: PWMxH Output Pin Polarity bit
1 = PWMxH pin is active-low
0 = PWMxH pin is active-high
bit 12
POLL: PWMxL Output Pin Polarity bit
1 = PWMxL pin is active-low
0 = PWMxL pin is active-high
bit 11-10
PMOD<1:0>: PWM # I/O Pin Mode bits(1)
11 = PWM I/O pin pair is in the True Independent Output mode
10 = PWM I/O pin pair is in the Push-Pull Output mode
01 = PWM I/O pin pair is in the Redundant Output mode
00 = PWM I/O pin pair is in the Complementary Output mode
bit 9
OVRENH: Override Enable for PWMxH Pin bit
1 = OVRDAT<1> provides data for output on PWMxH pin
0 = PWM generator provides data for output on PWMxH pin
bit 8
OVRENL: Override Enable for PWMxL Pin bit
1 = OVRDAT<0> provides data for output on PWMxL pin
0 = PWM generator provides data for output on PWMxL pin
bit 7-6
OVRDAT<1:0>: Data for PWMxH, PWMxL Pins if Override is Enabled bits
If OVERENH = 1, OVRDAT<1> provides data for PWMxH
If OVERENL = 1, OVRDAT<0> provides data for PWMxL
bit 5-4
FLTDAT<1:0>: State for PWMxH and PWMxL Pins if FLTMOD is Enabled bits(2)
IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode:
If Fault is active, then FLTDAT<1> provides the state for PWMxH.
If Fault is active, then FLTDAT<0> provides the state for PWMxL.
IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode:
If current-limit is active, then FLTDAT<1> provides the state for PWMxH.
If Fault is active, then FLTDAT<0> provides the state for PWMxL.
Note 1:
2:
These bits should not be changed after the PWM module is enabled (PTEN = 1).
State represents the active/inactive state of the PWM depending on the POLH and POLL bit settings.
DS70000591F-page 250
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-19: IOCONx: PWM I/O CONTROL x REGISTER (CONTINUED)
bit 3-2
CLDAT<1:0>: State for PWMxH and PWMxL Pins if CLMOD is Enabled bits(2)
IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode:
If current-limit is active, then CLDAT<1> provides the state for PWMxH.
If current-limit is active, then CLDAT<0> provides the state for PWMxL.
IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode:
CLDAT<1:0> is ignored.
bit 1
SWAP: SWAP PWMxH and PWMxL Pins bit
1 = PWMxH output signal is connected to the PWMxL pin; PWMxL output signal is connected to the
PWMxH pin
0 = PWMxH and PWMxL pins are mapped to their respective pins
bit 0
OSYNC: Output Override Synchronization bit
1 = Output overrides, via the OVRDAT<1:0> bits, are synchronized to the PWM time base
0 = Output overrides, via the OVDDAT<1:0> bits, occur on next CPU clock boundary
Note 1:
2:
These bits should not be changed after the PWM module is enabled (PTEN = 1).
State represents the active/inactive state of the PWM depending on the POLH and POLL bit settings.
REGISTER 16-20: TRIGx: PWM PRIMARY TRIGGER x COMPARE VALUE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRGCMP<12:5>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRGCMP<4:0>
U-0
U-0
U-0
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-3
TRGCMP<12:0>: Trigger Compare Value bits
When the primary PWM functions in the local time base, this register contains the compare values
that can trigger the ADC module.
bit 2-0
Unimplemented: Read as ‘0’
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REGISTER 16-21: FCLCONx: PWM FAULT CURRENT-LIMIT CONTROL x REGISTER
R/W-0
IFLTMOD
R/W-0
R/W-0
R/W-0
R/W-0
CLSRC4(2,3) CLSRC3(2,3) CLSRC2(2,3) CLSRC1(2,3)
R/W-0
R/W-0
R/W-0
CLSRC0(2,3)
CLPOL(1)
CLMOD
bit 15
bit 8
R/W-0
(2,3)
FLTSRC4
R/W-0
FLTSRC3
(2,3)
R/W-0
(2,3)
FLTSRC2
R/W-0
FLTSRC1
(2,3)
R/W-0
FLTSRC0
(2,3)
R/W-0
FLTPOL
(1)
R/W-0
R/W-0
FLTMOD1
FLTMOD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
IFLTMOD: Independent Fault Mode Enable bit
1 = Independent Fault mode: Current-limit input maps FLTDAT<1> to PWMxH output and Fault input
maps FLTDAT<0> to PWMxL output. The CLDAT<1:0> bits are not used for override functions.
0 = Normal Fault mode: Current-Limit mode maps CLDAT<1:0> bits to the PWMxH and PWMxL
outputs. The PWM Fault mode maps FLTDAT<1:0> to the PWMxH and PWMxL outputs.
bit 14-10
CLSRC<4:0>: Current-Limit Control Signal Source Select for PWM Generator # bits(2,3)
These bits also specify the source for the Dead-Time Compensation input signal, DTCMPx.
11111 = Reserved
11110 = Fault 23
11101 = Fault 22
11100 = Fault 21
11011 = Fault 20
11010 = Fault 19
11001 = Fault 18
11000 = Fault 17
10111 = Fault 16
10110 = Fault 15
10101 = Fault 14
10100 = Fault 13
10011 = Fault 12
10010 = Fault 11
10001 = Fault 10
10000 = Fault 9
01111 = Fault 8
01110 = Fault 7
01101 = Fault 6
01100 = Fault 5
01011 = Fault 4
01010 = Fault 3
01001 = Fault 2
01000 = Fault 1
00111 = Reserved
00110 = Reserved
00101 = Reserved
00100 = Reserved
00011 = Analog Comparator 4
00010 = Analog Comparator 3
00001 = Analog Comparator 2
00000 = Analog Comparator 1
Note 1: These bits should be changed only when PTEN (PTCON<15>) = 0.
2: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Current-Limit mode
(CLSRC<4:0> = b0000), the Fault Control Source Select bits (FLTSRC<4:0>) should be set to an unused
Fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs.
3: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Fault mode
(FLTSRC<4:0> = b0000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an unused
current-limit source to prevent the current-limit source from disabling both the PWMxH and PWMxL outputs.
DS70000591F-page 252
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-21: FCLCONx: PWM FAULT CURRENT-LIMIT CONTROL x REGISTER (CONTINUED)
bit 9
CLPOL: Current-Limit Polarity for PWM Generator # bit(1)
1 = The selected current-limit source is active-low
0 = The selected current-limit source is active-high
bit 8
CLMOD: Current-Limit Mode Enable for PWM Generator # bit
1 = Current-Limit mode is enabled
0 = Current-Limit mode is disabled
bit 7-3
FLTSRC<4:0>: Fault Control Signal Source Select for PWM Generator # bits(2,3)
11111 = Reserved
11110 = Fault 23
11101 = Fault 22
11100 = Fault 21
11011 = Fault 20
11010 = Fault 19
11001 = Fault 18
11000 = Fault 17
10111 = Fault 16
10110 = Fault 15
10101 = Fault 14
10100 = Fault 13
10011 = Fault 12
10010 = Fault 11
10001 = Fault 10
10000 = Fault 9
01111 = Fault 8
01110 = Fault 7
01101 = Fault 6
01100 = Fault 5
01011 = Fault 4
01010 = Fault 3
01001 = Fault 2
01000 = Fault 1
00111 = Reserved
00110 = Reserved
00101 = Reserved
00100 = Reserved
00011 = Analog Comparator 4
00010 = Analog Comparator 3
00001 = Analog Comparator 2
00000 = Analog Comparator 1
bit 2
FLTPOL: Fault Polarity for PWM Generator # bit(1)
1 = The selected Fault source is active-low
0 = The selected Fault source is active-high
bit 1-0
FLTMOD<1:0>: Fault Mode for PWM Generator # bits
11 = Fault input is disabled
10 = Reserved
01 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (cycle)
00 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (latched condition)
Note 1: These bits should be changed only when PTEN (PTCON<15>) = 0.
2: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Current-Limit mode
(CLSRC<4:0> = b0000), the Fault Control Source Select bits (FLTSRC<4:0>) should be set to an unused
Fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs.
3: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Fault mode
(FLTSRC<4:0> = b0000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an unused
current-limit source to prevent the current-limit source from disabling both the PWMxH and PWMxL outputs.
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REGISTER 16-22: STRIGx: PWM SECONDARY TRIGGER x COMPARE VALUE REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STRGCMP<12:5>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STRGCMP<4:0>
U-0
U-0
U-0
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-3
STRGCMP<12:0>: PWM Secondary Trigger Compare Value bits
When the secondary PWM functions in a local time base, this register contains the compare values
that can trigger the ADC module.
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
STRIGx cannot generate the PWM trigger interrupts.
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-23: LEBCONx: LEADING-EDGE BLANKING CONTROL x REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
PHR
PHF
PLR
PLF
FLTLEBEN
CLLEBEN
—
—
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
BCH(1)
BCL(1)
BPHH
BPHL
BPLH
BPLL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
PHR: PWMxH Rising Edge Trigger Enable bit
1 = Rising edge of PWMxH will trigger Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores rising edge of PWMxH
bit 14
PHF: PWMxH Falling Edge Trigger Enable bit
1 = Falling edge of PWMxH will trigger Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores falling edge of PWMxH
bit 13
PLR: PWMxL Rising Edge Trigger Enable bit
1 = Rising edge of PWMxL will trigger Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores rising edge of PWMxL
bit 12
PLF: PWMxL Falling Edge Trigger Enable bit
1 = Falling edge of PWMxL will trigger Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores falling edge of PWMxL
bit 11
FLTLEBEN: Fault Input Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to selected Fault input
0 = Leading-Edge Blanking is not applied to selected Fault input
bit 10
CLLEBEN: Current-Limit Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to selected current-limit input
0 = Leading-Edge Blanking is not applied to selected current-limit input
bit 9-6
Unimplemented: Read as ‘0’
bit 5
BCH: Blanking in Selected Blanking Signal High Enable bit(1)
1 = State blanking (of current-limit and/or Fault input signals) when selected blanking signal is high
0 = No blanking when selected blanking signal is high
bit 4
BCL: Blanking in Selected Blanking Signal Low Enable bit(1)
1 = State blanking (of current-limit and/or Fault input signals) when selected blanking signal is low
0 = No blanking when selected blanking signal is low
bit 3
BPHH: Blanking in PWMxH High Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when PWMxH output is high
0 = No blanking when PWMxH output is high
bit 2
BPHL: Blanking in PWMxH Low Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when PWMxH output is low
0 = No blanking when PWMxH output is low
Note 1:
The blanking signal is selected via the BLANKSELx bits in the AUXCONx register.
 2009-2014 Microchip Technology Inc.
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-23: LEBCONx: LEADING-EDGE BLANKING CONTROL x REGISTER (CONTINUED)
bit 1
BPLH: Blanking in PWMxL High Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when PWMxL output is high
0 = No blanking when PWMxL output is high
bit 0
BPLL: Blanking in PWMxL Low Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when PWMxL output is low
0 = No blanking when PWMxL output is low
Note 1:
The blanking signal is selected via the BLANKSELx bits in the AUXCONx register.
DS70000591F-page 256
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-24: LEBDLYx: LEADING-EDGE BLANKING DELAY x REGISTER
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
LEB<8:5>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEB<4:0>
U-0
U-0
U-0
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
Unimplemented: Read as ‘0’
bit 11-3
LEB<8:0>: Leading-Edge Blanking Delay for Current-Limit and Fault Inputs bits
The value is in 8.32 ns increments.
bit 2-0
Unimplemented: Read as ‘0’
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-25: AUXCONx: PWM AUXILIARY CONTROL x REGISTER
R/W-0
R/W-0
U-0
U-0
HRPDIS
HRDDIS
—
—
R/W-0
R/W-0
R/W-0
R/W-0
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
CHOPSEL3 CHOPSEL2 CHOPSEL1
R/W-0
R/W-0
R/W-0
CHOPSEL0
CHOPHEN
CHOPLEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
HRPDIS: High-Resolution PWM Period Disable bit
1 = High-resolution PWM period is disabled to reduce power consumption
0 = High-resolution PWM period is enabled
bit 14
HRDDIS: High-Resolution PWM Duty Cycle Disable bit
1 = High-resolution PWM duty cycle is disabled to reduce power consumption
0 = High-resolution PWM duty cycle is enabled
bit 13-12
Unimplemented: Read as ‘0’
bit 11-8
BLANKSEL<3:0>: PWM State Blank Source Select bits
The selected state blank signal will block the current limit and/or Fault input signals (if enabled via the
BCH and BCL bits in the LEBCONx register).
1001 = PWM9H is selected as state blank source
1000 = PWM8H is selected as state blank source
0111 = PWM7H is selected as state blank source
0110 = PWM6H is selected as state blank source
0101 = PWM5H is selected as state blank source
0100 = PWM4H is selected as state blank source
0011 = PWM3H is selected as state blank source
0010 = PWM2H is selected as state blank source
0001 = PWM1H is selected as state blank source
0000 = 1’b0 (no state blanking)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-2
CHOPSEL<3:0>: PWM Chop Clock Source Select bits
The selected signal will enable and disable (CHOPx) the selected PWM outputs.
1001 = PWM9H is selected as chop clock source
1000 = PWM8H is selected as chop clock source
0111 = PWM7H is selected as chop clock source
0110 = PWM6H is selected as chop clock source
0101 = PWM5H is selected as chop clock source
0100 = PWM4H is selected as chop clock source
0011 = PWM3H is selected as chop clock source
0010 = PWM2H is selected as chop clock source
0001 = PWM1H is selected as chop clock source
0000 = Chop clock generator is selected as the chop clock source
bit 1
CHOPHEN: PWMxH Output Chopping Enable bit
1 = PWMxH chopping function is enabled
0 = PWMxH chopping function is disabled
bit 0
CHOPLEN: PWMxL Output Chopping Enable bit
1 = PWMxL chopping function is enabled
0 = PWMxL chopping function is disabled
DS70000591F-page 258
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-26: PWMCAPx: PRIMARY PWM TIME BASE CAPTURE x REGISTER
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
PWMCAP<12:5>(1,2,3,4)
bit 15
bit 8
R-0
R-0
R-0
R-0
R-0
PWMCAP<4:0>(1,2,3,4)
U-0
U-0
U-0
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-3
PWMCAP<12:0>: Captured PWM Time Base Value bits(1,2,3,4)
The value in this register represents the captured PWM time base value when a leading edge is
detected on the current-limit input.
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
2:
3:
4:
The capture feature is only available on the primary output (PWMxH).
This feature is active only after LEB processing on the current-limit input signal is complete.
The minimum capture resolution is 8.32 ns.
This feature can be used when the XPRES bit (PWMCONx<1>) is set to ‘0’.
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS70000591F-page 260
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
17.0
QUADRATURE ENCODER
INTERFACE (QEI) MODULE
This chapter describes the Quadrature Encoder Interface (QEI) module and associated operational modes.
The QEI module provides the interface to incremental
encoders for obtaining mechanical position data.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Quadrature Encoder
Interface (QEI)” (DS70208) in the
“dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip
web site (www.microchip.com). The information in this data sheet supersedes
the information in the FRM.
The operational features of the QEI include:
• Three Input Channels for Two Phase Signals and
Index Pulse
• 16-Bit Up/Down Position Counter
• Count Direction Status
• Position Measurement (x2 and x4) mode
• Programmable Digital Noise Filters on Inputs
• Alternate 16-Bit Timer/Counter mode
• Quadrature Encoder Interface Interrupts
These operating modes are determined by setting the
appropriate bits, QEIM<2:0> in (QEIxCON<10:8>).
Figure 17-1 depicts the Quadrature Encoder Interface
block diagram.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 17-1:
Note:
An ‘x’ used in the names of pins, control/
status bits and registers denotes a
particular QEI module number (x = 1 or 2).
QUADRATURE ENCODER INTERFACE x BLOCK DIAGRAM (x = 1 OR 2)
TQCKPS<1:0>
2
TQCS
Sleep Input
TCY
0
Synchronize
Detect
Prescaler
1, 8, 64, 256
1
1
QEIM<2:0>
0
CK
QEAx(1)
Programmable
Digital Filter
UPDN_SRC
0
3
QEIM<2:0>
Mode Select
QEBx(1)
Programmable
Digital Filter
INDXx(1)
Programmable
Digital Filter
PCDOUT
0
1
Quadrature
Encoder
Interface Logic
Q
16-Bit Up/Down Counter
(POSxCNT)
Reset
Comparator/
Zero-Detect
QEIxCON<11>
1
UPDNx
2
3
Existing Pin Logic
Note 1:
QExIF
Event
Flag
Q
D
TQGATE
Equal
Max Count Register
(MAXxCNT)
The QEI1 module can be connected to the QEA1/QEB1/INDX1
or AQEA1/AQEB1/AINDX1 pins, which are controlled by clearing
or setting the ALTQIO bit in the FPOR Configuration register. See
Section 24.0 “Special Features” for more information.
Up/Down
 2009-2014 Microchip Technology Inc.
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 17-1:
QEIxCON: QEIx CONTROL REGISTER (x = 1 or 2)
R/W-0
U-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
CNTERR(1)
—
QEISIDL
INDX
UPDN(2)
QEIM2
QEIM1
QEIM0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
SWPAB
PCDOUT
TQGATE
R/W-0
R/W-0
TQCKPS1(3) TQCKPS0(3)
R/W-0
R/W-0
R/W-0
POSRES(4)
TQCS
UPDN_SRC(5)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CNTERR: Count Error Status Flag bit(1)
1 = Position count error has occurred
0 = No position count error has occurred
bit 14
Unimplemented: Read as ‘0’
bit 13
QEISIDL: QEIx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
INDX: Index Pin State Status bit (read-only)
1 = Index pin is high
0 = Index pin is low
bit 11
UPDN: Position Counter Direction Status bit(2)
1 = Position counter direction is positive (+)
0 = Position counter direction is negative (-)
bit 10-8
QEIM<2:0>: Quadrature Encoder Interface Mode Select bits
111 = Quadrature Encoder Interface is enabled (x4 mode) with the position counter reset by the match
(MAXxCNT)
110 = Quadrature Encoder Interface is enabled (x4 mode) with the Index Pulse Reset of the position
counter
101 = Quadrature Encoder Interface is enabled (x2 mode) with the position counter reset by the match
(MAXxCNT)
100 = Quadrature Encoder Interface is enabled (x2 mode) with the Index Pulse Reset of the position
counter
011 = Unused (module disabled)
010 = Unused (module disabled)
001 = Starts 16-bit timer
000 = Quadrature Encoder Interface/timer off
bit 7
SWPAB: Phase A and Phase B Input Swap Select bit
1 = Phase A and Phase B inputs are swapped
0 = Phase A and Phase B inputs are not swapped
bit 6
PCDOUT: Position Counter Direction State Output Enable bit
1 = Position counter direction status output is enabled (QEI logic controls state of I/O pin)
0 = Position counter direction status output is disabled (normal I/O pin operation)
Note 1:
2:
3:
4:
5:
CNTERR flag only applies when QEIM<2:0> = 110 or 100.
Read-only bit when QEIM<2:0> = 1xx; read/write bit when QEIM<2:0> = 001.
Prescaler utilized for 16-Bit Timer mode only.
This bit applies only when QEIM<2:0> = 100 or 110.
When configured for QEI mode, this control bit is a ‘don’t care’.
DS70000591F-page 262
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 17-1:
QEIxCON: QEIx CONTROL REGISTER (x = 1 or 2) (CONTINUED)
bit 5
TQGATE: Timer Gated Time Accumulation Enable bit
1 = Timer gated time accumulation is enabled
0 = Timer gated time accumulation is disabled
bit 4-3
TQCKPS<1:0>: Timer Input Clock Prescale Select bits(3)
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
bit 2
POSRES: Position Counter Reset Enable bit(4)
1 = Index pulse resets the position counter
0 = Index pulse does not reset the position counter
bit 1
TQCS: Timer Clock Source Select bit
1 = External clock from pin, QEAx (on the rising edge)
0 = Internal clock (TCY)
bit 0
UPDN_SRC: Position Counter Direction Selection Control bit(5)
1 = QEBx pin state defines the position counter direction
0 = Control/status bit, UPDN (QEIxCON<11>), defines the timer counter (POSxCNT) direction
Note 1:
2:
3:
4:
5:
CNTERR flag only applies when QEIM<2:0> = 110 or 100.
Read-only bit when QEIM<2:0> = 1xx; read/write bit when QEIM<2:0> = 001.
Prescaler utilized for 16-Bit Timer mode only.
This bit applies only when QEIM<2:0> = 100 or 110.
When configured for QEI mode, this control bit is a ‘don’t care’.
 2009-2014 Microchip Technology Inc.
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 17-2:
DFLTxCON: DIGITAL FILTER x CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
IMV1
IMV0
CEID
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
QEOUT
QECK2
QECK1
QECK0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
Unimplemented: Read as ‘0’
bit 10-9
IMV<1:0>: Index Match Value bits
These bits allow the user application to specify the state of the QEAx and QEBx input pins during an
index pulse when the POSxCNT register is to be reset.
In x4 Quadrature Count Mode:
IMV1 = Required state of Phase B input signal for match on index pulse
IMV0 = Required state of Phase A input signal for match on index pulse
In x2 Quadrature Count Mode:
IMV1 = Selects phase input signal for index state match (0 = Phase A, 1 = Phase B)
IMV0 = Required state of the selected phase input signal for match on index pulse
bit 8
CEID: Count Error Interrupt Disable bit
1 = Interrupts due to count errors are disabled
0 = Interrupts due to count errors are enabled
bit 7
QEOUT: QEAx/QEBx/INDXx Pin Digital Filter Output Enable bit
1 = Digital filter outputs are enabled
0 = Digital filter outputs are disabled (normal pin operation)
bit 6-4
QECK<2:0>: QEAx/QEBx/INDXx Digital Filter Clock Divide Select Bits
111 = 1:256 clock divide
110 = 1:128 clock divide
101 = 1:64 clock divide
100 = 1:32 clock divide
011 = 1:16 clock divide
010 = 1:4 clock divide
001 = 1:2 clock divide
000 = 1:1 clock divide
bit 3-0
Unimplemented: Read as ‘0’
DS70000591F-page 264
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
18.0
SERIAL PERIPHERAL
INTERFACE (SPI)
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface useful for communicating
with other peripheral or microcontroller devices. These
peripheral devices can be serial EEPROMs, shift
registers, display drivers, Analog-to-Digital Converters
and so on. The SPI module is compatible with the
Motorola® SPI and SIOP modules.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Serial Peripheral
Interface (SPI)” (DS70005185) in the
“dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip
web site (www.microchip.com). The
information in this data sheet supersedes
the information in the FRM.
The SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1 or 2), used for shifting data in and
out, and a buffer register, SPIxBUF. A control register,
SPIxCON, configures the module. Additionally, a status
register, SPIxSTAT, indicates status conditions.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
In Master mode operation, SCK is a clock output; in
Slave mode, it is a clock input.
FIGURE 18-1:
The serial interface consists of these four pins:
•
•
•
•
SDIx (Serial Data Input)
SDOx (Serial Data Output)
SCKx (Shift Clock Input Or Output)
SSx (Active-Low Slave Select)
SPIx MODULE BLOCK DIAGRAM
SCKx
1:1 to 1:8
Secondary
Prescaler
1:1/4/16/64
Primary
Prescaler
FCY
SSx(1)
Sync
Control
Select
Edge
Control
Clock
SPIxCON1<1:0>
Shift Control
SPIxCON1<4:2>
SDOx
Enable
Master Clock
bit 0
SDIx
SPIxSR
Transfer
Transfer
SPIxRXB
SPIxTXB
SPIxBUF
Read SPIxBUF
Write SPIxBUF
16
Internal Data Bus
Note 1:
The SPI1 module can be connected to the SS1 or ASS1 pins, which are controlled by clearing or setting the
ALTSS1 bit in the FPOR Configuration register. See Section 24.0 “Special Features” for more information.
 2009-2014 Microchip Technology Inc.
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 18-1:
SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
SPIEN
—
SPISIDL
—
—
—
—
—
bit 15
bit 8
U-0
R/C-0
U-0
U-0
U-0
U-0
R-0
R-0
—
SPIROV
—
—
—
—
SPITBF
SPIRBF
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
SPIEN: SPIx Enable bit
1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables module
bit 14
Unimplemented: Read as ‘0’
bit 13
SPISIDL: SPIx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7
Unimplemented: Read as ‘0’
bit 6
SPIROV: SPIx Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded; the user software has not read the
previous data in the SPIxBUF register
0 = No overflow has occurred
bit 5-2
Unimplemented: Read as ‘0’
bit 1
SPITBF: SPIx Transmit Buffer Full Status bit
1 = Transmit has not yet started, SPIxTXB is full
0 = Transmit has started, SPIxTXB is empty. Automatically set in hardware when CPU writes the
SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when the SPIx module
transfers data from SPIxTXB to SPIxSR.
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit
1 = Receive is complete, SPIxRXB is full
0 = Receive is not complete, SPIxRXB is empty. Automatically set in hardware when SPIx transfers
data from SPIxSR to SPIxRXB. Automatically cleared in hardware when the core reads the
SPIxBUF location, reading SPIxRXB.
DS70000591F-page 266
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 18-2:
SPIXCON1: SPIx CONTROL REGISTER 1
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
DISSCK
DISSDO
MODE16
SMP
CKE(1)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSEN(3)
CKP
MSTEN
SPRE2(2)
SPRE1(2)
SPRE0(2)
PPRE1(2)
PPRE0(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12
DISSCK: Disable SCKx Pin bit (SPI Master modes only)
1 = Internal SPI clock is disabled; pin functions as I/O
0 = Internal SPI clock is enabled
bit 11
DISSDO: Disable SDOx Pin bit
1 = SDOx pin is not used by module; pin functions as I/O
0 = SDOx pin is controlled by the module
bit 10
MODE16: Word/Byte Communication Select bit
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
bit 9
SMP: SPIx Data Input Sample Phase bit
Master mode:
1 = Input data is sampled at the end of data output time
0 = Input data is sampled at the middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8
CKE: SPIx Clock Edge Select bit(1)
1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
bit 7
SSEN: Slave Select Enable bit (Slave mode)(3)
1 = SSx pin is used for Slave mode
0 = SSx pin is not used by module; pin is controlled by port function
bit 6
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5
MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
Note 1:
2:
3:
The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes
(FRMEN = 1).
Do not set both primary and secondary prescalers to a value of 1:1.
This bit must be cleared when FRMEN = 1.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 267
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 18-2:
SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
bit 4-2
SPRE<2:0>: Secondary Prescale bits (Master mode)(2)
111 = Secondary prescale 1:1
110 = Secondary prescale 2:1
•
•
•
000 = Secondary prescale 8:1
bit 1-0
PPRE<1:0>: Primary Prescale bits (Master mode)(2)
11 = Primary prescale 1:1
10 = Primary prescale 4:1
01 = Primary prescale 16:1
00 = Primary prescale 64:1
Note 1:
2:
3:
The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes
(FRMEN = 1).
Do not set both primary and secondary prescalers to a value of 1:1.
This bit must be cleared when FRMEN = 1.
DS70000591F-page 268
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 18-3:
SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
—
—
—
—
—
—
FRMDLY
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
FRMEN: Framed SPIx Support bit
1 = Framed SPIx support is enabled (SSx pin is used as Frame Sync pulse input/output)
0 = Framed SPIx support is disabled
bit 14
SPIFSD: Frame Sync Pulse Direction Control bit
1 = Frame Sync pulse input (slave)
0 = Frame Sync pulse output (master)
bit 13
FRMPOL: Frame Sync Pulse Polarity bit
1 = Frame Sync pulse is active-high
0 = Frame Sync pulse is active-low
bit 12-2
Unimplemented: Read as ‘0’
bit 1
FRMDLY: Frame Sync Pulse Edge Select bit
1 = Frame Sync pulse coincides with first bit clock
0 = Frame Sync pulse precedes first bit clock
bit 0
Unimplemented: This bit must not be set to ‘1’ by the user application
 2009-2014 Microchip Technology Inc.
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS70000591F-page 270
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
19.0
INTER-INTEGRATED CIRCUIT
(I2C™)
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Inter-Integrated Circuit™ (I2C™)” (DS70000195) in the
“dsPIC33/PIC24
Family
Reference
Manual”, which is available from the Microchip web site (www.microchip.com). The
information in this data sheet supersedes
the information in the FRM.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Inter-Integrated Circuit (I2C) module provides
complete hardware support for both Slave and
Multi-Master modes of the I2C serial communication
standard with a 16-bit interface.
The I2C module has a 2-pin interface:
• The SCLx pin is clock.
• The SDAx pin is data.
The I2C module offers the following key features:
• I2C Interface Supporting Both Master and Slave
modes of Operation
• I2C Slave mode Supports 7-Bit and
10-Bit Addressing
• I2C Master mode Supports 7-Bit and
10-Bit Addressing
• I2C Port allows Bidirectional Transfers Between
Master and Slaves
• Serial Clock Synchronization for I2C Port can be
used as a Handshake Mechanism to Suspend
and Resume Serial Transfer (SCLREL control)
• I2C Supports Multi-Master Operation, Detects Bus
Collision and Arbitrates Accordingly
 2009-2014 Microchip Technology Inc.
19.1
Operating Modes
The hardware fully implements all the master and slave
functions of the I2C Standard and Fast mode
specifications, as well as 7-bit and 10-bit addressing.
The I2C module can operate either as a slave or a
master on an I2C bus.
The following types of I2C operation are supported:
•
•
•
I2C slave operation with 7-bit addressing
I2C slave operation with 10-bit addressing
I2C master operation with 7-bit or 10-bit addressing
For details about the communication sequence in each
of these modes, refer to the “dsPIC33/PIC24 Family
Reference Manual”. Please see the Microchip web site
(www.microchip.com) for the latest “dsPIC33/PIC24
Family Reference Manual” sections.
19.2
I2C Registers
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write:
• I2CxRSR is the shift register used for shifting data
internal to the module and the user application
has no access to it.
• I2CxRCV is the receive buffer and the register to
which data bytes are written or from which data
bytes are read.
• I2CxTRN is the transmit register to which bytes
are written during a transmit operation.
• The I2CxADD register holds the slave address.
• A status bit, ADD10, indicates 10-Bit Addressing
mode.
• The I2CxBRG acts as the Baud Rate Generator
(BRG) reload value.
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV
and an interrupt pulse is generated.
DS70000591F-page 271
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 19-1:
I2Cx BLOCK DIAGRAM (X = 1 or 2)
Internal
Data Bus
I2CxRCV
Read
SCLx
Shift
Clock
I2CxRSR
LSb
SDAx
Address Match
Match Detect
Write
I2CxMSK
Write
Read
I2CxADD
Read
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
Control Logic
I2CxSTAT
Collision
Detect
Read
Write
I2CxCON
Acknowledge
Generation
Read
Clock
Stretching
Write
I2CxTRN
LSb
Read
Shift Clock
Reload
Control
BRG Down Counter
Write
I2CxBRG
Read
TCY/2
DS70000591F-page 272
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 19-1:
I2CxCON: I2Cx CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-1, HC
R/W-0
R/W-0
R/W-0
R/W-0
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
I2CEN: I2Cx Enable bit
1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module; all I2C pins are controlled by port functions
bit 14
Unimplemented: Read as ‘0’
bit 13
I2CSIDL: I2Cx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
SCLREL: SCLx Release Control bit (when operating as I2C slave)
1 = Releases SCLx clock
0 = Holds SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear
at beginning of slave transmission. Hardware is clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware is clear at beginning of slave
transmission.
bit 11
IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1 = IPMI mode is enabled; all addresses are Acknowledged
0 = IPMI mode is disabled
bit 10
A10M: 10-Bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
bit 9
DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled
bit 8
SMEN: SMBus Input Levels bit
1 = Enables I/O pin thresholds compliant with SMBus specification
0 = Disables SMBus input thresholds
bit 7
GCEN: General Call Enable bit (when operating as I2C™ slave)
1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for
reception)
0 = General call address is disabled
bit 6
STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with the SCLREL bit.
1 = Enables software or receives clock stretching
0 = Disables software or receives clock stretching
 2009-2014 Microchip Technology Inc.
DS70000591F-page 273
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 19-1:
I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
bit 5
ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that is transmitted when the software initiates an Acknowledge sequence.
1 = Sends NACK during Acknowledge
0 = Sends ACK during Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master
receive)
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit.
Hardware clears at the end of the master Acknowledge sequence.
0 = Acknowledge sequence is not in progress
bit 3
RCEN: Receive Enable bit (when operating as I2C master)
1 = Enables Receive mode for I2C. Hardware clears at the end of the eighth bit of the master receive
data byte.
0 = Receive sequence is not in progress
bit 2
PEN: Stop Condition Enable bit (when operating as I2C master)
1 = Initiates Stop condition on SDAx and SCLx pins. Hardware clears at the end of the master Stop
sequence.
0 = Stop condition is not in progress
bit 1
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1 = Initiates Repeated Start condition on SDAx and SCLx pins. Hardware clears at the end of the
master Repeated Start sequence.
0 = Repeated Start condition is not in progress
bit 0
SEN: Start Condition Enable bit (when operating as I2C master)
1 = Initiates Start condition on SDAx and SCLx pins. Hardware clears at the end of the master Start
sequence.
0 = Start condition is not in progress
DS70000591F-page 274
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 19-2:
I2CxSTAT: I2Cx STATUS REGISTER
R-0, HSC
R-0, HSC
U-0
U-0
U-0
R/C-0, HSC
R-0, HSC
R-0, HSC
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
bit 15
bit 8
R/C-0, HS
R/C-0, HS
R-0, HSC
R/C-0, HSC
R/C-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
bit 7
bit 0
Legend:
C = Clearable bit
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
bit 15
ACKSTAT: Acknowledge Status bit (when operating as I2C™ master, applicable to master transmit operation)
1 = NACK received from slave
0 = ACK received from slave
Hardware is set or clear at the end of slave Acknowledge.
bit 14
TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware is set at the beginning of master transmission. Hardware is clear at the end of slave Acknowledge.
bit 13-11
Unimplemented: Read as ‘0’
bit 10
BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware set at detection of bus collision.
bit 9
GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware is set when the address matches the general call address. Hardware is clear at Stop detection.
bit 8
ADD10: 10-Bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware is set at the match of the 2nd byte of matched 10-bit address. Hardware is clear at Stop detection.
bit 7
IWCOL: Write Collision Detect bit
1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy
0 = No collision
Hardware is set at the occurrence of a write to I2CxTRN while busy (cleared by software).
bit 6
I2COV: Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow
Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
bit 5
D_A: Data/Address bit (when operating as I2C slave)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was a device address
Hardware is clear at a device address match. Hardware is set by reception of a slave byte.
bit 4
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware is set or clear when Start, Repeated Start or Stop is detected.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 275
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 19-2:
I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
bit 3
S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware is set or clear when Start, Repeated Start or Stop is detected.
bit 2
R_W: Read/Write Information bit (when operating as I2C slave)
1 = Read – indicates data transfer is output from slave
0 = Write – indicates data transfer is input to slave
Hardware is set or clear after reception of an I 2C device address byte.
bit 1
RBF: Receive Buffer Full Status bit
1 = Receive is complete, I2CxRCV is full
0 = Receive is not complete, I2CxRCV is empty
Hardware is set when I2CxRCV is written with a received byte. Hardware is clear when software reads
I2CxRCV.
bit 0
TBF: Transmit Buffer Full Status bit
1 = Transmit in progress, I2CxTRN is full
0 = Transmit is complete, I2CxTRN is empty
Hardware is set when software writes to I2CxTRN. Hardware is clear at completion of the data transmission.
DS70000591F-page 276
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 19-3:
I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
R/W-0
R/W-0
AMSK<9:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AMSK<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-10
Unimplemented: Read as ‘0’
bit 9-0
AMSK<9:0>: Mask for Address bit x Select bits
1 = Enables masking for bit x of incoming message address; bit match is not required in this position
0 = Disables masking for bit x; bit match is required in this position
 2009-2014 Microchip Technology Inc.
DS70000591F-page 277
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS70000591F-page 278
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
20.0
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “UART” (DS70188) in the
“dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip
web site (www.microchip.com). The information in this data sheet supersedes the
information in the FRM.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules
available in the dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610 device families. The
UART is a full-duplex, asynchronous system that can
communicate with peripheral devices, such as
personal computers, LIN/JS2602, RS-232 and RS-485
interfaces. The module also supports a hardware flow
control option with the UxCTS and UxRTS pins and
also includes an IrDA encoder and decoder.
FIGURE 20-1:
The primary features of the UARTx module are:
• Full-Duplex, 8-Bit or 9-Bit Data Transmission
through the UxTX and UxRX Pins
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
• Hardware Flow Control Option with UxCTS and
UxRTS Pins
• Fully Integrated Baud Rate Generator with 16-Bit
Prescaler
• Baud Rates Ranging from 10 Mbps to 38 bps at
40 MIPS
• Baud Rates Ranging from 12.5 Mbps to 47 bps at
50 MIPS
• 4-Deep, First-In First-Out (FIFO) Transmit Data
Buffer
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error Detection
• Support for 9-Bit mode with Address Detect
(9th bit = 1)
• Transmit and Receive Interrupts
• A Separate Interrupt for all UART Error Conditions
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Support for Automatic Baud Rate Detection
• IrDA Encoder and Decoder Logic
• 16x Baud Clock Output for IrDA® Support
• Support for DMA
A simplified block diagram of the UART module is
shown in Figure 20-1. The UART module consists of
these key hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
SIMPLIFIED UARTx BLOCK DIAGRAM
Baud Rate Generator
IrDA®
Hardware Flow Control
UxRTS/BCLK
UxCTS
UARTx Receiver
UxRX
UARTx Transmitter
UxTX
 2009-2014 Microchip Technology Inc.
DS70000591F-page 279
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 20-1:
R/W-0
UxMODE: UARTx MODE REGISTER
U-0
(1)
UARTEN
—
R/W-0
USIDL
R/W-0
IREN
(2)
R/W-0
U-0
R/W-0
R/W-0
RTSMD
—
UEN1
UEN0
bit 15
bit 8
R/W-0, HC
R/W-0
R/W-0, HC
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WAKE
LPBACK
ABAUD
URXINV
BRGH
PDSEL1
PDSEL0
STSEL
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
UARTEN: UARTx Enable bit(1)
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0 = UARTx is disabled; all UARTx pins are controlled by port latches, UARTx power consumption is
minimal
bit 14
Unimplemented: Read as ‘0’
bit 13
USIDL: UARTx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
IREN: IrDA® Encoder and Decoder Enable bit(2)
1 = IrDA encoder and decoder are enabled
0 = IrDA encoder and decoder are disabled
bit 11
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
bit 9-8
UEN<1:0>: UARTx Pin Enable bits
11 = UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin is controlled by port latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins are controlled by
port latches
bit 7
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1 = UARTx will continue to sample the UxRX pin; interrupt is generated on falling edge, bit is cleared
in hardware on following rising edge
0 = No wake-up is enabled
bit 6
LPBACK: UARTx Loopback Mode Select bit
1 = Enables Loopback mode
0 = Loopback mode is disabled
bit 5
ABAUD: Auto-Baud Enable bit
1 = Enables baud rate measurement on the next character – requires reception of a Sync field (55h)
before other data; cleared in hardware upon completion
0 = Baud rate measurement is disabled or completed
Note 1:
2:
Refer to “UART” (DS70188) in the “dsPIC33/PIC24 Family Reference Manual” for information on
enabling the UART module for receive or transmit operation. That section of the manual is available on the
Microchip web site: www.microchip.com.
This feature is only available for the 16x BRG mode (BRGH = 0).
DS70000591F-page 280
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 20-1:
UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 4
URXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3
BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1
PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0
STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
Note 1:
2:
Refer to “UART” (DS70188) in the “dsPIC33/PIC24 Family Reference Manual” for information on
enabling the UART module for receive or transmit operation. That section of the manual is available on the
Microchip web site: www.microchip.com.
This feature is only available for the 16x BRG mode (BRGH = 0).
 2009-2014 Microchip Technology Inc.
DS70000591F-page 281
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 20-2:
R/W-0
UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0
UTXISEL1
UTXINV
R/W-0
UTXISEL0
U-0
R/W-0, HC
—
UTXBRK
R/W-0
(1)
UTXEN
R-0
R-1
UTXBF
TRMT
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R-1
R-0
R-0
R/C-0
R-0
URXISEL1
URXISEL0
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15,13
UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result,
the transmit buffer becomes empty
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
least one character open in the transmit buffer)
bit 14
UTXINV: UARTx Transmit Polarity Inversion bit
If IREN = 0:
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’
If IREN = 1:
1 = IrDA® encoded UxTX Idle state is ‘1’
0 = IrDA encoded UxTX Idle state is ‘0’
bit 12
Unimplemented: Read as ‘0’
bit 11
UTXBRK: UARTx Transmit Break bit
1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop
bit; cleared by hardware upon completion
0 = Sync Break transmission is disabled or has completed
bit 10
UTXEN: UARTx Transmit Enable bit(1)
1 = Transmit is enabled, UxTX pin is controlled by UARTx
0 = Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is
controlled by the port
bit 9
UTXBF: UARTx Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full; at least one more character can be written
bit 8
TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6
URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits
11 = Interrupt is set on UxRSR transfer, making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on UxRSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive
buffer; receive buffer has one or more characters
Note 1:
Refer to “UART” (DS70188) in the “dsPIC33/PIC24 Family Reference Manual” for information on
enabling the UART module for transmit operation. That section of the manual is available on the Microchip
web site: www.microchip.com.
DS70000591F-page 282
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 20-2:
UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 5
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect
0 = Address Detect mode is disabled
bit 4
RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Receiver is active
bit 3
PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character (the character at the top of the receive
FIFO)
0 = Parity error has not been detected
bit 2
FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character (the character at the top of the receive
FIFO)
0 = Framing error has not been detected
bit 1
OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed; clearing a previously set OERR bit (1  0 transition) will reset
the receiver buffer and the UxRSR to the empty state
bit 0
URXDA: UARTx Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
Note 1:
Refer to “UART” (DS70188) in the “dsPIC33/PIC24 Family Reference Manual” for information on
enabling the UART module for transmit operation. That section of the manual is available on the Microchip
web site: www.microchip.com.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 283
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS70000591F-page 284
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
21.0
ENHANCED CAN (ECAN™)
MODULE
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “ECAN™” (DS70185) in the
dsPIC33/PIC24 Family Reference Manual,
which is available from the Microchip web
site (www.microchip.com). The information
in this data sheet supersedes the
information in the FRM.
21.1
• Programmable Wake-up Functionality with
Integrated Low-Pass Filter
• Programmable Loopback mode Supports
Self-Test Operation
• Signaling via Interrupt Capabilities for all CAN
Receiver and Transmitter Error States
• Programmable Clock Source
• Programmable Link to Input Capture module
(IC2 for CAN1) for Time-Stamping and Network
Synchronization
• Low-Power Sleep and Idle mode
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The CAN bus module consists of a protocol engine and
message buffering/control. The CAN protocol engine
handles all functions for receiving and transmitting
messages on the CAN bus. Messages are transmitted
by first loading the appropriate data registers. Status
and errors can be checked by reading the appropriate
registers. Any message detected on the CAN bus is
checked for errors and then matched against filters to
see if it should be received and stored in one of the
receive registers.
Overview
21.2
The Enhanced Controller Area Network (ECAN™)
module is a serial interface, useful for communicating with
other ECAN modules or microcontroller devices. This
interface/protocol was designed to allow communications
within noisy environments. The dsPIC33FJ64GS606/
608/610 devices contain one ECAN module.
The ECAN module is a communication controller implementing the CAN 2.0 A/B protocol, as defined in the
BOSCH CAN specification. The module supports
CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B
Active versions of the protocol. The module implementation is a full CAN system. The CAN specification is not
covered within this data sheet. The reader can refer to
the BOSCH CAN specification for further details.
The module features are as follows:
• Implementation of the CAN Protocol, CAN 1.2,
CAN 2.0A and CAN 2.0B
• Standard and Extended Data Frames
• 0-8 Bytes Data Length
• Programmable Bit Rate, up to 1 Mbit/sec
• Automatic Response to Remote Transmission
Requests
• Up to 8 Transmit Buffers with Application-Specified
Prioritization and Abort Capability (each buffer can
contain up to 8 bytes of data)
• Up to 32 Receive Buffers (each buffer can contain
up to 8 bytes of data)
• Up to 16 Full (Standard/Extended Identifier)
Acceptance Filters
• Three Full Acceptance Filter Masks
• DeviceNet™ Addressing Support
 2009-2014 Microchip Technology Inc.
Frame Types
The CAN module transmits various types of frames
which include data messages, or remote transmission
requests initiated by the user, as other frames that are
automatically generated for control purposes. The
following frame types are supported:
• Standard Data Frame: A standard data frame is
generated by a node when the node wishes to
transmit data. It includes an 11-bit Standard Identifier
(SID), but not an 18-bit Extended Identifier (EID).
• Extended Data Frame: An extended data frame is
similar to a standard data frame, but includes an
Extended Identifier as well.
• Remote Frame: It is possible for a destination
node to request the data from the source. For this
purpose, the destination node sends a remote
frame with an identifier that matches the identifier
of the required data frame. The appropriate data
source node sends a data frame as a response to
this remote request.
• Error Frame: An error frame is generated by any
node that detects a bus error. An error frame consists of two fields: an error flag field and an error
delimiter field.
• Overload Frame: An overload frame can be generated by a node as a result of two conditions.
First, the node detects a dominant bit during interframe space which is an illegal condition. Second,
due to internal conditions, the node is not yet able
to start reception of the next message. A node
can generate a maximum of 2 sequential overload
frames to delay the start of the next message.
• Interframe Space: Interframe space separates a
proceeding frame (of whatever type) from a
following data or remote frame.
DS70000591F-page 285
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 21-1:
ECANx MODULE BLOCK DIAGRAM
RxF15 Filter
RxF14 Filter
RxF13 Filter
RxF12 Filter
DMA Controller
RxF11 Filter
RxF10 Filter
RxF9 Filter
RxF8 Filter
TRB7 TX/RX Buffer Control Register
RxF7 Filter
TRB6 TX/RX Buffer Control Register
RxF6 Filter
TRB5 TX/RX Buffer Control Register
RxF5 Filter
TRB4 TX/RX Buffer Control Register
RxF4 Filter
TRB3 TX/RX Buffer Control Register
RxF3 Filter
TRB2 TX/RX Buffer Control Register
RxF2 Filter
RxM2 Mask
TRB1 TX/RX Buffer Control Register
RxF1 Filter
RxM1 Mask
TRB0 TX/RX Buffer Control Register
RxF0 Filter
RxM0 Mask
Transmit Byte
Sequencer
Message Assembly
Buffer
Control
Configuration
Logic
CPU
Bus
ECAN Protocol
Engine
Interrupts
C1Tx
DS70000591F-page 286
C1Rx
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
21.3
Modes of Operation
The ECAN™ module can operate in one of several
operation modes selected by the user. These modes
include:
•
•
•
•
•
•
Initialization mode
Disable mode
Normal Operation mode
Listen Only mode
Listen All Messages mode
Loopback mode
Modes are requested by setting the REQOP<2:0> bits
(CxCTRL1<10:8>). Entry into a mode is Acknowledged
by monitoring the OPMODE<2:0> bits (CxCTRL1<7:5>).
The module does not change the mode and the
OPMODE bits until a change in mode is acceptable,
generally during bus Idle time, which is defined as at least
11 consecutive recessive bits.
21.3.1
INITIALIZATION MODE
In the Initialization mode, the module does not transmit
or receive. The error counters are cleared and the interrupt flags remain unchanged. The user application has
access to Configuration registers that are access
restricted in other modes. The module protects the user
from accidentally violating the CAN protocol through
programming errors. All registers which control the
configuration of the module cannot be modified while
the module is on-line. The ECAN module is not allowed
to enter the Configuration mode while a transmission is
taking place. The Configuration mode serves as a lock
to protect the following registers:
•
•
•
•
•
All Module Control Registers
Baud Rate and Interrupt Configuration Registers
Bus Timing Registers
Identifier Acceptance Filter Registers
Identifier Acceptance Mask Registers
21.3.2
DISABLE MODE
In Disable mode, the module does not transmit or
receive. The module has the ability to set the WAKIF bit
due to bus activity, however, any pending interrupts
remain and the error counters retains their value.
If the REQOP<2:0> bits (CxCTRL1<10:8>) = 001, the
module enters the Module Disable mode. If the module
is active, the module waits for 11 recessive bits on the
CAN bus, detects that condition as an Idle bus, then
accepts the module disable command. When the
OPMODE<2:0> bits (CxCTRL1<7:5>) = 001, that
indicates whether the module successfully went into
Module Disable mode. The I/O pins revert to normal
I/O function when the module is in the Module Disable
mode.
 2009-2014 Microchip Technology Inc.
The module can be programmed to apply a low-pass
filter function to the CxRX input line while the module or
the CPU is in Sleep mode. The WAKFIL bit
(CxCFG2<14>) enables or disables the filter.
Note:
21.3.3
Typically, if the ECAN module is allowed to
transmit in a particular mode of operation,
and a transmission is requested immediately after the ECAN module has been
placed in that mode of operation, the
module waits for 11 consecutive recessive
bits on the bus before starting transmission.
If the user switches to Disable mode within
this 11-bit period, then this transmission is
aborted and the corresponding TXABTmn
bit is set and the TXREQmn bit is cleared.
NORMAL OPERATION MODE
Normal Operation mode is selected when
REQOP<2:0> = 000. In this mode, the module is
activated and the I/O pins assume the CAN bus
functions. The module transmits and receives CAN bus
messages via the CxTX and CxRX pins.
21.3.4
LISTEN ONLY MODE
If the Listen Only mode is activated, the module on the
CAN bus is passive. The transmitter buffers revert to
the port I/O function. The receive pins remain inputs.
For the receiver, no error flags or Acknowledge signals
are sent. The error counters are deactivated in this
state. The Listen Only mode can be used for detecting
the baud rate on the CAN bus. To use this, it is necessary that there are at least two further nodes that
communicate with each other.
21.3.5
LISTEN ALL MESSAGES MODE
The module can be set to ignore all errors and receive
any message. The Listen All Messages mode is activated by setting REQOP<2:0> = 111. In this mode, the
data, which is in the message assembly buffer until the
time an error occurred, is copied in the receive buffer
and can be read via the CPU interface.
21.3.6
LOOPBACK MODE
If the Loopback mode is activated, the module connects the internal transmit signal to the internal receive
signal at the module boundary. The transmit and
receive pins revert to their port I/O function.
DS70000591F-page 287
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-1:
CxCTRL1: ECANx CONTROL REGISTER 1
U-0
U-0
R/W-0
R/W-0
r-0
R/W-1
R/W-0
R/W-0
—
—
CSIDL
ABAT
r
REQOP2
REQOP1
REQOP0
bit 15
bit 8
R-1
R-0
R-0
U-0
R/W-0
U-0
U-0
R/W-0
OPMODE2
OPMODE1
OPMODE0
—
CANCAP
—
—
WIN
bit 7
bit 0
Legend:
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13
CSIDL: ECANx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
ABAT: Abort All Pending Transmissions bit
1 = Signals all transmit buffers to abort transmission
0 = Module will clear this bit when all transmissions are aborted
bit 11
Reserved: Do not use
bit 10-8
REQOP<2:0>: Request Operation Mode bits
111 = Sets Listen All Messages mode
110 = Reserved
101 = Reserved
100 = Sets Configuration mode
011 = Sets Listen Only Mode
010 = Sets Loopback mode
001 = Sets Disable mode
000 = Sets Normal Operation mode
bit 7-5
OPMODE<2:0>: Operation Mode bits
111 = Module is in Listen All Messages mode
110 = Reserved
101 = Reserved
100 = Module is in Configuration mode
011 = Module is in Listen Only mode
010 = Module is in Loopback mode
001 = Module is in Disable mode
000 = Module is in Normal Operation mode
bit 4
Unimplemented: Read as ‘0’
bit 3
CANCAP: ECAN Message Receive Timer Capture Event Enable bit
1 = Enables input capture based on ECAN message receive
0 = Disables ECAN capture
bit 2-1
Unimplemented: Read as ‘0’
bit 0
WIN: SFR Map Window Select bit
1 = Uses filter window
0 = Uses buffer window
DS70000591F-page 288
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-2:
CxCTRL2: ECANx CONTROL REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
—
—
—
R-0
R-0
R-0
R-0
R-0
DNCNT<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-5
Unimplemented: Read as ‘0’
bit 4-0
DNCNT<4:0>: DeviceNet™ Filter Bit Number bits
10010-11111 = Invalid selection
10001 = Compares up to Data Byte 3, bit 6 with EID<17>
•
•
•
00001 = Compares up to Data Byte 1, bit 7 with EID<0>
00000 = Does not compare data bytes
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 289
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-3:
CxVEC: ECANx INTERRUPT CODE REGISTER
U-0
U-0
U-0
R-0
R-0
R-0
R-0
R-0
—
—
—
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
bit 15
bit 8
U-0
R-1
R-0
R-0
R-0
R-0
R-0
R-0
—
ICODE6
ICODE5
ICODE4
ICODE3
ICODE2
ICODE1
ICODE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
FILHIT<4:0>: Filter Hit Number bits
10000-11111 = Reserved
01111 = Filter 15
•
•
•
00001 = Filter 1
00000 = Filter 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
ICODE<6:0>: Interrupt Flag Code bits
1000101-1111111 = Reserved
1000100 = FIFO almost full interrupt
1000011 = Receiver overflow interrupt
1000010 = Wake-up interrupt
1000001 = Error interrupt
1000000 = No interrupt
•
•
•
0010000-0111111 = Reserved
0001111 = RB15 buffer interrupt
•
•
•
0001001 = RB9 buffer interrupt
0001000 = RB8 buffer interrupt
0000111 = TRB7 buffer interrupt
0000110 = TRB6 buffer interrupt
0000101 = TRB5 buffer interrupt
0000100 = TRB4 buffer interrupt
0000011 = TRB3 buffer interrupt
0000010 = TRB2 buffer interrupt
0000001 = TRB1 buffer interrupt
0000000 = TRB0 Buffer interrupt
DS70000591F-page 290
x = Bit is unknown
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-4:
CxFCTRL: ECANx FIFO CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
DMABS2
DMABS1
DMABS0
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
FSA4(1)
FSA3(1)
FSA2(1)
FSA1(1)
FSA0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
DMABS<2:0>: DMA Buffer Size bits
111 = Reserved
110 = 32 buffers in DMA RAM
101 = 24 buffers in DMA RAM
100 = 16 buffers in DMA RAM
011 = 12 buffers in DMA RAM
010 = 8 buffers in DMA RAM
001 = 6 buffers in DMA RAM
000 = 4 buffers in DMA RAM
bit 12-5
Unimplemented: Read as ‘0’
bit 4-0
FSA<4:0>: FIFO Area Starts with Buffer bits(1)
11111 = Reads Buffer RB31
11110 = Reads Buffer RB30
•
•
•
00001 = TX/RX Buffer TRB1
00000 = TX/RX Buffer TRB0
Note 1:
x = Bit is unknown
FSA<4:0> bits are used to specify the start of the FIFO within the buffer area.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 291
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-5:
CxFIFO: ECANx FIFO STATUS REGISTER
U-0
U-0
R-0
R-0
R-0
R-0
R-0
R-0
—
—
FBP5
FBP4
FBP3
FBP2
FBP1
FBP0
bit 15
bit 8
U-0
U-0
R-0
R-0
R-0
R-0
R-0
R-0
—
—
FNRB5
FNRB4
FNRB3
FNRB2
FNRB1
FNRB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
FBP<5:0>: FIFO Buffer Pointer bits
011111 = RB31 buffer
011110 = RB30 buffer
•
•
•
000001 = TRB1 buffer
000000 = TRB0 buffer
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
FNRB<5:0>: FIFO Next Read Buffer Pointer bits
011111 = RB31 buffer
011110 = RB30 buffer
•
•
•
000001 = TRB1 buffer
000000 = TRB0 buffer
DS70000591F-page 292
x = Bit is unknown
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-6:
U-0
—
bit 15
CxINTF: ECANx INTERRUPT FLAG REGISTER
U-0
R-0
R-0
R-0
R-0
R-0
—
TXBO
TXBP
RXBP
TXWAR
RXWAR
R-0
EWARN
bit 8
R/C-0
R/C-0
R/C-0
U-0
R/C-0
R/C-0
R/C-0
R/C-0
IVRIF
bit 7
WAKIF
ERRIF
—
FIFOIF
RBOVIF
RBIF
TBIF
bit 0
Legend:
C = Writable, but only ‘0’ can be written to clear the bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13
TXBO: Transmitter in Error State Bus Off bit
1 = Transmitter is in Bus Off state
0 = Transmitter is not in Bus Off state
TXBP: Transmitter in Error State Bus Passive bit
1 = Transmitter is in Bus Passive state
0 = Transmitter is not in Bus Passive state
bit 12
bit 11
bit 10
bit 9
bit 8
RXBP: Receiver in Error State Bus Passive bit
1 = Receiver is in Bus Passive state
0 = Receiver is not in Bus Passive state
TXWAR: Transmitter in Error State Warning bit
1 = Transmitter is in Error Warning state
0 = Transmitter is not in Error Warning state
RXWAR: Receiver in Error State Warning bit
1 = Receiver is in Error Warning state
0 = Receiver is not in Error Warning state
EWARN: Transmitter or Receiver in Error State Warning bit
1 = Transmitter or receiver is in Error Warning state
0 = Transmitter or receiver is not in Error Warning state
bit 7
IVRIF: Invalid Message Received Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6
WAKIF: Bus Wake-up Activity Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
ERRIF: Error Interrupt Flag bit (multiple sources in CxINTF<13:8> register bits)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5
bit 4
bit 3
Unimplemented: Read as ‘0’
FIFOIF: FIFO Almost Full Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2
RBOVIF: RX Buffer Overflow Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
 2009-2014 Microchip Technology Inc.
DS70000591F-page 293
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-6:
bit 1
bit 0
CxINTF: ECANx INTERRUPT FLAG REGISTER (CONTINUED)
RBIF: RX Buffer Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
TBIF: TX Buffer Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
DS70000591F-page 294
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-7:
CxINTE: ECANx INTERRUPT ENABLE REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
IVRIE
WAKIE
ERRIE
—
FIFOIE
RBOVIE
RBIE
TBIE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
Unimplemented: Read as ‘0’
bit 7
IVRIE: Invalid Message Received Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 6
WAKIE: Bus Wake-up Activity Interrupt Flag bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 5
ERRIE: Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 4
Unimplemented: Read as ‘0’
bit 3
FIFOIE: FIFO Almost Full Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 2
RBOVIE: RX Buffer Overflow Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1
RBIE: RX Buffer Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0
TBIE: TX Buffer Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 295
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-8:
CxEC: ECANx TRANSMIT/RECEIVE ERROR COUNT REGISTER
R-0
R-0
TERRCNT7
TERRCNT6
R-0
R-0
R-0
TERRCNT5 TERRCNT4 TERRCNT3
R-0
R-0
R-0
TERRCNT2
TERRCNT1
TERRCNT0
bit 15
bit 8
R-0
R-0
RERRCNT7
RERRCNT6
R-0
R-0
R-0
RERRCNT5 RERRCNT4 RERRCNT3
R-0
RERRCNT2
R-0
R-0
RERRCNT1 RERRCNT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
TERRCNT<7:0>: Transmit Error Count bits
bit 7-0
RERRCNT<7:0>: Receive Error Count bits
REGISTER 21-9:
x = Bit is unknown
CxCFG1: ECANx BAUD RATE CONFIGURATION REGISTER 1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
Unimplemented: Read as ‘0’
bit 7-6
SJW<1:0>: Synchronization Jump Width bits
11 = Length is 4 x TQ
10 = Length is 3 x TQ
01 = Length is 2 x TQ
00 = Length is 1 x TQ
bit 5-0
BRP<5:0>: Baud Rate Prescaler bits
11 1111 = TQ = 2 x 64 x 1/FCAN
•
•
•
00 0010 = TQ = 2 x 3 x 1/FCAN
00 0001 = TQ = 2 x 2 x 1/FCAN
00 0000 = TQ = 2 x 1 x 1/FCAN
DS70000591F-page 296
x = Bit is unknown
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-10: CxCFG2: ECANx BAUD RATE CONFIGURATION REGISTER 2
U-0
R/W-x
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
—
WAKFIL
—
—
—
SEG2PH2
SEG2PH1
SEG2PH0
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SEG2PHTS
SAM
SEG1PH2
SEG1PH1
SEG1PH0
PRSEG2
PRSEG1
PRSEG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14
WAKFIL: Select ECAN Bus Line Filter for Wake-up bit
1 = Uses ECAN bus line filter for wake-up
0 = ECAN bus line filter is not used for wake-up
bit 13-11
Unimplemented: Read as ‘0’
bit 10-8
SEG2PH<2:0>: Phase Segment 2 bits
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
bit 7
SEG2PHTS: Phase Segment 2 Time Select bit
1 = Freely programmable
0 = Maximum of SEG1PHx bits or Information Processing Time (IPT), whichever is greater
bit 6
SAM: Sample of the ECAN Bus Line bit
1 = Bus line is sampled three times at the sample point
0 = Bus line is sampled once at the sample point
bit 5-3
SEG1PH<2:0>: Phase Segment 1 bits
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
bit 2-0
PRSEG<2:0>: Propagation Time Segment bits
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
 2009-2014 Microchip Technology Inc.
DS70000591F-page 297
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-11: CxFEN1: ECANx ACCEPTANCE FILTER ENABLE REGISTER 1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
FLTEN15
FLTEN14
FLTEN13
FLTEN12
FLTEN11
FLTEN10
FLTEN9
FLTEN8
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
FLTEN7
FLTEN6
FLTEN5
FLTEN4
FLTEN3
FLTEN2
FLTEN1
FLTEN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
FLTEN<15:0>: Enable Filter n to Accept Messages bits
1 = Enables Filter n
0 = Disables Filter n
REGISTER 21-12: CxBUFPNT1: ECANx FILTER 0-3 BUFFER POINTER REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F3BP3
F3BP2
F3BP1
F3BP0
F2BP3
F2BP2
F2BP1
F2BP0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F1BP3
F1BP2
F1BP1
F1BP0
F0BP3
F0BP2
F0BP1
F0BP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
F3BP<3:0>: RX Buffer Mask for Filter 3 bits
1111 = Filter hits received in RX FIFO buffer
1110 = Filter hits received in RX Buffer 14
•
•
•
0001 = Filter hits received in RX Buffer 1
0000 = Filter hits received in RX Buffer 0
bit 11-8
F2BP<3:0>: RX Buffer Mask for Filter 2 bits (same values as bits<15:12>)
bit 7-4
F1BP<3:0>: RX Buffer Mask for Filter 1 bits (same values as bits<15:12>)
bit 3-0
F0BP<3:0>: RX Buffer Mask for Filter 0 bits (same values as bits<15:12>)
DS70000591F-page 298
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-13: CxBUFPNT2: ECANx FILTER 4-7 BUFFER POINTER REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F7BP3
F7BP2
F7BP1
F7BP0
F6BP3
F6BP2
F6BP1
F6BP0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F5BP3
F5BP2
F5BP1
F5BP0
F4BP3
F4BP2
F4BP1
F4BP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
F7BP<3:0>: RX Buffer Mask for Filter 7 bits
1111 = Filter hits received in RX FIFO buffer
1110 = Filter hits received in RX Buffer 14
•
•
•
0001 = Filter hits received in RX Buffer 1
0000 = Filter hits received in RX Buffer 0
bit 11-8
F6BP<3:0>: RX Buffer Mask for Filter 6 bits (same values as bits<15:12>)
bit 7-4
F5BP<3:0>: RX Buffer Mask for Filter 5 bits (same values as bits<15:12>)
bit 3-0
F4BP<3:0>: RX Buffer Mask for Filter 4 bits (same values as bits<15:12>)
 2009-2014 Microchip Technology Inc.
DS70000591F-page 299
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-14: CxBUFPNT3: ECANx FILTER 8-11 BUFFER POINTER REGISTER 3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F11BP3
F11BP2
F11BP1
F11BP0
F10BP3
F10BP2
F10BP1
F10BP0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F9BP3
F9BP2
F9BP1
F9BP0
F8BP3
F8BP2
F8BP1
F8BP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
F11BP<3:0>: RX Buffer Mask for Filter 11 bits
1111 = Filter hits received in RX FIFO buffer
1110 = Filter hits received in RX Buffer 14
•
•
•
0001 = Filter hits received in RX Buffer 1
0000 = Filter hits received in RX Buffer 0
bit 11-8
F10BP<3:0>: RX Buffer Mask for Filter 10 bits (same values as bits<15:12>)
bit 7-4
F9BP<3:0>: RX Buffer Mask for Filter 9 bits (same values as bits<15:12>)
bit 3-0
F8BP<3:0>: RX Buffer Mask for Filter 8 bits (same values as bits<15:12>)
DS70000591F-page 300
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-15: CxBUFPNT4: ECANx FILTER 12-15 BUFFER POINTER REGISTER 4
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F15BP3
F15BP2
F15BP1
F15BP0
F14BP3
F14BP2
F14BP1
F14BP0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F13BP3
F13BP2
F13BP1
F13BP0
F12BP3
F12BP2
F12BP1
F12BP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
F15BP<3:0>: RX Buffer Mask for Filter 15 bits
1111 = Filter hits received in RX FIFO buffer
1110 = Filter hits received in RX Buffer 14
•
•
•
0001 = Filter hits received in RX Buffer 1
0000 = Filter hits received in RX Buffer 0
bit 11-8
F14BP<3:0>: RX Buffer Mask for Filter 14 bits (same values as bits<15:12>)
bit 7-4
F13BP<3:0>: RX Buffer Mask for Filter 13 bits (same values as bits<15:12>)
bit 3-0
F12BP<3:0>: RX Buffer Mask for Filter 12 bits (same values as bits<15:12>)
 2009-2014 Microchip Technology Inc.
DS70000591F-page 301
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-16: CxRXFnSID: ECANx ACCEPTANCE FILTER n STANDARD IDENTIFIER
REGISTER (n = 0-15)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
bit 15
bit 8
R/W-x
R/W-x
R/W-x
U-0
R/W-x
U-0
R/W-x
R/W-x
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-5
SID<10:0>: Standard Identifier bits
1 = Message address bit, SIDx, must be ‘1’ to match filter
0 = Message address bit, SIDx, must be ‘0’ to match filter
bit 4
Unimplemented: Read as ‘0’
bit 3
EXIDE: Extended Identifier Enable bit
If MIDE = 1, then:
1 = Matches only messages with Extended Identifier addresses
0 = Matches only messages with Standard Identifier addresses
If MIDE = 0, then:
Ignores EXIDE bit.
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID<17:16>: Extended Identifier bits
1 = Message address bit, EIDx, must be ‘1’ to match filter
0 = Message address bit, EIDx, must be ‘0’ to match filter
DS70000591F-page 302
x = Bit is unknown
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-17: CxRXFnEID: ECANx ACCEPTANCE FILTER n EXTENDED IDENTIFIER
REGISTER (n = 0-15)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID<15:8>
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
EID<15:0>: Extended Identifier bits
1 = Message address bit, EIDx, must be ‘1’ to match filter
0 = Message address bit, EIDx, must be ‘0’ to match filter
REGISTER 21-18: CxFMSKSEL1: ECANx FILTER 7-0 MASK SELECTION REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F7MSK1
F7MSK0
F6MSK1
F6MSK0
F5MSK1
F5MSK0
F4MSK1
F4MSK0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F3MSK1
F3MSK0
F2MSK1
F2MSK0
F1MSK1
F1MSK0
F0MSK1
F0MSK1
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
F7MSK<1:0>: Mask Source for Filter 7 bits
11 = Reserved
10 = Acceptance Mask 2 registers contain mask
01 = Acceptance Mask 1 registers contain mask
00 = Acceptance Mask 0 registers contain mask
bit 13-12
F6MSK<1:0>: Mask Source for Filter 6 bits (same values as bits<15:14>)
bit 11-10
F5MSK<1:0>: Mask Source for Filter 5 bits (same values as bits<15:14>)
bit 9-8
F4MSK<1:0>: Mask Source for Filter 4 bits (same values as bits<15:14>)
bit 7-6
F3MSK<1:0>: Mask Source for Filter 3 bits (same values as bits<15:14>)
bit 5-4
F2MSK<1:0>: Mask Source for Filter 2 bits (same values as bits<15:14>)
bit 3-2
F1MSK<1:0>: Mask Source for Filter 1 bits (same values as bits<15:14>)
bit 1-0
F0MSK<1:0>: Mask Source for Filter 0 bits (same values as bits<15:14>)
 2009-2014 Microchip Technology Inc.
DS70000591F-page 303
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-19: CxFMSKSEL2: ECANx FILTER 15-8 MASK SELECTION REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F15MSK1
F15MSK0
F14MSK1
F14MSK0
F13MSK1
F13MSK0
F12MSK1
F12MSK0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F11MSK1
F11MSK0
F10MSK1
F10MSK0
F9MSK1
F9MSK0
F8MSK1
F8MSK0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
F15MSK<1:0>: Mask Source for Filter 15 bits
11 = Reserved
10 = Acceptance Mask 2 registers contain mask
01 = Acceptance Mask 1 registers contain mask
00 = Acceptance Mask 0 registers contain mask
bit 13-12
F14MSK<1:0>: Mask Source for Filter 14 bits (same values as bits<15:14>)
bit 11-10
F13MSK<1:0>: Mask Source for Filter 13 bits (same values as bits<15:14>)
bit 9-8
F12MSK<1:0>: Mask Source for Filter 12 bits (same values as bits<15:14>)
bit 7-6
F11MSK<1:0>: Mask Source for Filter 11 bits (same values as bits<15:14>)
bit 5-4
F10MSK<1:0>: Mask Source for Filter 10 bits (same values as bits<15:14>)
bit 3-2
F9MSK<1:0>: Mask Source for Filter 9 bits (same values as bits<15:14>)
bit 1-0
F8MSK<1:0>: Mask Source for Filter 8 bits (same values as bits<15:14>)
DS70000591F-page 304
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-20: CxRXMnSID: ECANx ACCEPTANCE FILTER MASK n STANDARD IDENTIFIER
REGISTER (n = 0-2)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
bit 15
bit 8
R/W-x
R/W-x
R/W-x
U-0
R/W-x
U-0
R/W-x
R/W-x
SID2
SID1
SID0
—
MIDE
—
EID17
EID16
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
SID<10:0>: Standard Identifier bits
1 = Includes bit, SIDx, in filter comparison
0 = SIDx bit is don’t care in filter comparison
bit 4
Unimplemented: Read as ‘0’
bit 3
MIDE: Identifier Receive Mode bit
1 = Matches only message types (standard or extended address) that correspond to EXIDE bit in filter
0 = Matches either standard or extended address message if filters match
(i.e., if (Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID))
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID<17:16>: Extended Identifier bits
1 = Includes bit, EIDx, in filter comparison
0 = EIDx bit is don’t care in filter comparison
REGISTER 21-21: CxRXMnEID: ECANx ACCEPTANCE FILTER MASK n EXTENDED IDENTIFIER
REGISTER (n = 0-2)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
EID<15:0>: Extended Identifier bits
1 = Includes bit, EIDx, in filter comparison
0 = EIDx bit is don’t care in filter comparison
 2009-2014 Microchip Technology Inc.
DS70000591F-page 305
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-22: CxRXFUL1: ECANx RECEIVE BUFFER FULL REGISTER 1
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL15
RXFUL14
RXFUL13
RXFUL12
RXFUL11
RXFUL10
RXFUL9
RXFUL8
bit 15
bit 8
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL7
RXFUL6
RXFUL5
RXFUL4
RXFUL3
RXFUL2
RXFUL1
RXFUL0
bit 7
bit 0
Legend:
C = Writeable, but only ‘0’ can be written to clear the bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
RXFUL<15:0>: Receive Buffer n Full bits
1 = Buffer is full (set by module)
0 = Buffer is empty
REGISTER 21-23: CxRXFUL2: ECANx RECEIVE BUFFER FULL REGISTER 2
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL31
RXFUL30
RXFUL29
RXFUL28
RXFUL27
RXFUL26
RXFUL25
RXFUL24
bit 15
bit 8
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL23
RXFUL22
RXFUL21
RXFUL20
RXFUL19
RXFUL18
RXFUL17
RXFUL16
bit 7
bit 0
Legend:
C = Writeable, but only ‘0’ can be written to clear the bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
RXFUL<31:16>: Receive Buffer n Full bits
1 = Buffer is full (set by module)
0 = Buffer is empty
DS70000591F-page 306
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-24: CxRXOVF1: ECANx RECEIVE BUFFER OVERFLOW REGISTER 1
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF<15:8>
bit 15
bit 8
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF<7:0>
bit 7
bit 0
Legend:
C = Writeable, but only ‘0’ can be written to clear the bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
RXOVF<15:0>: Receive Buffer n Overflow bits
1 = Module attempted to write to a full buffer (set by module)
0 = No overflow condition
REGISTER 21-25: CxRXOVF2: ECANx RECEIVE BUFFER OVERFLOW REGISTER 2
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF<31:24>
bit 15
bit 8
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF<23:16>
bit 7
bit 0
Legend:
C = Writeable, but only ‘0’ can be written to clear the bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
RXOVF<31:16>: Receive Buffer n Overflow bits
1 = Module attempted to write to a full buffer (set by module)
0 = No overflow condition
 2009-2014 Microchip Technology Inc.
DS70000591F-page 307
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-26: CxTRmnCON: ECANx TX/RX BUFFER mn CONTROL REGISTER
(m = 0, 2, 4, 6; n = 1, 3, 5, 7)
R/W-0
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TXENn
TXABTn
TXLARBn
TXERRn
TXREQn
RTRENn
TXnPRI1
TXnPRI0
bit 15
bit 8
R/W-0
R-0
TXENm
R-0
(1)
TXABTm
TXLARBm
R-0
(1)
TXERRm
(1)
R/W-0
R/W-0
R/W-0
R/W-0
TXREQm
RTRENm
TXmPRI1
TXmPRI0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
See Definition for bits<7:0>, Controls Buffer n
bit 7
TXENm: TX/RX Buffer Selection bit
1 = Buffer TRBn is a transmit buffer
0 = Buffer TRBn is a receive buffer
bit 6
TXABTm: Message Aborted bit(1)
1 = Message was aborted
0 = Message completed transmission successfully
bit 5
TXLARBm: Message Lost Arbitration bit(1)
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
bit 4
TXERRm: Error Detected During Transmission bit(1)
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
bit 3
TXREQm: Message Send request bit
1 = Requests that a message be sent; the bit automatically clears when the message is successfully sent
0 = Clears the bit to ‘0’; while set, requests a message abort
bit 2
RTRENm: Auto-Remote Transmit Enable bit
1 = When a remote transmit is received, TXREQm will be set
0 = When a remote transmit is received, TXREQm will be unaffected
bit 1-0
TXmPRI<1:0>: Message Transmission Priority bits
11 = Highest message priority
10 = High intermediate message priority
01 = Low intermediate message priority
00 = Lowest message priority
Note 1:
Note:
This bit is cleared when TXREQm is set.
The buffers, SID, EID, DLC, Data Field, and Receive Status registers are located in DMA RAM.
DS70000591F-page 308
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
21.4
ECANx Message Buffers
ECANx message buffers are part of DMA RAM memory.
They are not ECAN Special Function Registers. The
user application must directly write into the DMA RAM
area that is configured for ECANx message buffers. The
location and size of the buffer area is defined by the user
application.
BUFFER 21-1:
ECANx MESSAGE BUFFER WORD 0
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
SID10
SID9
SID8
SID7
SID6
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SID5
SID4
SID3
SID2
SID1
SID0
SRR
IDE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
Unimplemented: Read as ‘0’
bit 12-2
SID<10:0>: Standard Identifier bits
bit 1
SRR: Substitute Remote Request bit
1 = Message will request remote transmission
0 = Normal message
bit 0
IDE: Extended Identifier bit
1 = Message will transmit the Extended Identifier
0 = Message will transmit the Standard Identifier
BUFFER 21-2:
x = Bit is unknown
ECANx MESSAGE BUFFER WORD 1
U-0
U-0
U-0
U-0
—
—
—
—
R/W-x
R/W-x
R/W-x
R/W-x
EID<17:14>
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID<13:6>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
Unimplemented: Read as ‘0’
bit 11-0
EID<17:6>: Extended Identifier bits
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 309
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
(
BUFFER 21-3:
ECANx MESSAGE BUFFER WORD 2
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID5
EID4
EID3
EID2
EID1
EID0
RTR
RB1
bit 15
bit 8
U-x
U-x
U-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
RB0
DLC3
DLC2
DLC1
DLC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-10
EID<5:0>: Extended Identifier bits
bit 9
RTR: Remote Transmission Request bit
1 = Message will request remote transmission
0 = Normal message
bit 8
RB1: Reserved Bit 1
User must set this bit to ‘0’ per ECAN™ protocol.
bit 7-5
Unimplemented: Read as ‘0’
bit 4
RB0: Reserved Bit 0
User must set this bit to ‘0’ per ECAN protocol.
bit 3-0
DLC<3:0>: Data Length Code bits
BUFFER 21-4:
R/W-x
x = Bit is unknown
ECANx MESSAGE BUFFER WORD 3
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 1
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
Byte 1<15:8>: ECANx Message Byte 1
bit 7-0
Byte 0<7:0>: ECANx Message Byte 0
DS70000591F-page 310
x = Bit is unknown
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
BUFFER 21-5:
R/W-x
ECANx MESSAGE BUFFER WORD 4
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 3
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 2
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
Byte 3<15:8>: ECANx Message Byte 3
bit 7-0
Byte 2<7:0>: ECANx Message Byte 2
BUFFER 21-6:
R/W-x
x = Bit is unknown
ECANx MESSAGE BUFFER WORD 5
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 5
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
Byte 5<15:8>: ECANx Message Byte 5
bit 7-0
Byte 4<7:0>: ECANx Message Byte 4
 2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000591F-page 311
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
BUFFER 21-7:
R/W-x
ECANx MESSAGE BUFFER WORD 6
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 7
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 6
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
Byte 7<15:8>: ECANx Message Byte 7
bit 7-0
Byte 6<7:0>: ECANx Message Byte 6
BUFFER 21-8:
U-0
ECANx MESSAGE BUFFER WORD 7
U-0
—
x = Bit is unknown
—
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
FILHIT<4:0>(1)
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
FILHIT<4:0>: Filter Hit Code bits(1)
Encodes number of filter that resulted in writing this buffer.
bit 7-0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
Only written by module for receive buffers, unused for transmit buffers.
DS70000591F-page 312
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
22.0
HIGH-SPEED, 10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to “High-Speed
10-Bit ADC” (DS70000321) in the
“dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
The information in this data sheet
supersedes the information in the FRM.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices provide
high-speed successive approximation Analog-to-Digital
conversions to support applications, such as AC/DC and
DC/DC power converters.
22.1
Features Overview
The ADC module incorporates the following features:
• 10-Bit Resolution
• Unipolar Inputs
• Up to Two Successive Approximation Registers
(SARs)
• Up to 24 External Input Channels
• Two Internal Analog Inputs
• Dedicated Result Register for each Analog Input
• ±1 LSB Accuracy at 3.3V
• Single Supply Operation
• 4 Msps Conversion Rate at 3.3V (devices with
two SARs)
• 2 Msps Conversion Rate at 3.3V (devices with
one SAR)
• Low-Power CMOS Technology
 2009-2014 Microchip Technology Inc.
22.2
Module Description
This ADC module is designed for applications that
require low latency between the request for conversion
and the resultant output data. Typical applications
include:
• AC/DC Power Supplies
• DC/DC Converters
• Power Factor Correction (PFC)
This ADC works with the High-Speed PWM module in
power control applications that require high-frequency
control loops. This module can Sample-and-Convert
two analog inputs in a 0.5 microsecond when two SARs
are used. This small conversion delay reduces the
“phase lag” between measurement and control system
response.
Up to five inputs may be sampled at a time (four inputs
from the dedicated Sample-and-Hold circuits and one
from the shared Sample-and-Hold circuit). If multiple
inputs request conversion, the ADC will convert them in
a sequential manner, starting with the lowest order
input.
This ADC design provides each pair of analog inputs
(AN1, AN0), (AN3, AN2),..., the ability to specify its own
trigger source out of a maximum of sixteen different
trigger sources. This capability allows this ADC to
Sample-and-Convert analog inputs that are associated
with PWM generators operating on independent time
bases.
The user application typically requires synchronization
between analog data sampling and PWM output to the
application circuit. The very high-speed operation of
this ADC module allows “data on demand”.
In addition, several hardware features have been
added to the peripheral interface to improve real-time
performance in a typical DSP-based application.
•
•
•
•
Result Alignment Options
Automated Sampling
External Conversion Start Control
Two Internal Inputs to Monitor the INTREF and
EXTREF Input Signals
Block diagrams of the ADC module for the family
devices are shown in Figure 22-1 through Figure 22-4.
DS70000591F-page 313
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
22.3
Module Functionality
The High-Speed, 10-Bit ADC is designed to support
power conversion applications when used with the
High-Speed PWM module. The ADC may have one or
two SAR modules, depending on the device variant. If
two SARs are present on a device, two conversions
can be processed at a time, yielding 4 Msps conversion
rate. If only one SAR is present on a device, only one
conversion can be processed at a time, yielding 2 Msps
conversion rate. The High-Speed, 10-Bit ADC produces
two 10-bit conversion results in a 0.5 microsecond.
The ADC module supports up to 24 external analog
inputs and two internal analog inputs. To monitor
reference voltage, two internal inputs, AN24 and AN25,
are connected to EXTREF and INTREF, respectively.
The analog reference voltage is defined as the device
supply voltage (AVDD/AVSS).
The ADC module uses the following control and status
registers:
•
•
•
•
•
•
•
•
•
•
•
•
ADCON: ADC Control Register
ADSTAT: ADC Status Register
ADBASE: ADC Base Register(1,2)
ADPCFG: ADC Port Configuration Register
ADPCFG2: ADC Port Configuration Register 2
ADCPC0: ADC Convert Pair Control Register 0
ADCPC1: ADC Convert Pair Control Register 1
ADCPC2: ADC Convert Pair Control Register 2
ADCPC3: ADC Convert Pair Control Register 3
ADCPC4: ADC Convert Pair Control Register 4
ADCPC5: ADC Convert Pair Control Register 5
ADCPC6: ADC Convert Pair Control Register 6(2)
The ADCON register controls the operation of the
ADC module. The ADSTAT register displays the
status of the conversion processes. The ADPCFG
registers configure the port pins as analog inputs or
as digital I/O. The ADCPCx registers control the
triggering of the ADC conversions. See Register 22-1
through Register 22-12 for detailed bit configurations.
Note:
DS70000591F-page 314
A unique feature of the ADC module is its
ability to sample inputs in an asynchronous
manner.
Individual
Sample-and-Hold
circuits can be triggered independently of
each other.
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 22-1:
ADC BLOCK DIAGRAM FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406
DEVICES WITH ONE SAR
Even Numbered Inputs with Dedicated
Sample-and-Hold (S&H) Circuits
AN0
AN4
Sixteen
16-Bit
Registers
Bus Interface
SAR
Core
Data
Format
AN2
AN6
AN1
Shared Sample-and-Hold
AN3
AN5
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
 2009-2014 Microchip Technology Inc.
DS70000591F-page 315
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 22-2:
ADC BLOCK DIAGRAM FOR dsPIC33FJ32GS606 AND dsPIC33FJ64GS606
DEVICES WITH TWO SARs
Even Numbered Inputs with Dedicated
Sample-and-Hold (S&H) Circuits
AN0
SAR
Core
Data
Format
Nine
16-Bit
Registers
SAR
Core
Data
Format
AN2
Nine
16-Bit
Registers
AN4
AN6
Even Numbered Inputs
with Shared S&H
Bus Interface
AN8
AN10
AN12
AN14
AN24(1)
(EXTREF)
Odd Numbered Inputs
with Shared S&H
AN1
AN3
AN5
AN7
AN9
AN11
AN13
AN15
AN25(2)
(INTREF)
Note 1:
2:
AN24 (EXTREF) is an internal analog input. To measure the voltage at AN24 (EXTREF), an analog comparator must be enabled
and EXTREF must be selected as the comparator reference.
AN25 (INTREF) is an internal analog input and is not available on a pin.
DS70000591F-page 316
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 22-3:
ADC BLOCK DIAGRAM FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608
DEVICES WITH TWO SARs
Even Numbered Inputs with Dedicated
Sample-and-Hold (S&H) Circuits
AN0
SAR
Core
Data
Format
Ten
16-Bit
Registers
SAR
Core
Data
Format
AN2
Ten
16-Bit
Registers
AN4
AN6
Even Numbered Inputs
with Shared S&H
Bus Interface
AN8
AN10
AN12
AN14
AN16
AN24(1)
(EXTREF)
Odd Numbered Inputs
with Shared S&H
AN1
AN3
AN5
AN7
AN9
AN11
AN13
AN15
AN17
AN25(2)
(INTREF)
Note 1:
2:
AN24 (EXTREF) is an internal analog input. To measure the voltage at AN24 (EXTREF), an analog comparator must be
enabled and EXTREF must be selected as the comparator reference.
AN25 (INTREF) is an internal analog input and is not available on a pin.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 317
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 22-4:
ADC BLOCK DIAGRAM FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610
DEVICES WITH TWO SARs
Even Numbered Inputs with Dedicated
Sample-and-Hold (S&H) Circuits
AN0
SAR
Core
Data
Format
Thirteen
16-Bit
Registers
SAR
Core
Data
Format
AN2
Thirteen
16-Bit
Registers
AN4
AN6
Even Numbered Inputs
with Shared S&H
Bus Interface
AN8
AN10
AN12
AN14
AN16
AN18
AN20
AN22
AN24(1)
(EXTREF)
AN1
Odd Numbered Inputs
with Shared S&H
AN3
AN5
AN7
AN9
AN11
AN13
AN15
AN17
AN19
AN21
AN23
AN25(2)
(INTREF)
Note 1:
2:
AN24 (EXTREF) is an internal analog input. To measure the voltage at AN24 (EXTREF), an analog comparator must
be enabled and EXTREF must be selected as the comparator reference.
AN25 (INTREF) is an internal analog input and is not available on a pin.
DS70000591F-page 318
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 22-1:
R/W-0
ADCON: ADC CONTROL REGISTER
U-0
—
ADON
R/W-0
ADSIDL
R/W-0
(1)
SLOWCLK
U-0
R/W-0
U-0
R/W-0
—
GSWTRG
—
FORM(1)
bit 15
bit 8
R/W-0
(1)
EIE
R/W-0
R/W-0
R/W-0
ORDER(1,2)
SEQSAMP(1,2)
ASYNCSAMP(1)
U-0
R/W-0
R/W-1
R/W-1
—
ADCS2(1)
ADCS1(1)
ADCS0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ADON: ADC Module Operating Mode bit
1 = ADC module is operating
0 = ADC module is off
bit 14
Unimplemented: Read as ‘0’
bit 13
ADSIDL: ADC Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
SLOWCLK: Enable the Slow Clock Divider bit(1)
1 = ADC is clocked by the auxiliary PLL (ACLK)
0 = ADC is clock by the primary PLL (FVCO)
bit 11
Unimplemented: Read as ‘0’
bit 10
GSWTRG: Global Software Trigger bit
When this bit is set by the user, it will trigger conversions if selected by the TRGSRCx<4:0> bits in the
ADCPCx registers. This bit must be cleared by the user prior to initiating another global trigger (i.e., this
bit is not auto-clearing).
bit 9
Unimplemented: Read as ‘0’
bit 8
FORM: Data Output Format bit(1)
1 = Fractional (DOUT = dddd dddd dd00 0000)
0 = Integer (DOUT = 0000 00dd dddd dddd)
bit 7
EIE: Early Interrupt Enable bit(1)
1 = Interrupt is generated after first conversion is completed
0 = Interrupt is generated after second conversion is completed
bit 6
ORDER: Conversion Order bit(1,2)
1 = Odd numbered analog input is converted first, followed by conversion of even numbered input
0 = Even numbered analog input is converted first, followed by conversion of odd numbered input
bit 5
SEQSAMP: Sequential S&H Sampling Enable bit(1,2)
1 = Shared Sample-and-Hold (S&H) circuit is sampled at the start of the second conversion if
ORDER = 0. If ORDER = 1, then the shared S&H is sampled at the start of the first conversion.
0 = Shared S&H is sampled at the same time the dedicated S&H is sampled if the shared S&H is not currently busy with an existing conversion process. If the shared S&H is busy at the time the dedicated
S&H is sampled, then the shared S&H will sample at the start of the new conversion cycle.
Note 1:
2:
This control bit can only be changed while the ADC is disabled (ADON = 0).
This control bit is only active on devices that have one SAR.
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REGISTER 22-1:
ADCON: ADC CONTROL REGISTER (CONTINUED)
bit 4
ASYNCSAMP: Asynchronous Dedicated S&H Sampling Enable bit(1)
1 = The dedicated S&H is constantly sampling and then terminates sampling as soon as the trigger
pulse is detected
0 = The dedicated S&H starts sampling when the trigger event is detected and completes the sampling
process in two ADC clock cycles
bit 3
Unimplemented: Read as ‘0’
bit 2-0
ADCS<2:0>: Analog-to-Digital Conversion Clock Divider Select bits(1)
111 = FADC/8
110 = FADC/7
101 = FADC/6
100 = FADC/5
011 = FADC/4 (default)
010 = FADC/3
001 = FADC/2
000 = FADC/1
Note 1:
2:
This control bit can only be changed while the ADC is disabled (ADON = 0).
This control bit is only active on devices that have one SAR.
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REGISTER 22-2:
U-0
ADSTAT: ADC STATUS REGISTER
U-0
—
U-0
—
—
R/C-0, HS
R/C-0, HS
R/C-0, HS
R/C-0, HS
R/C-0, HS
(1)
(1)
(1)
(1)
P8RDY(1)
P12RDY
P11RDY
P10RDY
P9RDY
bit 15
bit 8
R/C-0, HS
R/C-0, HS
R/C-0, HS
R/C-0, HS
R/C-0, HS
R/C-0, HS
R/C-0, HS
R/C-0, HS
(1)
(1)
(1)
(1)
(1)
(1)
(1)
P0RDY(1)
P7RDY
P6RDY
P5RDY
P4RDY
P3RDY
P2RDY
P1RDY
bit 7
bit 0
Legend:
C = Clearable bit
HS - Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 6
P12RDY: Conversion Data for Pair 12 Ready bit(1)
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 5
P11RDY: Conversion Data for Pair 11 Ready bit(1)
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 4
P10RDY: Conversion Data for Pair 10 Ready bit(1)
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 3
P9RDY: Conversion Data for Pair 9 Ready bit(1)
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 2
P8RDY: Conversion Data for Pair 8 Ready bit(1)
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 1
P7RDY: Conversion Data for Pair 7 Ready bit(1)
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 6
P6RDY: Conversion Data for Pair 6 Ready bit(1)
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 5
P5RDY: Conversion Data for Pair 5 Ready bit(1)
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 4
P4RDY: Conversion Data for Pair 4 Ready bit(1)
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 3
P3RDY: Conversion Data for Pair 3 Ready bit(1)
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 2
P2RDY: Conversion Data for Pair 2 Ready bit(1)
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 1
P1RDY: Conversion Data for Pair 1 Ready bit(1)
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 0
P0RDY: Conversion Data for Pair 0 Ready bit(1)
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
Note 1:
Not all PxRDY bits are available on all devices. See Figure 22-1, Figure 22-2, Figure 22-3 and Figure 22-4
for the available analog inputs.
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ADBASE: ADC BASE REGISTER(1,2)
REGISTER 22-3:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADBASE<15:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
ADBASE<7:1>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-1
ADBASE<15:1>: ADC Base Address bits
This register contains the base address of the user’s ADC Interrupt Service Routine jump table. This
register, when read, contains the sum of the ADBASE register contents and the encoded value of the
PxRDY status bits.
The encoder logic provides the bit number of the highest priority PxRDY bits where P0RDY is the
highest priority and P6RDY is the lowest priority.
bit 0
Unimplemented: Read as ‘0’
Note 1:
2:
The encoding results are shifted left two bits so bits 1-0 of the result are always zero.
As an alternative to using the ADBASE register, the ADCP0-ADCP12 ADC pair conversion complete
interrupts can be used to invoke Analog-to-Digital conversion completion routines for individual ADC input
pairs.
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REGISTER 22-4:
R/W-0
ADPCFG: ADC PORT CONFIGURATION REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
PCFG<15:8>
R/W-0
R/W-0
R/W-0
(1)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG<7:0>
R/W-0
R/W-0
R/W-0
(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
x = Bit is unknown
PCFG<15:0>: ADC Port Configuration Control bits(1)
1 = Port pin in Digital mode, port read input is enabled; Analog-to-Digital input multiplexer is
connected to AVSS
0 = Port pin in Analog mode, port read input is disabled; Analog-to-Digital samples the pin voltage
Not all PCFGx bits are available on all devices. See Figure 22-1, Figure 22-2, Figure 22-3 and Figure 22-4
for the available analog inputs (PCFGx = ANx, where x = 0-15).
REGISTER 22-5:
ADPCFG2: ADC PORT CONFIGURATION REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG<23:16>
R/W-0
R/W-0
R/W-0
(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented: Read as ‘0’
bit 7-0
PCFG<23:16>: ADC Port Configuration Control bits(1)
1 = Port pin in Digital mode, port read input is enabled; Analog-to-Digital input multiplexer is
connected to AVSS
0 = Port pin in Analog mode, port read input is disabled; Analog-to-Digital samples the pin voltage
Note 1:
Not all PCFGx bits are available on all devices. See Figure 22-1, Figure 22-2, Figure 22-3 and Figure 22-4
for the available analog inputs (PCFGx = ANx, where x can be 0 through 15).
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REGISTER 22-6:
ADCPC0: ADC CONVERT PAIR CONTROL REGISTER 0
R/W-0
R/W-0
R/W-0
IRQEN1
PEND1
SWTRG1
R/W-0
R/W-0
TRGSRC14 TRGSRC13
R/W-0
R/W-0
R/W-0
TRGSRC12
TRGSRC11
TRGSRC10
bit 15
bit 8
R/W-0
R/W-0
R/W-0
IRQEN0
PEND0
SWTRG0
R/W-0
R/W-0
TRGSRC04 TRGSRC03
R/W-0
R/W-0
R/W-0
TRGSRC02
TRGSRC01
TRGSRC00
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
IRQEN1: Interrupt Request Enable 1 bit
1 = Enables IRQ generation when requested conversion of Channels AN3 and AN2 is completed
0 = IRQ is not generated
bit 14
PEND1: Pending Conversion Status 1 bit
1 = Conversion of Channels AN3 and AN2 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 13
SWTRG1: Software Trigger 1 bit
1 = Starts conversion of AN3 and AN2 (if selected by the TRGSRCx<4:0> bits)(1)
This bit is automatically cleared by hardware when the PEND1 bit is set.
0 = Conversion has not started
Note 1:
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
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REGISTER 22-6:
ADCPC0: ADC CONVERT PAIR CONTROL REGISTER 0 (CONTINUED)
bit 12-8
TRGSRC1<4:0>: Trigger 1 Source Selection bits
Selects trigger source for conversion of Analog Channels AN3 and AN2.
11111 = Timer2 period match
11110 = PWM Generator 8 current-limit ADC trigger
11101 = PWM Generator 7 current-limit ADC trigger
11100 = PWM Generator 6 current-limit ADC trigger
11011 = PWM Generator 5 current-limit ADC trigger
11010 = PWM Generator 4 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = PWM Generator 9 secondary trigger is selected
10101 = PWM Generator 8 secondary trigger is selected
10100 = PWM Generator 7 secondary trigger is selected
10011 = PWM Generator 6 secondary trigger is selected
10010 = PWM Generator 5 secondary trigger is selected
10001 = PWM Generator 4 secondary trigger is selected
10000 = PWM Generator 3 secondary trigger is selected
01111 = PWM Generator 2 secondary trigger is selected
01110 = PWM Generator 1 secondary trigger is selected
01101 = PWM secondary Special Event Trigger is selected
01100 = Timer1 period match
01011 = PWM Generator 8 primary trigger is selected
01010 = PWM Generator 7 primary trigger is selected
01001 = PWM Generator 6 primary trigger is selected
01000 = PWM Generator 5 primary trigger is selected
00111 = PWM Generator 4 primary trigger selected
00110 = PWM Generator 3 primary trigger is selected
00101 = PWM Generator 2 primary trigger is selected
00100 = PWM Generator 1 primary trigger is selected
00011 = PWM Special Event Trigger selected
00010 = Global software trigger is selected
00001 = Individual software trigger is selected
00000 = No conversion is enabled
bit 7
IRQEN0: Interrupt Request Enable 0 bit
1 = Enables IRQ generation when requested conversion of Channels AN1 and AN0 is completed
0 = IRQ is not generated
bit 6
PEND0: Pending Conversion Status 0 bit
1 = Conversion of Channels AN1 and AN0 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 5
SWTRG0: Software Trigger 0 bit
1 = Starts conversion of AN1 and AN0 (if selected by the TRGSRCx<4:0> bits)(1)
This bit is automatically cleared by hardware when the PEND0 bit is set.
0 = Conversion has not started.
Note 1:
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
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REGISTER 22-6:
bit 4-0
Note 1:
ADCPC0: ADC CONVERT PAIR CONTROL REGISTER 0 (CONTINUED)
TRGSRC0<4:0>: Trigger 0 Source Selection bits
Selects trigger source for conversion of Analog Channels AN1 and AN0.
11111 = Timer2 period match
11110 = PWM Generator 8 current-limit ADC trigger
11101 = PWM Generator 7 current-limit ADC trigger
11100 = PWM Generator 6 current-limit ADC trigger
11011 = PWM Generator 5 current-limit ADC trigger
11010 = PWM Generator 4 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = PWM Generator 9 secondary trigger is selected
10101 = PWM Generator 8 secondary trigger is selected
10100 = PWM Generator 7 secondary trigger is selected
10011 = PWM Generator 6 secondary trigger is selected
10010 = PWM Generator 5 secondary trigger is selected
10001 = PWM Generator 4 secondary trigger is selected
10000 = PWM Generator 3 secondary trigger is selected
01111 = PWM Generator 2 secondary trigger is selected
01110 = PWM Generator 1 secondary trigger is selected
01101 = PWM secondary Special Event Trigger is selected
01100 = Timer1 period match
01011 = PWM Generator 8 primary trigger is selected
01010 = PWM Generator 7 primary trigger is selected
01001 = PWM Generator 6 primary trigger is selected
01000 = PWM Generator 5 primary trigger is selected
00111 = PWM Generator 4 primary trigger is selected
00110 = PWM Generator 3 primary trigger is selected
00101 = PWM Generator 2 primary trigger is selected
00100 = PWM Generator 1 primary trigger is selected
00011 = PWM Special Event Trigger is selected
00010 = Global software trigger is selected
00001 = Individual software trigger is selected
00000 = No conversion is enabled
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
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REGISTER 22-7:
ADCPC1: ADC CONVERT PAIR CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IRQEN3
PEND3
SWTRG3
TRGSRC34
TRGSRC33
TRGSRC32
TRGSRC31
TRGSRC30
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IRQEN2
PEND2
SWTRG2
TRGSRC24
TRGSRC23
TRGSRC22
TRGSRC21
TRGSRC20
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
IRQEN3: Interrupt Request Enable 3 bit
1 = Enables IRQ generation when requested conversion of Channels AN7 and AN6 is completed
0 = IRQ is not generated
bit 14
PEND3: Pending Conversion Status 3 bit
1 = Conversion of Channels AN7 and AN6 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 13
SWTRG3: Software Trigger 3 bit
1 = Starts conversion of AN7 and AN6 (if selected by the TRGSRCx<4:0> bits)(1)
This bit is automatically cleared by hardware when the PEND3 bit is set.
0 = Conversion has not started
Note 1:
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
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REGISTER 22-7:
ADCPC1: ADC CONVERT PAIR CONTROL REGISTER 1 (CONTINUED)
bit 12-8
TRGSRC3<4:0>: Trigger 3 Source Selection bits
Selects trigger source for conversion of analog channels AN7 and AN6.
11111 = Timer2 period match
11110 = PWM Generator 8 current-limit ADC trigger
11101 = PWM Generator 7 current-limit ADC trigger
11100 = PWM Generator 6 current-limit ADC trigger
11011 = PWM Generator 5 current-limit ADC trigger
11010 = PWM Generator 4 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = PWM Generator 9 secondary trigger is selected
10101 = PWM Generator 8 secondary trigger is selected
10100 = PWM Generator 7 secondary trigger is selected
10011 = PWM Generator 6 secondary trigger is selected
10010 = PWM Generator 5 secondary trigger is selected
10001 = PWM Generator 4 secondary trigger is selected
10000 = PWM Generator 3 secondary trigger is selected
01111 = PWM Generator 2 secondary trigger is selected
01110 = PWM Generator 1 secondary trigger is selected
01101 = PWM secondary Special Event Trigger is selected
01100 = Timer1 period match
01011 = PWM Generator 8 primary trigger is selected
01010 = PWM Generator 7 primary trigger is selected
01001 = PWM Generator 6 primary trigger is selected
01000 = PWM Generator 5 primary trigger is selected
00111 = PWM Generator 4 primary trigger is selected
00110 = PWM Generator 3 primary trigger is selected
00101 = PWM Generator 2 primary trigger is selected
00100 = PWM Generator 1 primary trigger is selected
00011 = PWM Special Event Trigger is selected
00010 = Global software trigger is selected
00001 = Individual software trigger is selected
00000 = No conversion is enabled
bit 7
IRQEN2: Interrupt Request Enable 2 bit
1 = Enables IRQ generation when requested conversion of Channels AN5 and AN4 is completed
0 = IRQ is not generated
bit 6
PEND2: Pending Conversion Status 2 bit
1 = Conversion of Channels AN5 and AN4 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 5
SWTRG2: Software Trigger 2 bit
1 = Starts conversion of AN5 and AN4 (if selected by the TRGSRCx<4:0> bits)(1)
This bit is automatically cleared by hardware when the PEND2 bit is set.
0 = Conversion has not started
Note 1:
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
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REGISTER 22-7:
bit 4-0
Note 1:
ADCPC1: ADC CONVERT PAIR CONTROL REGISTER 1 (CONTINUED)
TRGSRC2<4:0>: Trigger 2 Source Selection bits
Selects trigger source for conversion of Analog Channels AN5 and AN4.
11111 = Timer2 period match
11110 = PWM Generator 8 current-limit ADC trigger
11101 = PWM Generator 7 current-limit ADC trigger
11100 = PWM Generator 6 current-limit ADC trigger
11011 = PWM Generator 5 current-limit ADC trigger
11010 = PWM Generator 4 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = PWM Generator 9 secondary trigger is selected
10101 = PWM Generator 8 secondary trigger is selected
10100 = PWM Generator 7 secondary trigger is selected
10011 = PWM Generator 6 secondary trigger is selected
10010 = PWM Generator 5 secondary trigger is selected
10001 = PWM Generator 4 secondary trigger selected
10000 = PWM Generator 3 secondary trigger is selected
01111 = PWM Generator 2 secondary trigger is selected
01110 = PWM Generator 1 secondary trigger is selected
01101 = PWM secondary Special Event Trigger is selected
01100 = Timer1 period match
01011 = PWM Generator 8 primary trigger is selected
01010 = PWM Generator 7 primary trigger is selected
01001 = PWM Generator 6 primary trigger is selected
01000 = PWM Generator 5 primary trigger is selected
00111 = PWM Generator 4 primary trigger is selected
00110 = PWM Generator 3 primary trigger is selected
00101 = PWM Generator 2 primary trigger is selected
00100 = PWM Generator 1 primary trigger is selected
00011 = PWM Special Event Trigger is selected
00010 = Global software trigger is selected
00001 = Individual software trigger is selected
00000 = No conversion is enabled
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
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REGISTER 22-8:
ADCPC2: ADC CONVERT PAIR CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
IRQEN5
PEND5
SWTRG5
R/W-0
R/W-0
TRGSRC54 TRGSRC53
R/W-0
R/W-0
R/W-0
TRGSRC52
TRGSRC51
TRGSRC50
bit 15
bit 8
R/W-0
R/W-0
R/W-0
IRQEN4
PEND4
SWTRG4
R/W-0
R/W-0
TRGSRC44 TRGSRC43
R/W-0
R/W-0
R/W-0
TRGSRC42
TRGSRC41
TRGSRC40
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
IRQEN5: Interrupt Request Enable 5 bit
1 = Enables IRQ generation when requested conversion of Channels AN11 and AN10 is completed
0 = IRQ is not generated
bit 14
PEND5: Pending Conversion Status 5 bit
1 = Conversion of Channels AN11 and AN10 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 13
SWTRG5: Software Trigger 5 bit
1 = Starts conversion of AN11 and AN10 (if selected by the TRGSRCx<4:0> bits)(1)
This bit is automatically cleared by hardware when the PEND5 bit is set.
0 = Conversion has not started
Note 1:
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
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REGISTER 22-8:
ADCPC2: ADC CONVERT PAIR CONTROL REGISTER 2 (CONTINUED)
bit 12-8
TRGSRC5<4:0>: Trigger 5 Source Selection bits
Selects trigger source for conversion of Analog Channels AN11 and AN10.
11111 = Timer2 period match
11110 = PWM Generator 8 current-limit ADC trigger
11101 = PWM Generator 7 current-limit ADC trigger
11100 = PWM Generator 6 current-limit ADC trigger
11011 = PWM Generator 5 current-limit ADC trigger
11010 = PWM Generator 4 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = PWM Generator 9 secondary trigger selected
10101 = PWM Generator 8 secondary trigger selected
10100 = PWM Generator 7 secondary trigger selected
10011 = PWM Generator 6 secondary trigger selected
10010 = PWM Generator 5 secondary trigger selected
10001 = PWM Generator 4 secondary trigger selected
10000 = PWM Generator 3 secondary trigger selected
01111 = PWM Generator 2 secondary trigger selected
01110 = PWM Generator 1 secondary trigger selected
01101 = PWM secondary Special Event Trigger selected
01100 = Timer1 period match
01011 = PWM Generator 8 primary trigger selected
01010 = PWM Generator 7 primary trigger selected
01001 = PWM Generator 6 primary trigger selected
01000 = PWM Generator 5 primary trigger selected
00111 = PWM Generator 4 primary trigger selected
00110 = PWM Generator 3 primary trigger selected
00101 = PWM Generator 2 primary trigger selected
00100 = PWM Generator 1 primary trigger selected
00011 = PWM Special Event Trigger selected
00010 = Global software trigger selected
00001 = Individual software trigger selected
00000 = No conversion is enabled
bit 7
IRQEN4: Interrupt Request Enable 4 bit
1 = Enables IRQ generation when requested conversion of Channels AN9 and AN8 is completed
0 = IRQ is not generated
bit 6
PEND4: Pending Conversion Status 4 bit
1 = Conversion of Channels AN9 and AN8 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 5
SWTRG4: Software Trigger 4 bit
1 = Starts conversion of AN9 and AN8 (if selected by the TRGSRCx<4:0> bits)(1)
This bit is automatically cleared by hardware when the PEND4 bit is set.
0 = Conversion has not started
Note 1:
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
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REGISTER 22-8:
bit 4-0
Note 1:
ADCPC2: ADC CONVERT PAIR CONTROL REGISTER 2 (CONTINUED)
TRGSRC4<4:0>: Trigger 4 Source Selection bits
Selects trigger source for conversion of Analog Channels AN9 and AN8.
11111 = Timer2 period match
11110 = PWM Generator 8 current-limit ADC trigger
11101 = PWM Generator 7 current-limit ADC trigger
11100 = PWM Generator 6 current-limit ADC trigger
11011 = PWM Generator 5 current-limit ADC trigger
11010 = PWM Generator 4 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = PWM Generator 9 secondary trigger selected
10101 = PWM Generator 8 secondary trigger selected
10100 = PWM Generator 7 secondary trigger selected
10011 = PWM Generator 6 secondary trigger selected
10010 = PWM Generator 5 secondary trigger selected
10001 = PWM Generator 4 secondary trigger selected
10000 = PWM Generator 3 secondary trigger selected
01111 = PWM Generator 2 secondary trigger selected
01110 = PWM Generator 1 secondary trigger selected
01101 = PWM secondary Special Event Trigger selected
01100 = Timer1 period match
01011 = PWM Generator 8 primary trigger selected
01010 = PWM Generator 7 primary trigger selected
01001 = PWM Generator 6 primary trigger selected
01000 = PWM Generator 5 primary trigger selected
00111 = PWM Generator 4 primary trigger selected
00110 = PWM Generator 3 primary trigger selected
00101 = PWM Generator 2 primary trigger selected
00100 = PWM Generator 1 primary trigger selected
00011 = PWM Special Event Trigger selected
00010 = Global software trigger selected
00001 = Individual software trigger selected
00000 = No conversion is enabled
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
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REGISTER 22-9:
ADCPC3: ADC CONVERT PAIR CONTROL REGISTER 3
R/W-0
R/W-0
R/W-0
IRQEN7
PEND7
SWTRG7
R/W-0
R/W-0
TRGSRC74 TRGSRC73
R/W-0
R/W-0
R/W-0
TRGSRC72
TRGSRC71
TRGSRC70
bit 15
bit 8
R/W-0
R/W-0
R/W-0
IRQEN6
PEND6
SWTRG6
R/W-0
R/W-0
TRGSRC64 TRGSRC63
R/W-0
R/W-0
R/W-0
TRGSRC62
TRGSRC61
TRGSRC60
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
IRQEN7: Interrupt Request Enable 7 bit
1 = Enables IRQ generation when requested conversion of Channels AN15 and AN14 is completed
0 = IRQ is not generated
bit 14
PEND7: Pending Conversion Status 7 bit
1 = Conversion of Channels AN15 and AN14 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 13
SWTRG7: Software Trigger 7 bit
1 = Starts conversion of AN15 and AN14 (if selected by the TRGSRCx<4:0> bits)(1)
This bit is automatically cleared by hardware when the PEND7 bit is set.
0 = Conversion has not started
Note 1:
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
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REGISTER 22-9:
ADCPC3: ADC CONVERT PAIR CONTROL REGISTER 3 (CONTINUED)
bit 12-8
TRGSRC7<4:0>: Trigger 7 Source Selection bits
Selects trigger source for conversion of Analog Channels AN15 and 14.
11111 = Timer2 period match
11110 = PWM Generator 8 current-limit ADC trigger
11101 = PWM Generator 7 current-limit ADC trigger
11100 = PWM Generator 6 current-limit ADC trigger
11011 = PWM Generator 5 current-limit ADC trigger
11010 = PWM Generator 4 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = PWM Generator 9 secondary trigger selected
10101 = PWM Generator 8 secondary trigger selected
10100 = PWM Generator 7 secondary trigger selected
10011 = PWM Generator 6 secondary trigger selected
10010 = PWM Generator 5 secondary trigger selected
10001 = PWM Generator 4 secondary trigger selected
10000 = PWM Generator 3 secondary trigger selected
01111 = PWM Generator 2 secondary trigger selected
01110 = PWM Generator 1 secondary trigger selected
01101 = PWM secondary Special Event Trigger selected
01100 = Timer1 period match
01011 = PWM Generator 8 primary trigger selected
01010 = PWM Generator 7 primary trigger selected
01001 = PWM Generator 6 primary trigger selected
01000 = PWM Generator 5 primary trigger selected
00111 = PWM Generator 4 primary trigger selected
00110 = PWM Generator 3 primary trigger selected
00101 = PWM Generator 2 primary trigger selected
00100 = PWM Generator 1 primary trigger selected
00011 = PWM Special Event Trigger selected
00010 = Global software trigger selected
00001 = Individual software trigger selected
00000 = No conversion is enabled
bit 7
IRQEN6: Interrupt Request Enable 6 bit
1 = Enables IRQ generation when requested conversion of Channels AN13 and AN12 is completed
0 = IRQ is not generated
bit 6
PEND6: Pending Conversion Status 6 bit
1 = Conversion of Channels AN13 and AN12 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 5
SWTRG6: Software Trigger 6 bit
1 = Starts conversion of AN13 and AN12 (if selected by the TRGSRCx<4:0> bits)(1)
This bit is automatically cleared by hardware when the PEND6 bit is set.
0 = Conversion has not started
Note 1:
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
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REGISTER 22-9:
bit 4-0
Note 1:
ADCPC3: ADC CONVERT PAIR CONTROL REGISTER 3 (CONTINUED)
TRGSRC6<4:0>: Trigger 6 Source Selection bits
Selects trigger source for conversion of Analog Channels AN13 and AN12.
11111 = Timer2 period match
11110 = PWM Generator 8 current-limit ADC trigger
11101 = PWM Generator 7 current-limit ADC trigger
11100 = PWM Generator 6 current-limit ADC trigger
11011 = PWM Generator 5 current-limit ADC trigger
11010 = PWM Generator 4 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = PWM Generator 9 secondary trigger selected
10101 = PWM Generator 8 secondary trigger selected
10100 = PWM Generator 7 secondary trigger selected
10011 = PWM Generator 6 secondary trigger selected
10010 = PWM Generator 5 secondary trigger selected
10001 = PWM Generator 4 secondary trigger selected
10000 = PWM Generator 3 secondary trigger selected
01111 = PWM Generator 2 secondary trigger selected
01110 = PWM Generator 1 secondary trigger selected
01101 = PWM secondary Special Event Trigger selected
01100 = Timer1 period match
01011 = PWM Generator 8 primary trigger selected
01010 = PWM Generator 7 primary trigger selected
01001 = PWM Generator 6 primary trigger selected
01000 = PWM Generator 5 primary trigger selected
00111 = PWM Generator 4 primary trigger selected
00110 = PWM Generator 3 primary trigger selected
00101 = PWM Generator 2 primary trigger selected
00100 = PWM Generator 1 primary trigger selected
00011 = PWM Special Event Trigger selected
00010 = Global software trigger selected
00001 = Individual software trigger selected
00000 = No conversion is enabled
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
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REGISTER 22-10: ADCPC4: ADC CONVERT PAIR CONTROL REGISTER 4
R/W-0
R/W-0
R/W-0
IRQEN9
PEND9
SWTRG9
R/W-0
R/W-0
TRGSRC94 TRGSRC93
R/W-0
R/W-0
R/W-0
TRGSRC92
TRGSRC91
TRGSRC90
bit 15
bit 8
R/W-0
R/W-0
R/W-0
IRQEN8
PEND8
SWTRG8
R/W-0
R/W-0
TRGSRC84 TRGSRC83
R/W-0
R/W-0
R/W-0
TRGSRC82
TRGSRC81
TRGSRC80
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
IRQEN9: Interrupt Request Enable 9 bit
1 = Enable IRQ generation when requested conversion of channels AN19 and AN18 is completed
0 = IRQ is not generated
bit 14
PEND9: Pending Conversion Status 9 bit
1 = Conversion of channels AN19 and AN18 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 13
SWTRG9: Software Trigger 9 bit
1 = Starts conversion of AN19 and AN18 (if selected by the TRGSRCx<4:0> bits)(1)
This bit is automatically cleared by hardware when the PEND9 bit is set.
0 = Conversion is not started
Note 1:
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
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REGISTER 22-10: ADCPC4: ADC CONVERT PAIR CONTROL REGISTER 4 (CONTINUED)
bit 12-8
TRGSRC9<4:0>: Trigger 9 Source Selection bits
Selects trigger source for conversion of analog channels AN19 and AN18.
11111 = Timer2 period match
11110 = PWM Generator 8 current-limit ADC trigger
11101 = PWM Generator 7 current-limit ADC trigger
11100 = PWM Generator 6 current-limit ADC trigger
11011 = PWM Generator 5 current-limit ADC trigger
11010 = PWM Generator 4 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = PWM Generator 9 secondary trigger selected
10101 = PWM Generator 8 secondary trigger selected
10100 = PWM Generator 7 secondary trigger selected
10011 = PWM Generator 6 secondary trigger selected
10010 = PWM Generator 5 secondary trigger selected
10001 = PWM Generator 4 secondary trigger selected
10000 = PWM Generator 3 secondary trigger selected
01111 = PWM Generator 2 secondary trigger selected
01110 = PWM Generator 1 secondary trigger selected
01101 = PWM secondary Special Event Trigger selected
01100 = Timer1 period match
01011 = PWM Generator 8 primary trigger selected
01010 = PWM Generator 7 primary trigger selected
01001 = PWM Generator 6 primary trigger selected
01000 = PWM Generator 5 primary trigger selected
00111 = PWM Generator 4 primary trigger selected
00110 = PWM Generator 3 primary trigger selected
00101 = PWM Generator 2 primary trigger selected
00100 = PWM Generator 1 primary trigger selected
00011 = PWM Special Event Trigger selected
00010 = Global software trigger selected
00001 = Individual software trigger selected
00000 = No conversion is enabled
bit 7
IRQEN8: Interrupt Request Enable 8 bit
1 = Enables IRQ generation when requested conversion of Channels AN17 and AN16 is completed
0 = IRQ is not generated
bit 6
PEND8: Pending Conversion Status 8 bit
1 = Conversion of Channels AN17 and AN16 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 5
SWTRG8: Software Trigger 8 bit
1 = Starts conversion of AN17 and AN16 (if selected by TRGSRC bits)(1)
This bit is automatically cleared by hardware when the PEND8 bit is set.
0 = Conversion has not started
Note 1:
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
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REGISTER 22-10: ADCPC4: ADC CONVERT PAIR CONTROL REGISTER 4 (CONTINUED)
bit 4-0
Note 1:
TRGSRC8<4:0>: Trigger 8 Source Selection bits
Selects trigger source for conversion of Analog Channels AN17 and AN16.
11111 = Timer2 period match
11110 = PWM Generator 8 current-limit ADC trigger
11101 = PWM Generator 7 current-limit ADC trigger
11100 = PWM Generator 6 current-limit ADC trigger
11011 = PWM Generator 5 current-limit ADC trigger
11010 = PWM Generator 4 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = PWM Generator 9 secondary trigger selected
10101 = PWM Generator 8 secondary trigger selected
10100 = PWM Generator 7 secondary trigger selected
10011 = PWM Generator 6 secondary trigger selected
10010 = PWM Generator 5 secondary trigger selected
10001 = PWM Generator 4 secondary trigger selected
10000 = PWM Generator 3 secondary trigger selected
01111 = PWM Generator 2 secondary trigger selected
01110 = PWM Generator 1 secondary trigger selected
01101 = PWM secondary Special Event Trigger selected
01100 = Timer1 period match
01011 = PWM Generator 8 primary trigger selected
01010 = PWM Generator 7 primary trigger selected
01001 = PWM Generator 6 primary trigger selected
01000 = PWM Generator 5 primary trigger selected
00111 = PWM Generator 4 primary trigger selected
00110 = PWM Generator 3 primary trigger selected
00101 = PWM Generator 2 primary trigger selected
00100 = PWM Generator 1 primary trigger selected
00011 = PWM Special Event Trigger selected
00010 = Global software trigger selected
00001 = Individual software trigger selected
00000 = No conversion is enabled
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
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REGISTER 22-11: ADCPC5: ADC CONVERT PAIR CONTROL REGISTER 5
R/W-0
R/W-0
R/W-0
IRQEN11
PEND11
SWTRG11
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRGSRC114 TRGSRC113 TRGSRC112 TRGSRC111 TRGSRC110
bit 15
bit 8
R/W-0
R/W-0
R/W-0
IRQEN10
PEND10
SWTRG10
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRGSRC104 TRGSRC103 TRGSRC102 TRGSRC101 TRGSRC100
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
IRQEN11: Interrupt Request Enable 11 bit
1 = Enables IRQ generation when requested conversion of Channels AN23 and AN22 is completed
0 = IRQ is not generated
bit 14
PEND11: Pending Conversion Status 11 bit
1 = Conversion of Channels AN23 and AN22 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 13
SWTRG11: Software Trigger 11 bit
1 = Starts conversion of AN23 and AN22 (if selected by the TRGSRCx<4:0> bits)(1)
This bit is automatically cleared by hardware when the PEND11 bit is set.
0 = Conversion is not started
Note 1:
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
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REGISTER 22-11: ADCPC5: ADC CONVERT PAIR CONTROL REGISTER 5 (CONTINUED)
bit 12-8
TRGSRC11<4:0>: Trigger 11 Source Selection bits
Selects trigger source for conversion of analog channels AN23 and AN22.
11111 = Timer2 period match
11110 = PWM Generator 8 current-limit ADC trigger
11101 = PWM Generator 7 current-limit ADC trigger
11100 = PWM Generator 6 current-limit ADC trigger
11011 = PWM Generator 5 current-limit ADC trigger
11010 = PWM Generator 4 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = PWM Generator 9 secondary trigger selected
10101 = PWM Generator 8 secondary trigger selected
10100 = PWM Generator 7 secondary trigger selected
10011 = PWM Generator 6 secondary trigger selected
10010 = PWM Generator 5 secondary trigger selected
10001 = PWM Generator 4 secondary trigger selected
10000 = PWM Generator 3 secondary trigger selected
01111 = PWM Generator 2 secondary trigger selected
01110 = PWM Generator 1 secondary trigger selected
01101 = PWM secondary Special Event Trigger selected
01100 = Timer1 period match
01011 = PWM Generator 8 primary trigger selected
01010 = PWM Generator 7 primary trigger selected
01001 = PWM Generator 6 primary trigger selected
01000 = PWM Generator 5 primary trigger selected
00111 = PWM Generator 4 primary trigger selected
00110 = PWM Generator 3 primary trigger selected
00101 = PWM Generator 2 primary trigger selected
00100 = PWM Generator 1 primary trigger selected
00011 = PWM Special Event Trigger selected
00010 = Global software trigger selected
00001 = Individual software trigger selected
00000 = No conversion is enabled
bit 7
IRQEN10: Interrupt Request Enable 10 bit
1 = Enables IRQ generation when requested conversion of Channels AN21 and AN20 is completed
0 = IRQ is not generated
bit 6
PEND10: Pending Conversion Status 10 bit
1 = Conversion of Channels AN21 and AN20 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 5
SWTRG10: Software Trigger 10 bit
1 = Starts conversion of AN21 and AN20 (if selected by the TRGSRCx<4:0> bits)(1)
This bit is automatically cleared by hardware when the PEND10 bit is set.
0 = Conversion has not started
Note 1:
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
DS70000591F-page 340
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REGISTER 22-11: ADCPC5: ADC CONVERT PAIR CONTROL REGISTER 5 (CONTINUED)
bit 4-0
Note 1:
TRGSRC10<4:0>: Trigger 10 Source Selection bits
Selects trigger source for conversion of analog channels AN21 and AN20.
11111 = Timer2 period match
11110 = PWM Generator 8 current-limit ADC trigger
11101 = PWM Generator 7 current-limit ADC trigger
11100 = PWM Generator 6 current-limit ADC trigger
11011 = PWM Generator 5 current-limit ADC trigger
11010 = PWM Generator 4 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = PWM Generator 9 secondary trigger selected
10101 = PWM Generator 8 secondary trigger selected
10100 = PWM Generator 7 secondary trigger selected
10011 = PWM Generator 6 secondary trigger selected
10010 = PWM Generator 5 secondary trigger selected
10001 = PWM Generator 4 secondary trigger selected
10000 = PWM Generator 3 secondary trigger selected
01111 = PWM Generator 2 secondary trigger selected
01110 = PWM Generator 1 secondary trigger selected
01101 = PWM secondary Special Event Trigger selected
01100 = Timer1 period match
01011 = PWM Generator 8 primary trigger selected
01010 = PWM Generator 7 primary trigger selected
01001 = PWM Generator 6 primary trigger selected
01000 = PWM Generator 5 primary trigger selected
00111 = PWM Generator 4 primary trigger selected
00110 = PWM Generator 3 primary trigger selected
00101 = PWM Generator 2 primary trigger selected
00100 = PWM Generator 1 primary trigger selected
00011 = PWM Special Event Trigger selected
00010 = Global software trigger selected
00001 = Individual software trigger selected
00000 = No conversion enabled
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
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REGISTER 22-12: ADCPC6: ADC CONVERT PAIR CONTROL REGISTER 6(2)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
IRQEN12
PEND12
SWTRG12
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRGSRC124 TRGSRC123 TRGSRC122 TRGSRC121 TRGSRC120
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented: Read as ‘0’
bit 7
IRQEN12: Interrupt Request Enable 12 bit
1 = Enables IRQ generation when requested conversion of Channels AN25 and AN24 is completed
0 = IRQ is not generated
bit 6
PEND12: Pending Conversion Status 12 bit
1 = Conversion of Channels AN25 and AN24 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 5
SWTRG12: Software Trigger 12 bit
1 = Starts conversion of AN25 (INTREF) and AN24 (EXTREF) if selected by the TRGSRCx<4:0> bits(1)
This bit is automatically cleared by hardware when the PEND12 bit is set.
0 = Conversion has not started
Note 1:
2:
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
This register is not available on dsPIC33FJ32GS406 and dsPIC33FJ64GS406 devices.
DS70000591F-page 342
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 22-12: ADCPC6: ADC CONVERT PAIR CONTROL REGISTER 6(2) (CONTINUED)
bit 4-0
TRGSRC12<4:0>: Trigger 12 Source Selection bits
Selects trigger source for conversion of analog channels AN25 and AN24.
11111 = Timer2 period match
11110 = PWM Generator 8 current-limit ADC trigger
11101 = PWM Generator 7 current-limit ADC trigger
11100 = PWM Generator 6 current-limit ADC trigger
11011 = PWM Generator 5 current-limit ADC trigger
11010 = PWM Generator 4 current-limit ADC trigger
11001 = PWM Generator 3 current-limit ADC trigger
11000 = PWM Generator 2 current-limit ADC trigger
10111 = PWM Generator 1 current-limit ADC trigger
10110 = PWM Generator 9 secondary trigger selected
10101 = PWM Generator 8 secondary trigger selected
10100 = PWM Generator 7 secondary trigger selected
10011 = PWM Generator 6 secondary trigger selected
10010 = PWM Generator 5 secondary trigger selected
10001 = PWM Generator 4 secondary trigger selected
10000 = PWM Generator 3 secondary trigger selected
01111 = PWM Generator 2 secondary trigger selected
01110 = PWM Generator 1 secondary trigger selected
01101 = PWM secondary Special Event Trigger selected
01100 = Timer1 period match
01011 = PWM Generator 8 primary trigger selected
01010 = PWM Generator 7 primary trigger selected
01001 = PWM Generator 6 primary trigger selected
01000 = PWM Generator 5 primary trigger selected
00111 = PWM Generator 4 primary trigger selected
00110 = PWM Generator 3 primary trigger selected
00101 = PWM Generator 2 primary trigger selected
00100 = PWM Generator 1 primary trigger selected
00011 = PWM Special Event Trigger selected
00010 = Global software trigger selected
00001 = Individual software trigger selected
00000 = No conversion is enabled
Note 1:
2:
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
This register is not available on dsPIC33FJ32GS406 and dsPIC33FJ64GS406 devices.
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NOTES:
DS70000591F-page 344
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23.0
HIGH-SPEED ANALOG
COMPARATOR
•
•
•
•
•
10-Bit DAC for each Analog Comparator
Programmable Output Polarity
Interrupt Generation Capability
DACOUT Pin to provide DAC Output
DAC has Three Ranges of Operation:
- AVDD/2
- Internal Reference (INTREF)
- External Reference (EXTREF)
• ADC Sample-and-Convert Trigger Capability
• Disable Capability reduces Power Consumption
• Functional Support for PWM module:
- PWM duty cycle control
- PWM period control
- PWM Fault detect
Note 1: This data sheet summarizes the features of
the
dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “High-Speed Analog
Comparator”
(DS70296)
in
the
“dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip
web site (www.microchip.com). The information in this data sheet supersedes the
information in the FRM.
23.2
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Figure 23-1 shows a functional block diagram of one
analog comparator from the SMPS comparator
module. The analog comparator provides high-speed
operation with a typical delay of 20 ns. The comparator
has a typical offset voltage of ±5 mV. The negative
input of the comparator is always connected to the
DAC circuit. The positive input of the comparator is
connected to an analog multiplexer that selects the
desired source pin.
The dsPIC33F Switch Mode Power Supply (SMPS)
comparator module monitors current and/or voltage
transients that may be too fast for the CPU and ADC to
capture.
23.1
The analog comparator input pins are typically shared
with pins used by the Analog-to-Digital Converter
(ADC) module. Both the comparator and the ADC can
use the same pins at the same time. This capability
enables a user to measure an input voltage with the
ADC and detect voltage transients with the
comparator.
Features Overview
The SMPS comparator module offers the following
major features:
• 16 Selectable Comparator Inputs
• Up to Four Analog Comparators
FIGURE 23-1:
Module Description
HIGH-SPEED ANALOG COMPARATOR x MODULE BLOCK DIAGRAM
INSEL<1:0>
CMPxA*
Trigger to PWM
CMPxB*
Status
M
U
X
CMPxC*
0
CMPx*
CMPxD*
Glitch Filter
Pulse
Generator
1
RANGE
CMPPOL
AVDD/2
M
U
X
INTREF(1)
DAC
AVSS
10
CMREF
EXTREF(1)
*
Note 1:
Interrupt
Request
DACOUT
DACOE
x = 1, 2, 3 and 4
Refer to Parameters DA01 and DA08 in the DAC Module Specifications (Table 27-43) for details.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 345
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
23.3
Module Applications
23.5
Interaction with I/O Buffers
This module provides a means for the SMPS dsPIC®
DSC devices to monitor voltage and currents in a
power conversion application. The ability to detect
transient conditions and stimulate the dsPIC DSC
processor and/or peripherals, without requiring the
processor and ADC to constantly monitor voltages or
currents, frees the dsPIC DSC to perform other tasks.
If the comparator module is enabled and a pin has
been selected as the source for the comparator, then
the chosen I/O pad must disable the digital input buffer
associated with the pad to prevent excessive currents
in the digital buffer due to analog input voltages.
The comparator module has a high-speed comparator
and an associated 10-bit DAC that provides a programmable reference voltage to the inverting input of
the comparator. The polarity of the comparator output
is user-programmable. The output of the module can
be used in the following modes:
The CMPCONx register (see Register 23-1) provides
the control logic that configures the comparator
module. The digital logic provides a glitch filter for the
comparator output to mask transient signals in less
than two instruction cycles. In Sleep or Idle mode, the
glitch filter is bypassed to enable an asynchronous
path from the comparator to the interrupt controller.
This asynchronous path can be used to wake-up the
processor from Sleep or Idle mode.
•
•
•
•
•
Generate an Interrupt
Trigger an ADC Sample-and-Convert Process
Truncate the PWM Signal (current limit)
Truncate the PWM Period (current minimum)
Disable the PWM Outputs (Fault latch)
The output of the comparator module may be used in
multiple modes at the same time, such as: 1) generate
an interrupt, 2) have the ADC take a sample and convert it, and 3) truncate the PWM output in response to
a voltage being detected beyond its expected value.
The comparator module can also be used to wake-up
the system from Sleep or Idle mode when the analog
input voltage exceeds the programmed threshold
voltage.
23.4
DAC
The range of the DAC is controlled via an analog
multiplexer that selects either AVDD/2, an internal reference source, INTREF, or an external reference
source, EXTREF. The full range of the DAC (AVDD/2)
will typically be used when the chosen input source pin
is shared with the ADC. The reduced range option
(INTREF) will likely be used when monitoring current
levels using a current sense resistor. Usually, the
measured voltages in such applications are small
(<1.25V); therefore the option of using a reduced
reference range for the comparator extends the
available DAC resolution in these applications. The
use of an external reference enables the user to
connect to a reference that better suits their
application.
DACOUT, shown in Figure 23-1, can only be
associated with a single comparator at a given time.
Note:
It should be ensured in software that
multiple DACOE bits are not set. The
output on the DACOUT pin will be indeterminate if multiple comparators enable the
DAC output.
23.6
Digital Logic
The comparator can be disabled while in Idle mode if
the CMPSIDL bit is set. If a device has multiple
comparators, if any CMPSIDL bit is set, then the entire
group of comparators will be disabled while in Idle
mode. This behavior reduces complexity in the design
of the clock control logic for this module.
The digital logic also provides a one TCY width pulse
generator for triggering the ADC and generating
interrupt requests.
The CMPDACx (see Register 23-2) register provides
the digital input value to the reference DAC.
If the module is disabled, the DAC and comparator are
disabled to reduce power consumption.
23.7
Comparator Input Range
The comparator has a limitation for the input
Common-Mode Range (CMR) of (AVDD – 1.5V),
typical. This means that both inputs should not exceed
this range. As long as one of the inputs is within the
Common-Mode Range, the comparator output will be
correct. However, any input exceeding the CMR
limitation will cause the comparator input to be
saturated.
If both inputs exceed the CMR, the comparator output
will be indeterminate.
23.8
DAC Output Range
The DAC has a limitation for the maximum reference
voltage input of (AVDD – 1.6) volts. An external
reference voltage input should not exceed this value or
the reference DAC output will become indeterminate.
23.9
Comparator Registers
The comparator module is controlled by the following
registers:
• CMPCONx: Comparator Control x Register
• CMPDACx: Comparator DAC Control x Register
DS70000591F-page 346
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 23-1:
CMPCONx: COMPARATOR CONTROL x REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
R/W-0
CMPON
—
CMPSIDL
—
—
—
—
DACOE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
R/W-0
R/W-0
INSEL1
INSEL0
EXTREF
—
CMPSTAT
—
CMPPOL
RANGE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CMPON: Comparator Operating Mode bit
1 = Comparator module is enabled
0 = Comparator module is disabled (reduces power consumption)
bit 14
Unimplemented: Read as ‘0’
bit 13
CMPSIDL: Comparator Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode.
0 = Continues module operation in Idle mode
If a device has multiple comparators, any CMPSIDL bit set to ‘1’ disables ALL comparators while in
Idle mode.
bit 12-9
Unimplemented: Read as ‘0’
bit 8
DACOE: DAC Output Enable
1 = DAC analog voltage is output to the DACOUT pin(1)
0 = DAC analog voltage is not connected to the DACOUT pin
bit 7-6
INSEL<1:0>: Input Source Select for Comparator bits
11 = Selects CMPxD input pin
10 = Selects CMPxC input pin
01 = Selects CMPxB input pin
00 = Selects CMPxA input pin
bit 5
EXTREF: Enable External Reference bit
1 = External source provides reference to DAC (maximum DAC voltage determined by external
voltage source)
0 = Internal reference sources provide reference to DAC (maximum DAC voltage determined by
RANGE bit setting)
bit 4
Unimplemented: Read as ‘0’
bit 3
CMPSTAT: Current State of Comparator Output Including CMPPOL Selection bit
bit 2
Unimplemented: Read as ‘0’
bit 1
CMPPOL: Comparator Output Polarity Control bit
1 = Output is inverted
0 = Output is non-inverted
bit 0
RANGE: Selects DAC Output Voltage Range bit
1 = High Range: Max DAC Value = AVDD/2, 1.65V at 3.3V AVDD
0 = Low Range: Max DAC Value = INTREF
Note 1:
DACOUT can be associated only with a single comparator at any given time. The software must ensure
that multiple comparators do not enable the DAC output by setting their respective DACOE bit.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 347
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 23-2:
CMPDACx: COMPARATOR DAC CONTROL x REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
R/W-0
R/W-0
CMREF<9:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMREF<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-10
Unimplemented: Read as ‘0’
bit 9-0
CMREF<9:0>: Comparator Reference Voltage Select bits
1111111111 = (CMREF * INTREF/1024) or (CMREF * (AVDD/2)/1024) volts depending on the
RANGE bit or (CMREF * EXTREF/1024) if EXTREF is set
•
•
•
0000000000 = 0.0 volts
DS70000591F-page 348
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
24.0
SPECIAL FEATURES
24.1
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices provide
non-volatile memory implementations for device
Configuration bits. Refer to “Device Configuration”
(DS70194) in the “dsPIC33/PIC24 Family Reference
Manual” for more information on this implementation.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
devices. It is not intended to be a comprehensive reference source. To complement
the information in this data sheet, refer to
the “dsPIC33/PIC24 Family Reference
Manual”. Please see the Microchip web
site (www.microchip.com) for the latest
“dsPIC33/PIC24 Family Reference Manual” sections. The information in this
data sheet supersedes the information
in the FRM.
The Configuration bits can be programmed (read
as ‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 0xF80000.
The individual Configuration bit descriptions for the
Configuration registers are shown in Table 24-2.
Note that address, 0xF80000, is beyond the user program memory space. It belongs to the configuration
memory space (0x800000-0xFFFFFF), which can only
be accessed using Table Reads and Table Writes.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written again. Changing a
device configuration requires that power to the device
be cycled.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices include
several features intended to maximize application
flexibility and reliability, and minimize cost through
elimination of external components. These are:
•
•
•
•
•
•
•
Configuration Bits
The device Configuration register map is shown in
Table 24-1.
Flexible Configuration
Watchdog Timer (WDT)
Code Protection and CodeGuard™ Security
JTAG Boundary Scan Interface
In-Circuit Serial Programming™ (ICSP™)
In-Circuit Emulation
Brown-out Reset (BOR)
TABLE 24-1:
Address
DEVICE CONFIGURATION REGISTER MAP
Name
Bit 7
Bit 6
Bit 5
Bit 4
0xF80000 FBS
—
—
—
—
0xF80002 RESERVED
—
—
—
—
—
—
—
—
IESO
—
—
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
0xF80010 FCMP
FCKSM<1:0>
FWDTEN
WINDIS
—
ALTQIO
Reserved(1) Reserved(1)
—
—
Bit 3
Bit 2
BSS<2:0>
—
—
GSS<1:0>
—
—
GWRP
FNOSC<2:0>
—
—
—
WDTPRE
ALTSS1
—
—
JTAGEN
—
—
CMPPOL1
Bit 0
BWRP
—
—
(2)
Bit 1
—
OSCIOFNC
POSCMD<1:0>
WDTPOST<3:0>
(2)
HYST1<1:0>
FPWRT<2:0>
—
ICS<1:0>
(2)
CMPPOL0
HYST0<1:0>(2)
Legend: — = unimplemented bit, read as ‘0’.
Note 1: These bits are reserved for use by development tools and must be programmed as ‘1’.
2: These bits are reserved on dsPIC33FJXXXGS406 devices and always read as ‘1’.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 349
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 24-2:
Bit Field
dsPIC33F CONFIGURATION BITS DESCRIPTION
Register
RTSP Effect
BWRP
FBS
Immediate
Boot Segment Program Flash Write Protection bit
1 = Boot segment can be written
0 = Boot segment is write-protected
BSS<2:0>
FBS
Immediate
Boot Segment Program Flash Code Protection Size bits
X11 = No boot program Flash segment
Boot Space is 256 Instruction Words (except interrupt vectors):
110 = Standard security; boot program Flash segment ends at
0x0003FE
010 = High security; boot program Flash segment ends at
0x0003FE
Boot Space is 768 Instruction Words (except interrupt vectors):
101 = Standard security; boot program Flash segment ends at
0x0007FE
001 = High security; boot program Flash segment ends at
0x0007FE
Boot Space is 1792 Instruction Words (except interrupt vectors):
100 = Standard security; boot program Flash segment ends at
0x000FFE
000 = High security; boot program Flash segment ends at
0x000FFE
GSS<1:0>
FGS
Immediate
General Segment Code-Protect bits
11 = User program memory is not code-protected
10 = Standard security
0x = High security
GWRP
FGS
Immediate
General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
IESO
FOSCSEL
Immediate
Two-Speed Oscillator Start-up Enable bit
1 = Start-up device with FRC, then automatically switch to the user
selected oscillator source when ready
0 = Start-up device with user selected oscillator source
FNOSC<2:0>
FOSCSEL
If clock switch
is enabled,
RTSP effect
is on any
device Reset;
otherwise,
immediate
FCKSM<1:0>
FOSC
Immediate
Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
OSCIOFNC
FOSC
Immediate
OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is the clock output
0 = OSC2 is the general purpose digital I/O pin
POSCMD<1:0>
FOSC
Immediate
Primary Oscillator Mode Select bits
11 = Primary Oscillator is disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
DS70000591F-page 350
Description
Initial Oscillator Source Selection bits
111 = Internal Fast RC (FRC) Oscillator with Postscaler
110 = Internal Fast RC (FRC) Oscillator with Divide-by-16
101 = LPRC Oscillator
100 = Secondary (LP) Oscillator
011 = Primary (XT, HS, EC) Oscillator with PLL
010 = Primary (XT, HS, EC) Oscillator
001 = Internal Fast RC (FRC) Oscillator with PLL
000 = FRC Oscillator
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 24-2:
Bit Field
dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED)
Register
RTSP Effect
Description
FWDTEN
FWDT
Immediate
Watchdog Timer Enable bit
1 = Watchdog Timer is always enabled (LPRC oscillator cannot be
disabled; clearing the SWDTEN bit in the RCON register will
have no effect)
0 = Watchdog Timer is enabled/disabled by user software (LPRC can
be disabled by clearing the SWDTEN bit in the RCON register)
WINDIS
FWDT
Immediate
Watchdog Timer Window Enable bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
WDTPRE
FWDT
Immediate
Watchdog Timer Prescaler bit
1 = 1:128
0 = 1:32
WDTPOST<3:0>
FWDT
Immediate
Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
•
•
•
0001 = 1:2
0000 = 1:1
FPWRT<2:0>
FPOR
Immediate
Power-on Reset Timer Value Select bits
111 = PWRT = 128 ms
110 = PWRT = 64 ms
101 = PWRT = 32 ms
100 = PWRT = 16 ms
011 = PWRT = 8 ms
010 = PWRT = 4 ms
001 = PWRT = 2 ms
000 = PWRT = Disabled
JTAGEN
FICD
Immediate
JTAG Enable bit
1 = JTAG is enabled
0 = JTAG is disabled
ICS<1:0>
FICD
Immediate
ICD Communication Channel Select Enable bits
11 = Communicate on PGEC1 and PGED1
10 = Communicate on PGEC2 and PGED2
01 = Communicate on PGEC3 and PGED3
00 = Reserved, do not use
ALTQIO
FPOR
Immediate
Enable Alternate QEI1 Pin bit
1 = QEA1, QEB1 and INDX1 are selected as inputs to QEI1
0 = AQEA1, AQEB1 and AINDX1 are selected as inputs to QEI1
ALTSS1
FPOR
Immediate
Enable Alternate SS1 pin bit
1 = ASS1 is selected as the I/O pin for SPI1
0 = SS1 is selected as the I/O pin for SPI1
CMPPOL0
FCMP
Immediate
Comparator Hysteresis Polarity bit (for even numbered comparators)
1 = Hysteresis is applied to falling edge
0 = Hysteresis is applied to rising edge
HYST0<1:0>
FCMP
Immediate
Comparator Hysteresis Select bits
11 = 45 mV hysteresis
10 = 30 mV hysteresis
01 = 15 mV hysteresis
00 = No hysteresis
 2009-2014 Microchip Technology Inc.
DS70000591F-page 351
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 24-2:
Bit Field
dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED)
Register
RTSP Effect
Description
CMPPOL1
FCMP
Immediate
Comparator Hysteresis Polarity bit (for odd numbered comparators)
1 = Hysteresis is applied to falling edge
0 = Hysteresis is applied to rising edge
HYST1<1:0>
FCMP
Immediate
Comparator Hysteresis Select bits
11 = 45 mV hysteresis
10 = 30 mV hysteresis
01 = 15 mV hysteresis
00 = No hysteresis
DS70000591F-page 352
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
24.2
On-Chip Voltage Regulator
24.3
Brown-out Reset (BOR)
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices power
their core digital logic at a nominal 2.5V. This can create
a conflict for designs that are required to operate at a
higher typical voltage, such as 3.3V. To simplify system
design, all devices in the dsPIC33FJ32GS406/606/608/
610 and dsPIC33FJ64GS406/606/608/610 families
incorporate an on-chip regulator that allows the device to
run its core logic from VDD.
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit. The main purpose of
the BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines, or voltage sags
due to excessive current draw when a large inductive
load is turned on).
The regulator provides power to the core from the other
VDD pins. When the regulator is enabled, a low-ESR
(less than 5 ohms) capacitor (such as tantalum or
ceramic) must be connected to the VCAP pin
(Figure 24-1). This helps to maintain the stability of the
regulator. The recommended value for the filter
capacitor is provided in Table 27-13, located in
Section 27.1 “DC Characteristics”.
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source based on the
device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
Note:
It is important for the low-ESR capacitor to
be placed as close as possible to the VCAP
pin.
On a POR, it takes approximately 20 s for the on-chip
voltage regulator to generate an output voltage. During
this time, designated as TSTARTUP, code execution is
disabled. TSTARTUP is applied every time the device
resumes operation after any power-down.
FIGURE 24-1:
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR(1,2,3)
3.3V
dsPIC33F
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the Power-up Timer (PWRT) Time-out
(TPWRT) is applied before the internal Reset is
released. If TPWRT = 0 and a crystal oscillator is being
used, then a nominal delay of TFSCM = 100 is applied.
The total delay in this case is TFSCM.
The BOR status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit continues to
operate while in Sleep or Idle modes and resets the
device should VDD fall below the BOR threshold
voltage.
24.4
Watchdog Timer (WDT)
For
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices, the WDT
is driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
VDD
24.4.1
VCAP
CEFC
VSS
Note 1:
2:
3:
These are typical operating voltages. Refer
to Table 27-13 located in Section 27.1 “DC
Characteristics” for the full operating
ranges of VDD.
It is important for the low-ESR capacitor to
be placed as close as possible to the VCAP
pin.
Typical VCAP pin voltage = 2.5V when
VDD  VDDMIN.
 2009-2014 Microchip Technology Inc.
PRESCALER/POSTSCALER
The nominal WDT clock source from LPRC is
32.767 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128)
operation. The prescaler is set by the WDTPRE Configuration bit. With a 32.767 kHz input, the prescaler yields
a nominal WDT Time-out (TWDT) period of 1 ms in 5-bit
mode or 4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST<3:0>
Configuration bits (FWDT<3:0>), which allow the
selection of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler, time-out periods, ranging
from 1 ms to 131 seconds, can be achieved.
DS70000591F-page 353
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
The WDT, prescaler and postscaler are reset:
24.4.3
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSCx bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDT instruction during normal execution
The WDT is enabled or disabled by the FWDTEN
Configuration bit in the FWDT Configuration register.
When the FWDTEN Configuration bit is set, the WDT is
always enabled.
Note:
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN
control bit is cleared on any device Reset. The software
WDT option allows the user application to enable the
WDT for critical code segments and disable the WDT
during non-critical segments for maximum power
savings.
Note:
24.4.2
SLEEP AND IDLE MODES
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the WDT will wake the device and code execution will
continue from where the PWRSAV instruction was
executed. The corresponding SLEEP or IDLE bits
(RCON<3:2>) will need to be cleared in software after
the device wakes up.
FIGURE 24-2:
ENABLING WDT
If the WINDIS bit (FWDT<6>) is cleared,
the CLRWDT instruction should be executed
by the application software only during the
last 1/4 of the WDT period. This CLRWDT
window can be determined by using a timer.
If a CLRWDT instruction is executed before
this window, a WDT Reset occurs.
The WDT flag bit, WDTO (RCON<4>), is not automatically
cleared following a WDT time-out. To detect subsequent
WDT events, the flag must be cleared in software.
WDT BLOCK DIAGRAM
All Device Resets
Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAV Instruction
CLRWDT Instruction
Watchdog Timer
Sleep/Idle
WDTPOST<3:0>
WDTPRE
SWDTEN
FWDTEN
WDT
Wake-up
RS
Prescaler
(Divide-by-N1)
LPRC Clock
1
RS
Postscaler
(Divide-by-N2)
0
WINDIS
WDT
Reset
WDT Window Select
CLRWDT Instruction
DS70000591F-page 354
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
24.5
JTAG Interface
24.7
In-Circuit Debugger
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices implement
a JTAG interface, which supports boundary scan
device testing. Detailed information on this interface
will be provided in future revisions of the document.
When MPLAB® ICD 3 is selected as a debugger, the incircuit debugging functionality is enabled. This function
allows simple debugging functions when used with
MPLAB X IDE. Debugging functionality is controlled
through the EMUCx (Emulation/Debug Clock) and
EMUDx (Emulation/Debug Data) pin functions.
24.6
Any of the three pairs of debugging clock/data pins can
be used:
In-Circuit Serial Programming
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610
family
Digital
Signal Controllers (DSCs) can be serially programmed
while in the end application circuit. This is done with
two lines for clock and data and three other lines for
power, ground and the programming sequence. Serial
programming allows customers to manufacture boards
with unprogrammed devices and then program the
Digital Signal Controller just before shipping the
product. Serial programming also allows the most
recent firmware or a custom firmware to be
programmed. Refer to the “dsPIC33F/PIC24H Flash
Programming Specification” (DS70152) for details
about In-Circuit Serial Programming™ (ICSP™).
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS, PGECx, PGEDx and the EMUDx/
EMUCx pin pair. In addition, when the feature is
enabled, some of the resources are not available for
general use. These resources include the first 80 bytes
of data RAM and two I/O pins.
Any of the three pairs of programming clock/data pins
can be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
 2009-2014 Microchip Technology Inc.
DS70000591F-page 355
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
24.8
Code Protection and
CodeGuard™ Security
The code protection features are controlled by the
Configuration registers: FBS and FGS.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices offer the
intermediate implementation of CodeGuard™ Security.
CodeGuard Security enables multiple parties to securely
share resources (memory, interrupts and peripherals) on
a single chip. This feature helps protect individual
Intellectual Property in collaborative system designs.
Secure segment and RAM protection is not implemented in dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610 devices.
Note:
When coupled with software encryption libraries,
CodeGuard Security can be used to securely update
Flash even when multiple IPs reside on a single chip.
TABLE 24-3:
CODE FLASH SECURITY SEGMENT SIZES FOR 64-KBYTE DEVICES
BSS<2:0> = x11, 0K
VS = 256 IW
000000h
0001FEh
000200h
GS = 21760 IW
BSS<2:0> = x10, 1K
VS = 256 IW
BS = 768 IW
000000h
0001FEh
000200h
0007FEh
000800h
BSS<2:0> = x01, 4K
VS = 256 IW
BS = 3840 IW
BSS<2:0> = x00, 8K
VS = 256 IW
BS = 7936 IW
001FFEh
002000h
00ABFEh
000000h
0001FEh
000200h
003FFEh
004000h
GS = 13824 IW
00ABFEh
00ABFEh
CODE FLASH SECURITY SEGMENT SIZES FOR 32-KBYTE DEVICES
BSS<2:0> = x11, 0K
000000h
0001FEh
000200h
BSS<2:0> = x10, 1K
BSS<2:0> = x01, 4K
000000h
0001FEh
000200h
0007FEh
000800h
BS = 3840 IW
GS = 11008 IW 0057FEh
GS = 10240 IW 0057FEh
GS = 7168 IW
00ABFEh
00ABFEh
VS = 256 IW
000000h
0001FEh
000200h
GS = 17920 IW
GS = 20992 IW
00ABFEh
TABLE 24-4:
Refer to “CodeGuard™ Security”
(DS70199) in the “dsPIC33/PIC24 Family
Reference Manual” for further information
on usage, configuration and operation of
CodeGuard Security.
DS70000591F-page 356
VS = 256 IW
BS = 768 IW
VS = 256 IW
000000h
0001FEh
000200h
BSS<2:0> = x00, 8K
BS = 7936 IW
000000h
0001FEh
000200h
GS = 3072 IW
003FFEh
004000h
0057FEh
VS = 256 IW
001FFEh
002000h
0057FEh
00ABFEh
00ABFEh
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
25.0
Note:
INSTRUCTION SET SUMMARY
This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33/PIC24 Family
Reference Manual”. Please see the
Microchip web site (www.microchip.com) for
the latest “dsPIC33F/PIC24H Family
Reference Manual” sections. The
information in this data sheet supersedes
the information in the FRM.
Most bit-oriented instructions (including
rotate/shift instructions) have two operands:
simple
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register
(specified by a literal value or indirectly by the
contents of register ‘Wb’)
The literal instructions that involve data movement can
use some of the following operands:
• A literal value to be loaded into a W register or file
register (specified by ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
The dsPIC33F instruction set is identical to that of the
dsPIC30F.
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction.
• The first source operand, which is a register ‘Wb’
without any address modifier
• The second source operand, which is a literal
value
• The destination of the result (only if not the same
as the first source operand), which is typically a
register ‘Wd’ with or without an address modifier
The instruction set is highly orthogonal and is grouped
into five basic categories:
The MAC class of DSP instructions can use some of the
following operands:
•
•
•
•
•
• The accumulator (A or B) to be used (required
operand)
• The W registers to be used as the two operands
• The X and Y address space prefetch operations
• The X and Y address space prefetch destinations
• The accumulator write-back destination
Word or byte-oriented operations
Bit-oriented operations
Literal operations
DSP operations
Control operations
Table 25-1 shows the general symbols used in
describing the instructions.
The dsPIC33F instruction set summary in Table 25-2
lists all the instructions, along with the status flags
affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The first source operand, which is typically a
register ‘Wb’ without any address modifier
• The second source operand, which is typically a
register ‘Ws’ with or without an address modifier
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier
The other DSP instructions do not involve any
multiplication and can include:
• The accumulator to be used (required)
• The source or destination operand (designated as
Wso or Wdo, respectively) with or without an
address modifier
• The amount of shift specified by a W register,
‘Wn’, or a literal value
The control instructions can use some of the following
operands:
• A program memory address
• The mode of the Table Read and Table Write
instructions
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value, ‘f’
• The destination, which could be either the file
register, ‘f’, or the W0 register, which is denoted
as ‘WREG’
 2009-2014 Microchip Technology Inc.
DS70000591F-page 357
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Most instructions are a single word. Certain
double-word instructions are designed to provide all the
required information in these 48 bits. In the second
word, the 8 MSbs are ‘0’s. If this second word is
executed as an instruction (by itself), it will execute as
a NOP.
The double-word instructions execute in two instruction
cycles.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
Program Counter is changed as a result of the
instruction. In these cases, the execution takes two
instruction cycles with the additional instruction cycle(s)
executed as a NOP. Notable exceptions are the BRA
TABLE 25-1:
(unconditional/computed branch), indirect CALL/GOTO,
all Table Reads and Writes, and RETURN/RETFIE
instructions, which are single-word instructions but take
two or three cycles. Certain instructions that involve
skipping over the subsequent instruction require either
two or three cycles if the skip is performed, depending
on whether the instruction being skipped is a single-word
or two-word instruction. Moreover, double-word moves
require two cycles.
Note:
For more details on the instruction set,
refer to the “16-bit MCU and DSC
Programmer’s
Reference
Manual”
(DS70157).
SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
#text
Description
Means “literal defined by text”
(text)
Means “content of text”
[text]
Means “the location addressed by text”
{ }
Optional field or operation
<n:m>
Register bit field
.b
Byte mode selection
.d
Double-Word mode selection
.S
Shadow register select
.w
Word mode selection (default)
Acc
One of two accumulators {A, B}
AWB
Accumulator Write-Back Destination Address register {W13, [W13]+ = 2}
bit4
4-bit bit selection field (used in word-addressed instructions) {0...15}
C, DC, N, OV, Z
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr
Absolute address, label or expression (resolved by the linker)
f
File register address {0x0000...0x1FFF}
lit1
1-bit unsigned literal {0,1}
lit4
4-bit unsigned literal {0...15}
lit5
5-bit unsigned literal {0...31}
lit8
8-bit unsigned literal {0...255}
lit10
10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit14
14-bit unsigned literal {0...16384}
lit16
16-bit unsigned literal {0...65535}
lit23
23-bit unsigned literal {0...8388608}; LSb must be ‘0’
None
Field does not require an entry, can be blank
OA, OB, SA, SB
DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
PC
Program Counter
Slit10
10-bit signed literal {-512...511}
Slit16
16-bit signed literal {-32768...32767}
Slit6
6-bit signed literal {-16...16}
Wb
Base W register {W0..W15}
Wd
Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register 
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Dividend, Divisor Working register pair (Direct Addressing)
DS70000591F-page 358
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 25-1:
SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field
Description
Wm*Wm
Multiplicand and Multiplier Working register pair for Square instructions 
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Wm*Wn
Multiplicand and Multiplier Working register pair for DSP instructions 
{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn
One of 16 Working registers {W0..W15}
Wnd
One of 16 Destination Working registers {W0...W15}
Wns
One of 16 Source Working registers {W0...W15}
WREG
W0 (Working register used in file register instructions)
Ws
Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register 
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx
X Data Space Prefetch Address register for DSP instructions
 {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2,
[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2,
[W9 + W12], none}
Wxd
X Data Space Prefetch Destination register for DSP instructions {W4...W7}
Wy
Y Data Space Prefetch Address register for DSP instructions
 {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,
[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2,
[W11 + W12], none}
Wyd
Y Data Space Prefetch Destination register for DSP instructions {W4...W7}
 2009-2014 Microchip Technology Inc.
DS70000591F-page 359
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 25-2:
Base
Instr
#
1
2
3
4
5
6
7
8
INSTRUCTION SET OVERVIEW
Assembly
Mnemonic
ADD
ADDC
AND
ASR
BCLR
BRA
BSET
BSW
Assembly Syntax
# of
# of
Words Cycles
Description
Status Flags
Affected
ADD
Acc
Add Accumulators
1
1
ADD
f
f = f + WREG
1
1
OA,OB,SA,SB
C,DC,N,OV,Z
ADD
f,WREG
WREG = f + WREG
1
1
C,DC,N,OV,Z
ADD
#lit10,Wn
Wd = lit10 + Wd
1
1
C,DC,N,OV,Z
ADD
Wb,Ws,Wd
Wd = Wb + Ws
1
1
C,DC,N,OV,Z
ADD
Wb,#lit5,Wd
Wd = Wb + lit5
1
1
C,DC,N,OV,Z
OA,OB,SA,SB
ADD
Wso,#Slit4,Acc
16-Bit Signed Add to Accumulator
1
1
ADDC
f
f = f + WREG + (C)
1
1
C,DC,N,OV,Z
ADDC
f,WREG
WREG = f + WREG + (C)
1
1
C,DC,N,OV,Z
ADDC
#lit10,Wn
Wd = lit10 + Wd + (C)
1
1
C,DC,N,OV,Z
ADDC
Wb,Ws,Wd
Wd = Wb + Ws + (C)
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
ADDC
Wb,#lit5,Wd
Wd = Wb + lit5 + (C)
1
1
AND
f
f = f .AND. WREG
1
1
N,Z
AND
f,WREG
WREG = f .AND. WREG
1
1
N,Z
AND
#lit10,Wn
Wd = lit10 .AND. Wd
1
1
N,Z
AND
Wb,Ws,Wd
Wd = Wb .AND. Ws
1
1
N,Z
AND
Wb,#lit5,Wd
Wd = Wb .AND. lit5
1
1
N,Z
ASR
f
f = Arithmetic Right Shift f
1
1
C,N,OV,Z
ASR
f,WREG
WREG = Arithmetic Right Shift f
1
1
C,N,OV,Z
ASR
Ws,Wd
Wd = Arithmetic Right Shift Ws
1
1
C,N,OV,Z
ASR
Wb,Wns,Wnd
Wnd = Arithmetic Right Shift Wb by Wns
1
1
N,Z
ASR
Wb,#lit5,Wnd
Wnd = Arithmetic Right Shift Wb by lit5
1
1
N,Z
BCLR
f,#bit4
Bit Clear f
1
1
None
BCLR
Ws,#bit4
Bit Clear Ws
1
1
None
BRA
C,Expr
Branch if Carry
1
1 (2)
None
BRA
GE,Expr
Branch if Greater Than or Equal
1
1 (2)
None
BRA
GEU,Expr
Branch if Unsigned Greater Than or Equal
1
1 (2)
None
BRA
GT,Expr
Branch if Greater Than
1
1 (2)
None
BRA
GTU,Expr
Branch if Unsigned Greater Than
1
1 (2)
None
BRA
LE,Expr
Branch if Less Than or Equal
1
1 (2)
None
BRA
LEU,Expr
Branch if Unsigned Less Than or Equal
1
1 (2)
None
BRA
LT,Expr
Branch if Less Than
1
1 (2)
None
BRA
LTU,Expr
Branch if Unsigned Less Than
1
1 (2)
None
BRA
N,Expr
Branch if Negative
1
1 (2)
None
BRA
NC,Expr
Branch if Not Carry
1
1 (2)
None
BRA
NN,Expr
Branch if Not Negative
1
1 (2)
None
BRA
NOV,Expr
Branch if Not Overflow
1
1 (2)
None
BRA
NZ,Expr
Branch if Not Zero
1
1 (2)
None
BRA
OA,Expr
Branch if Accumulator A Overflow
1
1 (2)
None
BRA
OB,Expr
Branch if Accumulator B Overflow
1
1 (2)
None
BRA
OV,Expr
Branch if Overflow
1
1 (2)
None
BRA
SA,Expr
Branch if Accumulator A Saturated
1
1 (2)
None
BRA
SB,Expr
Branch if Accumulator B Saturated
1
1 (2)
None
BRA
Expr
Branch Unconditionally
1
2
None
BRA
Z,Expr
Branch if Zero
1
1 (2)
None
BRA
Wn
Computed Branch
1
2
None
BSET
f,#bit4
Bit Set f
1
1
None
BSET
Ws,#bit4
Bit Set Ws
1
1
None
BSW.C
Ws,Wb
Write C bit to Ws<Wb>
1
1
None
BSW.Z
Ws,Wb
Write Z bit to Ws<Wb>
1
1
None
DS70000591F-page 360
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 25-2:
Base
Instr
#
9
10
11
12
13
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
BTG
BTSC
BTSS
BTST
BTSTS
Assembly Syntax
Description
# of
# of
Words Cycles
Status Flags
Affected
BTG
f,#bit4
Bit Toggle f
1
1
None
BTG
Ws,#bit4
Bit Toggle Ws
1
1
None
BTSC
f,#bit4
Bit Test f, Skip if Clear
1
1
(2 or 3)
None
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
1
(2 or 3)
None
BTSS
f,#bit4
Bit Test f, Skip if Set
1
1
(2 or 3)
None
BTSS
Ws,#bit4
Bit Test Ws, Skip if Set
1
1
(2 or 3)
None
BTST
f,#bit4
Bit Test f
1
1
Z
BTST.C
Ws,#bit4
Bit Test Ws to C
1
1
C
BTST.Z
Ws,#bit4
Bit Test Ws to Z
1
1
Z
BTST.C
Ws,Wb
Bit Test Ws<Wb> to C
1
1
C
BTST.Z
Ws,Wb
Bit Test Ws<Wb> to Z
1
1
Z
BTSTS
f,#bit4
Bit Test then Set f
1
1
Z
BTSTS.C
Ws,#bit4
Bit Test Ws to C, then Set
1
1
C
BTSTS.Z
Ws,#bit4
Bit Test Ws to Z, then Set
1
1
Z
lit23
Call Subroutine
2
2
None
14
CALL
CALL
CALL
Wn
Call Indirect Subroutine
1
2
None
15
CLR
CLR
f
f = 0x0000
1
1
None
CLR
WREG
WREG = 0x0000
1
1
None
CLR
Ws
Ws = 0x0000
1
1
None
CLR
Acc,Wx,Wxd,Wy,Wyd,AWB
Clear Accumulator
1
1
OA,OB,SA,SB
Clear Watchdog Timer
1
1
WDTO,Sleep
16
CLRWDT
CLRWDT
17
COM
COM
f
f=f
1
1
N,Z
COM
f,WREG
WREG = f
1
1
N,Z
COM
Ws,Wd
Wd = Ws
1
1
N,Z
CP
f
Compare f with WREG
1
1
C,DC,N,OV,Z
CP
Wb,#lit5
Compare Wb with lit5
1
1
C,DC,N,OV,Z
CP
Wb,Ws
Compare Wb with Ws (Wb – Ws)
1
1
C,DC,N,OV,Z
CP0
f
Compare f with 0x0000
1
1
C,DC,N,OV,Z
CP0
Ws
Compare Ws with 0x0000
1
1
C,DC,N,OV,Z
CPB
f
Compare f with WREG, with Borrow
1
1
C,DC,N,OV,Z
CPB
Wb,#lit5
Compare Wb with lit5, with Borrow
1
1
C,DC,N,OV,Z
CPB
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
1
1
C,DC,N,OV,Z
18
19
20
CP
CP0
CPB
21
CPSEQ
CPSEQ
Wb, Wn
Compare Wb with Wn, Skip if =
1
1
(2 or 3)
None
22
CPSGT
CPSGT
Wb, Wn
Compare Wb with Wn, Skip if >
1
1
(2 or 3)
None
23
CPSLT
CPSLT
Wb, Wn
Compare Wb with Wn, Skip if <
1
1
(2 or 3)
None
24
CPSNE
CPSNE
Wb, Wn
Compare Wb with Wn, Skip if 
1
1
(2 or 3)
None
25
DAW
DAW
Wn
Wn = Decimal Adjust Wn
1
1
C
26
DEC
DEC
f
f=f–1
1
1
C,DC,N,OV,Z
DEC
f,WREG
WREG = f – 1
1
1
C,DC,N,OV,Z
DEC
Ws,Wd
Wd = Ws – 1
1
1
C,DC,N,OV,Z
DEC2
f
f=f–2
1
1
C,DC,N,OV,Z
DEC2
f,WREG
WREG = f – 2
1
1
C,DC,N,OV,Z
DEC2
Ws,Wd
Wd = Ws – 2
1
1
C,DC,N,OV,Z
DISI
#lit14
Disable Interrupts for k Instruction Cycles
1
1
None
27
28
DEC2
DISI
 2009-2014 Microchip Technology Inc.
DS70000591F-page 361
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 25-2:
Base
Instr
#
29
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
DIV
Assembly Syntax
# of
# of
Words Cycles
Description
Status Flags
Affected
DIV.S
Wm,Wn
Signed 16/16-Bit Integer Divide
1
18
DIV.SD
Wm,Wn
Signed 32/16-Bit Integer Divide
1
18
N,Z,C,OV
N,Z,C,OV
DIV.U
Wm,Wn
Unsigned 16/16-Bit Integer Divide
1
18
N,Z,C,OV
DIV.UD
Wm,Wn
Unsigned 32/16-Bit Integer Divide
1
18
N,Z,C,OV
30
DIVF
DIVF
Wm,Wn
Signed 16/16-Bit Fractional Divide
1
18
N,Z,C,OV
31
DO
DO
#lit14,Expr
Do code to PC + Expr, lit14 + 1 times
2
2
None
DO
Wn,Expr
Do code to PC + Expr, (Wn) + 1 times
2
2
None
32
ED
ED
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance (no accumulate)
1
1
OA,OB,OAB,
SA,SB,SAB
33
EDAC
EDAC
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance
1
1
OA,OB,OAB,
SA,SB,SAB
34
EXCH
EXCH
Wns,Wnd
Swap Wns with Wnd
1
1
None
35
FBCL
FBCL
Ws,Wnd
Find Bit Change from Left (MSb) Side
1
1
C
36
FF1L
FF1L
Ws,Wnd
Find First One from Left (MSb) Side
1
1
C
37
FF1R
FF1R
Ws,Wnd
Find First One from Right (LSb) Side
1
1
C
38
GOTO
GOTO
Expr
Go to Address
2
2
None
GOTO
Wn
Go to Indirect
1
2
None
INC
f
f=f+1
1
1
C,DC,N,OV,Z
INC
f,WREG
WREG = f + 1
1
1
C,DC,N,OV,Z
INC
Ws,Wd
Wd = Ws + 1
1
1
C,DC,N,OV,Z
INC2
f
f=f+2
1
1
C,DC,N,OV,Z
INC2
f,WREG
WREG = f + 2
1
1
C,DC,N,OV,Z
39
40
41
INC
INC2
IOR
INC2
Ws,Wd
Wd = Ws + 2
1
1
C,DC,N,OV,Z
IOR
f
f = f .IOR. WREG
1
1
N,Z
IOR
f,WREG
WREG = f .IOR. WREG
1
1
N,Z
IOR
#lit10,Wn
Wd = lit10 .IOR. Wd
1
1
N,Z
IOR
Wb,Ws,Wd
Wd = Wb .IOR. Ws
1
1
N,Z
IOR
Wb,#lit5,Wd
Wd = Wb .IOR. lit5
1
1
N,Z
42
LAC
LAC
Wso,#Slit4,Acc
Load Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
43
LNK
LNK
#lit14
Link Frame Pointer
1
1
None
44
LSR
LSR
f
f = Logical Right Shift f
1
1
C,N,OV,Z
LSR
f,WREG
WREG = Logical Right Shift f
1
1
C,N,OV,Z
LSR
Ws,Wd
Wd = Logical Right Shift Ws
1
1
C,N,OV,Z
LSR
Wb,Wns,Wnd
Wnd = Logical Right Shift Wb by Wns
1
1
N,Z
LSR
Wb,#lit5,Wnd
Wnd = Logical Right Shift Wb by lit5
1
1
N,Z
MAC
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
,
AWB
Multiply and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
MAC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
MOV
f,Wn
Move f to Wn
1
1
None
MOV
f
Move f to f
1
1
N,Z
MOV
f,WREG
Move f to WREG
1
1
None
45
46
47
MAC
MOV
MOVSAC
MOV
#lit16,Wn
Move 16-Bit Literal to Wn
1
1
None
MOV.b
#lit8,Wn
Move 8-Bit Literal to Wn
1
1
None
MOV
Wn,f
Move Wn to f
1
1
None
MOV
Wso,Wdo
Move Ws to Wd
1
1
None
MOV
WREG,f
Move WREG to f
1
1
None
MOV.D
Wns,Wd
Move Double from W(ns):W(ns + 1) to Wd
1
2
None
MOV.D
Ws,Wnd
Move Double from Ws to W(nd + 1):W(nd)
1
2
None
Prefetch and Store Accumulator
1
1
None
MOVSAC
DS70000591F-page 362
Acc,Wx,Wxd,Wy,Wyd,AWB
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 25-2:
Base
Instr
#
48
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
MPY
Assembly Syntax
Description
# of
# of
Words Cycles
Status Flags
Affected
MPY
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
Multiply Wm by Wn to Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
MPY
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square Wm to Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
49
MPY.N
MPY.N
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
-(Multiply Wm by Wn) to Accumulator
1
1
None
50
MSC
MSC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,
AWB
Multiply and Subtract from Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
51
MUL
MUL.SS
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) * signed(Ws)
1
1
None
MUL.SU
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws)
1
1
None
MUL.US
Wb,Ws,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws)
1
1
None
MUL.UU
Wb,Ws,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(Ws)
1
1
None
MUL.SU
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5)
1
1
None
MUL.UU
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(lit5)
1
1
None
52
53
54
NEG
NOP
POP
MUL
f
W3:W2 = f * WREG
1
1
None
NEG
Acc
Negate Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
NEG
f
f=f+1
1
1
C,DC,N,OV,Z
NEG
f,WREG
WREG = f + 1
1
1
C,DC,N,OV,Z
NEG
Ws,Wd
Wd = Ws + 1
1
1
C,DC,N,OV,Z
NOP
No Operation
1
1
None
NOPR
No Operation
1
1
None
None
POP
f
Pop f from Top-of-Stack (TOS)
1
1
POP
Wdo
Pop from Top-of-Stack (TOS) to Wdo
1
1
None
POP.D
Wnd
Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1)
1
2
None
Pop Shadow Registers
1
1
All
f
Push f to Top-of-Stack (TOS)
1
1
None
PUSH
Wso
Push Wso to Top-of-Stack (TOS)
1
1
None
PUSH.D
Wns
Push W(ns):W(ns + 1) to Top-of-Stack (TOS)
1
2
None
Push Shadow Registers
1
1
None
Go into Sleep or Idle mode
1
1
WDTO,Sleep
POP.S
55
PUSH
PUSH
PUSH.S
56
PWRSAV
PWRSAV
57
RCALL
RCALL
Expr
Relative Call
1
2
None
RCALL
Wn
Computed Call
1
2
None
REPEAT
#lit14
Repeat Next Instruction lit14 + 1 times
1
1
None
REPEAT
Wn
Repeat Next Instruction (Wn) + 1 times
1
1
None
None
58
REPEAT
#lit1
59
RESET
RESET
Software Device Reset
1
1
60
RETFIE
RETFIE
Return from interrupt
1
3 (2)
None
61
RETLW
RETLW
Return with Literal in Wn
1
3 (2)
None
62
RETURN
RETURN
Return from Subroutine
1
3 (2)
None
63
RLC
RLC
f
f = Rotate Left through Carry f
1
1
C,N,Z
RLC
f,WREG
WREG = Rotate Left through Carry f
1
1
C,N,Z
RLC
Ws,Wd
Wd = Rotate Left through Carry Ws
1
1
C,N,Z
RLNC
f
f = Rotate Left (No Carry) f
1
1
N,Z
RLNC
f,WREG
WREG = Rotate Left (No Carry) f
1
1
N,Z
64
65
RLNC
RRC
#lit10,Wn
RLNC
Ws,Wd
Wd = Rotate Left (No Carry) Ws
1
1
N,Z
RRC
f
f = Rotate Right through Carry f
1
1
C,N,Z
RRC
f,WREG
WREG = Rotate Right through Carry f
1
1
C,N,Z
RRC
Ws,Wd
Wd = Rotate Right through Carry Ws
1
1
C,N,Z
 2009-2014 Microchip Technology Inc.
DS70000591F-page 363
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 25-2:
Base
Instr
#
66
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
RRNC
Assembly Syntax
# of
# of
Words Cycles
Description
Status Flags
Affected
RRNC
f
f = Rotate Right (No Carry) f
1
1
N,Z
RRNC
f,WREG
WREG = Rotate Right (No Carry) f
1
1
N,Z
RRNC
Ws,Wd
Wd = Rotate Right (No Carry) Ws
1
1
N,Z
67
SAC
SAC
Acc,#Slit4,Wdo
Store Accumulator
1
1
None
SAC.R
Acc,#Slit4,Wdo
Store Rounded Accumulator
1
1
None
68
SE
SE
Ws,Wnd
Wnd = Sign-Extended Ws
1
1
C,N,Z
69
SETM
SETM
f
f = 0xFFFF
1
1
None
SETM
WREG
WREG = 0xFFFF
1
1
None
SETM
Ws
Ws = 0xFFFF
1
1
None
SFTAC
Acc,Wn
Arithmetic Shift Accumulator by (Wn)
1
1
OA,OB,OAB,
SA,SB,SAB
SFTAC
Acc,#Slit6
Arithmetic Shift Accumulator by Slit6
1
1
OA,OB,OAB,
SA,SB,SAB
SL
f
f = Left Shift f
1
1
C,N,OV,Z
SL
f,WREG
WREG = Left Shift f
1
1
C,N,OV,Z
SL
Ws,Wd
Wd = Left Shift Ws
1
1
C,N,OV,Z
SL
Wb,Wns,Wnd
Wnd = Left Shift Wb by Wns
1
1
N,Z
SL
Wb,#lit5,Wnd
Wnd = Left Shift Wb by lit5
1
1
N,Z
SUB
Acc
Subtract Accumulators
1
1
OA,OB,OAB,
SA,SB,SAB
SUB
f
f = f – WREG
1
1
C,DC,N,OV,Z
SUB
f,WREG
WREG = f – WREG
1
1
C,DC,N,OV,Z
SUB
#lit10,Wn
Wn = Wn – lit10
1
1
C,DC,N,OV,Z
SUB
Wb,Ws,Wd
Wd = Wb – Ws
1
1
C,DC,N,OV,Z
SUB
Wb,#lit5,Wd
Wd = Wb – lit5
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
70
71
72
73
74
75
76
SFTAC
SL
SUB
SUBB
SUBR
SUBBR
SWAP
SUBB
f
f = f – WREG – (C)
1
1
SUBB
f,WREG
WREG = f – WREG – (C)
1
1
C,DC,N,OV,Z
SUBB
#lit10,Wn
Wn = Wn – lit10 – (C)
1
1
C,DC,N,OV,Z
SUBB
Wb,Ws,Wd
Wd = Wb – Ws – (C)
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
SUBB
Wb,#lit5,Wd
Wd = Wb – lit5 – (C)
1
1
SUBR
f
f = WREG – f
1
1
C,DC,N,OV,Z
SUBR
f,WREG
WREG = WREG – f
1
1
C,DC,N,OV,Z
SUBR
Wb,Ws,Wd
Wd = Ws – Wb
1
1
C,DC,N,OV,Z
SUBR
Wb,#lit5,Wd
Wd = lit5 – Wb
1
1
C,DC,N,OV,Z
SUBBR
f
f = WREG – f – (C)
1
1
C,DC,N,OV,Z
SUBBR
f,WREG
WREG = WREG – f – (C)
1
1
C,DC,N,OV,Z
SUBBR
Wb,Ws,Wd
Wd = Ws – Wb – (C)
1
1
C,DC,N,OV,Z
SUBBR
Wb,#lit5,Wd
Wd = lit5 – Wb – (C)
1
1
C,DC,N,OV,Z
SWAP.b
Wn
Wn = Nibble Swap Wn
1
1
None
SWAP
Wn
Wn = Byte Swap Wn
1
1
None
1
2
None
77
TBLRDH
TBLRDH
Ws,Wd
Read Prog<23:16> to Wd<7:0>
78
TBLRDL
TBLRDL
Ws,Wd
Read Prog<15:0> to Wd
1
2
None
79
TBLWTH
TBLWTH
Ws,Wd
Write Ws<7:0> to Prog<23:16>
1
2
None
80
TBLWTL
TBLWTL
Ws,Wd
Write Ws to Prog<15:0>
1
2
None
81
ULNK
ULNK
Unlink Frame Pointer
1
1
None
82
XOR
XOR
f
f = f .XOR. WREG
1
1
N,Z
XOR
f,WREG
WREG = f .XOR. WREG
1
1
N,Z
XOR
#lit10,Wn
Wd = lit10 .XOR. Wd
1
1
N,Z
XOR
Wb,Ws,Wd
Wd = Wb .XOR. Ws
1
1
N,Z
XOR
Wb,#lit5,Wd
Wd = Wb .XOR. lit5
1
1
N,Z
ZE
Ws,Wnd
Wnd = Zero-Extend Ws
1
1
C,Z,N
83
ZE
DS70000591F-page 364
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
26.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
26.1
MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for highperformance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic code formatting based on user-defined
rules
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
•
•
•
•
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
 2009-2014 Microchip Technology Inc.
DS7000591F-page 365
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
26.2
MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16 and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other
relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler
to produce its object file. Notable features of the
assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
26.3
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
26.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
26.5
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
DS7000591F-page 366
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
26.6
MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
26.7
MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
 2009-2014 Microchip Technology Inc.
26.8
MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
26.9
PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the
target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
26.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
DS7000591F-page 367
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
26.11 Demonstration/Development
Boards, Evaluation Kits and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide application firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
26.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS7000591F-page 368
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
27.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
electrical characteristics. Additional information will be provided in future revisions of this document as it becomes
available.
Absolute maximum ratings for the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 family are
listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional
operation of the device at these or any other conditions above the parameters indicated in the operation listings of this
specification is not implied.
Absolute Maximum Ratings(1)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS(3) .................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD  3.0V(3) .................................................. -0.3V to +5.6V
Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(3)......................................... -0.3V to (VDD + 0.3V)
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2) ...........................................................................................................................250 mA
Maximum current sourced/sunk by any 4x I/O pin ..................................................................................................15 mA
Maximum current sourced/sunk by any 8x I/O pin ..................................................................................................25 mA
Maximum current sourced/sunk by any 16x I/O pin ................................................................................................45 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports(2) ...............................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of the device maximum power dissipation (see Table 27-2).
3: See the “Pin Diagrams” section for 5V tolerant pins.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 369
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
27.1
DC Characteristics
TABLE 27-1:
OPERATING MIPS vs. VOLTAGE
Max MIPS
Characteristic
VDD Range
(in Volts)
Temp Range
(in °C)
—
3.0-3.6V(1)
-40°C to +85°C
40
—
(1)
-40°C to +125°C
40
Note 1:
3.0-3.6V
dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610
Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device
analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. See
Parameter BO10 in Table 27-11 for the BOR values.
TABLE 27-2:
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
Operating Junction Temperature Range
TJ
-40
—
+125
°C
Operating Ambient Temperature Range
TA
-40
—
+85
°C
Operating Junction Temperature Range
TJ
-40
—
+140
°C
Operating Ambient Temperature Range
TA
-40
—
+125
°C
Industrial Temperature Devices
Extended Temperature Devices
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD –  IOH)
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/JA
W
I/O Pin Power Dissipation:
I/O =  ({VDD – VOH} x IOH) +  (VOL x IOL)
Maximum Allowed Power Dissipation
TABLE 27-3:
THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Notes
Package Thermal Resistance, 64-Pin QFN (9x9x0.9 mm)
JA
28
—
°C/W
1
Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm)
JA
39
—
°C/W
1
Package Thermal Resistance, 80-Pin TQFP (12x12x1 mm)
JA
53.1
—
°C/W
1
Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm)
JA
43
—
°C/W
1
Package Thermal Resistance, 100-Pin TQFP (14x14x1 mm)
JA
43
—
°C/W
1
Note 1:
Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
DS70000591F-page 370
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-4:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
Operating Voltage
DC10
VDD
Supply Voltage(4)
3.0
—
3.6
V
DC12
VDR
RAM Data Retention Voltage(2)
1.8
—
—
V
DC16
VPOR
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
—
—
VSS
V
DC17
SVDD
VDD Rise Rate(3)
to Ensure Internal
Power-on Reset Signal
0.03
—
—
V/ms
Note 1:
2:
3:
4:
Industrial and extended
0-3.0V in 0.1s
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
This is the limit to which VDD may be lowered without losing RAM data.
These parameters are characterized but not tested in manufacturing.
Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device
analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN. See
Parameter BO10 in Table 27-11 for the BOR values.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 371
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-5:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Parameter
Typical(1)
No.
Max
Units
Conditions
Operating Current (IDD)(2)
DC20d
21
30
mA
-40°C
DC20a
21
30
mA
+25°C
DC20b
21
30
mA
+85°C
DC20c
22
30
mA
+125°C
DC21d
28
40
mA
-40°C
DC21a
28
40
mA
+25°C
DC21b
28
40
mA
+85°C
DC21c
29
40
mA
+125°C
DC22d
35
45
mA
-40°C
DC22a
35
45
mA
+25°C
DC22b
35
45
mA
+85°C
DC22c
36
45
mA
+125°C
DC23d
49
60
mA
-40°C
DC23a
49
60
mA
+25°C
DC23b
49
60
mA
+85°C
DC23c
50
60
mA
+125°C
DC24d
66
75
mA
-40°C
DC24a
66
75
mA
+25°C
DC24b
66
75
mA
+85°C
DC24c
67
75
mA
+125°C
DC25d
153
170
mA
-40°C
DC25a
154
170
mA
+25°C
DC25b
155
170
mA
+85°C
156
170
mA
+125°C
DC25c
Note 1:
2:
3:
3.3V
10 MIPS
(See Note 2)
3.3V
16 MIPS
(See Notes 2 and 3)
3.3V
20 MIPS
(See Notes 2 and 3)
3.3V
30 MIPS
(See Notes 2 and 3)
3.3V
40 MIPS
(See Note 2)
3.3V
40 MIPS
(See Notes 2 and 3), except PWM is
operating at maximum speed
(PTCON2 = 0x0000)
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDD measurements are as follows:
• Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from
rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are all ‘0’s)
• CPU executing while(1) statement
• JTAG disabled
These parameters are characterized but not tested in manufacturing.
DS70000591F-page 372
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-5:
DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Parameter
Typical(1)
No.
Max
Units
Conditions
Operating Current (IDD)(2)
DC26d
122
135
mA
-40°C
DC26a
123
135
mA
+25°C
DC26b
124
135
mA
+85°C
DC26c
125
135
mA
+125°C
DC27d
107
120
mA
-40°C
DC27a
108
120
mA
+25°C
DC27b
109
120
mA
+85°C
DC27c
110
120
mA
+125°C
DC28d
88
100
mA
-40°C
DC28a
89
100
mA
+25°C
DC28b
89
100
mA
+85°C
DC28c
89
100
mA
+125°C
Note 1:
2:
3:
3.3V
40 MIPS
(See Notes 2 and 3), except PWM is
operating at 1/2 speed
(PTCON2 = 0x0001))
3.3V
40 MIPS
(See Notes 2 and 3), except PWM is
operating at 1/4 speed
(PTCON2 = 0x0002))
3.3V
40 MIPS
(See Notes 2 and 3), except PWM is
operating at 1/8 speed
(PTCON2 = 0x0003)
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDD measurements are as follows:
• Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from
rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are all ‘0’s)
• CPU executing while(1) statement
• JTAG disabled
These parameters are characterized but not tested in manufacturing.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 373
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-6:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Idle Current (IIDLE): Core Off, Clock On Base Current(2)
DC40d
8
15
mA
-40°C
DC40a
9
15
mA
+25°C
DC40b
9
15
mA
+85°C
DC40c
10
15
mA
+125°C
DC41d
11
20
mA
-40°C
DC41a
11
20
mA
+25°C
DC41b
11
20
mA
+85°C
DC41c
12
20
mA
+125°C
DC42d
14
25
mA
-40°C
DC42a
14
25
mA
+25°C
DC42b
14
25
mA
+85°C
DC42c
15
25
mA
+125°C
DC43d
20
30
mA
-40°C
DC43a
20
30
mA
+25°C
DC43b
21
30
mA
+85°C
DC43c
22
30
mA
+125°C
DC44d
29
40
mA
-40°C
DC44a
29
40
mA
+25°C
DC44b
30
40
mA
+85°C
31
40
mA
+125°C
DC44c
Note 1:
2:
3:
3.3V
10 MIPS
3.3V
16 MIPS(3)
3.3V
20 MIPS(3)
3.3V
30 MIPS(3)
3.3V
40 MIPS
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
Base Idle current (IIDLE) is measured as follows:
• CPU core is off, oscillator is configured in EC mode and external clock is active, OSC1 is driven with
external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD, WDT and FSCM are disabled
• No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are
all ‘0’s)
• JTAG is disabled
These parameters are characterized but not tested in manufacturing.
DS70000591F-page 374
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-7:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
500
A
Conditions
Power-Down Current (IPD)(2,4)
DC60d
50
-40°C
DC60a
50
500
A
+25°C
DC60b
200
500
A
+85°C
DC60c
600
1000
A
+125°C
DC61d
8
13
A
-40°C
DC61a
10
15
A
+25°C
DC61b
12
20
A
+85°C
13
25
A
+125°C
DC61c
Note 1:
2:
3:
4:
3.3V
Base Power-Down Current
3.3V
Watchdog Timer Current: IWDT(3)
Data in the Typical column is at 3.3V, +25°C unless otherwise stated.
IPD (Sleep) current is measured as follows:
• CPU core is off, oscillator is configured in EC mode and external clock is active, OSC1 is driven with
external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD, WDT and FSCM are disabled
• All peripheral modules are disabled (all PMDx bits are all ‘1’s)
• The VREGS bit (RCON<8>) = 0 (i.e., core regulator is set to standby while the device is in Sleep
mode)
• JTAG disabled
The  current is the additional current consumed when the WDT module is enabled. This current should
be added to the base IPD current.
These currents are measured on the device containing the most memory in this family.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 375
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-8:
DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Parameter No.
Typical(1)
Max
Doze
Ratio
Units
60
1:2
mA
Conditions
Doze Current (IDOZE)(2)
DC73a
45
DC73f
40
60
1:64
mA
DC73g
40
60
1:128
mA
DC70a
43
60
1:2
mA
DC70f
38
60
1:64
mA
DC70g
38
60
1:128
mA
DC71a
42
60
1:2
mA
DC71f
37
60
1:64
mA
DC71g
37
60
1:128
mA
DC72a
41
60
1:2
mA
DC72f
36
60
1:64
mA
36
60
1:128
mA
DC72g
Note 1:
2:
-40°C
3.3V
40 MIPS
+25°C
3.3V
40 MIPS
+85°C
3.3V
40 MIPS
+125°C
3.3V
40 MIPS
Data in the Typical column is at 3.3V, +25°C unless otherwise stated.
IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDOZE measurements are as follows:
• Oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square
wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are
all ‘0’s)
• CPU executing while(1) statement
• JTAG disabled
DS70000591F-page 376
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-9:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
VIL
Characteristic
Min
Typ(1)
Max
Units
Conditions
Input Low Voltage
DI10
I/O Pins
VSS
—
0.2 VDD
V
DI15
MCLR
VSS
—
0.2 VDD
V
DI16
I/O Pins with OSC1 or SOSCI
VSS
—
0.2 VDD
V
DI18
I/O Pins with SDAx, SCLx
VSS
—
0.3 VDD
V
SMBus disabled
I/O Pins with SDAx, SCLx
VSS
—
0.8
V
SMBus enabled
DI19
VIH
Input High Voltage
DI20
DI21
I/O Pins Non 5V Tolerant(4)
I/O Pins 5V Tolerant(4)
0.7 VDD
0.7 VDD
—
—
VDD
5.5
V
V
DI28
DI29
SDAx, SCLx
SDAx, SCLx
0.7 VDD
2.1
—
—
5.5
5.5
V
V
SMBus disabled
SMBus enabled
—
250
—
A
VDD = 3.3V, VPIN = VSS
—
—
±2
A
VSS  VPIN  VDD,
Pin at high-impedance
8x Driver Pins: RC15
—
—
±4
A
VSS  VPIN  VDD,
Pin at high-impedance
16x Driver Pins: RA9, RA10,
RD3-RD7, RD13, RE0-RE7,
RG12, RG13
—
—
±8
A
VSS  VPIN  VDD,
Pin at high-impedance
DI55
MCLR
—
—
±2
A
VSS VPIN VDD
DI56
OSC1
—
—
±2
A
VSS VPIN VDD,
XT and HS modes
ICNPU
CNx Pull-up Current
IIL
Input Leakage Current(2,3,4)
DI30
DI50
I/O Pins with:
4x Driver Pins: RA0-RA7, RA14,
RA15, RB0-RB15(10), RC1-RC4,
RC12-RC14, RD0-RD2,
RD8-RD12, RD14, RD15, RE8,
RE9, RF0-RF8, RF12, RF13,
RG0-RG3, RG6-RG9, RG14, RG15
Note 1:
2:
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
4: See the “Pin Diagrams” section for the list of 5V tolerant I/O pins.
5: VIL source < (VSS – 0.3). Characterized but not tested.
6: VIH source > (VDD + 0.3) for non-5V tolerant pins only.
7: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any
“positive” input injection current.
8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted,
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
10: RB11 has also been tested up to ±8 µA test limits.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 377
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-9:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
IICL
Characteristic
IICT
Max
Units
Conditions
0
—
-5(3,5,8)
mA
All pins except VDD, VSS,
AVDD, AVSS, MCLR,
VCAP, SOSCI, SOSCO
and RB11
0
—
+5(6,7,8)
mA
All pins except VDD, VSS,
AVDD, AVSS, MCLR,
VCAP, SOSCI, SOSCO,
RB11 and digital 5V
tolerant designated
pins(3)
-20(9)
—
+20(9)
mA
Absolute instantaneous
sum of all ± input
injection currents from all
I/O pins
(| IICL + | IICH |)  IICT
Input High Injection Current
DI60b
DI60c
Typ(1)
Input Low Injection Current
DI60a
IICH
Min
Total Input Injection Current
(sum of all I/O and control pins)
Note 1:
2:
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
4: See the “Pin Diagrams” section for the list of 5V tolerant I/O pins.
5: VIL source < (VSS – 0.3). Characterized but not tested.
6: VIH source > (VDD + 0.3) for non-5V tolerant pins only.
7: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any
“positive” input injection current.
8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted,
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
10: RB11 has also been tested up to ±8 µA test limits.
DS70000591F-page 378
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Param. Symbol
VOL
DO10
Characteristic
Output Low Voltage
I/O Pins:
4x Sink Driver Pins – RA0-RA7,
RA14, RA15, RB0-RB15,
RC1-RC4, RC12-RC14, RD0-RD2,
RD8-RD12, RD14, RD15, RE8,
RE9, RF0-RF8, RF12, RF13,
RG0-RG3, RG6-RG9, RG14, RG15
Output Low Voltage
I/O Pins:
8x Sink Driver Pin – RC15
Output Low Voltage
I/O Pins:
16x Sink Driver Pins – RA9, RA10,
RD3-RD7, RD13, RE0-RE7,
RG12, RG13
VOH
DO20
Output High Voltage
I/O Pins:
4x Sink Driver Pins – RA0-RA7,
RA14, RA15, RB0-RB15,
RC1-RC4, RC12-RC14, RD0-RD2,
RD8-RD12, RD14, RD15, RE8,
RE9, RF0-RF8, RF12, RF13,
RG0-RG3, RG6-RG9, RG14, RG15
Output High Voltage
I/O Pins:
8x Sink Driver Pin – RC15
Output High Voltage
I/O Pins:
16x Sink Driver Pins – RA9, RA10,
RD3-RD7, RD13, RE0-RE7,
RG12, RG13
Note 1:
Min.
Typ.
Max.
Units
Conditions
—
—
0.4
V
IOL  6 mA, VDD = 3.3V
(See Note 1)
—
—
0.4
V
IOL  10 mA, VDD = 3.3V
(See Note 1)
—
—
0.4
V
IOL  18 mA, VDD = 3.3V
(See Note 1)
2.4
—
—
V
IOH  -6 mA, VDD = 3.3V
(See Note 1)
2.4
—
—
V
IOH  -10 mA, VDD = 3.3V
(See Note 1)
2.4
—
—
V
IOH  -18 mA, VDD = 3.3V
(See Note 1)
Parameters are characterized, but not tested.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 379
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Param. Symbol
VOH1
DO20A
Characteristic
Output High Voltage
I/O Pins:
4x Sink Driver Pins – RA0-RA7,
RA14, RA15, RB0-RB15,
RC1-RC4, RC12-RC14, RD0-RD2,
RD8-RD12, RD14, RD15, RE8,
RE9, RF0-RF8, RF12, RF13,
RG0-RG3, RG6-RG9, RG14, RG15
Output High Voltage
I/O Pins:
8x Sink Driver Pin – RC15
Output High Voltage
I/O Pins:
16x Sink Driver Pins – RA9, RA10,
RD3-RD7, RD13, RE0-RE7,
RG12, RG13
Note 1:
Min.
Typ.
Max.
Units
Conditions
1.5
—
—
V
IOH  -12 mA, VDD = 3.3V
(See Note 1)
2.0
—
—
V
IOH  -11 mA, VDD = 3.3V
(See Note 1)
3.0
—
—
V
IOH  -3 mA, VDD = 3.3V
(See Note 1)
1.5
—
—
V
IOH  -16 mA, VDD = 3.3V
(See Note 1)
2.0
—
—
V
IOH  -12 mA, VDD = 3.3V
(See Note 1)
3.0
—
—
V
IOH  -4 mA, VDD = 3.3V
(See Note 1)
1.5
—
—
V
IOH  -30 mA, VDD = 3.3V
(See Note 1)
2.0
—
—
V
IOH  -25 mA, VDD = 3.3V
(See Note 1)
3.0
—
—
V
IOH  -8 mA, VDD = 3.3V
(See Note 1)
Parameters are characterized, but not tested.
TABLE 27-11: ELECTRICAL CHARACTERISTICS: BROWN-OUT RESET (BOR)
DC CHARACTERISTICS
Param
No.
Symbol
Standard Operating Conditions: 3.0V to 3.6V(3)
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Characteristic
BOR Event on VDD Transition
High-to-Low
Min(1)
Typ
Max
Units
2.6
—
2.95
V
Conditions
See Note 2
BO10
VBOR
Note 1:
2:
3:
Parameters are for design guidance only and are not tested in manufacturing.
The device will operate as normal until the VDDMIN threshold is reached.
Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device
analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN.
DS70000591F-page 380
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-12: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
Program Flash Memory
D130
EP
Cell Endurance
10,000
—
—
E/W
D131
VPR
VDD for Read
VMIN
—
3.6
V
VMIN = Minimum operating
voltage
D132B
VPEW
VDD for Self-Timed Write
VMIN
—
3.6
V
VMIN = Minimum operating
voltage
D134
TRETD
Characteristic Retention
20
—
—
Year
D135
IDDP
Supply Current during
Programming
—
10
—
mA
D136a
TRW
Row Write Time
1.488
—
1.518
ms
TRW = 11064 FRC cycles,
TA = +85°C (See Note 2)
D136b
TRW
Row Write Time
1.473
—
1.533
ms
TRW = 11064 FRC cycles,
TA = +125°C (See Note 2)
D137a
TPE
Page Erase Time
22.7
—
23.1
ms
TPE = 168517 FRC cycles,
TA = +85°C (See Note 2)
D137b
TPE
Page Erase Time
22.4
—
23.3
ms
TPE = 168517 FRC cycles,
TA = +125°C (See Note 2)
D138a
TWW
Word Write Cycle Time
47.7
—
48.7
µs
TWW = 355 FRC cycles,
TA = +85°C (See Note 2)
D138b
TWW
Word Write Cycle Time
47.3
—
49.2
µs
TWW = 355 FRC cycles,
TA = +125°C (See Note 2)
Note 1:
2:
-40C to +125C
Provided no other specifications
are violated, -40C to +125C
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
Other conditions: FRC = 7.37 MHz, TUN<5:0> = b'011111 (for Min.), TUN<5:0> = b'100000 (for Max.).
This parameter depends on the FRC accuracy (see Table 27-20) and the value of the FRC Oscillator
Tuning register (see Register 9-4). For complete details on calculating the minimum and maximum time,
see Section 5.3 “Programming Operations”.
TABLE 27-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions:
Param
No.
—
Note 1:
Symbol
CEFC
-40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Characteristics
External Filter Capacitor
Value(1)
Min
Typ
Max
Units
22
—
—
µF
Comments
Capacitor must be low
series resistance
(< 0.5 Ohms)
Typical VCAP voltage = 2.5 volts when VDD  VDDMIN.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 381
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
27.2
AC Characteristics and Timing Parameters
This section defines dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 AC characteristics and
timing parameters.
TABLE 27-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Operating voltage VDD range as described in Section 27.0 “Electrical
Characteristics”.
AC CHARACTERISTICS
FIGURE 27-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
VSS
TABLE 27-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
Conditions
DO50
COSCO
OSC2 Pin
—
—
15
pF
In XT and HS modes, when
external clock is used to drive
OSC1
DO56
CIO
All I/O Pins and OSC2
—
—
50
pF
EC mode
DO58
CB
SCLx, SDAx
—
—
400
pF
In I2C™ mode
DS70000591F-page 382
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-2:
EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
Q1
Q2
OS30
OS30
Q3
Q4
OSC1
OS20
OS31
OS31
OS25
CLKO
OS41
OS40
TABLE 27-16: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
OS10
Symb
FIN
OS20
TOSC
Min
Typ(1)
Max
Units
External CLKI Frequency
(external clocks allowed only
in EC and ECPLL modes)
DC
—
40
MHz
EC
Oscillator Crystal Frequency
3.5
—
10
—
—
—
10
33
40
MHz
kHz
MHz
XT
SOSC
HS
TOSC = 1/FOSC
12.5
—
DC
ns
Characteristic
Time(2)
Conditions
OS25
TCY
Instruction Cycle
25
—
DC
ns
OS30
TosL,
TosH
External Clock in (OSC1)
High or Low Time
0.375 x TOSC
—
0.625 x TOSC
ns
EC
OS31
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time
—
—
20
ns
EC
OS40
TckR
CLKO Rise Time(3)
—
5.2
—
ns
OS41
TckF
CLKO Fall Time(3)
—
5.2
—
ns
OS41
GM
External Oscillator
Transconductance
14
16
18
mA/V
Note 1:
2:
3:
VDD = 3.3V,
TA = +25ºC
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type, under standard operating conditions,
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “Min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“Max.” cycle time limit is “DC” (no clock) for all devices.
Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 383
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
OS50
Characteristic
Min
Typ(1)
Max
Units
FPLLI
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
0.8
—
8
MHz
OS51
FSYS
On-Chip VCO System
Frequency
100
—
200
MHz
OS52
TLOCK
PLL Start-up Time (Lock Time)
0.9
1.5
3.1
mS
-3
0.5
3
%
OS53
DCLK
Note 1:
2:
CLKO Stability (Jitter)
(2)
Conditions
ECPLL, XTPLL modes
Measured over a 100 ms
period
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested in manufacturing.
These parameters are characterized by similarity, but are not tested in manufacturing. This specification is
based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time
bases or communication clocks, use this formula:
D CLK
Peripheral Clock Jitter = -----------------------------------------------------------------------F OSC
 -------------------------------------------------------------
 Peripheral Bit Rate Clock
For example: FOSC = 32 MHz, DCLK = 3%, SPI bit rate clock (i.e., SCK) is 2 MHz.
D CLK
3%
3%
SPI SCK Jitter = ------------------------------ = ---------- = -------- = 0.75%
4
16
32
MHz
 --------------------
 2 MHz 
TABLE 27-18: AUXILIARY PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max
Units
OS56
FHPOUT
On-Chip, 16x PLL CCO
Frequency
112
118
120
MHz
OS57
FHPIN
On-Chip, 16x PLL Phase
Detector Input Frequency
7.0
7.37
7.5
MHz
OS58
TSU
Frequency Generator Lock
Time
—
—
10
µs
Note 1:
Conditions
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested in manufacturing.
DS70000591F-page 384
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-19: AC CHARACTERISTICS: INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C  TA +85°C for industrial
-40°C  TA  +125°C for Extended
Min
Typ
Max
Units
Conditions
Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1)
F20a
FRC
-1
—
+1
%
-40°C  TA +85°C
VDD = 3.0-3.6V
F20b
FRC
-2
—
+2
%
-40°C  TA +125°C
VDD = 3.0-3.6V
Note 1:
Frequency calibrated at +25°C and 3.3V. The TUN<5:0> bits can be used to compensate for temperature
drift.
TABLE 27-20: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Min
Typ
Max
Units
Conditions
LPRC @ 32.768 kHz(1)
F21a
LPRC
-40
—
+40
%
-40°C  TA +85°C
F21b
LPRC
-50
—
+50
%
-40°C  TA +125°C
Note 1:
Change of LPRC frequency as VDD changes.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 385
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-3:
I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
Old Value
New Value
DO31
DO32
Note: Refer to Figure 27-1 for load conditions.
TABLE 27-21: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Min
Typ(1)
Max
Units
4x Source Driver Pins – RA0-RA7,
RA14, RA15, RB0-RB15, RC1-RC4,
RC12-RC14, RD0-RD2, RD8-RD12,
RD14, RD15, RE8, RE9, RF0-RF8,
RF12, RF13, RG0-RG3, RG6-RG9,
RG14, RG15
—
10
25
ns
8x Source Driver Pins – RC15
—
8
20
ns
16x Source Driver Pins – RE0-RE7,
RG12, RG13
—
6
15
ns
4x Source Driver Pins – RA0-RA7,
RA14, RA15, RB0-RB15, RC1-RC4,
RC12-RC14, RD0-RD2, RD8-RD12,
RD14, RD15, RE8, RE9, RF0-RF8,
RF12, RF13, RG0-RG3, RG6-RG9,
RG14, RG15
—
10
25
ns
8x Source Driver Pins – RC15
—
8
20
ns
16x Source Driver Pins – RE0-RE7,
RG12, RG13
—
6
15
ns
TINP
INTx Pin High or Low Time (input)
20
—
—
ns
DI40
TRBP
CNx High or Low Time (input)
2
—
—
TCY
Note 1:
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
DO31
DO32
DI35
Symbol
TIOR
TIOF
DS70000591F-page 386
Characteristic
Conditions
Port Output Rise Time
Refer to Figure 27-1
for test conditions
Port Output Fall Time
Refer to Figure 27-1
for test conditions
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-4:
VDD
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS
SY12
MCLR
SY10
Internal
POR
SY11
PWRT
Time-out
OSC
Time-out
SY30
Internal
Reset
Watchdog
Timer Reset
SY13
SY20
SY13
I/O Pins
FSCM
Delay
SY35
Note: Refer to Figure 27-1 for load conditions.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 387
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SY10
TMCL
MCLR Pulse Width (low)
2
—
—
s
-40°C to +85°C
SY11
TPWRT
Power-up Timer Period
—
2
4
8
16
32
64
128
—
ms
-40°C to +85°C,
User programmable
SY12
TPOR
Power-on Reset Delay
3
10
30
s
-40°C to +85°C
SY13
TIOZ
I/O High-Impedance from
MCLR Low or Watchdog
Timer Reset
0.68
0.72
1.2
s
SY20
TWDT1
Watchdog Timer Time-out
Period
—
—
—
ms
See Section 24.4 “Watchdog
Timer (WDT)” and LPRC
Parameter F21a (Table 27-20)
SY30
TOST
Oscillator Start-up Time
—
1024 TOSC
—
—
TOSC = OSC1 period
Note 1:
2:
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
DS70000591F-page 388
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-5:
TIMER1/2/3 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx10
Tx11
Tx15
OS60
Tx20
TMRx
Note: Refer to Figure 27-1 for load conditions.
TABLE 27-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
TA10
Symbol
TTXH
Characteristic
T1CK High Time Synchronous,
no Prescaler
Synchronous,
with Prescaler
Asynchronous
TA11
TTXL
TTXP
T1CK Input
Period
Typ
Max
Units
Conditions
TCY + 20
—
—
ns
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TA15,
N = Prescale value
(1, 8, 64, 256)
20
—
—
ns
(TCY + 20)
—
—
ns
(TCY + 20)/N
—
—
ns
Asynchronous
20
—
—
ns
Synchronous,
no Prescaler
2 TCY + 40
—
—
ns
Synchronous,
with Prescaler
Greater of:
40 ns or
(2 TCY + 40)/N
—
—
—
40
—
—
ns
DC
—
50
kHz
—
1.75 TCY + 40
—
T1CK Low Time Synchronous,
no Prescaler
Synchronous,
with Prescaler
TA15
Min
Asynchronous
OS60
Ft1
TA20
TCKEXTMRL Delay from External T1CK Clock 0.75 TCY + 40
Edge to Timer Increment
Note 1:
SOSCI/T1CK Oscillator Input
Frequency Range (oscillator
enabled by setting bit, TCS
(T1CON<1>))
Must also meet
Parameter TA15,
N = Prescale value
(1, 8, 64, 256)
N = Prescale value
(1, 8, 64, 256)
Timer1 is a Type A.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 389
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-24: TIMER2/4 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
Min
Typ
Max
Units
Conditions
TB10
TtxH
TxCK High Synchronous
Time
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TB15,
N = Prescale value
(1, 8, 64, 256)
TB11
TtxL
TxCK Low
Time
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TB15,
N = Prescale value
(1, 8, 64, 256)
TB15
TtxP
TxCK Input Synchronous
Period
mode
Greater of:
40 or
(2 TCY + 40)/N
—
—
ns
N = Prescale value
(1, 8, 64, 256)
TB20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
0.75 TCY + 40
—
1.75 TCY + 40
ns
Note 1:
Synchronous
mode
These parameters are characterized, but are not tested in manufacturing.
TABLE 27-25: TIMER3/5 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
Conditions
TC10
TtxH
TxCK High
Time
Synchronous
TCY + 20
—
—
ns
Must also meet
Parameter TC15
TC11
TtxL
TxCK Low
Time
Synchronous
TCY + 20
—
—
ns
Must also meet
Parameter TC15
TC15
TtxP
TxCK Input
Period
Synchronous,
with Prescaler
2 TCY + 40
—
—
ns
TC20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
0.75 TCY + 40
—
1.75 TCY + 40
ns
Note 1:
These parameters are characterized, but are not tested in manufacturing.
DS70000591F-page 390
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-6:
INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 27-1 for load conditions.
TABLE 27-26: INPUT CAPTURE x TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
IC10
TccL
Characteristic(1)
ICx Input Low Time
No Prescaler
With Prescaler
IC11
TccH
ICx Input High Time No Prescaler
With Prescaler
IC15
TccP
Note 1:
ICx Input Period
Min
Max
Units
0.5 TCY + 20
—
ns
10
—
ns
0.5 TCY + 20
—
ns
10
—
ns
(TCY + 40)/N
—
ns
Conditions
N = Prescale value
(1, 4, 16)
These parameters are characterized but not tested in manufacturing.
FIGURE 27-7:
OUTPUT COMPARE x (OCx) MODULE TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC11
OC10
Note: Refer to Figure 27-1 for load conditions.
TABLE 27-27: OUTPUT COMPARE x MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Min
Typ
Max
Units
Conditions
OC10
TccF
OCx Output Fall Time
—
—
—
ns
See Parameter DO32
OC11
TccR
OCx Output Rise Time
—
—
—
ns
See Parameter DO31
Note 1:
These parameters are characterized but not tested in manufacturing.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 391
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-8:
OUTPUT COMPARE x/PWMx MODULE TIMING CHARACTERISTICS
OC20
OCFA
OC15
OCx
Active
Tri-State
TABLE 27-28: SIMPLE OCx/PWMx MODE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
OC15
TFD
Fault Input to PWM I/O
Change
—
—
TCY + 20
ns
OC20
TFLT
Fault Input Pulse Width
TCY + 20
—
—
ns
Note 1:
These parameters are characterized but not tested in manufacturing.
DS70000591F-page 392
Conditions
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-9:
HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS
MP30
FLTx
MP20
PWMx
FIGURE 27-10:
HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS
MP11
MP10
PWMx
Note: Refer to Figure 27-1 for load conditions.
TABLE 27-29: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
—
ns
MP10
TFPWM
PWMx Output Fall Time
—
2.5
MP11
TRPWM
PWMx Output Rise Time
—
2.5
—
ns
MP20
TFD
Fault Input  to PWMx
I/O Change
—
—
15
ns
MP30
TFH
Minimum PWMx Fault Pulse
Width
8
—
—
ns
MP31
TPDLY
Tap Delay
1.04
—
—
ns
MP32
ACLK
PWMx Input Clock
—
—
120
MHz
Note 1:
2:
Conditions
DTC<1:0> = 10
ACLK = 120 MHz
See Note 2
These parameters are characterized but not tested in manufacturing.
This parameter is a maximum allowed input clock for the PWM module.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 393
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-30: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Maximum
Data Rate
Master
Transmit Only
(Half-Duplex)
Master
Transmit/Receive
(Full-Duplex)
Slave
Transmit/Receive
(Full-Duplex)
CKE
CKP
SMP
15 MHz
Table 27-31
—
—
0,1
0,1
0,1
10 MHz
—
Table 27-32
—
1
0,1
1
10 MHz
—
Table 27-33
—
0
0,1
1
15 MHz
—
—
Table 27-34
1
0
0
11 MHz
—
—
Table 27-35
1
1
0
15 MHz
—
—
Table 27-36
0
1
0
11 MHz
—
—
Table 27-37
0
0
0
FIGURE 27-11:
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0) TIMING
CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
SP30, SP31
LSb
SP30, SP31
Note: Refer to Figure 27-1 for load conditions.
FIGURE 27-12:
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING
CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
SDOx
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
Note: Refer to Figure 27-1 for load conditions.
DS70000591F-page 394
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-31: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP10
TscP
Maximum SCKx Frequency
—
—
15
MHz
SP20
TscF
SCKx Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
—
6
20
ns
SP36
TdiV2scH,
TdiV2scL
SDOx Data Output Setup to
First SCKx Edge
30
—
—
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 395
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-13:
SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
MSb
SDOx
LSb
SP30, SP31
SP40
SDIx
Bit 14 - - - - - -1
MSb In
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 27-1 for load conditions.
TABLE 27-32: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
See Parameter DO32
and Note 4
See Parameter DO31
and Note 4
See Parameter DO32
and Note 4
See Parameter DO31
and Note 4
SP10
SP20
TscP
TscF
Maximum SCKx Frequency
SCKx Output Fall Time
—
—
—
—
10
—
MHz
ns
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
SP35
TscH2doV, SDOx Data Output Valid after
—
6
20
ns
TscL2doV SCKx Edge
TdoV2sc, SDOx Data Output Setup to
30
—
—
ns
TdoV2scL First SCKx Edge
TdiV2scH, Setup Time of SDIx Data
30
—
—
ns
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
30
—
—
ns
TscL2diL
to SCKx Edge
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this
specification.
Assumes 50 pF load on all SPIx pins.
SP36
SP40
SP41
Note 1:
2:
3:
4:
DS70000591F-page 396
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-14:
SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING
CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
SP30, SP31
SDIx
MSb In
LSb
Bit 14 - - - - - -1
MSb
SDOx
SP30, SP31
LSb In
Bit 14 - - - -1
SP40 SP41
Note: Refer to Figure 27-1 for load conditions.
TABLE 27-33: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING
REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
-40ºC to +125ºC and
see Note 3
See Parameter DO32
and Note 4
See Parameter DO31
and Note 4
See Parameter DO32
and Note 4
See Parameter DO31
and Note 4
SP10
TscP
Maximum SCKx Frequency
—
—
10
MHz
SP20
TscF
SCKx Output Fall Time
—
—
—
ns
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
SP35
TscH2doV, SDOx Data Output Valid after
—
6
20
ns
TscL2doV SCKx Edge
TdoV2scH, SDOx Data Output Setup to
30
—
—
ns
TdoV2scL First SCKx Edge
TdiV2scH, Setup Time of SDIx Data
30
—
—
ns
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
30
—
—
ns
TscL2diL
to SCKx Edge
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this
specification.
Assumes 50 pF load on all SPIx pins.
SP36
SP40
SP41
Note 1:
2:
3:
4:
 2009-2014 Microchip Technology Inc.
DS70000591F-page 397
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-15:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP30, SP31
SDIx
MSb In
Bit 14 - - - -1
SP51
LSb In
SP41
SP40
Note: Refer to Figure 27-1 for load conditions.
DS70000591F-page 398
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscP
Maximum SCKx Input Frequency
—
—
15
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx  to SCKx  or SCKx Input
120
—
—
ns
SP51
TssH2doZ
SSx  to SDOx Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
SP60
TssL2doV SDOx Data Output Valid after
SSx Edge
—
—
50
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock, generated by the master, must
not violate this specification.
Assumes 50 pF load on all SPIx pins.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 399
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-16:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING
CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
SP52
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP51
SP30, SP31
SDIx
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
Note: Refer to Figure 27-1 for load conditions.
DS70000591F-page 400
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING
REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscP
Maximum SCKx Input Frequency
—
—
11
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx  to SCKx  or SCKx Input
120
—
—
ns
SP51
TssH2doZ
SSx  to SDOx Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
SP60
TssL2doV SDOx Data Output Valid after
SSx Edge
—
—
50
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock, generated by the master, must
not violate this specification.
Assumes 50 pF load on all SPIx pins.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 401
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-17:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING
CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
SDOX
Bit 14 - - - - - -1
MSb
LSb
SP51
SP30, SP31
SDIX
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
Note: Refer to Figure 27-1 for load conditions.
DS70000591F-page 402
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING
REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscP
Maximum SCKx Input Frequency
—
—
15
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx  to SCKx  or SCKx Input
120
—
—
ns
SP51
TssH2doZ
SSx  to SDOx Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock, generated by the master, must
not violate this specification.
Assumes 50 pF load on all SPIx pins.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 403
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-18:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
SDOX
MSb
Bit 14 - - - - - -1
LSb
SP51
SP30, SP31
SDIX
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
Note: Refer to Figure 27-1 for load conditions.
DS70000591F-page 404
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-37: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING
REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscP
Maximum SCKx Input Frequency
—
—
11
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx  to SCKx  or SCKx Input
120
—
—
ns
SP51
TssH2doZ
SSx  to SDOx Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock, generated by the master, must
not violate this specification.
Assumes 50 pF load on all SPIx pins.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 405
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-19:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Start
Condition
Stop
Condition
Note: Refer to Figure 27-1 for load conditions.
FIGURE 27-20:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM10
IM25
IM33
SDAx
In
IM40
IM40
IM45
SDAx
Out
Note: Refer to Figure 27-1 for load conditions.
DS70000591F-page 406
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-38: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
IM10
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
IM40
IM45
IM50
IM51
Note
Characteristic
Min(1)
Max
Units
Conditions
—
s
TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1)
400 kHz mode TCY/2 (BRG + 1)
—
s
(2)
1 MHz mode
TCY/2 (BRG + 1)
—
s
—
s
THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1)
400 kHz mode TCY/2 (BRG + 1)
—
s
1 MHz mode(2) TCY/2 (BRG + 1)
—
s
SDAx and SCLx 100 kHz mode
—
300
ns
CB is specified to be
TF:SCL
Fall Time
from 10 to 400 pF
400 kHz mode
20 + 0.1 CB
300
ns
(2)
1 MHz mode
—
100
ns
TR:SCL SDAx and SCLx 100 kHz mode
—
1000
ns
CB is specified to be
Rise Time
from 10 to 400 pF
400 kHz mode
20 + 0.1 CB
300
ns
(2)
1 MHz mode
—
300
ns
TSU:DAT Data Input
100 kHz mode
250
—
ns
Setup Time
400 kHz mode
100
—
ns
(2)
1 MHz mode
40
—
ns
THD:DAT Data Input
100 kHz mode
0
—
s
Hold Time
400 kHz mode
0
0.9
s
1 MHz mode(2)
0.2
—
s
TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
—
s
Only relevant for
Setup Time
Repeated Start
400 kHz mode TCY/2 (BRG + 1)
—
s
condition
(2)
1 MHz mode
TCY/2 (BRG + 1)
—
s
THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
—
s
After this period, the
Hold Time
first clock pulse is
400 kHz mode TCY/2 (BRG + 1)
—
s
generated
(2)
1 MHz mode
TCY/2 (BRG + 1)
—
s
TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1)
—
s
Setup Time
400 kHz mode TCY/2 (BRG + 1)
—
s
(2)
1 MHz mode
TCY/2 (BRG + 1)
—
s
—
ns
THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1)
Hold Time
400 kHz mode TCY/2 (BRG + 1)
—
ns
1 MHz mode(2) TCY/2 (BRG + 1)
—
ns
100 kHz mode
—
3500
ns
TAA:SCL Output Valid
from Clock
400 kHz mode
—
1000
ns
1 MHz mode(2)
—
400
ns
4.7
—
s
Time the bus must be
TBF:SDA Bus Free Time 100 kHz mode
free before a new
400 kHz mode
1.3
—
s
transmission can start
(2)
1 MHz mode
0.5
—
s
Bus Capacitive Loading
—
400
pF
CB
TPGD
Pulse Gobbler Delay
65
390
ns
See Note 3
2
1: BRG is the value of the I C™ Baud Rate Generator. Refer to “Inter-Integrated Circuit™ (I2C™)”
(DS70000195) in the “dsPIC33/PIC24 Family Reference Manual”.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
3: Typical value for this parameter is 130 ns.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 407
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-21:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
FIGURE 27-22:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS25
IS33
SDAx
In
IS40
IS40
IS45
SDAx
Out
DS70000591F-page 408
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-39: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param. Symbol
IS10
IS11
IS20
IS21
IS25
IS26
TLO:SCL
THI:SCL
TF:SCL
TR:SCL
TSU:DAT
Characteristic
Clock Low Time
Clock High Time
SDAx and SCLx
Fall Time
SDAx and SCLx
Rise Time
Data Input
Setup Time
THD:DAT Data Input
Hold Time
Min
Max
Units
100 kHz mode
4.7
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
s
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
—
s
100 kHz mode
4.0
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
s
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
—
s
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
100
ns
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode(1)
100
—
ns
100 kHz mode
0
—
s
400 kHz mode
0
0.9
s
(1)
1 MHz mode
IS30
IS31
IS33
IS34
TSU:STA
Start Condition
Setup Time
THD:STA Start Condition
Hold Time
TSU:STO
Stop Condition
Setup Time
THD:STO Stop Condition
Hold Time
100 kHz mode
IS45
IS50
Note 1:
TAA:SCL
Output Valid
From Clock
TBF:SDA Bus Free Time
CB
0
0.3
s
4.7
—
s
400 kHz mode
0.6
—
s
1 MHz mode(1)
0.25
—
s
100 kHz mode
4.0
—
s
400 kHz mode
0.6
—
s
1 MHz mode(1)
0.25
—
s
100 kHz mode
4.7
—
s
400 kHz mode
0.6
—
s
1 MHz mode(1)
0.6
—
s
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
(1)
250
1 MHz mode
IS40
Conditions
CB is specified to be from
10 to 400 pF
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
ns
100 kHz mode
0
3500
ns
400 kHz mode
0
1000
ns
1 MHz mode(1)
0
350
ns
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
1 MHz mode(1)
0.5
—
s
—
400
pF
Bus Capacitive Loading
CB is specified to be from
10 to 400 pF
Time the bus must be free
before a new transmission
can start
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
 2009-2014 Microchip Technology Inc.
DS70000591F-page 409
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-40: 10-BIT, HIGH-SPEED ADC MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V and 3.6V(2)
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply
Greater of:
VDD – 0.3
or 3.0
—
Lesser of
VDD + 0.3
or 3.6
V
AD02
AVSS
Module VSS Supply
Vss – 0.3
—
VSS + 0.3
V
Analog Input
AD10
VINH-VINL Full-Scale Input Span
AD11
VIN
Absolute Input Voltage
AD12
IAD
AD13
—
VSS
—
VDD
V
AVSS
—
AVDD
V
Operating Current
—
8
—
mA
Leakage Current
—
±0.6
—
A
—
—
100

AD17
RIN
Recommended Impedance
of Analog Voltage Source
AD20
Nr
Resolution
VINL = AVSS = 0V,
AVDD = 3.3V,
Source Impedance = 100
DC Accuracy
10 data bits
bits
AD21A INL
Integral Nonlinearity
> -2
±0.5
<2
LSb VINL = AVSS = 0V,
AVDD = 3.3V
AD22A DNL
Differential Nonlinearity
> -1
±0.5
<1
LSb VINL = AVSS = 0V,
AVDD = 3.3V
AD23A GERR
Gain Error
> -5
±2.0
<5
LSb VINL = AVSS = 0V,
AVDD = 3.3V
AD24A EOFF
Offset Error
> -3
±0.75
<3
LSb VINL = AVSS = VSS = 0V,
AVDD = VDD = 3.3V
AD25
Monotonicity(1)
—
—
—
—
—
Guaranteed
Dynamic Performance
AD30
THD
Total Harmonic Distortion
—
-73
—
dB
AD31
SINAD
Signal to Noise and
Distortion
—
58
—
dB
AD32
SFDR
Spurious Free Dynamic
Range
—
-73
—
dB
AD33
FNYQ
Input Signal Bandwidth
—
—
1
MHz
AD34
ENOB
Effective Number of Bits
—
9.4
—
bits
Note 1:
2:
The Analog-to-Digital conversion result never decreases with an increase in the input voltage and has no
missing codes.
Overall functional device operation at VBOR < VDD < VDDMIN is ensured but not characterized. All device
analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN.
DS70000591F-page 410
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-41: 10-BIT, HIGH-SPEED ADC MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V(2)
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
—
ns
—
—
Conditions
Clock Parameters
AD50b TAD
ADC Clock Period
35.8
—
Conversion Rate
AD55b tCONV
Conversion Time
AD56b FCNV
Throughput Rate
—
14 TAD
Devices with Single SAR
—
—
2.0
Msps
Devices with Dual SARs
—
—
4.0
Msps
10
s
Timing Parameters
AD63b tDPU
Note 1:
2:
Time to Stabilize Analog Stage
from ADC Off to ADC On(1)
1.0
—
These parameters are characterized but not tested in manufacturing.
Overall functional device operation at VBOR < VDD < VDDMIN is guaranteed but not characterized. All
device analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN.
FIGURE 27-23:
ANALOG-TO-DIGITAL CONVERSION TIMING PER INPUT
TCONV
Trigger Pulse
TAD
ADC Clock
ADC Data
ADBUFx
9
Old Data
8
2
1
0
New Data
CONV
 2009-2014 Microchip Technology Inc.
DS70000591F-page 411
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-42: COMPARATOR MODULE SPECIFICATIONS
AC and DC CHARACTERISTICS
Param.
Symbol Characteristic
No.
Standard Operating Conditions (unless otherwise stated)
Operating temperature: -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Min
Typ
Max
Units
CM10
VIOFF
Input Offset Voltage
±5
±15
mV
CM11
VICM
Input Common-Mode
Voltage Range(1)
0
—
AVDD – 1.5
V
CM12
VGAIN
Open-Loop Gain(1)
90
—
—
db
CM13
CMRR
Common-Mode
Rejection Ratio(1)
70
—
—
db
CM14
TRESP
Large Signal Response
20
30
ns
Note 1:
Comments
V+ input step of 100 mv while
V- input held at AVDD/2. Delay
measured from analog input pin
to PWM output pin.
Parameters are for design guidance only and are not tested in manufacturing.
TABLE 27-43: DAC MODULE SPECIFICATIONS
AC and DC CHARACTERISTICS
Param
. No.
Symbol
Characteristic
Standard Operating Conditions (unless otherwise stated)
Operating temperature: -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Min
Typ
Max
Units
0
—
AVDD – 1.6
V
1.25
1.32
1.41
V
DA01
EXTREF External Reference Voltage(1)
DA08
INTREF
Internal Reference Voltage(1)
DA02
CVRES
Resolution
DA03
INL
Integral Nonlinearity Error
—
±1.0
—
—
10 data bits
bits
DA04
DNL
Differential Nonlinearity Error
—
±0.8
—
LSB
DA05
EOFF
Offset Error
—
±2.0
—
LSB
DA06
EG
Gain Error
—
±2.0
—
LSB
DA07
TSET
Settling Time(1)
—
—
650
nsec
Note 1:
Comments
AVDD = 3.3V,
DACREF = (AVDD/2)V
Measured when range = 1
(high range) and
CMREF<9:0> transitions
from 0x1FF to 0x300.
Parameters are for design guidance only and are not tested in manufacturing.
DS70000591F-page 412
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-44: DAC OUTPUT BUFFER SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Operating temperature: -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Param.
Symbol Characteristic
No.
Min
Typ
Max
Units
DA10
RLOAD
Resistive Output Load
Impedance
3K
—
—

DA11
CLOAD
Output Load
Capacitance
—
20
35
pF
DA12
IOUT
Output Current Drive
Strength
200
300
400
A
DA13
VRANGE
Full Output Drive
Strength Voltage Range
AVSS + 250 mV
—
AVDD – 900 mV
V
DA14
VLRANGE Output Drive Voltage
Range at Reduced
Current Drive of 50 A
AVSS + 50 mV
—
AVDD – 500 mV
V
DA15
IDD
Current Consumed when
Module is Enabled,
High-Power Mode
—
—
1.3 x IOUT
A
DA16
ROUTON Output Impedance when
Module is Enabled
—
500
—

FIGURE 27-24:
Comments
Sink and source
Module will always
consume this current
even if no load is
connected to the
output
QEA/QEB INPUT CHARACTERISTICS
TQ36
QEA
(input)
TQ30
TQ31
TQ35
QEB
(input)
TQ40
TQ41
TQ31
TQ30
TQ35
QEB
Internal
 2009-2014 Microchip Technology Inc.
DS70000591F-page 413
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-45: QUADRATURE DECODER TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
Typ(2)
Max
Units
Conditions
TQ30
TQUL
Quadrature Input Low Time
6 TCY
—
ns
TQ31
TQUH
Quadrature Input High Time
6 TCY
—
ns
TQ35
TQUIN
Quadrature Input Period
12 TCY
—
ns
TQ36
TQUP
Quadrature Phase Period
3 TCY
—
ns
TQ40
TQUFL
Filter Time to Recognize Low,
with Digital Filter
3 * N * TCY
—
ns
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 3)
TQ41
TQUFH
Filter Time to Recognize High,
with Digital Filter
3 * N * TCY
—
ns
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 3)
Note 1:
2:
3:
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
N = Index Channel Digital Filter Clock Divide Select bits. Refer to “Quadrature Encoder Interface (QEI)”
(DS70208) in the “dsPIC33/PIC24 Family Reference Manual”.
FIGURE 27-25:
QEI MODULE INDEX PULSE TIMING CHARACTERISTICS
QEA
(input)
QEB
(input)
Ungated
Index
TQ50
TQ51
Index Internal
TQ55
Position Counter
Reset
DS70000591F-page 414
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-46: QEI INDEX PULSE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
TQ50
TqIL
TQ51
TQ55
Note 1:
2:
Characteristic(1)
Min
Max
Units
Conditions
Filter Time to Recognize Low,
with Digital Filter
3 * N * TCY
—
ns
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 2)
TqiH
Filter Time to Recognize High,
with Digital Filter
3 * N * TCY
—
ns
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 2)
Tqidxr
Index Pulse Recognized to Position
Counter Reset (ungated index)
3 TCY
—
ns
These parameters are characterized but not tested in manufacturing.
Alignment of index pulses to QEA and QEB is shown for Position Counter Reset timing only. Shown for
forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but
index pulse recognition occurs on the falling edge.
FIGURE 27-26:
TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS
QEB
TQ11
TQ10
TQ15
TQ20
POSCNT
TABLE 27-47: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
Conditions
TQ10
TtQH
TQCK High Time
Synchronous,
with Prescaler
TCY + 20
—
—
ns
Must also meet
Parameter TQ15
TQ11
TtQL
TQCK Low Time
Synchronous,
with Prescaler
TCY + 20
—
—
ns
Must also meet
Parameter TQ15
TQ15
TtQP
TQCP Input
Period
Synchronous, 2 * TCY + 40
with Prescaler
—
—
ns
TQ20
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
—
1.5 TCY
—
Note 1:
0.5 TCY
These parameters are characterized but not tested in manufacturing.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 415
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-27:
ECAN™ MODULE I/O TIMING CHARACTERISTICS
CxTx Pin
(output)
New Value
Old Value
CA10
CA11
CxRx Pin
(input)
CA20
TABLE 27-48: ECAN™ MODULE I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
Min
Typ
Max
Units
Conditions
CA10
TioF
Port Output Fall Time
—
—
—
ns
See Parameter DO32
CA11
TioR
Port Output Rise Time
—
—
—
ns
See Parameter DO31
CA20
Tcwf
Pulse Width to Trigger
CAN Wake-up Filter
120
—
—
ns
Note 1:
These parameters are characterized but not tested in manufacturing.
TABLE 27-49: DMA READ/WRITE TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
DM1
Characteristic
DMA Read/Write Cycle Time
DS70000591F-page 416
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Min.
Typ
Max.
Units
—
—
1 TCY
ns
Conditions
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
28.0
50 MIPS ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
electrical characteristics for devices operating at 50 MIPS.
Specifications are identical to those shown in Section 27.0 “Electrical Characteristics”, with the exception of the
parameters listed in this section.
Absolute maximum ratings for the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 50 MIPS
devices are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability.
Functional operation of the device at these or any other conditions above the parameters indicated in the operation
listings of this specification is not implied.
Absolute Maximum Ratings(1)
Ambient temperature under bias.............................................................................................................. .-40°C to +85°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS(2) .................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD  3.0V(2) .................................................. -0.3V to +5.6V
Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(2)......................................... -0.3V to (VDD + 0.3V)
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2) ...........................................................................................................................250 mA
Maximum current sourced/sunk by any 4x I/O pin ..................................................................................................15 mA
Maximum current sourced/sunk by any 8x I/O pin ..................................................................................................25 mA
Maximum current sourced/sunk by any 16x I/O pin ................................................................................................45 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports(2) ...............................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: See the “Pin Diagrams” section for 5V tolerant pins.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 417
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
28.1
DC Characteristics
TABLE 28-1:
OPERATING MIPS vs. VOLTAGE
Max MIPS
Characteristic
VDD Range
(in Volts)
Temp Range
(in °C)
—
3.0-3.6V(1)
-40°C to +85°C
Note 1:
dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610
50
Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device
analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. See
Parameter BO10 in Table 27-11 for the BOR values.
TABLE 28-2:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
DC CHARACTERISTICS
Parameter
No.
Typical
Max
Units
Conditions
Operating Current (IDD)(1)
MDC29d
85
100
mA
-40°C
MDC29a
85
100
mA
+25°C
85
100
mA
+85°C
MDC29b
Note 1:
3.3V
50 MIPS
IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDD measurements are as follows:
• Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from
rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are
zeroed)
• CPU executing while(1) statement
• JTAG is disabled
DS70000591F-page 418
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 28-3:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
DC CHARACTERISTICS
Parameter
No.
Typical
Max
Units
Conditions
Idle Current (IIDLE): Core Off Clock On Base Current(1)
MDC45d
40
50
mA
-40°C
MDC45a
40
50
mA
+25°C
40
50
mA
+85°C
MDC45b
Note 1:
3.3V
50 MIPS
Base Idle current (IIDLE) is measured as follows:
• CPU core is off, oscillator is configured in EC mode and external clock is active, OSC1 is driven with
external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD, WDT and FSCM are disabled
• No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits
are ‘0’s)
• JTAG is disabled
 2009-2014 Microchip Technology Inc.
DS70000591F-page 419
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 28-4:
DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
DC CHARACTERISTICS
Parameter No.
Typical
Max
Doze
Ratio
Units
Conditions
Doze Current (IDOZE)(1)
MDC74a
49
70
1:2
mA
MDC74f
43
70
1:64
mA
MDC74g
43
70
1:128
mA
MDC75a
47
70
1:2
mA
MDC75f
41
70
1:64
mA
MDC75g
41
70
1:128
mA
MDC76a
46
70
1:2
mA
MDC76f
40
70
1:64
mA
40
70
1:128
mA
MDC76g
Note 1:
-40°C
3.3V
50 MIPS
+25°C
3.3V
50 MIPS
+85°C
3.3V
50 MIPS
IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDOZE measurements are as follows:
• Oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square
wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits
are ‘0’s)
• CPU executing while(1) statement
• JTAG is disabled
DS70000591F-page 420
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
28.2
AC Characteristics and Timing Parameters
This section defines the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 AC characteristics
and timing parameters for 50 MIPS devices.
TABLE 28-5:
EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param
No.
MOS10
MOS20
Symb
FIN
TOSC
Min
Typ(1)
Max
Units
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
—
50
MHz
EC
Oscillator Crystal Frequency
3.5
—
10
—
—
—
10
33
50
MHz
kHz
MHz
XT
SOSC
HS
TOSC = 1/FOSC
10
—
DC
ns
Characteristic
Time(2)
Conditions
MOS25
TCY
Instruction Cycle
20
—
DC
ns
MOS30
TosL,
TosH
External Clock in (OSC1)
High or Low Time
0.375 x TOSC
—
0.625 x TOSC
ns
EC
MOS31
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time
—
—
20
ns
EC
MOS40
TckR
CLKO Rise Time(3)
—
5.2
—
ns
MOS41
TckF
CLKO Fall Time(3)
—
5.2
—
ns
MOS41
GM
External Oscillator
Transconductance
14
16
18
mA/V
Note 1:
2:
3:
VDD = 3.3V,
TA = +25ºC
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“max.” cycle time limit is “DC” (no clock) for all devices.
Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 421
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS70000591F-page 422
 2009-2014 Microchip Technology Inc.
DC AND AC DEVICE CHARACTERISTICS GRAPHS
Note:
The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes
only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating
range (e.g., outside specified power supply range) and therefore, outside the warranted range.
FIGURE 29-1:
VOH – 4x DRIVER PINS
-0.080
-0.030
3.6V
-0.070
-0.025
IOH (A)
IOH (A)
3V
-0.015
Absolute Maximum
-0.010
3.3V
-0.050
3V
Absolute Maximum
-0.040
-0.030
-0.020
-0.005
-0.010
0.000
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
FIGURE 29-2:
VOH – 8x DRIVER PINS
-0.040
3.6V
-0.030
3.3V
-0.025
Absolute Maximum
3V
-0.020
DS70000591F-page 423
-0.015
-0.010
-0.005
0.000
0.00
1.00
2.00
VOH (V)
0.000
0.00
1.00
2.00
VOH (V)
VOH (V)
IOH (A)
3.6V
-0.060
3.3V
-0.020
-0.035
VOH – 16x DRIVER PINS
FIGURE 29-3:
3.00
4.00
3.00
4.00
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
29.0
VOL – 4x DRIVER PINS
FIGURE 29-6:
0.120
0.040
0.035
3.6V
0.030
3.6V
0.100
3.3V
0.025
3.3V
0.080
3V
IOL (A)
IOL (A)
VOL – 16x DRIVER PINS
0.020
0.015
Absolute Maximum
3V
0.060
Absolute Maximum
0.040
0.010
0.020
0.005
0.000
0.00
1.00
2.00
3.00
4.00
VOL (V)
FIGURE 29-5:
0.060
3.6V
0.050
3.3V
IOL (A)
 2009-2014 Microchip Technology Inc.
3V
0.030
Absolute Maximum
0.020
0.010
0.000
0.00
1.00
2.00
VOL (V)
1.00
2.00
VOL (V)
VOL – 8x DRIVER PINS
0.040
0.000
0.00
3.00
4.00
3.00
4.00
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS70000591F-page 424
FIGURE 29-4:
TYPICAL IPD CURRENT @ VDD = 3.3V
FIGURE 29-9:
TYPICAL IIDLE CURRENT @ VDD = 3.3V
40
IPD Current (A)
Average Current (mA)
35
30
25
20
15
10
5
0
10
30
TYPICAL IDD CURRENT @ VDD = 3.3V
FIGURE 29-10:
TYPICAL FRC FREQUENCY @ VDD = 3.3V
90
FRC Frequency (MHz)
DS70000591F-page 425
Average Current (mA)
80
70
60
50
40
30
20
10
10
20
30
MIPS
40
MIPS
Temperature (Celsius)
FIGURE 29-8:
20
40
50
Temperature (Celsius)
50
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
 2009-2014 Microchip Technology Inc.
FIGURE 29-7:
FIGURE 29-12:
TYPICAL INTREF @ VDD = 3.3V
INTREF (V)
LPRC Frequency (kHz)
TYPICAL LPRC FREQUENCY @ VDD = 3.3V
Temperature (Celsius)
Temperature (Celsius)
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS70000591F-page 426
FIGURE 29-11:
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
30.0
PACKAGING INFORMATION
30.1
Package Marking Information
64-Lead QFN (9x9x0.9mm)
XXXXXXXXXX
XXXXXXXXXX
33FJ32GS
406-I/MR e3
YYWWNNN
1210017
64-Lead TQFP (10x10x1mm)
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
80-Lead TQFP (12x12x1mm)
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example
Example
dsPIC33FJ
32GS406
-I/PT e3
1210017
Example
33FJ32GS608
-I/PT e3
1210017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
If the full Microchip part number cannot be marked on one line, it is carried over to the next
line, thus limiting the number of available characters for customer-specific information.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 427
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
30.1
Package Marking Information (Continued)
100-Lead TQFP (12x12x1 mm)
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
100-Lead TQFP (14x14x1mm)
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
DS70000591F-page 428
Example
dsPIC33FJ64
GS608-I/PT e3
1210017
Example
33FJ32GS610
-I/PF e3
1210017
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
30.2
Package Details
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2009-2014 Microchip Technology Inc.
DS70000591F-page 429
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS70000591F-page 430
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2009-2014 Microchip Technology Inc.
DS70000591F-page 431
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
D1/2
D
NOTE 2
A
B
E1/2
E1
A
E
A
SEE DETAIL 1
N
4X N/4 TIPS
0.20 C A-B D
1 3
2
4X
NOTE 1
0.20 H A-B D
TOP VIEW
A2
A
0.05
C
SEATING
PLANE
0.08 C
64 X b
0.08
e
A1
C A-B D
SIDE VIEW
Microchip Technology Drawing C04-085C Sheet 1 of 2
DS70000591F-page 432
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
H
c
E
L
(L1)
T
X=A—B OR D
X
SECTION A-A
e/2
DETAIL 1
Notes:
Units
Dimension Limits
Number of Leads
N
e
Lead Pitch
Overall Height
A
Molded Package Thickness
A2
Standoff
A1
Foot Length
L
Footprint
L1
I
Foot Angle
Overall Width
E
Overall Length
D
Molded Package Width
E1
Molded Package Length
D1
c
Lead Thickness
b
Lead Width
D
Mold Draft Angle Top
E
Mold Draft Angle Bottom
MIN
0.95
0.05
0.45
0°
0.09
0.17
11°
11°
MILLIMETERS
NOM
64
0.50 BSC
1.00
0.60
1.00 REF
3.5°
12.00 BSC
12.00 BSC
10.00 BSC
10.00 BSC
0.22
12°
12°
MAX
1.20
1.05
0.15
0.75
7°
0.20
0.27
13°
13°
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-085C Sheet 2 of 2
 2009-2014 Microchip Technology Inc.
DS70000591F-page 433
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS70000591F-page 434
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
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 2009-2014 Microchip Technology Inc.
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 2009-2014 Microchip Technology Inc.
DS70000591F-page 437
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS70000591F-page 438
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
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 2009-2014 Microchip Technology Inc.
DS70000591F-page 439
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS70000591F-page 440
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
APPENDIX A:
MIGRATING FROM dsPIC33FJ06GS101/X02 AND
dsPIC33FJ16GSX02/X04 TO dsPIC33FJ32GS406/606/608/610 AND
dsPIC33FJ64GS406/606/608/610 DEVICES
This appendix provides an overview of considerations
for migrating from the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 family of devices to the
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 family of devices.
The code developed for the dsPIC33FJ06GS101/X02
and dsPIC33FJ16GSX02/X04 devices can be ported
to
the
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610
devices
after
making the appropriate changes outlined below.
A.1
Device Pins and Peripheral Pin
Select (PPS)
On
dsPIC33FJ06GS101/X02
and
dsPIC33FJ16GSX02/X04 devices, some peripherals
such as the Timer, Input Capture, Output Compare,
UART, SPI, External Interrupts, Analog Comparator
Output, as well as the PWM4 pin pair, were mapped to
physical pins via Peripheral Pin Select (PPS)
functionality. On dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610 devices, these
peripherals are hard-coded to dedicated pins. Because
of this, as well as pinout differences between the two
devices families, software must be updated to utilize
peripherals on the desired pin locations.
A.2
A.2.1
High-Speed PWM
FAULT AND CURRENT-LIMIT
CONTROL SIGNAL SOURCE
SELECTION
Fault and Current-Limit Control Signal Source selection has changed between the two families of devices.
On
dsPIC33FJ06GS101/X02
and
dsPIC33FJ16GSX02/X04 devices, Fault1 through
Fault8 were assigned to Fault and Current-Limit
Controls with the following values:
•
•
•
•
•
•
•
•
00000 = Fault 1
00001 = Fault 2
00010 = Fault 3
00011 = Fault 4
00100 = Fault 5
00101 = Fault 6
00110 = Fault 7
00111 = Fault 8
 2009-2014 Microchip Technology Inc.
On
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices, Fault1
through Fault8 were assigned to Fault and CurrentLimit Controls with the following values:
•
•
•
•
•
•
•
•
01000 = Fault 1
01001 = Fault 2
01010 = Fault 3
01011 = Fault 4
01100 = Fault 5
01101 = Fault 6
01110 = Fault 7
01111 = Fault 8
A.2.2
ANALOG COMPARATORS
CONNECTION
Connection of analog comparators to the PWM Fault
and Current-Limit Control Signal Sources on
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 devices is performed by assigning a comparator to
one of the Fault sources via the virtual PPS pins, and
then selecting the desired Fault as the source for Fault
and Current-Limit Control. On dsPIC33FJ32GS406/
606/608/610 and dsPIC33FJ64GS406/606/608/610
devices, analog comparators have a direct connection
to Fault and Current-Limit Control, and can be selected
with the following values for the CLSRC or FLTSRC
bits:
•
•
•
•
00000 = Analog Comparator 1
00001 = Analog Comparator 2
00010 = Analog Comparator 3
00011 = Analog Comparator 4
A.2.3
LEADING-EDGE BLANKING (LEB)
The Leading-Edge Blanking Delay (LEB) bits have
been moved from the LEBCOx register on
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 devices to the LEBDLYx register on
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices.
DS70000591F-page 441
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
APPENDIX B:
REVISION HISTORY
Revision B (November 2009)
The revision includes the following global update:
Revision A (March 2009)
• Added Note 2 to the shaded table that appears at
the beginning of each chapter. This new note
provides information regarding the availability of
registers and their associated bits
This is the initial release of this document.
This revision also includes minor typographical and
formatting changes throughout the data sheet text.
All other major changes are referenced by their
respective section in Table B-1.
TABLE B-1:
MAJOR SECTION UPDATES
Section Name
“High-Performance, 16-bit Digital
Signal Controllers”
Update Description
Added “DMA Channels” column and updated the RAM size to 9K for the
dsPIC33FJ64GS406 devices in the controller families table (see Table 1).
Updated the pin diagrams as follows:
• 64-pin TQFP and QFN
- Removed FLT8 from pin 51
- Added FLT8 to pin 60
- Added FLT17 to pin 31
- Added FLT18 to pin32
• 80-pin TQFP
- Removed FLT8 from pin 63
- Added FLT8 to pin 76
- Added FLT19 to pin 53
- Added FLT20 to pin 52
• 100-pin TQFP
- Removed FLT8 from pin 78
- Added FLT8 to pin 93
- Added SYNCO1 to pin 95
Section 4.0 “Memory Organization”
Added Data Memory Map for Devices with 8 KB RAM (see Figure 4-4).
Removed SFRs IPC25 and IPC26 from the Interrupt Controller Register
Map for dsPIC33FJ32GS406 and dsPIC33FJ64GS406 devices (see
Table 4-7).
The following bits in the Interrupt Controller Register Map for
dsPIC33FJ32GS406 and dsPIC33FJ64GS406 devices were changed to
unimplemented (see Table 4-7):
•
•
•
•
•
Bit 2 of IFS1
Bits 9-7 of IFS6
Bit 2 of IEC1
Bits 9-7 of IEC6
Bits 10-8 of IPC4
Removed OSCTUN2 and LFSR, updated OSCCON and OSCTUN,
renamed bit 13 of the REFOCON SFR in the System Control Register
Map from ROSIDL to ROSSLP and changed the All Resets value from
‘0000’ to ‘2300’ for the ACLKCON SFR (see Table 4-56).
Updated bit 1 of the PMD Register Map for dsPIC33FJ64GS608 devices
from unimplemented to C1MD (see Table 4-60).
DS70000591F-page 442
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE B-1:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
Update Description
Section 9.0 “Oscillator Configuration” Removed Section 9.2 “FRC Tuning”.
Removed the PRCDEN, TSEQEN, and LPOSCEN bits from the Oscillator
Control Register (see Register 9-1).
Updated the Oscillator Tuning Register (see Register 9-4).
Removed the Oscillator Tuning Register 2 and the Linear Feedback Shift
Register.
Updated the default Reset values from R/W-0 to R/W-1 for the SELACLK
and APSTSCLR<2:0> bits in the ACLKCON register (see Register 9-5).
Renamed the ROSIDL bit to ROSSLP in the REFOCON register (see
Register 9-6).
Section 10.0 “Power-Saving Features” Updated the last paragraph of Section 10.2.2 “Idle Mode” to clarify when
instruction execution begins.
Added Note 1 to the PMD1 register (see Register 10-1).
Section 11.0 “I/O Ports”
Changed the reference to digital-only pins to 5V tolerant pins in the
second paragraph of Section 11.2 “Open-Drain Configuration”.
Section 16.0 “High-Speed PWM”
Updated the High-Speed PWM Module Register Interconnect Diagram
(see Figure 16-2).
Updated the SYNCSRC<2:0> = 111, 101, and 100 definitions to
Reserved in the PTCON and STCON registers (see Register 16-1 and
Register 16-5).
Updated the PWM time base maximum value from 0xFFFB to 0xFFF8 in
the PTPER register (Register 16-3).
Updated the smallest pulse width value from 0x0008 to 0x0009 in Note 1
of the shaded note that follows the MDC register (see Register 16-10).
Updated the smallest pulse width value from 0x0008 to 0x0009 in Note 2
of the shaded note that follows the PDCx and SDCx registers (see
Register 16-12 and Register 16-13).
Added Note 2 and updated the FLTDAT<1:0> and CLDAT<1:0> bits,
changing the word ‘data’ to ‘state’ in the IOCONx register (see
Register 16-19).
Section 20.0 “Universal
Asynchronous Receiver Transmitter
(UART)”
Updated the two baud rate range features to: 10 Mbps to 38 bps at 40
MIPS.
Section 22.0 “High-Speed 10-bit
Analog-to-Digital Converter (ADC)”
Updated the TRGSRCx<4:0> = 01101 definition from Reserved to PWM
secondary special event trigger selected, and updated Note 1 in the
ADCP0-ADCP6 registers (see Register 22-6 through Register 22-12).
Section 24.0 “Special Features”
Updated the second paragraph and removed the fourth paragraph in
Section 24.1 “Configuration Bits”.
Updated the Device Configuration Register Map (see Table 24-1).
 2009-2014 Microchip Technology Inc.
DS70000591F-page 443
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE B-1:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
Section 27.0 “Electrical
Characteristics”
Update Description
Updated the Absolute Maximum Ratings for high temperature and added
Note 4.
Updated all Operating Current (IDD) Typical and Max values in Table 27-5.
Updated all Idle Current (IIDLE) Typical and Max values in Table 27-6.
Updated all Power-Down Current (IPD) Typical and Max values in
Table 27-7.
Updated all Doze Current (IDOZE) Typical and Max values in Table 27-8.
Updated the Typ and Max values for parameter D150 and removed
parameters DI26, DI28, and DI29 from the I/O Pin Input Specifications
(see Table 27-9).
Updated the Typ and Max values for parameter DO10 and DO27 and the
Min and Typ values for parameter DO20 in the I/O Pin Output
Specifications (see Table 27-10).
Added parameter numbers to the Auxiliary PLL Clock Timing
Specifications (see Table 27-18).
Added parameters numbers and updated the Internal RC Accuracy Min,
Typ, and Max values (see Table 27-19 and Table 27-20).
Added parameter numbers, Note 2, updated the Min and Typ parameter
values for MP31 and MP32, and removed the conditions for MP10 and
MP11 in the High-Speed PWM Module Timing Requirements (see
Table 27-29).
Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics
(see Figure 27-14).
Added parameter IM51 to the I2Cx Bus Data Timing Requirements
(Master Mode) (see Table 27-34).
Updated the Max value for parameter AD33 in the 10-bit High-Speed ADC
Module Specifications (see Table 27-36).
Updated the titles and added parameter numbers to the Comparator and
DAC Module Specifications (see Table 27-38 and Table 27-39) and the
DAC Output Buffer Specifications (see Table 27-40).
DS70000591F-page 444
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Revision C (February 2010)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
All other changes are referenced by their respective
section in Table B-2.
TABLE B-2:
MAJOR SECTION UPDATES
Section Name
Section 16.0 “High-Speed PWM”
Update Description
Added Note 2 to PTPER (Register 16-3).
Added Note 1 to SEVTCMP (Register 16-4).
Updated Note 1 in MDC (Register 16-10).
Updated Note 5 and added Note 6 to PWMCONx (Register 16-11).
Updated Note 1 in PDCx (Register 16-12).
Updated Note 1 in SDCx (Register 16-13).
Updated Note 1 and Note 2 in PHASEx (Register 16-14).
Updated Note 2 in SPHASEx (Register 16-15).
Updated Note 1 in FCLCONx (Register 16-21).
Added Note 1 to STRIGx (Register 16-22).
Updated Leading-Edge Blanking Delay increment value from 8.4 ns to
8.32 ns and added a shaded note in LEBDLYx (Register 16-24).
Added Note 3 and Note 4 to PWMCAPx (Register 16-26).
Section 27.0 “Electrical
Characteristics”
Updated the Min and Typ values for the Internal Voltage Regulator
specifications in Table 27-13.
Updated the Min and Max values for the Internal RC Accuracy
specifications in Table 27-20.
 2009-2014 Microchip Technology Inc.
DS70000591F-page 445
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Revision D (January 2012)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
All other changes are referenced by their respective
section in Table B-3.
All occurrences of PGCn and PGDn (where n = 1, 2,
or 3) were updated to: PGECn and PGEDn throughout
the document.
TABLE B-3:
MAJOR SECTION UPDATES
Section Name
Update Description
“16-Bit Digital Signal Controllers with
High-Speed PWM, ADC and
Comparators”
Added 50 MIPS to Operating Range.
Section 1.0 “Device Overview”
Updated the block diagram of the core and peripheral modules (see
Figure 1-1).
Section 2.0 “Guidelines for Getting
Started with 16-Bit Digital Signal
Controllers”
Updated the Recommended Minimum Connection diagram (see
Figure 2-1).
Changed the Oscillator frequency range in System Management.
Added the “Referenced Sources” section.
Section 4.0 “Memory Organization”
Updated the VCAP pin capacitor specification in Section 2.3
“Capacitor on Internal Voltage Regulator (VCAP)”.
Removed IPC20 and updated IFS5, IFS7, IEC5, IEC7, and IPC29 in
the Interrupt Controller Register Map for dsPIC33FJ64GS606 devices
(see Table 4-6).
Removed IPC20 and IPC21 and updated IFS5, IFS7, IEC5, IEC7, and
IPC29 in the Interrupt Controller Register Map for dsPIC33FJ32GS406
and dsPIC33FJ64GS406 devices (see Table 4-7).
Removed IPC20 and updated IFS5, IFS7, IEC5, IEC7, and IPC29 in
the Interrupt Controller Register Map for dsPIC33FJ32GS606 devices
(see Table 4-10).
Added High-Speed 10-bit ADC Register Map for dsPIC33FJ32GS406
and dsPIC33FJ64GS406 devices (see Table 4-35).
Updated ODCG in PORTG Register Map for dsPIC33FJ32GS610 and
dsPIC33FJ64GS610 devices (see Table 4-54).
Updated ODCG in PORTG Register Map for dsPIC33FJ32GS608 and
dsPIC33FJ64GS608 devices (see Table 4-55).
Updated ODCG in PORTG Register Map for dsPIC33FJ32GS406/606
and dsPIC33FJ64GS406/606 devices (see Table 4-56).
Section 9.0 “Oscillator Configuration”
Changed the High-Speed Crystal (HS) frequency range in
Section 9.1.1 “System Clock sources”.
Updated the device operating speed to up to 50 MHz in Section 9.1.2
“System Clock Selection”.
Updated Section 9.1.3 “PLL Configuration” to reflect the new
operating range/speed of 50 MIPS/50 MHz.
Updated Section 9.2 “Auxiliary Clock Generation”.
DS70000591F-page 446
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE B-3:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
Update Description
Section 22.0 “High-Speed, 10-Bit Analog- Updated the ADC Block Diagram for dsPIC33FJ32GS406 and
to-Digital Converter (ADC)”
dsPIC33FJ64GS406 Devices with one SAR (see Table 22-1).
Added Note 2 to ADCPC6: ADC Convert Pair Control Register 6 (see
Register 22-12).
Section 23.0 “High-Speed Analog
Comparator”
Added Note 1 to the High-Speed Analog Comparator Module block
diagram (see Figure 23-1).
Section 24.0 “Special Features”
Updated Section 24.1 “Configuration Bits”.
Added the RTSP Effect column to the dsPIC33F Configuration Bits
Description (see Table 24-2).
Added Note 3 to the Connections for the On-chip Voltage Regulator
(see Figure 24-1).
Section 27.0 “Electrical Characteristics”
Updated the Absolute Maximum Ratings.
Updated the Operating MIPS vs. Voltage and added Note 1 (see
Table 27-1).
Updated Note 4 and removed parameter DC18 from the DC
Temperature and Voltage Specifications (see Table 27-4).
Updated Note 2, Typical and Maximum values for parameters DC20DC24, and the Conditions for parameters DC25-DC28 in the Operating
Current DC Characteristics (see Table 27-5).
Updated Note 2 in the Idle Current DC Characteristics (see Table 27-6).
Updated Note 2 in the Power-down Current DC Characteristics (see
Table 27-7).
Added Note 2 to the Doze Current DC Characteristics (see Table 27-8).
Added parameters DI60a, DI60b, and DI60c to the I/O Pin Input
Specifications (see Table 27-9).
Updated all I/O Pin Output Specifications (see Table 27-10).
Updated parameter BO10 and added Note 2 and Note 3 to the BOR
Electrical Characteristics (see Table 27-11).
Added Note 1 to the Internal Voltage Regulator Specifications (see
Table 27-13).
Updated the OS25 parameter in the External Clock Timing diagram
(see Figure 27-2).
Added the Secondary Oscillator (SOSC) to parameter OS10, added
parameter OS42 (GM), and added Note 2 to the External Clock Timing
Requirements (see Table 27-16).
Updated Note 2 in the Internal FRC Accuracy AC Characteristics (see
Table 27-19).
Updated parameters DO31 and DO32 in the I/O Timing Requirements
(see Table 27-21).
 2009-2014 Microchip Technology Inc.
DS70000591F-page 447
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE B-3:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
Section 27.0 “Electrical Characteristics”
(Continued)
Update Description
Updated the Timer1, Timer2, and Timer3 External Clock Timing
Requirements (see Table 27-23, Table 27-24, and Table 27-25).
Updated the Simple OC/PWM Mode Timing Requirements (see
Table 27-28).
Updated all SPI Timing specifications (see Figure 27-11-Figure 27-18
and Table 27-30-Table 27-37).
Added Note 2 to the 10-bit High-Speed ADC Module Specifications (see
Table 27-40).
Added Note 2 to the 10-bit High-Speed ADC Module Timing
Requirements (see Table 27-41).
Added parameter DA08 to the DAC Module Specifications (see
Table 27-43).
Updated parameter DA16 in the DAC Output Buffer Specifications (see
Table 27-44).
Added DMA Read/Write Timing Requirements (see Table 27-49).
Section 28.0 “50 MIPS Electrical
Characteristics”
Added new chapter with electrical specifications for 50 MIPS devices.
Section 29.0 “DC and AC Device
Characteristics Graphs”
Added new chapter.
Revision E (October 2012)
This revision removes the Preliminary watermark and
includes minor typographical and formatting changes
throughout the data sheet.
Revision F (July 2014)
Changes CHOP bit to CHOPCLK in the High Speed
PWM Register Map and CHOPCLK PWMCHOP Clock
Generator
Register
(see
Register 4-16
and
Register 16-9).
Changes values in the Minimum Row Write Time and
Maximum Row Write time equation examples (see
Equation 5-2 and Equation 5-3).
Adds Register 29-7 through Register 29-12 to
Section 29.0 “DC and AC Device Characteristics
Graphs”
Also includes minor typographical and formatting
changes throughout the data sheet.
Adds the Oscillator Delay table (see Table 6-2).
Updates TUN bit ranges in the OSCTUN: Oscillator
Tuning Register (see Register 9-4).
Updates the Type C Timer Block Diagram (see
Figure 13-2).
Adds Note 1 to the CxFCTRL: ECANx FIFO Control
Register (see Register 21-4).
Adds Note 10 to the DC Characteristics: I/O Pin Input
Specifications (see Table 27-9).
Updates values in the DC Characteristics: Program
Memory Table (see Table 27-12).
DS70000591F-page 448
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
INDEX
A
AC Characteristics ............................................................ 382
10-Bit, High-Speed ADC ........................................... 410
Internal FRC Accuracy.............................................. 385
Internal LPRC Accuracy............................................ 385
Load Conditions ........................................................ 382
Temperature and Voltage Specifications .................. 382
Arithmetic Logic Unit (ALU)................................................. 39
Assembler
MPASM Assembler................................................... 366
B
Barrel Shifter ....................................................................... 43
Bit-Reversed Addressing .................................................. 102
Example .................................................................... 103
Implementation ......................................................... 102
Sequence Table (16-Entry)....................................... 103
Block Diagrams
16-Bit Timer1 Module................................................ 217
AC-to-DC Power Supply with PFC and 3 Outputs..........32
ADC Module with 1 SAR for dsPIC33FJ32GS406,
dsPIC33FJ64GS406 Devices...............................315
ADC Module with 2 SARs for dsPIC33FJ32GS606,
dsPIC33FJ64GS606 Devices...............................316
ADC Module with 2 SARs for dsPIC33FJ32GS608,
dsPIC33FJ64GS608 Devices...............................317
ADC Module with 2 SARs for dsPIC33FJ32GS610,
dsPIC33FJ64GS610 Devices...............................318
Boost Converter Implementation ................................ 27
Conceptual High-Speed PWMx ................................ 233
Connections for On-Chip Voltage Regulator............. 353
Digital PFC.................................................................. 27
DMA Top Level Architecture Using Dedicated
Transaction Bus ................................................ 180
DSP Engine ................................................................ 40
dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610 .........................18
dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610 CPU Core........34
ECANx Module ......................................................... 286
High-Speed Analog Comparator x Module ............... 345
High-Speed PWMx Architecture ............................... 232
I2Cx Module.............................................................. 272
Input Capture x ......................................................... 225
Interleaved PFC .......................................................... 30
MCLR Pin Connections............................................... 24
Minimum Connections ................................................ 24
Multi-Phase Synchronous Buck Converter ................. 28
Off-Line Ups................................................................ 29
Oscillator Circuit Placement........................................ 25
Oscillator System ...................................................... 190
Output Compare x Module........................................ 227
Phase-Shifted Full-Bridge Converter .......................... 31
PLL............................................................................ 192
Quadrature Encoder Interface x................................ 261
Reset System............................................................ 116
Shared Port Structure ............................................... 214
Simplified UARTx Module ......................................... 279
Single-Phase Synchronous Buck Converter............... 28
SPIx Module.............................................................. 265
Timer2/3/4/5 (32-Bit) ................................................. 221
 2009-2014 Microchip Technology Inc.
Type B Timer ............................................................ 219
Type C Timer............................................................ 219
Watchdog Timer (WDT)............................................ 354
Brown-out Reset (BOR).................................... 120, 349, 353
C
C Compilers
MPLAB XC Compilers .............................................. 366
Clock Generation
Auxiliary .................................................................... 193
Reference ................................................................. 193
Clock Switching ................................................................ 201
Enabling.................................................................... 201
Sequence ................................................................. 201
Code Examples
Erasing a Program Memory Page ............................ 113
Initiating a Programming Sequence ......................... 114
Loading Write Buffers ............................................... 114
Port Write/Read ........................................................ 215
PWRSAV Instruction Syntax .................................... 203
Code Protection ........................................................ 349, 356
CodeGuard Security ................................................. 349, 356
Configuration Bits ............................................................. 349
Description................................................................ 350
Configuration Register Map .............................................. 349
Configuring Analog Port Pins............................................ 215
CPU
Control Registers........................................................ 36
Data Addressing Overview ......................................... 33
DSP Engine Overview ................................................ 33
Special MCU Features ............................................... 34
CPU Clocking System ...................................................... 191
PLL Configuration..................................................... 192
Selection................................................................... 191
Sources .................................................................... 191
Customer Change Notification Service............................. 455
Customer Notification Service .......................................... 455
Customer Support............................................................. 455
D
Data Accumulators and Adder/Subtracter .......................... 41
Data Space Write Saturation ...................................... 43
Overflow and Saturation ............................................. 41
Round Logic ............................................................... 42
Write-Back .................................................................. 42
Data Address Space........................................................... 47
Alignment.................................................................... 47
Memory Map for 4-Kbyte RAM Devices ..................... 48
Memory Map for 8-Kbyte RAM Devices ..................... 49
Memory Map for 9-Kbyte RAM Devices ..................... 50
Near Data Space ........................................................ 47
SFR Space ................................................................. 47
Software Stack ........................................................... 99
Width .......................................................................... 47
DC and AC Characteristics
Graphs and Tables ................................................... 423
DC Characteristics
Brown-out Reset (BOR)............................................ 380
Doze Current (IDOZE)................................................ 376
I/O Pin Input Specifications ...................................... 377
I/O Pin Output Specifications.................................... 379
DS70000591F-page 449
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Idle Current (IIDLE) .................................................... 374
Internal Voltage Regulator Specifications ................. 381
Operating Current (IDD)............................................. 372
Operating MIPS vs. Voltage...................................... 370
Power-Down Current (IPD) ........................................ 375
Program Memory ...................................................... 381
Temperature and Voltage Specifications .................. 371
DC Characteristics (50 MIPS)
Doze Current (IDOZE) ................................................ 420
Idle Current (IIDLE) .................................................... 419
Operating Current (IDD)............................................. 418
Operating MIPS vs. Voltage...................................... 418
Demo/Development Boards, Evaluation and
Starter Kits ................................................................ 368
Development Support ....................................................... 365
Third-Party Tools ...................................................... 368
DMA Controller
Channel to Peripheral Associations .......................... 179
Control Registers ...................................................... 180
Doze Mode........................................................................ 204
DSP Engine......................................................................... 39
Multiplier...................................................................... 41
E
ECAN Module
Frame Types ............................................................. 285
Modes of Operation .................................................. 287
Overview ................................................................... 285
ECANx Message Buffers
ECANx Word 0.......................................................... 309
ECANx Word 1.......................................................... 309
ECANx Word 2.......................................................... 310
ECANx Word 3.......................................................... 310
ECANx Word 4.......................................................... 311
ECANx Word 5.......................................................... 311
ECANx Word 6.......................................................... 312
ECANx Word 7.......................................................... 312
Electrical Characteristics................................................... 369
Absolute Maximum Ratings ...................................... 369
AC Characteristics and Timing Parameters .............. 382
Electrical Characteristics (50 MIPS).................................. 417
AC Characteristics and Timing Parameters .............. 421
Enhanced CAN (ECAN) Module ....................................... 285
Equations
Device Operating Frequency .................................... 191
FOSC Calculation....................................................... 192
Maximum Row Write Time ........................................ 110
Minimum Row Write Time ......................................... 110
Programming Time ................................................... 110
XT with PLL Mode Example...................................... 192
Errata .................................................................................. 14
External Reset (EXTR)...................................................... 121
F
Fail-Safe Clock Monitor (FSCM) ....................................... 201
Flash Program Memory..................................................... 109
Control Registers ...................................................... 110
Operations ................................................................ 110
Programming Algorithm ............................................ 113
RTSP Operation........................................................ 110
Table Instructions...................................................... 109
Flexible Configuration ....................................................... 349
DS70000591F-page 450
G
Getting Started with 16-Bit DSCs ....................................... 23
Application Connection Examples .............................. 26
Capacitor on Internal Voltage Regulator (VCAP)......... 24
Configuring Analog and Digital Pins During
ICSP Operations................................................. 26
Connection Requirements .......................................... 23
Decoupling Capacitors................................................ 23
External Oscillator Pins............................................... 25
ICSP Pins ................................................................... 25
Master Clear (MCLR) Pin ........................................... 24
Oscillator Value Conditions on Start-up...................... 26
Unused I/Os................................................................ 26
H
High-Speed Analog Comparator....................................... 345
Applications .............................................................. 346
Comparator Input Range .......................................... 346
Control Registers ...................................................... 346
DAC .......................................................................... 346
Output Range ................................................... 346
Digital Logic .............................................................. 346
Features Overview.................................................... 345
Interaction with I/O Buffers ....................................... 346
Module Description ................................................... 345
High-Speed PWM ............................................................. 231
Control Registers ...................................................... 234
High-Speed, 10-Bit ADC
Control Registers ...................................................... 314
Description................................................................ 313
Module Functionality................................................. 314
I
I/O Ports............................................................................ 213
Parallel I/O (PIO) ...................................................... 213
Write/Read Timing .................................................... 215
I2C
Control Registers ...................................................... 271
Operating Modes ...................................................... 271
Illegal Opcode Reset (IOPUWR) ...................................... 121
In-Circuit Debugger........................................................... 355
In-Circuit Emulation .......................................................... 349
In-Circuit Serial Programming (ICSP)....................... 349, 355
Input Capture .................................................................... 225
Control Registers ...................................................... 226
Input Change Notification ................................................. 215
Instruction Addressing Modes ............................................ 99
File Register Instructions ............................................ 99
Fundamental Modes Supported ............................... 100
MAC Instructions ...................................................... 100
MCU Instructions ........................................................ 99
Move and Accumulator Instructions.......................... 100
Other Instructions ..................................................... 100
Instruction Set
Overview................................................................... 360
Summary .................................................................. 357
Symbols Used in Opcode Descriptions .................... 358
Instruction-Based Power-Saving Modes........................... 203
Idle ............................................................................ 204
Sleep ........................................................................ 203
Interfacing Program and Data Memory Spaces................ 104
Inter-Integrated Circuit. See I2C.
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Internet Address................................................................ 455
Interrupts
Alternate Interrupt Vector Table (AIVT) .................... 123
Control and Status Registers .................................... 127
Interrupt Control and Status Registers
IECx .................................................................. 127
IFSx .................................................................. 127
INTCON1 .......................................................... 127
INTCON2 .......................................................... 127
INTTREG .......................................................... 127
IPCx .................................................................. 127
Interrupt Vector Table (IVT) ...................................... 123
Reset Sequence ....................................................... 123
Setup Procedures ..................................................... 178
Initialization ....................................................... 178
Interrupt Disable ............................................... 178
Interrupt Service Routine .................................. 178
Trap Service Routine ........................................ 178
J
JTAG Boundary Scan Interface ........................................ 349
JTAG Interface .................................................................. 355
L
Leading-Edge Blanking (LEB)........................................... 231
LPRC Oscillator
Use with WDT ........................................................... 353
M
Memory Organization.......................................................... 45
Microchip Internet Web Site .............................................. 455
Migrating from dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 to dsPIC33FJ32GS406/606/
608/610 and dsPIC33FJ64GS406/606/608/610
Devices ..................................................................... 441
Migration
Analog Comparators Connection.............................. 441
Device Pins and Peripheral Pin Select (PPS)........... 441
Fault and Current-Limit Control Signal
Source Selection............................................... 441
Leading-Edge Blanking (LEB)................................... 441
Modes of Operation
Disable ...................................................................... 287
Initialization ............................................................... 287
Listen All Messages .................................................. 287
Listen Only ................................................................ 287
Loopback .................................................................. 287
Normal ...................................................................... 287
Modulo Addressing ........................................................... 101
Applicability ............................................................... 102
Operation Example ................................................... 101
Start and End Address.............................................. 101
W Address Register Selection .................................. 101
MPLAB Assembler, Linker, Librarian ................................ 366
MPLAB ICD 3 In-Circuit Debugger ................................... 367
MPLAB PM3 Device Programmer .................................... 367
MPLAB REAL ICE In-Circuit Emulator System................. 367
MPLAB X Integrated Development
Environment Software............................................... 365
MPLAB X SIM Software Simulator.................................... 367
MPLIB Object Librarian ..................................................... 366
MPLINK Object Linker ...................................................... 366
 2009-2014 Microchip Technology Inc.
O
Open-Drain Configuration................................................. 215
Oscillator Configuration .................................................... 189
Control Registers...................................................... 194
Output Compare ............................................................... 227
Modes....................................................................... 228
P
Packaging ......................................................................... 427
Details....................................................................... 429
Marking..................................................................... 427
Peripheral Module Disable (PMD) .................................... 205
PICkit 3 In-Circuit Debugger/Programmer ........................ 367
Pinout I/O Descriptions (table)............................................ 19
Power Save Instructions
Coincident Interrupts ................................................ 204
Power-on Reset (POR)..................................................... 120
Power-Saving Features .................................................... 203
Clock Frequency....................................................... 203
Clock Switching ........................................................ 203
Power-up Timer (PWRT) .................................................. 120
Program Address Space..................................................... 45
Construction ............................................................. 104
Data Access from Program Memory
Using PSV ........................................................ 107
Data Access from Program Memory Using
Table Instructions ............................................. 106
Data Access from, Address Generation ................... 105
Memory Maps............................................................. 45
Table Read High Instructions
TBLRDH ........................................................... 106
Table Read Low Instructions
TBLRDL............................................................ 106
Visibility Operation.................................................... 107
Program Memory
Interrupt Vector........................................................... 46
Organization ............................................................... 46
Reset Vector............................................................... 46
Programmer’s Model .......................................................... 35
PWM
Power-Saving Features ............................................ 204
Q
Quadrature Encoder Interface (QEI)................................. 261
R
RCON Register
Use of Status Bits ..................................................... 122
Register Maps
Analog Comparator Control........................................ 91
Change Notification (dsPIC33FJ32GS406/606 and
dsPIC33FJ64GS406/606 Devices)........................ 54
Change Notification (dsPIC33FJ32GS608/610 and
dsPIC33FJ64GS608/610 Devices)........................ 54
CPU Core ................................................................... 52
DMA............................................................................ 88
ECAN1 (WIN (C1CTRL1) = 0 or 1)............................. 89
ECAN1 (WIN (C1CTRL1) = 0).................................... 89
ECAN1 (WIN (C1CTRL1) = 1).................................... 90
High-Speed 10-Bit ADC Module (dsPIC33FJ32GS608
and dsPIC33FJ64GS608 Devices)........................ 85
DS70000591F-page 451
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
High-Speed 10-Bit ADC Module (dsPIC33FJ32GS610
and dsPIC33FJ64GS610 Devices) ........................ 83
High-Speed 10-Bit ADC Module (for
dsPIC33FJ32GS406 and dsPIC33FJ64GS406
Devices) .............................................................. 87
High-Speed 10-Bit ADC Module (for
dsPIC33FJ32GS606 and dsPIC33FJ64GS606
Devices) .............................................................. 86
High-Speed PWM ....................................................... 71
High-Speed PWM Generator 1 ................................... 71
High-Speed PWM Generator 2 ................................... 72
High-Speed PWM Generator 3 ................................... 73
High-Speed PWM Generator 4 ................................... 74
High-Speed PWM Generator 5 ................................... 75
High-Speed PWM Generator 6 ................................... 76
High-Speed PWM Generator 7 (All Devices
except dsPIC33FJ32GS406 and
dsPIC33FJ64GS406) ............................................. 77
High-Speed PWM Generator 8 (All Devices
except dsPIC33FJ32GS406 and
dsPIC33FJ64GS406) ............................................. 78
High-Speed PWM Generator 9 (dsPIC33FJ32GS610
and dsPIC33FJ64GS610 Devices) ........................ 79
I2C1 ............................................................................ 80
I2C2 ............................................................................ 80
Input Capture .............................................................. 69
Interrupt Controller (dsPIC33FJ32GS406 and
dsPIC33FJ64GS406 Devices) ............................ 61
Interrupt Controller (dsPIC33FJ32GS606
Devices) .............................................................. 67
Interrupt Controller (dsPIC33FJ32GS608
Devices) .............................................................. 65
Interrupt Controller (dsPIC33FJ32GS610
Devices) .............................................................. 63
Interrupt Controller (dsPIC33FJ64GS606
Devices) .............................................................. 59
Interrupt Controller (dsPIC33FJ64GS608
Devices) .............................................................. 57
Interrupt Controller (dsPIC33FJ64GS610
Devices) .............................................................. 55
NVM ............................................................................ 96
Output Compare ......................................................... 70
PMD (dsIPC33FJ64GS606 Devices) .......................... 98
PMD (dsPIC33FJ32GS406 and
dsPIC33FJ64GS406 Devices) ............................ 98
PMD (dsPIC33FJ32GS606 Devices) .......................... 98
PMD (dsPIC33FJ32GS608 Devices) .......................... 97
PMD (dsPIC33FJ32GS610 Devices) .......................... 97
PMD (dsPIC33FJ64GS608 Devices) .......................... 97
PMD (dsPIC33FJ64GS610 Devices) .......................... 96
PORTA (dsPIC33FJ32GS608 and
dsPIC33FJ64GS608 Devices) ............................ 92
PORTA (dsPIC33FJ32GS610 and
dsPIC33FJ64GS610 Devices) ............................ 92
PORTB........................................................................ 92
PORTC (dsPIC33FJ32GS406/606 and
dsPIC33FJ64GS406/606 Devices) ..................... 93
PORTC (dsPIC33FJ32GS608 and
dsPIC33FJ64GS608 Devices) ............................ 93
PORTC (dsPIC33FJ32GS610 and
dsPIC33FJ64GS610 Devices) ............................ 92
PORTD (dsPIC33FJ32GS406/606 and
dsPIC33FJ64GS406/606 Devices) ..................... 93
PORTD (dsPIC33FJ32GS608/610 and
dsPIC33FJ64GS608/610 Devices) ..................... 93
DS70000591F-page 452
PORTE (dsPIC33FJ32GS406/606 and
dsPIC33FJ64GS406/606 Devices)..................... 94
PORTE (dsPIC33FJ32GS608/610 and
dsPIC33FJ64GS608/610 Devices)..................... 94
PORTF (dsPIC33FJ32GS406/606 and
dsPIC33FJ64GS406/606 Devices)..................... 95
PORTF (dsPIC33FJ32GS608 and
dsPIC33FJ64GS608 Devices)............................ 94
PORTF (dsPIC33FJ32GS610 and
dsPIC33FJ64GS610 Devices)............................ 94
PORTG (dsPIC33FJ32GS406/606 and
dsPIC33FJ64GS406/606 Devices)..................... 95
PORTG (dsPIC33FJ32GS608 and
dsPIC33FJ64GS608 Devices)............................ 95
PORTG (dsPIC33FJ32GS610 and
dsPIC33FJ64GS610 Devices)............................ 95
Quadrature Encoder Interface 1 (QEI1)...................... 70
Quadrature Encoder Interface 2 (QEI2)...................... 70
SPI1 ............................................................................ 82
SPI2 ............................................................................ 82
System Control ........................................................... 96
Timers......................................................................... 69
UART1 ........................................................................ 81
UART2 ........................................................................ 81
Registers
ACLKCON (Auxiliary Clock Divisor Control)............. 199
ADBASE (ADC Base) ............................................... 322
ADC Base Register (ADBASE)................................. 322
ADCON (ADC Control) ............................................. 319
ADCPC0 (ADC Convert Pair Control 0).................... 324
ADCPC1 (ADC Convert Pair Control 1).................... 327
ADCPC2 (ADC Convert Pair Control 2).................... 330
ADCPC3 (ADC Convert Pair Control 3).................... 333
ADCPC4 (ADC Convert Pair Control 4).................... 336
ADCPC5 (ADC Convert Pair Control 5).................... 339
ADCPC6 (ADC Convert Pair Control 6).................... 342
ADPCFG (ADC Port Configuration).......................... 323
ADPCFG2 (ADC Port Configuration 2)..................... 323
ADSTAT (ADC Status) ............................................. 321
ALTDTRx (PWM Alternate Dead-Time x)................. 248
AUXCONx (PWM Auxiliary Control x) ...................... 258
CHOP (PWM Chop Clock Generator) ...................... 241
CLKDIV (Clock Divisor) ............................................ 196
CMPCONx (Comparator Control x) .......................... 347
CMPDACx (Comparator DAC Control x) .................. 348
CORCON (Core Control) .................................... 38, 128
CxBUFPNT1 (ECANx Filter 0-3
Buffer Pointer 1) ............................................... 298
CxBUFPNT2 (ECANx Filter 4-7
Buffer Pointer 2) ............................................... 299
CxBUFPNT3 (ECANx Filter 8-11
Buffer Pointer 3) ............................................... 300
CxBUFPNT4 (ECANx Filter 12-15
Buffer Pointer 4) ............................................... 301
CxCFG1 (ECANx Baud Rate Configuration 1) ......... 296
CxCFG2 (ECANx Baud Rate Configuration 2) ......... 297
CxCTRL1 (ECANx Control 1) ................................... 288
CxCTRL2 (ECANx Control 2) ................................... 289
CxEC (ECANx Transmit/Receive Error Count)......... 296
CxFCTRL (ECANx FIFO Control)............................. 291
CxFEN1 (ECANx Acceptance Filter Enable 1) ......... 298
CxFIFO (ECANx FIFO Status).................................. 292
CxFMSKSEL1 (ECANx Filter 7-0 Mask
Selection 1)....................................................... 303
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
CxFMSKSEL2 (ECANx Filter 15-8 Mask
Selection 2) ....................................................... 304
CxINTE (ECANx Interrupt Enable)............................ 295
CxINTF (ECANx Interrupt Flag) ................................ 293
CxRXFnEID (ECANx Acceptance Filter n
Extended Identifier)........................................... 303
CxRXFnSID (ECANx Acceptance Filter n
Standard Identifier) ........................................... 302
CxRXFUL1 (ECANx Receive Buffer Full 1) .............. 306
CxRXFUL2 (ECANx Receive Buffer Full 2) .............. 306
CxRXMnEID (ECANx Acceptance Filter Mask n
Extended Identifier)........................................... 305
CxRXMnSID (ECANx Acceptance Filter Mask n
Standard Identifier) ........................................... 305
CxRXOVF1 (ECANx Receive Buffer
Overflow 1) ....................................................... 307
CxRXOVF2 (ECANx Receive Buffer
Overflow 2) ....................................................... 307
CxTRmnCON (ECANx TX/RX
Buffer mn Control) ............................................ 308
CxVEC (ECANx Interrupt Code) ............................... 290
DFLTxCON (Digital Filter x Control) ......................... 264
DMACS0 (DMA Controller Status 0)......................... 185
DMACS1 (DMA Controller Status 1)......................... 186
DMAxCNT (DMA Channel x Transfer Count) ........... 184
DMAxCON (DMA Channel x Control) ....................... 181
DMAxPAD (DMA Channel x
Peripheral Address) .......................................... 183
DMAxREQ (DMA Channel x IRQ Select) ................. 182
DMAxSTA (DMA Channel x RAM Start Address
Offset A)............................................................ 182
DMAxSTB (DMA Channel x RAM Start Address
Offset B)............................................................ 183
DSADR (Most Recent DMA RAM Address).............. 187
DTRx (PWM Dead-Time x) ....................................... 248
FCLCONx (PWM Fault Current-Limit Control x) ....... 252
I2CxCON (I2Cx Control) ........................................... 273
I2CxMSK (I2Cx Slave Mode Address Mask) ............ 277
I2CxSTAT (I2Cx Status) ........................................... 275
ICxCON (Input Capture x Control) ............................ 226
IEC0 (Interrupt Enable Control 0) ............................. 142
IEC1 (Interrupt Enable Control 1) ............................. 144
IEC2 (Interrupt Enable Control 2) ............................. 146
IEC3 (Interrupt Enable Control 3) ............................. 147
IEC4 (Interrupt Enable Control 4) ............................. 148
IEC5 (Interrupt Enable Control 5) ............................. 149
IEC6 (Interrupt Enable Control 6) ............................. 150
IEC7 (Interrupt Enable Control 7) ............................. 151
IFS0 (Interrupt Flag Status 0) ................................... 132
IFS1 (Interrupt Flag Status 1) ................................... 134
IFS2 (Interrupt Flag Status 2) ................................... 136
IFS3 (Interrupt Flag Status 3) ................................... 137
IFS4 (Interrupt Flag Status 4) ................................... 138
IFS5 (Interrupt Flag Status 5) ................................... 139
IFS6 (Interrupt Flag Status 6) ................................... 140
IFS7 (Interrupt Flag Status 7) ................................... 141
INTCON1 (Interrupt Control 1).................................. 129
INTCON2 (Interrupt Control 2).................................. 131
INTTREG (Interrupt Control and Status)................... 177
IOCONx (PWM I/O Control x) ................................... 250
IPC0 (Interrupt Priority Control 0) ............................. 152
IPC1 (Interrupt Priority Control 1) ............................. 153
IPC12 (Interrupt Priority Control 12) ......................... 162
IPC13 (Interrupt Priority Control 13) ......................... 163
IPC14 (Interrupt Priority Control 14) ......................... 164
 2009-2014 Microchip Technology Inc.
IPC16 (Interrupt Priority Control 16) ......................... 165
IPC17 (Interrupt Priority Control 17) ......................... 166
IPC18 (Interrupt Priority Control 18) ......................... 167
IPC2 (Interrupt Priority Control 2) ............................. 154
IPC20 (Interrupt Priority Control 20) ......................... 168
IPC21 (Interrupt Priority Control 21) ......................... 169
IPC23 (Interrupt Priority Control 23) ......................... 170
IPC24 (Interrupt Priority Control 24) ......................... 171
IPC25 (Interrupt Priority Control 25) ......................... 172
IPC26 (Interrupt Priority Control 26) ......................... 173
IPC27 (Interrupt Priority Control 27) ......................... 174
IPC28 (Interrupt Priority Control 28) ......................... 175
IPC29 (Interrupt Priority Control 29) ......................... 176
IPC3 (Interrupt Priority Control 3) ............................. 155
IPC4 (Interrupt Priority Control 4) ............................. 156
IPC5 (Interrupt Priority Control 5) ............................. 157
IPC6 (Interrupt Priority Control 6) ............................. 158
IPC7 (Interrupt Priority Control 7) ............................. 159
IPC8 (Interrupt Priority Control 8) ............................. 160
IPC9 (Interrupt Priority Control 9) ............................. 161
LEBCONx (Leading-Edge Blanking Control x) ......... 255
LEBDLYx (Leading-Edge Blanking Delay x) ............ 257
MDC (PWM Master Duty Cycle)............................... 242
NVMCON (Flash Memory Control)........................... 111
NVMKEY (Nonvolatile Memory Key) ........................ 112
OCxCON (Output Compare x Control, x = 1-4) ........ 229
OSCCON (Oscillator Control)................................... 194
OSCTUN (Oscillator Tuning) .................................... 198
PDCx (PWM Generator Duty Cycle x)...................... 245
PHASEx (PWM Primary Phase-Shift x).................... 246
PLLFBD (PLL Feedback Divisor) ............................. 197
PMD1 (Peripheral Module Disable Control 1) .......... 206
PMD2 (Peripheral Module Disable Control 2) .......... 208
PMD3 (Peripheral Module Disable Control 3) .......... 209
PMD4 (Peripheral Module Disable Control 4) .......... 209
PMD6 (Peripheral Module Disable Control 6) .......... 210
PMD7 (Peripheral Module Disable Control 7) .......... 211
PTCON (PWM Time Base Control) .......................... 235
PTCON2 (PWM Clock Divider Select 2)................... 237
PTPER (PWM Primary Master
Time Base Period)............................................ 237
PWMCAPx (Primary PWM Time Base
Capture x)......................................................... 259
PWMCONx (PWM Control x) ................................... 243
QEIxCON (QEIx Control, x = 1 or 2)......................... 262
RCON (Reset Control).............................................. 117
REFOCON (Reference Oscillator Control) ............... 200
SDCx (PWM Secondary Duty Cycle x)..................... 245
SEVTCMP (PWM Special Event Compare) ............. 238
SPHASEx (PWM Secondary Phase-Shift x) ............ 247
SPIxCON1 (SPIx Control 1) ..................................... 267
SPIxCON2 (SPIx Control 2) ..................................... 269
SPIxSTAT (SPIx Status and Control) ....................... 266
SR (CPU STATUS) ............................................ 36, 128
SSEVTCMP (PWM Secondary Special Event
Compare).......................................................... 241
STCON (PWM Secondary Master Time Base
Control)............................................................. 239
STCON2 (PWM Secondary Clock Divider
Select 2) ........................................................... 240
STPER (PWM Secondary Master Time Base
Period) .............................................................. 240
STRIGx (PWM Secondary Trigger x
Compare Value) ............................................... 254
T1CON (Timer1 Control) .......................................... 218
DS70000591F-page 453
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TRGCONx (PWM Trigger Control x)......................... 249
TRIGx (PWM Primary Trigger x
Compare Value)................................................ 251
TxCON (Timerx Control, x = 2, 4) ............................. 222
TyCON (Timery Control, y = 3, 5) ............................. 223
UxMODE (UARTx Mode) .......................................... 280
UxSTA (UARTx Status and Control) ......................... 282
Resets ............................................................................... 115
Brown-out Reset (BOR) ............................................ 115
Illegal Condition Reset (IOPUWR) ............................ 115
Illegal Opcode ................................................... 115, 121
Master Clear Pin Reset (MCLR) ............................... 115
Power-on Reset (POR) ............................................. 115
Security ..................................................................... 121
Security Reset........................................................... 115
Software RESET Instruction (SWR) ......................... 115
Trap Conflict Reset (TRAPR).................................... 115
Uninitialized W Register .................................... 115, 121
Watchdog Timer Reset (WDTO) ............................... 115
Revision History ................................................................ 442
S
Serial Peripheral Interface (SPI) ....................................... 265
Software RESET Instruction (SWR).................................. 121
Software Stack Pointer, Frame Pointer
CALL Stack Frame...................................................... 99
Special Features of the CPU............................................. 349
T
Thermal Operating Conditions .......................................... 370
Thermal Packaging Characteristics .................................. 370
Timer1 ............................................................................... 217
Mode Settings ........................................................... 217
Timer2/3/4/5 ...................................................................... 219
16-Bit Operation ........................................................ 220
32-Bit Operation ........................................................ 220
32-Bit Timer .............................................................. 220
Mode Settings ........................................................... 220
Timing Diagrams
Analog-to-Digital Conversion per Input ..................... 411
Brown-out Situations ................................................. 120
ECAN I/O .................................................................. 416
External Clock ........................................................... 383
High-Speed PWMx Characteristics........................... 393
High-Speed PWMx Fault Characteristics.................. 393
I/O Characteristics .................................................... 386
I2Cx Bus Data (Master Mode) .................................. 406
I2Cx Bus Data (Slave Mode) .................................... 408
I2Cx Bus Start/Stop Bits (Master Mode) ................... 406
I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 408
Input Capture x (ICx) Characteristics ........................ 391
OCx/PWMx Characteristics ...................................... 392
Output Compare x (OCx) Characteristics ................. 391
Output Compare x Operation .................................... 228
QEA/QEB Input Characteristics ................................ 413
QEI Module Index Pulse ........................................... 414
Reset, Watchdog Timer, Oscillator Start-up Timer
and Power-up Timer ......................................... 387
SPIx Master Mode (Full-Duplex, CKE = 0,
CKP = x, SMP = 1)............................................ 397
SPIx Master Mode (Full-Duplex, CKE = 1,
CKP = x, SMP = 1)............................................ 396
SPIx Master Mode (Half-Duplex,
Transmit Only, CKE = 0) ................................... 394
SPIx Master Mode (Half-Duplex,
Transmit Only, CKE = 1) ................................... 394
DS70000591F-page 454
SPIx Slave Mode (Full-Duplex, CKE = 0,
CKP = 0, SMP = 0) ........................................... 404
SPIx Slave Mode (Full-Duplex, CKE = 0,
CKP = 1, SMP = 0) ........................................... 402
SPIx Slave Mode (Full-Duplex, CKE = 1,
CKP = 0, SMP = 0) ........................................... 398
SPIx Slave Mode (Full-Duplex, CKE = 1,
CKP = 1, SMP = 0) ........................................... 400
System Reset ........................................................... 119
Timer1/2/3 External Clock ........................................ 389
TimerQ (QEI Module) External Clock
Characteristics.................................................. 415
Timing Requirements
10-Bit, High-Speed ADC........................................... 411
Auxiliary PLL Clock Specifications............................ 384
Capacitive Loading on Output Pins .......................... 382
DMA Read/Write....................................................... 416
ECAN I/O .................................................................. 416
External Clock........................................................... 383
High-Speed PWMx ................................................... 393
I/O ............................................................................. 386
I2Cx Bus Data (Master Mode) .................................. 407
I2Cx Bus Data (Slave Mode) .................................... 409
Input Capture x (ICx) ................................................ 391
Output Compare x (OCx).......................................... 391
PLL Clock Specifications .......................................... 384
QEI External Clock ................................................... 415
QEI Index Pulse........................................................ 415
Quadrature Decoder ................................................. 414
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset ............. 388
Simple OCx/PWMx Mode ......................................... 392
SPIx Master Mode (Full-Duplex, CKE = 0,
CKP = x, SMP = 1) ........................................... 397
SPIx Master Mode (Full-Duplex, CKE = 1,
CKP = x, SMP = 1) ........................................... 396
SPIx Master Mode (Half-Duplex,
Transmit Only) .................................................. 395
SPIx Slave Mode (Full-Duplex, CKE = 0,
CKP = 0, SMP = 0) ........................................... 405
SPIx Slave Mode (Full-Duplex, CKE = 0,
CKP = 1, SMP = 0) ........................................... 403
SPIx Slave Mode (Full-Duplex, CKE = 1,
CKP = 0, SMP = 0) ........................................... 399
SPIx Slave Mode (Full-Duplex, CKE = 1,
CKP = 1, SMP = 0) ........................................... 401
Timer1 External Clock .............................................. 389
Timer2/4 External Clock ........................................... 390
Timer3/5 External Clock ........................................... 390
Timing Requirements (50 MIPS)
External Clock........................................................... 421
Timing Specifications
Comparator Module .................................................. 412
DAC Module ............................................................. 412
DAC Output Buffer.................................................... 413
Trap Conflict Reset (TRAPR) ........................................... 121
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
U
W
Universal Asynchronous Receiver
Transmitter (UART)................................................... 279
Watchdog Timer (WDT)............................................ 349, 353
Programming Considerations ................................... 354
Watchdog Timer Time-out Reset (WDTO) ....................... 121
WWW Address ................................................................. 455
WWW, On-Line Support ..................................................... 14
V
Voltage Regulator (On-Chip) ............................................ 353
 2009-2014 Microchip Technology Inc.
DS70000591F-page 455
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS70000591F-page 456
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
 2009-2014 Microchip Technology Inc.
DS7000591F-page 457
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS7000591F-page 458
 2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
dsPIC 33 FJ 32 GS4 06 T - 50 I / PT - XXX
Examples:
a) dsPIC33FJ32GS406-50-I/PT:
SMPS dsPIC33, 32-Kbyte
program memory, 64-pin,
50 MIPS, Industrial temp., TQFP
package.
Microchip Trademark
Architecture
Flash Memory Family
Program Memory Size (Kbytes)
Product Group
Pin Count
Tape and Reel Flag (if applicable)
Speed
Temperature Range
Package
Pattern
Architecture:
33
=
16-Bit Digital Signal Controller
Flash Memory
Family:
FJ
=
Flash program memory, 3.3V
Product Group:
GS4
GS6
=
=
Switch Mode Power Supply (SMPS) family
Switch Mode Power Supply (SMPS) family
Pin Count:
06
08
10
=
=
=
64-pin
80-pin
100-pin
Speed:
50
=
=
50 MIPS
40 MIPS (marking intentionally absent)
Temperature Range:
I
E
=
=
-40C to +85C (Industrial)
-40C to +125C (Extended)
Package:
PT
PT
PF
MR
=
=
=
=
Plastic Thin Quad Flatpack – 10x10x1 mm body (TQFP)
Plastic Thin Quad Flatpack – 12x12x1 mm body (TQFP)
Plastic Thin Quad Flatpack – 14x14x1 mm body (TQFP)
Plastic Quad Flat, No Lead Package – 9x9x0.9 mm body (QFN)
 2009-2014 Microchip Technology Inc.
DS70000591F-page 459
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS70000591F-page 460
 2009-2014 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2014, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63276-374-7
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2009-2014 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS7000591F-page 461
Worldwide Sales and Service
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Technical Support:
http://www.microchip.com/
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Web Address:
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DS70000591F-page 462
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03/25/14
 2009-2014 Microchip Technology Inc.