Data Sheet

PCA9956B
24-channel Fm+ I2C-bus 57 mA/20 V constant current LED
driver
Rev. 1.1 — 15 December 2015
Product data sheet
1. General description
The PCA9956B is an I2C-bus controlled 24-channel constant current LED driver optimized
for dimming and blinking 57 mA Red/Green/Blue/Amber (RGBA) LEDs in amusement
products. Each LED output has its own 8-bit resolution (256 steps) fixed frequency
individual PWM controller that operates at 31.25 kHz with a duty cycle that is adjustable
from 0 % to 99.6 % to allow the LED to be set to a specific brightness value. An additional
8-bit resolution (256 steps) group PWM controller has both a fixed frequency of 122 Hz
and an adjustable frequency between 15 Hz to once every 16.8 seconds with a duty cycle
that is adjustable from 0 % to 99.6 % that is used to either dim or blink all LEDs with the
same value.
Each LED output can be off, on (no PWM control), set at its individual PWM controller
value or at both individual and group PWM controller values. The PCA9956B operates
with a supply voltage range of 3 V to 5.5 V and the constant current sink LED outputs
allow up to 20 V for the LED supply. The output peak current is adjustable with an 8-bit
linear DAC from 225 A to 57 mA.
This device has built-in open, short load and overtemperature detection circuitry. The error
information from the corresponding register can be read via the I2C-bus. Additionally, a
thermal shutdown feature protects the device when internal junction temperature exceeds
the limit allowed for the process.
The PCA9956B device has a Fast-mode Plus (Fm+) I2C-bus interface. Fm+ devices offer
higher frequency (up to 1 MHz) or more densely populated bus operation (up to 4000 pF).
The active LOW output enable input pin (OE) blinks all the LED outputs and can be used
to externally PWM the outputs, which is useful when multiple devices need to be dimmed
or blinked together without using software control.
Software programmable LED Group and three Sub Call I2C-bus addresses allow all or
defined groups of PCA9956B devices to respond to a common I2C-bus address, allowing
for example, all red LEDs to be turned on or off at the same time or marquee chasing
effect, thus minimizing I2C-bus commands. On power-up, PCA9956B will have a unique
Sub Call address to identify it as a 24-channel LED driver. This allows mixing of devices
with different channel widths. Three hardware address pins on PCA9956B allow up to
125 devices on the same bus.
The Software Reset (SWRST) function allows the master to perform a reset of the
PCA9956B through the I2C-bus, identical to the Power-On Reset (POR) that initializes the
registers to their default state causing the output current switches to be OFF (LED off).
This allows an easy and quick way to reconfigure all device registers to the same
condition.
PCA9956B
NXP Semiconductors
24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
2. Features and benefits
 24 LED drivers. Each output programmable at:
 Off
 On
 Programmable LED brightness
 Programmable group dimming/blinking mixed with individual LED brightness
 Programmable LED output delay to reduce EMI and surge currents
 24 constant current output channels can sink up to 57 mA, tolerate up to 20 V when
OFF
 Output current adjusted through an external resistor (REXT input)
 Output current accuracy
 4 % between output channels
 6 % between PCA9956B devices
 Open/short load/overtemperature detection mode to detect individual LED errors
 1 MHz Fast-mode Plus compatible I2C-bus interface with 30 mA high drive capability
on SDA output for driving high capacitive buses
 256-step (8-bit) linear programmable brightness per LED output varying from fully off
(default) to maximum brightness using a 31.25 kHz PWM signal
 256-step group brightness control allows general dimming (using a 122 Hz PWM
signal) from fully off to maximum brightness (default)
 256-step group blinking with frequency programmable from 15 Hz to 16.8 s and duty
cycle from 0 % to 99.6 %
 Output state change programmable on the Acknowledge or the STOP Command to
update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’).
 Active LOW Output Enable (OE) input pin allows for hardware blinking and dimming of
the LEDs
 Three quinary hardware address pins allow 125 PCA9956B devices to be connected
to the same I2C-bus and to be individually programmed
 Four software programmable I2C-bus addresses (one LED Group Call address and
three LED Sub Call addresses) allow groups of devices to be addressed at the same
time in any combination (for example, one register used for ‘All Call’ so that all the
PCA9956Bs on the I2C-bus can be addressed at the same time and the second
register used for three different addresses so that 1⁄3 of all devices on the bus can be
addressed at the same time in a group). Software enable and disable for each
programmable I2C-bus address.
 Unique power-up default Sub Call address allows mixing of devices with different
channel widths
 Software Reset feature (SWRST Call) allows the device to be reset through the
I2C-bus
 8 MHz internal oscillator requires no external components
 Internal power-on reset
 Noise filter on SDA/SCL inputs
 No glitch on LEDn outputs on power-up
 Low standby current
 Operating power supply voltage (VDD) range of 3 V to 5.5 V
 5.5 V tolerant inputs on non-LED pins
PCA9956B
Product data sheet
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Rev. 1.1 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 53
PCA9956B
NXP Semiconductors
24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver




40 C to +85 C operation
ESD protection exceeds 3000 V HBM per JESD22-A114
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: HTSSOP38
3. Applications






Amusement products
RGB or RGBA LED drivers
LED status information
LED displays
LCD backlights
Keypad backlights for cellular phones or handheld devices
4. Ordering information
Table 1.
Ordering information
Type number
PCA9956BTW
Topside mark
PCA9956BTW
Package
Name
Description
Version
HTSSOP38
plastic thermal enhanced thin shrink small outline package; SOT1331-1
38 leads; body width 4.4 mm; lead pitch 0.5 mm;
exposed die pad
4.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order
quantity
Temperature
PCA9956BTW
PCA9956BTWY
HTSSOP38
Reel 13” Q1/T1
*Standard mark SMD dry pack
2500
Tamb = 40 C to +85 C
PCA9956B
Product data sheet
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Rev. 1.1 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 53
PCA9956B
NXP Semiconductors
24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
5. Block diagram
AD0 AD1 AD2
REXT
LED0
LED1
LED22
LED23
I/O
REGULATOR
PCA9956B
DAC0
SCL
INPUT FILTER
DAC1
SDA
I2C-BUS
CONTROL
individual LED
current setting
8-bit DACs
DAC
22
DAC
23
POWER-ON
RESET
VDD
OUTPUT DRIVER, DELAY CONTROL,
ERROR DETECTION AND THERMAL SHUTDOWN
VSS
INPUT
FILTER
RESET
LED STATE
SELECT
REGISTER
PWM
REGISTER X
BRIGHTNESS
CONTROL
÷ 256
31.25 kHz
8 MHz
OSCILLATOR
GRPFREQ
REGISTER
DIM CLOCK
MUX/
CONTROL
GRPPWM
REGISTER
'0' – permanently OFF
'1' – permanently ON
OE
aaa-017232
Dim repetition rate = 122 Hz.
Blink repetition rate = 15 Hz to every 16.8 seconds.
Fig 1.
Block diagram of PCA9956B
PCA9956B
Product data sheet
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Rev. 1.1 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PCA9956B
NXP Semiconductors
24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
6. Pinning information
6.1 Pinning
REXT
1
38
VDD
AD0
2
37
SDA
AD1
3
36
SCL
AD2
4
35
RESET
OE
5
34
VSS
LED0
6
33
LED23
LED1
7
32
LED22
LED2
8
31
LED21
LED3
9
30
LED20
PCA9956BTW
LED4
10
29
LED19
LED5
11
28
LED18
LED6
12
27
LED17
LED7
13
26
LED16
VSS
14
25
VSS
LED8
15
24
LED15
LED9
16
23
LED14
LED10
17
22
LED13
VSS
18
21
VSS
LED11
19
20
LED12
(1)
Transparant top view
aaa-017233
(1) Thermal pad; connected to VSS.
Fig 2.
PCA9956B
Product data sheet
Pin configuration for HTSSOP38
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PCA9956B
NXP Semiconductors
24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
6.2 Pin description
Table 3.
Pin
Type
Description
REXT
1
I
current set resistor input; resistor to ground
AD0
2
I
address input 0
AD1
3
I
address input 1
AD2
4
I
address input 2
OE
5
I
active LOW output enable for LEDs
LED0
6
O
LED driver 0
LED1
7
O
LED driver 1
LED2
8
O
LED driver 2
LED3
9
O
LED driver 3
LED4
10
O
LED driver 4
LED5
11
O
LED driver 5
LED6
12
O
LED driver 6
LED7
13
O
LED driver 7
LED8
15
O
LED driver 8
LED9
16
O
LED driver 9
LED10
17
O
LED driver 10
LED11
19
O
LED driver 11
LED12
20
O
LED driver 12
LED13
22
O
LED driver 13
LED14
23
O
LED driver 14
LED15
24
O
LED driver 15
LED16
26
O
LED driver 16
LED17
27
O
LED driver 17
LED18
28
O
LED driver 18
LED19
29
O
LED driver 19
LED20
30
O
LED driver 20
LED21
31
O
LED driver 21
LED22
32
O
LED driver 22
LED23
33
O
LED driver 23
RESET
35
I
active LOW reset input with external 10 k
pull-up resistor
SCL
36
I
serial clock line
SDA
37
I/O
serial data line
ground
supply ground
power supply
supply voltage
VSS
14, 18, 21, 25, 34
VDD
38
[1]
PCA9956B
Product data sheet
Pin description
Symbol
[1]
HTSSOP38 package supply ground is connected to both VSS pins and exposed center pad. VSS pins must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
printed-circuit board in the thermal pad region.
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Rev. 1.1 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 53
PCA9956B
NXP Semiconductors
24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
7. Functional description
Refer to Figure 1 “Block diagram of PCA9956B”.
7.1 Device addresses
Following a START condition, the bus master must output the address of the slave it is
accessing.
For PCA9956B there are a maximum of 125 possible programmable addresses using the
three quinary hardware address pins.
7.1.1 Regular I2C-bus slave address
The I2C-bus slave address of the PCA9956B is shown in Figure 3. The 7-bit slave
address is determined by the quinary input pads AD0, AD1 and AD2. Each pad can have
one of five states (GND, pull-up, floating, pull-down, and VDD) based on how the input pad
is connected on the board. At power-up or hardware/software reset, the quinary input
pads are sampled and set the slave address of the device internally. To conserve power,
once the slave address is determined, the quinary input pads are turned off and will not be
sampled until the next time the device is power cycled. Table 4 lists the five possible
connections for the quinary input pads along with the external resistor values that must be
used.
Table 4.
Quinary input pad connection
Pad connection
(pins AD2, AD1, AD0)[1]
Mnemonic
Min.
Max.
tie to ground
GND
0
17.9
resistor pull-down to ground
PD
34.8
270
open (floating)
FLT
503

resistor pull-up to VDD
PU
31.7
340
tie to VDD
VDD
0
22.1
[1]
External resistor (k)
These AD[2:0] inputs must be stable before the supply VDD to the chip.
Table 5 lists all 125 possible slave addresses of the device based on all combinations of
the five states connected to three address input pins AD0, AD1 and AD2.
Table 5.
Hardware selectable input pins
I2C-bus slave address for PCA9956B
AD2
Decimal
AD0
Hex
Binary (A[6:0])
Address (R/W = 0)
02h
GND
GND
GND
1
01
GND
GND
PD
2
02
0000010[1]
04h
03
0000011[1]
06h
04
0000100[1]
08h
0Ah
GND
Product data sheet
AD1
0000001[1]
GND
PCA9956B
I2C-bus slave address
GND
GND
FLT
PU
3
4
GND
GND
VDD
5
05
0000101[1]
GND
PD
GND
6
06
0000110[1]
0Ch
0Eh
GND
PD
PD
7
07
0000111[1]
GND
PD
FLT
8
08
0001000
10h
GND
PD
PU
9
09
0001001
12h
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Rev. 1.1 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PCA9956B
NXP Semiconductors
24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
Table 5.
PCA9956B
Product data sheet
I2C-bus slave address …continued
Hardware selectable input pins
I2C-bus slave address for PCA9956B
AD2
AD1
AD0
Decimal
Hex
Binary (A[6:0])
Address (R/W = 0)
GND
PD
VDD
10
0A
0001010
14h
GND
FLT
GND
11
0B
0001011
16h
GND
FLT
PD
12
0C
0001100
18h
GND
FLT
FLT
13
0D
0001101
1Ah
GND
FLT
PU
14
0E
0001110
1Ch
GND
FLT
VDD
15
0F
0001111
1Eh
GND
PU
GND
16
10
0010000
20h
GND
PU
PD
17
11
0010001
22h
GND
PU
FLT
18
12
0010010
24h
GND
PU
PU
19
13
0010011
26h
GND
PU
VDD
20
14
0010100
28h
GND
VDD
GND
21
15
0010101
2Ah
GND
VDD
PD
22
16
0010110
2Ch
GND
VDD
FLT
23
17
0010111
2Eh
GND
VDD
PU
24
18
0011000
30h
GND
VDD
VDD
25
19
0011001
32h
PD
GND
GND
26
1A
0011010
34h
PD
GND
PD
27
1B
0011011
36h
PD
GND
FLT
28
1C
0011100
38h
PD
GND
PU
29
1D
0011101
3Ah
PD
GND
VDD
30
1E
0011110
3Ch
PD
PD
GND
31
1F
0011111
3Eh
PD
PD
PD
32
20
0100000
40h
PD
PD
FLT
33
21
0100001
42h
PD
PD
PU
34
22
0100010
44h
PD
PD
VDD
35
23
0100011
46h
PD
FLT
GND
36
24
0100100
48h
PD
FLT
PD
37
25
0100101
4Ah
PD
FLT
FLT
38
26
0100110
4Ch
PD
FLT
PU
39
27
0100111
4Eh
PD
FLT
VDD
40
28
0101000
50h
PD
PU
GND
41
29
0101001
52h
PD
PU
PD
42
2A
0101010
54h
PD
PU
FLT
43
2B
0101011
56h
PD
PU
PU
44
2C
0101100
58h
PD
PU
VDD
45
2D
0101101
5Ah
PD
VDD
GND
46
2E
0101110
5Ch
PD
VDD
PD
47
2F
0101111
5Eh
PD
VDD
FLT
48
30
0110000
60h
PD
VDD
PU
49
31
0110001
62h
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Rev. 1.1 — 15 December 2015
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PCA9956B
NXP Semiconductors
24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
Table 5.
PCA9956B
Product data sheet
I2C-bus slave address …continued
Hardware selectable input pins
I2C-bus slave address for PCA9956B
AD2
AD1
AD0
Decimal
Hex
Binary (A[6:0])
Address (R/W = 0)
PD
VDD
VDD
50
32
0110010
64h
FLT
GND
GND
51
33
0110011
66h
FLT
GND
PD
52
34
0110100
68h
FLT
GND
FLT
53
35
0110101
6Ah
FLT
GND
PU
54
36
0110110
6Ch
FLT
GND
VDD
55
37
0110111
6Eh
FLT
PD
GND
56
38
0111000
70h
FLT
PD
PD
57
39
0111001
72h
FLT
PD
FLT
58
3A
0111010
74h
FLT
PD
PU
59
3B
0111011
76h
FLT
PD
VDD
60
3C
0111100
78h
FLT
FLT
GND
61
3D
0111101
7Ah
FLT
FLT
PD
62
3E
0111110
7Ch
FLT
FLT
FLT
63
3F
0111111
7Eh
FLT
FLT
PU
64
40
1000000
80h
FLT
FLT
VDD
65
41
1000001
82h
FLT
PU
GND
66
42
1000010
84h
FLT
PU
PD
67
43
1000011
86h
FLT
PU
FLT
68
44
1000100
88h
FLT
PU
PU
69
45
1000101
8Ah
FLT
PU
VDD
70
46
1000110
8Ch
FLT
VDD
GND
71
47
1000111
8Eh
FLT
VDD
PD
72
48
1001000
90h
FLT
VDD
FLT
73
49
1001001
92h
FLT
VDD
PU
74
4A
1001010
94h
FLT
VDD
VDD
75
4B
1001011
96h
PU
GND
GND
76
4C
1001100
98h
PU
GND
PD
77
4D
1001101
9Ah
PU
GND
FLT
78
4E
1001110
9Ch
PU
GND
PU
79
4F
1001111
9Eh
PU
GND
VDD
80
50
1010000
A0h
PU
PD
GND
81
51
1010001
A2h
PU
PD
PD
82
52
1010010
A4h
PU
PD
FLT
83
53
1010011
A6h
PU
PD
PU
84
54
1010100
A8h
PU
PD
VDD
85
55
1010101
AAh
PU
FLT
GND
86
56
1010110
ACh
PU
FLT
PD
87
57
1010111
AEh
PU
FLT
FLT
88
58
1011000
B0h
PU
FLT
PU
89
59
1011001
B2h
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Rev. 1.1 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PCA9956B
NXP Semiconductors
24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
Table 5.
I2C-bus slave address …continued
Hardware selectable input pins
I2C-bus slave address for PCA9956B
AD2
AD1
AD0
Decimal
Hex
Binary (A[6:0])
Address (R/W = 0)
PU
FLT
VDD
90
5A
1011010
B4h
PU
PU
GND
91
5B
1011011
B6h
PU
PU
PD
92
5C
1011100
B8h
PU
PU
FLT
93
5D
1011101
BAh
PU
PU
PU
94
5E
1011110
BCh
PU
PU
VDD
95
5F
1011111
BEh
PU
VDD
GND
96
60
1100000
C0h
PU
VDD
PD
97
61
1100001
C2h
PU
VDD
FLT
98
62
1100010
C4h
PU
VDD
PU
99
63
1100011
C6h
PU
VDD
VDD
100
64
1100100
C8h
VDD
GND
GND
101
65
1100101
CAh
VDD
GND
PD
102
66
1100110
CCh
VDD
GND
FLT
103
67
1100111
CEh
VDD
GND
PU
104
68
1101000
D0h
VDD
GND
VDD
105
69
1101001
D2h
VDD
PD
GND
106
6A
1101010
D4h
VDD
PD
PD
107
6B
1101011
D6h
VDD
PD
FLT
108
6C
1101100
D8h
VDD
PD
PU
109
6D
1101101
DAh
VDD
PD
VDD
110
6E
1101110
DCh
VDD
FLT
GND
111
6F
1101111
DEh
VDD
FLT
PD
112
70
1110000
E0h
VDD
FLT
FLT
113
71
1110001
E2h
VDD
FLT
PU
114
72
1110010
E4h
VDD
FLT
VDD
115
73
1110011
E6h
VDD
PU
GND
116
74
1110100
E8h
VDD
PU
PD
117
75
1110101
EAh
VDD
PU
FLT
118
76
1110110
ECh
VDD
PU
PU
119
77
1110111
EEh
F0h
VDD
PU
VDD
120
78
1111000[1]
VDD
VDD
GND
121
79
1111001[1]
F2h
7A
1111010[1]
F4h
7B
1111011[1]
F6h
F8h
FAh
VDD
VDD
VDD
PD
VDD
FLT
122
123
VDD
VDD
PU
124
7C
1111100[1]
VDD
VDD
VDD
125
7D
1111101[1]
[1]
See ‘Remark’ below.
Remark: Reserved I2C-bus addresses must be used with caution since they can interfere
with:
PCA9956B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
10 of 53
PCA9956B
NXP Semiconductors
24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
•
•
•
•
‘reserved for future use’ I2C-bus addresses (0000 011, 1111 1XX)
slave devices that use the 10-bit addressing scheme (1111 0XX)
slave devices that are designed to respond to the General Call address (0000 000)
High-speed mode (Hs-mode) master code (0000 1XX)
slave address(1)
A6
A5
A4
A3
A2
A1
A0 R/W
002aaf132
(1) This slave address must match one of the 125 internal addresses as shown in Table 5.
Fig 3.
PCA9956B slave address
The last bit of the address byte defines the operation to be performed. When set to logic 1
a read is selected, while a logic 0 selects a write operation.
7.1.2 LED All Call I2C-bus address
• Default power-up value (ALLCALLADR register): E0h or 1110 000X
• Programmable through I2C-bus (volatile programming)
• At power-up, LED All Call I2C-bus address is enabled. PCA9956B sends an ACK
when E0h (R/W = 0) or E1h (R/W = 1) is sent by the master.
See Section 7.3.10 “ALLCALLADR, LED All Call I2C-bus address” for more detail.
Remark: The default LED All Call I2C-bus address (E0h or 1110 000X) must not be used
as a regular I2C-bus slave address since this address is enabled at power-up. All of the
PCA9956Bs on the I2C-bus will acknowledge the address if sent by the I2C-bus master.
7.1.3 LED Sub Call I2C-bus addresses
• Three different I2C-bus addresses can be used
• Default power-up values:
– SUBADR1 register: EEh or 1110 111X
– SUBADR2 register: EEh or 1110 111X
– SUBADR3 register: EEh or 1110 111X
• Programmable through I2C-bus (volatile programming)
• At power-up, SUBADR1 is enabled while SUBADR2 and SUBADR3 I2C-bus
addresses are disabled.
Remark: At power-up SUBADR1 identifies this device as a 24-channel driver.
See Section 7.3.9 “LED Sub Call I2C-bus addresses for PCA9956B” for more detail.
Remark: The default LED Sub Call I2C-bus addresses may be used as regular I2C-bus
slave addresses as long as they are disabled.
PCA9956B
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
7.2 Control register
Following the successful acknowledgement of the slave address, LED All Call address or
LED Sub Call address, the bus master will send a byte to the PCA9956B, which will be
stored in the Control register.
The lowest 7 bits are used as a pointer to determine which register will be accessed
(D[6:0]). The highest bit is used as Auto-Increment Flag (AIF).
This bit along with the MODE1 register bit 5 and bit 6 provide the Auto-Increment feature.
register address
AIF
D6
D5
D4
D3
D2
Auto-Increment Flag
D1
D0
002aad850
reset state = 80h
Remark: The Control register does not apply to the Software Reset I2C-bus address.
Fig 4.
Control register
When the Auto-Increment Flag is set (AIF = logic 1), the seven low order bits of the
Control register are automatically incremented after a read or write. This allows the user to
program the registers sequentially. Four different types of Auto-Increment are possible,
depending on AI1 and AI0 values of MODE1 register.
Table 6.
Auto-Increment options
AIF
AI1[1]
AI0[1] Function
0
0
0
no Auto-Increment
1
0
0
Auto-Increment for registers (00h to 3Eh). D[6:0] roll over to 00h after the last
register 3Eh is accessed.
1
0
1
Auto-Increment for individual brightness registers only (0Ah to 21h).
D[6:0] roll over to 0Ah after the last register (21h) is accessed.
1
1
0
Auto-Increment for MODE1 to IREF23 control registers (00h to 39h). D[6:0]
roll over to 00h after the last register (39h) is accessed.
1
1
1
Auto-Increment for global control registers and individual brightness registers
(08h to 21h). D[6:0] roll over to 08h after the last register (21h) is accessed.
[1]
AI1 and AI0 come from MODE1 register.
Remark: Other combinations not shown in Table 6 (AIF + AI[1:0] = 001b, 010b and 011b)
are reserved and must not be used for proper device operation.
AIF + AI[1:0] = 000b is used when the same register must be accessed several times
during a single I2C-bus communication, for example, changes the brightness of a single
LED. Data is overwritten each time the register is accessed during a write operation.
AIF + AI[1:0] = 100b is used when all the registers must be sequentially accessed, for
example, power-up programming.
AIF + AI[1:0] = 101b is used when the 24 LED drivers must be individually programmed
with different values during the same I2C-bus communication, for example, changing color
setting to another color setting.
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
AIF + AI[1:0] = 110b is used when MODE1 to IREF23 registers must be programmed with
different settings during the same I2C-bus communication.
AIF + AI[1:0] = 111b is used when the 24 LED drivers must be individually programmed
with different values in addition to global programming.
Only the 7 least significant bits D[6:0] are affected by the AIF, AI1 and AI0 bits.
When the Control register is written, the register entry point determined by D[6:0] is the
first register that will be addressed (read or write operation), and can be anywhere
between 00h and 3Eh (as defined in Table 7). When AIF = 1, the Auto-Increment Flag is
set and the rollover value at which the register increment stops and goes to the next one
is determined by AIF, AI1 and AI0. See Table 6 for rollover values. For example, if MODE1
register bit AI1 = 0 and AI0 = 1 and if the Control register = 1001 0000, then the register
addressing sequence will be (in hexadecimal):
10  11  …  21  0A  0B  …  21  0A  0B  … as long as the master
keeps sending or reading data.
If MODE1 register bit AI1 = 0 and AI0 = 0 and if the Control register = 1010 0010, then the
register addressing sequence will be (in hexadecimal):
22  23  …  3E  00  01  …  21  0A  0B  … as long as the master
keeps sending or reading data.
If MODE1 register bit AI1 = 0 and AI0 = 1 and if the Control register = 1000 0101, then the
register addressing sequence will be (in hexadecimal):
05  06  …  21  0A  0B  …  21  0A  0B  … as long as the master
keeps sending or reading data.
Remark: Writing to registers marked ‘not used’ will return NACK.
7.3 Register definitions
Table 7.
Register summary
Register
D6
number (hex)
D5
D4
D3
D2
D1
D0
Name
Type
Function
00h
0
0
0
0
0
0
0
MODE1
read/write
Mode register 1
01h
0
0
0
0
0
0
1
MODE2
read/write
Mode register 2
02h
0
0
0
0
0
1
0
LEDOUT0
read/write
LED output state 0
03h
0
0
0
0
0
1
1
LEDOUT1
read/write
LED output state 1
04h
0
0
0
0
1
0
0
LEDOUT2
read/write
LED output state 2
05h
0
0
0
0
1
0
1
LEDOUT3
read/write
LED output state 3
06h
0
0
0
0
1
1
0
LEDOUT4
read/write
LED output state 4
07h
0
0
0
0
1
1
1
LEDOUT5
read/write
LED output state 5
08h
0
0
0
1
0
0
0
GRPPWM
read/write
group duty cycle control
09h
0
0
0
1
0
0
1
GRPFREQ
read/write
group frequency
0Ah
0
0
0
1
0
1
0
PWM0
read/write
brightness control LED0
0Bh
0
0
0
1
0
1
1
PWM1
read/write
brightness control LED1
0Ch
0
0
0
1
1
0
0
PWM2
read/write
brightness control LED2
0Dh
0
0
0
1
1
0
1
PWM3
read/write
brightness control LED3
0Eh
0
0
0
1
1
1
0
PWM4
read/write
brightness control LED4
PCA9956B
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
Table 7.
Register summary …continued
Register
D6
number (hex)
D5
D4
D3
D2
D1
D0
Name
Type
Function
0Fh
0
0
0
1
1
1
1
PWM5
read/write
brightness control LED5
10h
0
0
1
0
0
0
0
PWM6
read/write
brightness control LED6
11h
0
0
1
0
0
0
1
PWM7
read/write
brightness control LED7
12h
0
0
1
0
0
1
0
PWM8
read/write
brightness control LED8
13h
0
0
1
0
0
1
1
PWM9
read/write
brightness control LED9
14h
0
0
1
0
1
0
0
PWM10
read/write
brightness control LED10
15h
0
0
1
0
1
0
1
PWM11
read/write
brightness control LED11
16h
0
0
1
0
1
1
0
PWM12
read/write
brightness control LED12
17h
0
0
1
0
1
1
1
PWM13
read/write
brightness control LED13
18h
0
0
1
1
0
0
0
PWM14
read/write
brightness control LED14
19h
0
0
1
1
0
0
1
PWM15
read/write
brightness control LED15
1Ah
0
0
1
1
0
1
0
PWM16
read/write
brightness control LED16
1Bh
0
0
1
1
0
1
1
PWM17
read/write
brightness control LED17
1Ch
0
0
1
1
1
0
0
PWM18
read/write
brightness control LED18
1Dh
0
0
1
1
1
0
1
PWM19
read/write
brightness control LED19
1Eh
0
0
1
1
1
1
0
PWM20
read/write
brightness control LED20
1Fh
0
0
1
1
1
1
1
PWM21
read/write
brightness control LED21
20h
0
1
1
0
0
0
0
PWM22
read/write
brightness control LED22
21h
0
1
1
0
0
0
1
PWM23
read/write
brightness control LED23
22h
0
1
0
0
0
1
0
IREF0
read/write
output gain control register 0
23h
0
1
0
0
0
1
1
IREF1
read/write
output gain control register 1
24h
0
1
0
0
1
0
0
IREF2
read/write
output gain control register 2
25h
0
1
0
0
1
0
1
IREF3
read/write
output gain control register 3
26h
0
1
0
0
1
1
0
IREF4
read/write
output gain control register 4
27h
0
1
0
0
1
1
1
IREF5
read/write
output gain control register 5
28h
0
1
0
1
0
0
0
IREF6
read/write
output gain control register 6
29h
0
1
0
1
0
0
1
IREF7
read/write
output gain control register 7
2Ah
0
1
0
1
0
1
0
IREF8
read/write
output gain control register 8
2Bh
0
1
0
1
0
1
1
IREF9
read/write
output gain control register 9
2Ch
0
1
0
1
1
0
0
IREF10
read/write
output gain control register 10
2Dh
0
1
0
1
1
0
1
IREF11
read/write
output gain control register 11
2Eh
0
1
0
1
1
1
0
IREF12
read/write
output gain control register 12
2Fh
0
1
0
1
1
1
1
IREF13
read/write
output gain control register 13
30h
0
1
1
0
0
0
0
IREF14
read/write
output gain control register 14
31h
0
1
1
0
0
0
1
IREF15
read/write
output gain control register 15
32h
0
1
1
0
0
1
0
IREF16
read/write
output gain control register 16
33h
0
1
1
0
0
1
1
IREF17
read/write
output gain control register 17
34h
0
1
1
0
1
0
0
IREF18
read/write
output gain control register 18
35h
0
1
1
0
1
0
1
IREF19
read/write
output gain control register 19
36h
0
1
1
0
1
1
0
IREF20
read/write
output gain control register 20
PCA9956B
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
Table 7.
Register summary …continued
Register
D6
number (hex)
D5
D4
D3
D2
D1
D0
Name
Type
Function
37h
0
1
1
0
1
1
1
IREF21
read/write
output gain control register 21
38h
0
1
1
1
0
0
0
IREF22
read/write
output gain control register 22
39h
0
1
1
1
0
0
1
IREF23
read/write
output gain control register 23
3Ah
0
1
1
1
0
1
0
OFFSET
read/write
Offset/delay on LEDn outputs
3Bh
0
1
1
1
0
1
1
SUBADR1
read/write
I2C-bus subaddress 1
3Ch
0
1
1
1
1
0
0
SUBADR2
read/write
I2C-bus subaddress 2
3Dh
0
1
1
1
1
0
1
SUBADR3
read/write
I2C-bus subaddress 3
3Eh
0
1
1
1
1
1
0
ALLCALLADR
read/write
All Call I2C-bus address
3Fh
0
1
1
1
1
1
1
PWMALL
write only
brightness control for all LEDn
40h
1
0
0
0
0
0
0
IREFALL
write only
output gain control for all
registers IREF0 to IREF23
41h
1
0
0
0
0
0
1
EFLAG0
read only
output error flag 0
42h
1
0
0
0
0
1
0
EFLAG1
read only
output error flag 1
43h
1
0
0
0
0
1
1
EFLAG2
read only
output error flag 2
44h
1
0
0
0
1
0
0
EFLAG3
read only
output error flag 3
45h
1
0
0
0
1
0
1
EFLAG4
read only
output error flag 4
46h
1
0
0
0
1
1
0
EFLAG5
read only
output error flag 5
reserved
read only
not used[1]
47h to 7Fh
[1]
Reserved registers should not be written to and will always read back as zeros.
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
7.3.1 MODE1 — Mode register 1
Table 8.
MODE1 - Mode register 1 (address 00h) bit description
Legend: * default value.
Bit
Symbol
Access
Value
Description
7
AIF
read only
0
Register Auto-Increment disabled.
1*
Register Auto-Increment enabled.
0*
Auto-Increment bit 1 = 0. Auto-increment range as defined in Table 6.
1
Auto-Increment bit 1 = 1. Auto-increment range as defined in Table 6.
0*
Auto-Increment bit 0 = 0. Auto-increment range as defined in Table 6.
1
Auto-Increment bit 0 = 1. Auto-increment range as defined in Table 6.
0*
Normal mode[1].
1
Low power mode. Oscillator off[2][3].
0
PCA9956B does not respond to I2C-bus subaddress 1.
1*
PCA9956B responds to I2C-bus subaddress 1.
0*
PCA9956B does not respond to I2C-bus subaddress 2.
1
PCA9956B responds to I2C-bus subaddress 2.
0*
PCA9956B does not respond to I2C-bus subaddress 3.
1
PCA9956B responds to I2C-bus subaddress 3.
0
PCA9956B does not respond to LED All Call I2C-bus address.
1*
PCA9956B responds to LED All Call I2C-bus address.
6
AI1
5
AI0
4
R/W
SLEEP
3
SUB1
2
R/W
SUB3
0
R/W
R/W
SUB2
1
[1]
R/W
R/W
ALLCALL
R/W
It takes 500 s max. for the oscillator to be up and running once SLEEP bit has been set to logic 0. Timings on LEDn outputs are not
guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 s window.
[2]
No blinking or dimming is possible when the oscillator is off.
[3]
The device must be reset if the LED driver output state is set to LDRx=11 after the device is set back to Normal mode.
7.3.2 MODE2 — Mode register 2
Table 9.
MODE2 - Mode register 2 (address 01h) bit description
Legend: * default value.
Bit
Symbol
Access
7
OVERTEMP
read only
6
5
4
3
PCA9956B
Product data sheet
ERROR
DMBLNK
CLRERR
OCH
read only
R/W
write only
R/W
Value
Description
0*
O.K.
1
overtemperature condition
0*
no error at LED outputs
1
any open or short-circuit detected in error flag registers
(EFLAGn)
0*
group control = dimming
1
group control = blinking
0*
self clear after write ‘1’
1
Write ‘1’ to clear all error status bits in EFLAGn register
and ERROR (bit 6). The EFLAGn and ERROR bit will
set to ‘1’ if open or short-circuit is detected again.
0*
outputs change on STOP command
1
outputs change on ACK
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
Table 9.
MODE2 - Mode register 2 (address 01h) bit description …continued
Legend: * default value.
Bit
Symbol
Access
Value
Description
2
-
read only
1*
reserved
1
-
read only
0*
reserved
0
-
read only
1*
reserved
7.3.3 LEDOUT0 to LEDOUT5, LED driver output state
Table 10.
LEDOUT0 to LEDOUT5 - LED driver output state registers (address 02h to 07h)
bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
02h
LEDOUT0
7:6
LDR3
R/W
10*
LED3 output state control
5:4
LDR2
R/W
10*
LED2 output state control
3:2
LDR1
R/W
10*
LED1 output state control
1:0
LDR0
R/W
10*
LED0 output state control
7:6
LDR7
R/W
10*
LED7 output state control
5:4
LDR6
R/W
10*
LED6 output state control
3:2
LDR5
R/W
10*
LED5 output state control
1:0
LDR4
R/W
10*
LED4 output state control
7:6
LDR11
R/W
10*
LED11 output state control
5:4
LDR10
R/W
10*
LED10 output state control
3:2
LDR9
R/W
10*
LED9 output state control
1:0
LDR8
R/W
10*
LED8 output state control
7:6
LDR15
R/W
10*
LED15 output state control
5:4
LDR14
R/W
10*
LED14 output state control
3:2
LDR13
R/W
10*
LED13 output state control
1:0
LDR12
R/W
10*
LED12 output state control
7:6
LDR19
R/W
10*
LED19 output state control
5:4
LDR18
R/W
10*
LED18 output state control
3:2
LDR17
R/W
10*
LED17 output state control
1:0
LDR16
R/W
10*
LED16 output state control
7:6
LDR23
R/W
10*
LED23 output state control
5:4
LDR22
R/W
10*
LED22 output state control
3:2
LDR21
R/W
10*
LED21 output state control
1:0
LDR20
R/W
10*
LED20 output state control
03h
04h
05h
06h
07h
LEDOUT1
LEDOUT2
LEDOUT3
LEDOUT4
LEDOUT5
LDRx = 00 — LED driver x is off (x = 0 to 23).
LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking
not controlled). The OE pin can be used as external dimming/blinking control in this state.
LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx
register (default power-up state) or PWMALL register for all LEDn outputs.
LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be
controlled through its PWMx register and the GRPPWM registers.
PCA9956B
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
Remark: Setting the device in low power mode while being on group dimming/blinking
mode may cause the LED output state to be in an unknown state after the device is set
back to normal mode. The device must be reset and all register values reprogrammed.
7.3.4 GRPPWM, group duty cycle control
Table 11. GRPPWM - Group brightness control register (address 08h) bit description
Legend: * default value
Address
Register
Bit
Symbol
Access
Value
Description
08h
GRPPWM
7:0
GDC[7:0]
R/W
1111 1111*
GRPPWM register
When DMBLNK bit (MODE2 register) is programmed with logic 0, a 122 Hz fixed
frequency signal is superimposed with the 31.25 kHz individual brightness control signal.
GRPPWM is then used as a global brightness control allowing the LED outputs to be
dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’.
General brightness for the 24 outputs is controlled through 256 linear steps from 00h
(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT5
registers).
When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers
define a global blinking pattern, where GRPFREQ contains the blinking period (from
67 ms to 16.8 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
 7:0 
duty cycle = GDC
-------------------------256
(1)
7.3.5 GRPFREQ, group frequency
Table 12. GRPFREQ - Group frequency register (address 09h) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
09h
GRPFREQ
7:0
GFRQ[7:0]
R/W
0000 0000*
GRPFREQ register
GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2
register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT5
registers).
Blinking period is controlled through 256 linear steps from 00h (67 ms, frequency 15 Hz)
to FFh (16.8 s).
GFRQ  7:0  + 1
global blinking period = ----------------------------------------  s 
15.26
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
7.3.6 PWM0 to PWM23, individual brightness control
Table 13. PWM0 to PWM23 - PWM registers 0 to 23 (address 0Ah to 21h) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access Value
Description
0Ah
PWM0
7:0
IDC0[7:0]
R/W
0000 0000* PWM0 Individual Duty Cycle
0Bh
PWM1
7:0
IDC1[7:0]
R/W
0000 0000* PWM1 Individual Duty Cycle
0Ch
PWM2
7:0
IDC2[7:0]
R/W
0000 0000* PWM2 Individual Duty Cycle
0Dh
PWM3
7:0
IDC3[7:0]
R/W
0000 0000* PWM3 Individual Duty Cycle
0Eh
PWM4
7:0
IDC4[7:0]
R/W
0000 0000* PWM4 Individual Duty Cycle
0Fh
PWM5
7:0
IDC5[7:0]
R/W
0000 0000* PWM5 Individual Duty Cycle
10h
PWM6
7:0
IDC6[7:0]
R/W
0000 0000* PWM6 Individual Duty Cycle
11h
PWM7
7:0
IDC7[7:0]
R/W
0000 0000* PWM7 Individual Duty Cycle
12h
PWM8
7:0
IDC8[7:0]
R/W
0000 0000* PWM8 Individual Duty Cycle
13h
PWM9
7:0
IDC9[7:0]
R/W
0000 0000* PWM9 Individual Duty Cycle
14h
PWM10
7:0
IDC10[7:0]
R/W
0000 0000* PWM10 Individual Duty Cycle
15h
PWM11
7:0
IDC11[7:0]
R/W
0000 0000* PWM11 Individual Duty Cycle
16h
PWM12
7:0
IDC12[7:0]
R/W
0000 0000* PWM12 Individual Duty Cycle
17h
PWM13
7:0
IDC13[7:0]
R/W
0000 0000* PWM13 Individual Duty Cycle
18h
PWM14
7:0
IDC14[7:0]
R/W
0000 0000* PWM14 Individual Duty Cycle
19h
PWM15
7:0
IDC15[7:0]
R/W
0000 0000* PWM15 Individual Duty Cycle
1Ah
PWM16
7:0
IDC16[7:0]
R/W
0000 0000* PWM16 Individual Duty Cycle
1Bh
PWM17
7:0
IDC17[7:0]
R/W
0000 0000* PWM17 Individual Duty Cycle
1Ch
PWM18
7:0
IDC18[7:0]
R/W
0000 0000* PWM18 Individual Duty Cycle
1Dh
PWM19
7:0
IDC19[7:0]
R/W
0000 0000* PWM19 Individual Duty Cycle
1Eh
PWM20
7:0
IDC20[7:0]
R/W
0000 0000* PWM20 Individual Duty Cycle
1Fh
PWM21
7:0
IDC21[7:0]
R/W
0000 0000* PWM21 Individual Duty Cycle
20h
PWM22
7:0
IDC22[7:0]
R/W
0000 0000* PWM22 Individual Duty Cycle
21h
PWM23
7:0
IDC23[7:0]
R/W
0000 0000* PWM23 Individual Duty Cycle
A 31.25 kHz fixed frequency signal is used for each output. Duty cycle is controlled
through 256 linear steps from 00h (0 % duty cycle = LED output off) to FFh
(99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs
programmed with LDRx = 10 or 11 (LEDOUT0 to LEDOUT5 registers).
IDCx  7:0 
duty cycle = --------------------------256
(3)
Remark: The first lower end 8 steps of PWM and the last (higher end) steps of PWM will
not have effective brightness control of LEDs due to edge rate control of LED output pins.
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
7.3.7 IREF0 to IREF23, LED output current value registers
These registers reflect the gain settings for output current for LED0 to LED23.
Table 14.
IREF0 to IREF23 - LED output gain control registers (address 22h to 39h)
bit description
Legend: * default value.
Address
Register
Bit
Access
Value
Description
22h
IREF0
7:0
R/W
00h*
LED0 output current setting
23h
IREF1
7:0
R/W
00h*
LED1 output current setting
24h
IREF2
7:0
R/W
00h*
LED2 output current setting
25h
IREF3
7:0
R/W
00h*
LED3 output current setting
26h
IREF4
7:0
R/W
00h*
LED4 output current setting
27h
IREF5
7:0
R/W
00h*
LED5 output current setting
28h
IREF6
7:0
R/W
00h*
LED6 output current setting
29h
IREF7
7:0
R/W
00h*
LED7 output current setting
2Ah
IREF8
7:0
R/W
00h*
LED8 output current setting
2Bh
IREF9
7:0
R/W
00h*
LED9 output current setting
2Ch
IREF10
7:0
R/W
00h*
LED10 output current setting
2Dh
IREF11
7:0
R/W
00h*
LED11 output current setting
2Eh
IREF12
7:0
R/W
00h*
LED12 output current setting
2Fh
IREF13
7:0
R/W
00h*
LED13 output current setting
30h
IREF14
7:0
R/W
00h*
LED14 output current setting
31h
IREF15
7:0
R/W
00h*
LED15 output current setting
32h
IREF16
7:0
R/W
00h*
LED16 output current setting
33h
IREF17
7:0
R/W
00h*
LED17 output current setting
34h
IREF18
7:0
R/W
00h*
LED18 output current setting
35h
IREF19
7:0
R/W
00h*
LED19 output current setting
36h
IREF20
7:0
R/W
00h*
LED20 output current setting
37h
IREF21
7:0
R/W
00h*
LED21 output current setting
38h
IREF22
7:0
R/W
00h*
LED22 output current setting
39h
IREF23
7:0
R/W
00h*
LED23 output current setting
7.3.8 OFFSET — LEDn output delay offset register
Table 15. OFFSET - LEDn output delay offset register (address 3Ah) bit description
Legend: * default value.
Address
Register
Bit
Access
Value
3Ah
OFFSET
7:4
read only 0000*
not used
3:0
R/W
LEDn output delay offset factor
1000*
Description
The PCA9956B can be programmed to have turn-on delay between LED outputs. This
helps to reduce peak current for the VDD supply and reduces EMI.
The order in which the LED outputs are enabled will always be the same (channel 0 will
enable first and channel 23 will enable last).
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
OFFSET control register bits [3:0] determine the delay used between the turn-on times as
follows:
0000 = no delay between outputs (all on, all off at the same time)
0001 = delay of 1 clock cycle (125 ns) between successive outputs
0010 = delay of 2 clock cycles (250 ns) between successive outputs
0011 = delay of 3 clock cycles (375 ns) between successive outputs
:
0111 = delay of 7 clock cycles (875 ns) between successive outputs
1000 = delay of 8 clock cycles (1 s) between successive outputs
1001 = delay of 9 clock cycles (1.125 s) between successive outputs
1010 = delay of 10 clock cycles (1.25 s) between successive outputs
1011 = delay of 11 clock cycles (1.375 s) between successive outputs
1100 to 1111 = reserved and do not use
Example: If the value in the OFFSET register is 1000 the corresponding delay =
8  125 ns = 1 s delay between successive outputs.
channel 0 turns on at time 0 s
channel 1 turns on at time 1 s
channel 2 turns on at time 2 s
channel 3 turns on at time 3 s
channel 4 turns on at time 4 s
channel 5 turns on at time 5 s
channel 6 turns on at time 6 s
channel 7 turns on at time 7 s
channel 8 turns on at time 8 s
channel 9 turns on at time 9 s
channel 10 turns on at time 10 s
channel 11 turns on at time 11 s
channel 12 turns on at time 12 s
channel 13 turns on at time 13 s
channel 14 turns on at time 14 s
channel 15 turns on at time 15 s
channel 16 turns on at time 16 s
channel 17 turns on at time 17 s
channel 18 turns on at time 18 s
channel 19 turns on at time 19 s
channel 20 turns on at time 20 s
channel 21 turns on at time 21 s
channel 22 turns on at time 22 s
channel 23 turns on at time 23 s
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
7.3.9 LED Sub Call I2C-bus addresses for PCA9956B
SUBADR1 to SUBADR3 - I2C-bus subaddress registers 1 to 3 (address 3Bh to
3Dh) bit description
Legend: * default value.
Table 16.
Address
Register
Bit
Symbol
Access Value
Description
3Bh
SUBADR1
7:1
A1[7:1]
R/W
1110 111*
I2C-bus subaddress 1
0
A1[0]
R only
0*
reserved
A2[7:1]
R/W
1110 111*
I2C-bus subaddress 2
3Ch
SUBADR2
7:1
0
A2[0]
R only
0*
reserved
3Dh
SUBADR3
7:1
A3[7:1]
R/W
1110 111*
I2C-bus subaddress 3
0
A3[0]
R only
0*
reserved
Default power-up values are EEh, EEh, EEh. At power-up, SUBADR1 is enabled while
SUBADR2 and SUBADR3 are disabled. The power-up default bit subaddress of EEh
indicates that this device is a 24-channel LED driver.
All three subaddresses are programmable. Once subaddresses have been programmed
to their right values, SUBx bits need to be set to logic 1 in order to have the device
acknowledging these addresses (MODE1 register) (0). When SUBx is set to logic 1, the
corresponding I2C-bus subaddress can be used during either an I2C-bus read or write
sequence.
7.3.10 ALLCALLADR, LED All Call I2C-bus address
ALLCALLADR - LED All Call I2C-bus address register (address 3Eh) bit
description
Legend: * default value.
Table 17.
Address
Register
Bit
Symbol
Access Value
Description
3Eh
ALLCALLADR
7:1
AC[7:1]
R/W
1110 000*
ALLCALL I2C-bus
address register
0
AC[0]
R only
0*
reserved
The LED All Call I2C-bus address allows all the PCA9956Bs on the bus to be programmed
at the same time (ALLCALL bit in register MODE1 must be equal to logic 1 [power-up
default state]). This address is programmable through the I2C-bus and can be used during
either an I2C-bus read or write sequence. The register address can also be programmed
as a Sub Call.
Only the 7 MSBs representing the All Call I2C-bus address are valid. The LSB in
ALLCALLADR register is a read-only bit (0).
If ALLCALL bit = 0 in MODE1 register, the device does not acknowledge the address
programmed in register ALLCALLADR.
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
7.3.11 PWMALL — brightness control for all LEDn outputs
When programmed, the value in this register will be used for PWM duty cycle for all the
LEDn outputs and will be reflected in PWM 0 through PWM23 registers.
Table 18.
PWMALL - brightness control for all LEDn outputs register (address 3Fh)
bit description
Legend: * default value.
Address
Register
Bit
Access
Value
Description
3Fh
PWMALL
7:0
write only
0000 0000*
duty cycle for all LEDn outputs
Remark: Write to any of the PWM0 to PWM23 registers will overwrite the value in
corresponding PWMn register programmed by PWMALL.
7.3.12 IREFALL register: output current value for all LED outputs
The output current setting for all outputs is held in this register. When this register is
written to or updated, all LED outputs will be set to a current corresponding to this register
value.
Writes to IREF0 to IREF23 will overwrite the output current settings.
Table 19. IREFALL - Output gain control for all LED outputs (address 40h) bit description
Legend: * default value.
Address
Register
Bit
Access
Value
Description
40h
IREFALL
7:0
write only
00h*
Current gain setting for all LED outputs.
7.3.13 LED driver constant current outputs
In LED display applications, PCA9956B provides nearly no current variations from
channel to channel and from device to device. The maximum current skew between
channels is less than 4 % and less than 6 % between devices.
7.3.13.1
Adjusting output current
The PCA9956B scales up the reference current (Iref) set by the external resistor (Rext) to
sink the output current (IO) at each output port. The maximum output current for the
outputs can be set using Rext. In addition, the constant value for current drive at each of
the outputs is independently programmable using command registers IREF0 to IREF23.
Alternatively, programming the IREFALL register allows all outputs to be set at one current
value determined by the value in IREFALL register.
Equation 4 and Equation 5 can be used to calculate the minimum and maximum constant
current values that can be programmed for the outputs for a chosen Rext.
900 mV 1
I O _LED_MIN = -------------------  ---  minimum constant current 
4
R ext
(4)
900 mV 255
I O _LED_MAX =  255  I O _LED_MIN  =  -------------------  ---------
 R ext
4 
(5)
900 mV 1
For a given IREFx setting, I O _LED = IREFx  -------------------  --- .
4
R ext
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
002aag288
80
IREFx = 255
IO(LEDn)
(mA)
60
40
20
0
1
2
4
3
5
6
8
7
9
10
Rext (kΩ)
IO(LEDn) (mA) = IREFx  (0.9 / 4) / Rext (k)
maximum IO(LEDn) (mA) = 255  (0.9 / 4) / Rext (k)
Remark: Default IREFx at power-up = 0.
Fig 5.
Maximum ILED versus Rext
Example 1: If Rext = 1 k, IO_LED_MIN = 225 A, IO_LED_MAX = 57.375 mA (as shown
in Figure 6).
So each channel can be programmed with its individual IREFx in 256 steps and in 225 A
increments to a maximum output current of 57.375 mA independently.
002aah691
60
IO(target)
(mA)
50
57.375
40
30
20
10
0
0
Fig 6.
32
64
96
128
160
192
224
255
IREFx[7:0] value
IO(target) versus IREFx value with Rext = 1 k
Example 2: If Rext = 2 k, IO_LED_MIN = 112.5 A, IO_LED_MAX = 28.687 mA
(as shown in Figure 7).
So each channel can be programmed with its individual IREFx in 256 steps and in
112.5 A increments to a maximum output channel of 28.687 mA independently.
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
002aah667
30
IO(target)
(mA)
20
10
0
0
Fig 7.
64
32
96
128
160
192
255
224
IREFx[7:0] value
IO(target) versus IREFx value with Rext = 2 k
7.3.14 LED error detection
The PCA9956B is capable of detecting an LED open or a short condition at its open-drain
LED outputs. Users will recognize these faults by reading the status of a pair of error bits
(ERRx) in error flag registers (EFLAGn) for each channel. Both LDRx value in LEDOUTx
registers and IREFx value must be set to ‘00’ for those unused LED output channels. If the
output is selected to be fully on, individual dim, or individual and group dim, that channel
will be tested.
The user can poll the ERROR status bit (bit 6 in MODE2 register) to check if there is a
fault condition in any of the 24 channels. The EFLAGn registers can then be read to
determine which channels are at fault and the type of fault in those channels. The error
status reported by the EFLAGn register is real time information that will get self cleared
once the error is fixed and write ‘1’ to CLRERR (bit 4 in MODE2 register).
Remark: Checks for open and short-circuit will not occur if the PWM value in PWM0 to
PWM23 registers is less than 8.
Table 20. EFLAG0 to EFLAG5 - Error flag registers (address 41h to 46h) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
41h
EFLAG0
7:6
ERR3
R only
00*
Error status for LED3 output
5:4
ERR2
R only
00*
Error status for LED2 output
3:2
ERR1
R only
00*
Error status for LED1 output
1:0
ERR0
R only
00*
Error status for LED0 output
7:6
ERR7
R only
00*
Error status for LED7 output
5:4
ERR6
R only
00*
Error status for LED6 output
3:2
ERR5
R only
00*
Error status for LED5 output
1:0
ERR4
R only
00*
Error status for LED4 output
7:6
ERR11
R only
00*
Error status for LED11 output
5:4
ERR10
R only
00*
Error status for LED10 output
3:2
ERR9
R only
00*
Error status for LED9 output
1:0
ERR8
R only
00*
Error status for LED8 output
42h
43h
PCA9956B
Product data sheet
EFLAG1
EFLAG2
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
Table 20.
EFLAG0 to EFLAG5 - Error flag registers (address 41h to 46h) bit description
…continued
Address
Register
Bit
Symbol
Access
Value
Description
44h
EFLAG3
7:6
ERR15
R only
00*
Error status for LED15 output
5:4
ERR14
R only
00*
Error status for LED14 output
3:2
ERR13
R only
00*
Error status for LED13 output
1:0
ERR12
R only
00*
Error status for LED12 output
7:6
ERR19
R only
00*
Error status for LED19 output
5:4
ERR18
R only
00*
Error status for LED18 output
3:2
ERR17
R only
00*
Error status for LED17 output
1:0
ERR16
R only
00*
Error status for LED16 output
7:6
ERR23
R only
00*
Error status for LED23 output
5:4
ERR22
R only
00*
Error status for LED22 output
3:2
ERR21
R only
00*
Error status for LED21 output
1:0
ERR20
R only
00*
Error status for LED20 output
45h
EFLAG4
46h
EFLAG5
Table 21.
ERRx bit description
LED error detection
status
7.3.14.1
ERRx
Description
Bit 1
Bit 0
No error
0
0
In normal operation and no error
Short-circuit
0
1
Detected LED short-circuit condition
Open-circuit
1
0
Detected LED open-circuit condition
DNE (Do Not Exist)
1
1
This condition does not exist
Open-circuit detection principle
The PCA9956B LED open-circuit detection compares the effective current level IO with the
open load detection threshold current Ith(det). If IO is below the threshold Ith(det), the
PCA9956B detects an open load condition. This error status can be read out as an
error flag through the EFLAGn registers. For open-circuit error detection of an output
channel, that channel must be ON.
Table 22.
State of
output port
Condition of
output current
Error status code
Description
OFF
IO = 0 mA
ON
[1]
PCA9956B
Product data sheet
Open-circuit detection
0
detection not possible
IO <
Ith(det)[1]
1
open-circuit
IO 
Ith(det)[1]
this channel open error
status bit is 0
normal
Ith(det) = 0.5  IO(target) (typical). This threshold may be different for each I/O and only depends on IREFx and
Rext.
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
7.3.14.2
Short-circuit detection principle
The LED short-circuit detection compares the effective output voltage level (VO) with the
shorted-load detection threshold voltages Vth(trig). If VO is above the Vth(trig) threshold, the
PCA9956B detects a shorted-load condition. If VO is below the Vth(trig) threshold, no error
is detected and error bit is set to ‘0’. This error status can be read out as an error flag
through the EFLAGn registers. For short-circuit error detection of an output channel, that
channel must be ON.
Table 23.
Short-circuit detection
State of
output port
Condition of
output voltage
Error status code
Description
OFF
-
0
detection not possible
ON
VO 
1
short-circuit
this channel short error
status bit is 0
normal
Vth(trig)[1]
VO < Vth(trig)
[1]
[1]
Vth  2.85 V.
Remark: The error status distinguishes between an LED short condition and an LED
open condition. Upon detecting an LED short or open, the corresponding LED outputs
should be turned OFF to prevent heat dissipation for a short in the chip. Although an open
event will not be harmful, the outputs should be turned OFF for both occasions to repair
the LED string.
7.3.15 Overtemperature protection
If the PCA9956B chip temperature exceeds its limit (Tmax, see Table 26), all output
channels will be disabled until the temperature drops below its limit minus a small
hysteresis (Thys, see Table 26). When an overtemperature situation is encountered, the
OVERTEMP flag (bit 7) is set in the MODE2 register. Once the die temperature reduces
below the Tmax  Thys, the chip will return to the same condition it was prior to the
overtemperature event and the OVERTEMP flag will be cleared.
PCA9956B
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
7.4 Active LOW output enable input
The active LOW output enable (OE) pin on PCA9956B allows to enable or disable all the
LED outputs at the same time.
• When a LOW level is applied to OE pin, all the LED outputs are enabled.
• When a HIGH level is applied to OE pin, all the LED outputs are high-impedance.
The OE pin can be used as a synchronization signal to switch on/off several PCA9956B
devices at the same time when LED drive output state is set fully ON (LDRx = 01 in
LEDOUTx register) in these devices. This requires an external clock reference that
provides blinking period and the duty cycle.
The OE pin can also be used as an external dimming control signal. The frequency of the
external clock must be high enough not to be seen by the human eye, and the duty cycle
value determines the brightness of the LEDs.
Remark: Do not use OE as an external blinking control signal when internal global
blinking is selected (DMBLNK = 1, MODE2 register) since it will result in an undefined
blinking pattern. Do not use OE as an external dimming control signal when internal global
dimming is selected (DMBLNK = 0, MODE2 register) since it will result in an undefined
dimming pattern.
7.5 Power-on reset
When power is applied to VDD, an internal power-on reset holds the PCA9956B in a reset
condition until VDD has reached VPOR. At this point, the reset condition is released and the
PCA9956B registers and I2C-bus state machine are initialized to their default states (all
zeroes) causing all the channels to be deselected. Thereafter, VDD must be pulled lower
than 1 V and stay LOW for longer than 20 s. The device will reset itself, and allow 2 ms
for the device to fully wake up.
7.6 Hardware reset recovery
When a reset of PCA9956B is activated using an active LOW input on the RESET pin, a
reset pulse width of 2.5 s minimum is required. The maximum wait time after RESET pin
is released is 1.5 ms.
PCA9956B
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
7.7 Software reset
The Software Reset Call (SWRST Call) allows all the devices in the I2C-bus to be reset to
the power-up state value through a specific formatted I2C-bus command. To be performed
correctly, it implies that the I2C-bus is functional and that there is no device hanging the
bus.
The maximum wait time after software reset is 1 ms.
The SWRST Call function is defined as the following:
1. A START command is sent by the I2C-bus master.
2. The reserved General Call address ‘0000 000’ with the R/W bit set to ‘0’ (write) is sent
by the I2C-bus master.
3. The PCA9956B device(s) acknowledge(s) after seeing the General Call address
‘0000 0000’ (00h) only. If the R/W bit is set to ‘1’ (read), no acknowledge is returned to
the I2C-bus master.
4. Once the General Call address has been sent and acknowledged, the master sends
1 byte with 1 specific value (SWRST data byte 1):
a. Byte 1 = 06h: the PCA9956B acknowledges this value only. If byte 1 is not equal to
06h, the PCA9956B does not acknowledge it.
If more than 1 byte of data is sent, the PCA9956B does not acknowledge any more.
5. Once the correct byte (SWRST data byte 1) has been sent and correctly
acknowledged, the master sends a STOP command to end the SWRST function: the
PCA9956B then resets to the default value (power-up value) and is ready to be
addressed again within the specified bus free time (tBUF).
General Call address
S
0
0
0
0
START condition
0
0
0
SWRST data byte 1
0
A
0
0
0
acknowledge
from slave
0
0
1
1
0
A
P
acknowledge
from slave
STOP
condition
002aac900
Fig 8.
SWRST Call
The I2C-bus master must interpret a non-acknowledge from the PCA9956B (at any time)
as a ‘SWRST Call Abort’. The PCA9956B does not initiate a reset of its registers. This
happens only when the format of the SWRST Call sequence is not correct.
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
7.8 Individual brightness control with group dimming/blinking
A 31.25 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is
used to control individually the brightness for each LED.
On top of this signal, one of the following signals can be superimposed (this signal can be
applied to the 24 LED outputs LED0 to LED23).
• A lower 122 Hz fixed frequency signal with programmable duty cycle (8 bits,
256 steps) is used to provide a global brightness control.
• A programmable frequency signal from 15 Hz to every 16.8 seconds (8 bits,
256 steps) with programmable duty cycle (8 bits, 256 steps) is used to provide a
global blinking control.
1
2
3
4
5
6
7
8
9 10 11 12
251
252
253
254
255
256
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9 10 11
Brightness Control signal (LEDn)
N × 125 ns
with N = (0 to 255)
(PWMx Register)
M × 256 × 125 ns
with M = (0 to 255)
(GRPPWM Register)
256 × 125 ns = 32 μs
(31.25 kHz)
Group Dimming signal
256 × 256 × 125 ns = 8.19 ms (122 Hz)
1
2
3
4
5
6
7
8
resulting Brightness + Group Dimming signal
002aaf935
Minimum pulse width for LEDn Brightness Control is 125 ns.
Minimum pulse width for Group Dimming is 32 s.
When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal will have 1 pulse of the
LED Brightness Control signal (pulse width = N  125 ns, with ‘N’ defined in PWMx register).
This resulting Brightness + Group Dimming signal above shows a resulting Control signal with M = 8.
Fig 9.
Brightness + Group Dimming signals
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
8. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 10).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 10. Bit transfer
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 11).
SDA
SCL
S
P
START condition
STOP condition
mba608
Fig 11. Definition of START and STOP conditions
8.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 12).
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
I2C-BUS
MULTIPLEXER
SLAVE
002aaa966
Fig 12. System configuration
8.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from master
1
2
S
START
condition
8
9
clock pulse for
acknowledgement
002aaa987
Fig 13. Acknowledgement on the I2C-bus
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
9. Bus transactions
slave address
control register
S A6 A5 A4 A3 A2 A1 A0 0
START condition
A
data for register D[7:0]
X D6 D5 D4 D3 D2 D1 D0 A
register address(1)
R/W
Auto-Increment flag
A
acknowledge
from slave
P
acknowledge
from slave
acknowledge
from slave
STOP
condition
002aaf134
(1) See Table 7 for register definition.
Fig 14. Write to a specific register
slave address
S A6 A5 A4 A3 A2 A1 A0 0
START condition
MODE1 register data(1)
control register
A
R/W
acknowledge
from slave
1
0
0
0
0
0
0
0
MODE1
register selection
Auto-Increment on
A
acknowledge
from slave
MODE2 register data
A
A
acknowledge
from slave
acknowledge
from slave
(cont.)
ALLCALLADR register data
(cont.)
A
P
acknowledge
from slave
STOP
condition
002aaf135
(1) AI1, AI0 = 00. See Table 6 for Auto-Increment options.
Remark: Care should be taken to load the appropriate value here in the AI1 and AI0 bits of the MODE1 register for
programming the part with the required Auto-Increment options.
Fig 15. Write to all registers using the Auto-Increment feature
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PCA9956B
Product data sheet
slave address
control register
START condition
A
0
0
0
1
0
1
0
PWM0
register selection
R/W
acknowledge
from slave
A
acknowledge
from slave
A
A
acknowledge
from slave
acknowledge
from slave
(cont.)
Auto-Increment on
register rollover
PWM23 register data
PWM0 register data
PWM22 register data
(cont.)
1
PWM1 register data
PWM22 register data
PWM23 register data
A
A
A
A
A
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
P
STOP
condition
002aaf136
Fig 16. Multiple writes to Individual Brightness registers only using the Auto-Increment feature
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This example assumes that AIF + AI[1:0] = 101b.
24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
Rev. 1.1 — 15 December 2015
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S A6 A5 A4 A3 A2 A1 A0 0
PWM0 register data
PCA9956B
NXP Semiconductors
24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
slave address
ReSTART
condition
control register
S A6 A5 A4 A3 A2 A1 A0 0
START condition
A
R/W
acknowledge
from slave
data from MODE2 register
(cont.)
1
0
0
0
0
0
0
0
MODE1
register selection
Auto-Increment on
slave address
A Sr A6 A5 A4 A3 A2 A1 A0 1
A (cont.)
A
R/W
acknowledge
from slave
acknowledge
from master
acknowledge
from slave
data from
ALLCALLADR register
data from LEDOUT0
data from MODE1 register
data from
MODE1 register
A
A
A
acknowledge
from master
acknowledge
from master
acknowledge
from master
A (cont.)
acknowledge
from master
data from last read byte
(cont.)
A
not acknowledge
from master
P
STOP
condition
002aaf137
This example assumes that the MODE1[5] = 0 and MODE1[6] = 0.
Fig 17. Read all registers using the Auto-Increment feature
slave address
data from register
data from register
S A6 A5 A4 A3 A2 A1 A0 1
A
A
START condition
acknowledge
from slave
acknowledge
from master
R/W
data from register
A
no acknowledge
from master
P
STOP
condition
002aaf138
Remark: A read operation can be done without doing a write operation before it. In this case, the data sent out is from the
register pointed to by the control register (written to during the last write operation) with the Auto-Increment options in the
MODE1 register (written to during the last write operation).
Fig 18. Read of registers
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
slave address(1)
new LED All Call I2C address(2)
control register
sequence (A) S A6 A5 A4 A3 A2 A1 A0 0
START condition
A
1
0
1
1
1
1
1
0
A
ALLCALLADR
register selection
R/W
acknowledge
from slave
1
0
1
0
1
acknowledge
from slave
0
1
X
A
P
acknowledge
from slave
Auto-Increment on
STOP condition
the 24 LEDs are on at the acknowledge(3)
LED All Call I2C address
sequence (B) S
1
0
1
0
1
0
1
START condition
control register
0
A
1
0
0
0
LEDOUT3 register (LED fully ON)
1
0
1
0
1
0
1
1
0
A
acknowledge
from the 4 devices
1
0
1
0
1
0
1
A (cont.)
acknowledge
from the 4 devices
acknowledge
from the 4 devices
the 24 LEDs are on
at the acknowledge(3)
LEDOUT4 register (LED fully ON)
A
0
Auto-Increment on
the 24 LEDs are on
at the acknowledge(3)
0
0
LEDOUT0
register selection
R/W
acknowledge
from the 4 devices
(cont.)
0
LEDOUT0 register (LED fully ON)
0
1
0
1
0
1
0
1
the 24 LEDs are on
at the acknowledge(3)
LEDOUT5 register (LED fully ON)
A
0
1
acknowledge
from the 4 devices
0
1
0
1
0
1
A
acknowledge
from the 4 devices
P
STOP condition
002aaf139
(1) In this example, several PCA9956Bs are used and the same sequence (A) (above) is sent to each of them.
(2) ALLCALL bit in MODE1 register is previously set to 1 for this example.
(3) OCH bit in MODE2 register is previously set to 1 for this example.
Fig 19. LED All Call I2C-bus address programming and LED All Call sequence example
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
10. Application design-in information
VDD = 3.3 V or 5.0 V
1.6 kΩ
1.6 kΩ
10 kΩ(1)
10 kΩ(3)
up to 20 V
I2C-BUS/SMBus
MASTER
SDA
SDA
SCL
SCL
OE
OE
VDD
RESET
LED0
LED1
LED2
RESET
LED3
LED4
PCA9956B
LED5
LED6
LED7
REXT
LED8
ISET
LED9
LED10
LED18
AD0(2)
LED19
AD1
AD2
LED20
LED21
LED22
VSS
LED23
VSS
C
10 μF
aaa-017235
(1) OE requires pull-up resistor if control signal from the master is open-drain.
(2) I2C-bus address = 1101001 when AD0, AD2 tied to VDD and AD1 tied to VSS (see Table 5).
(3) RESET requires a pull-up resistor of <100 k if not used or connected to open-drain output
Fig 20. Typical application
10.1 Thermal considerations
Since the PCA9956B device integrates 24 linear current sources, thermal considerations
should be taken into account to prevent overheating, which can cause the device to go
into thermal shutdown.
Perhaps the major contributor for device’s overheating is the LED forward voltage
mismatch. This is because it can cause significant voltage differences between the LED
strings of the same type (e.g., 2 V to 3 V), which ultimately translates into higher power
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
dissipation in the device. The voltage drop across the LED channels of the device is given
by the difference between the supply voltage and the LED forward voltage of each LED
string. Reducing this to a minimum (e.g., 0.8 V) helps to keep the power dissipation down.
Therefore LEDs binning is recommended to minimize LED voltage forward variation and
reduce power dissipation in the device.
In order to ensure that the device will not go into thermal shutdown when operating under
certain application conditions, its junction temperature (Tj) should be calculated to ensure
that is below the overtemperature threshold limit (130 C). The Tj of the device depends
on the ambient temperature (Tamb), device’s total power dissipation (Ptot), and thermal
resistance.
The device junction temperature can be calculated by using the following equation:
T j = T amb + R th  j-a   P tot
(6)
where:
Tj = junction temperature
Tamb = ambient temperature
Rth(j-a) = junction to ambient thermal resistance
Ptot = (device) total power dissipation
An example of this calculation is show below:
Conditions:
Tamb = 50 C
Rth(j-a) = 33.9 C/W (per JEDEC 51 standard for multilayer PCB)
ILED = 30 mA / channel
IDD(max) = 20 mA
VDD = 5 V
LEDs per channel = 5 LEDs / channel
LED VF(typ) = 3 V per LED (15 V total for 5 LEDs in series)
LED VF mismatch = 0.2 V per LED (1 V total for 5 LEDs in series)
Vreg(drv) = 0.8 V (This will be present only in the LED string with the highest LED forward
voltage.)
Vsup = LED VF(typ) + LED VF mismatch + Vreg(drv) = 15 V + 1 V + 0.8 V = 16.8 V
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
Ptot calculation:
Ptot = IC_power + LED drivers_power;
IC_power = (IDD  VDD) + (SDA_VOL  IOL)
IC_power = (0.02 A  5 V) + (0.4 V  0.03 A) = 0.112 W
LED drivers_power = [(24  1)  (ILED)  (LED VF mismatch + Vreg(drv))] +
(ILED  Vreg(drv))
LED drivers_power = [23  0.03 A  (1 V + 0.8 V)] + (0.03 A  0.8 V)] = 1.266 W
Ptot = 0.112 W + 1.266 W = 1.378 W
Tj calculation:
Tj = Tamb + Rth(j-a)  Ptot
Tj = 50 C + (33.9 C/W  1.378 W) = 96.71 C
This confirms that the junction temperature is below the minimum overtemperature
threshold of 130 C, which ensures the device will not go into thermal shutdown under
these conditions.
It is important to mention that the value of the thermal resistance junction-to-ambient
(Rth(j-a)) strongly depends in the PCB design. Therefore, the thermal pad of the device
should be attached to a big enough PCB copper area to ensure proper thermal dissipation
(similar to JEDEC 51 standard). Several thermal vias in the PCB thermal pad should be
used as well to increase the effectiveness of the heat dissipation (e.g., 15 thermal vias).
The thermal vias should be distributed evenly in the PCB thermal pad.
Finally, it is important to point out that this calculation should be taken as a reference only
and therefore evaluations should still be performed under the application environment and
conditions to confirm proper system operation.
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
11. Limiting values
Table 24. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
Min
Max
Unit
supply voltage
0.5
+6.0
V
VI/O
voltage on an input/output pin
VSS  0.5
5.5
V
Vdrv(LED)
LED driver voltage
VSS  0.5
20
V
IO(LEDn)
output current on pin LEDn
-
65
mA
ISS
ground supply current
-
2.5
A
Ptot
total power dissipation
Tamb = 25 C
-
2.95
W
Tamb = 85 C
-
1.18
W
65
+150
C
40
+85
C
40
+125
C
Tstg
storage temperature
Tamb
ambient temperature
Tj
junction temperature
Conditions
operating
12. Thermal characteristics
Table 25.
Thermal characteristics
Symbol
Parameter
Conditions
Rth(j-a)
thermal resistance from junction to ambient
HTSSOP38
[1]
[1]
Typ
Unit
33.9
C/W
Per JEDEC 51 standard for multilayer PCB and Wind Speed (m/s) = 0.
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
13. Static characteristics
Table 26. Static characteristics
VDD = 3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Min
Typ[1]
Max
Unit
3
-
5.5
V
Rext = 2 k; LED[23:0] = off;
IREFx = 00h
-
11
12
mA
Rext = 1 k; LED[23:0] = off;
IREFx = 00h
-
13
14
mA
Rext = 2 k; LED[23:0] = on;
IREFx = FFh
-
15
19
mA
Rext = 1 k; LED[23:0] = on;
IREFx = FFh
-
17
21
mA
VDD = 3.3 V
-
100
600
A
VDD = 5.5 V
-
100
700
A
-
2
-
V
-
1
-
V
-
+0.3VDD V
Conditions
Supply
VDD
supply voltage
IDD
supply current
Istb
VPOR
VPDR
standby current
power-on reset voltage
power-down reset voltage
on pin VDD; operating mode;
fSCL = 1 MHz
on pin VDD; no load; fSCL = 0 Hz;
MODE1[4] = 1; VI = VDD
no load; VI = VDD or VSS
no load; VI = VDD or VSS
[2][3]
Input SCL; input/output SDA
VIL
LOW-level input voltage
0.5
VIH
HIGH-level input voltage
0.7VDD -
5.5
V
IOL
LOW-level output current
VOL = 0.4 V; VDD = 3 V
20
-
-
mA
VOL = 0.4 V; VDD = 5 V
30
-
-
mA
IL
leakage current
VI = VDD or VSS
1
-
+1
A
Ci
input capacitance
VI = VSS
-
6
10
pF
Current controlled outputs (LED[23:0])
IO(LEDn)
output current on pin LEDn
VO = 0.8 V; IREFx = 80h; Rext = 1 k
25
-
30
mA
[3]
50
-
60
mA
between bits (different ICs, same
channel)
[4]
-
-
6
%
between bits (2 channels, same IC)
[5]
VO = 0.8 V; IREFx = FFh; Rext = 1 k
IO
output current variation
VDD = 3.0 V; Tamb = 25 C; VO = 0.8 V;
IREFx = 80h; Rext = 1 k; guaranteed
by design
-
-
4
%
Vreg(drv)
driver regulation voltage
minimum regulation voltage;
IREFx = FFh; Rext = 1 k
0.8
1
20
V
IL(off)
off-state leakage current
VO = 20 V
-
-
1
A
Vtrip
trip voltage
short LED protection; Error flag will trip
during verification test if VO  Vtrip;
Rext = 1 k
2.7
2.85
-
V
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Table 26. Static characteristics …continued
VDD = 3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
-
+0.3VDD V
Unit
OE input, RESET input
VIL
LOW-level input voltage
0.5
VIH
HIGH-level input voltage
0.7VDD -
5.5
V
ILI
input leakage current
1
-
+1
A
-
3.7
5
pF
[3]
input capacitance
Ci
Address inputs AD2, AD1, AD0
VI
input voltage
ILI
input leakage current
0.5
-
5.5
V
1
-
+1
A
[3]
-
3.7
5
pF
rising
[3]
130
-
150
C
hysteresis
[3]
15
-
30
C
voltage on an input pin
input capacitance
Ci
Overtemperature protection
Tth(otp)
[1]
overtemperature protection
threshold temperature
Typical limits at VDD = 3.3 V, Tamb = 25 C.
[2]
VDD must be lowered to 1 V in order to reset part.
[3]
Value not tested in production, but guaranteed by design and characterization.
[4]
Part-to-part mismatch is calculated:
I O  LED0  + I O  LED1  +  + I O  LED22  + I O  LED23 
  --------------------------------------------------------------------------------------------------------------------------- – ideal output current 


24
% =  ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------  100
ideal
output
current




where ‘ideal output current’ = 28.68 mA (Rext = 1 k, IREFx = 80h).
[5]
Channel-to-channel mismatch is calculated:




I O  LEDn   where n = 0 to 23 
– 1  100
% =  --------------------------------------------------------------------------------------------------------------------------------  I O  LED0  + I O  LED1  +  + I O  LED22  + I O  LED23 

  --------------------------------------------------------------------------------------------------------------------------

24
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14. Dynamic characteristics
Table 27.
Symbol
Dynamic characteristics
Parameter
Conditions
Standard-mode
I2C-bus
Min
Max
Fast-mode
I2C-bus
Fast-mode
Plus I2C-bus
Min
Max
Min
Max
Unit
fSCL
SCL clock frequency
0
100
0
400
0
1000
tBUF
bus free time between a
STOP and START condition
4.7
-
1.3
-
0.5
-
kHz
s
tHD;STA
hold time (repeated) START
condition
4.0
-
0.6
-
0.26
-
s
tSU;STA
set-up time for a repeated
START condition
4.7
-
0.6
-
0.26
-
s
tSU;STO
set-up time for STOP
condition
4.0
-
0.6
-
0.26
-
s
tHD;DAT
data hold time
0
-
0
-
0
-
ns
data valid acknowledge time
[1]
0.3
3.45
0.1
0.9
0.05
0.45
s
tVD;DAT
data valid time
[2]
0.3
3.45
0.1
0.9
0.05
0.45
s
tSU;DAT
data set-up time
250
-
100
-
50
-
ns
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
0.5
-
s
tHIGH
HIGH period of the SCL clock
4.0
-
0.6
tVD;ACK
tf
fall time of both SDA and
SCL signals
tr
rise time of both SDA and
SCL signals
tSP
pulse width of spikes that
must be suppressed by the
input filter
tw(rst)
reset pulse width
[1]
[3][4]
[6]
-
0.26
-
s
[5]
300
-
120
ns
-
300
20 + 0.1Cb
-
1000
20 + 0.1Cb[5]
300
-
120
ns
-
50
-
50
-
50
ns
2.5
-
2.5
-
2.5
-
s
tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2]
tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3]
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
[4]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (tf) for the SDA output stage is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified tf.
[5]
Cb = total capacitance of one bus line in pF.
[6]
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
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0.7 × VDD
SDA
0.3 × VDD
tr
tBUF
tf
tHD;STA
tSP
tLOW
0.7 × VDD
SCL
0.3 × VDD
tHD;STA
P
tSU;STA
tHD;DAT
S
tHIGH
tSU;DAT
tSU;STO
Sr
P
002aaa986
Fig 21. Definition of timing
protocol
START
condition
(S)
bit 7
MSB
(A7)
tSU;STA
tLOW
bit 6
(A6)
tHIGH
bit 1
(D1)
bit 0
(D0)
STOP
condition
(P)
acknowledge
(A)
1 / fSCL
0.7 × VDD
SCL
0.3 × VDD
tBUF
tf
tr
0.7 × VDD
SDA
0.3 × VDD
tSU;DAT
tHD;STA
tVD;ACK
tVD;DAT
tHD;DAT
tSU;STO
002aab285
Rise and fall times refer to VIL and VIH.
Fig 22. I2C-bus timing diagram
15. Test information
VDD
PULSE
GENERATOR
VI
VO
RL
100 Ω
VDD or VLED
open
VSS
DUT
RT
CL
50 pF
002aag359
RL = Load resistor for LEDn.
CL = Load capacitance includes jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generators.
Fig 23. Test circuitry for switching times
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16. Package outline
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Fig 24. Package outline SOT1331-1 (HTSSOP38)
PCA9956B
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
17. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
18. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
18.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
18.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
18.3 Wave soldering
Key characteristics in wave soldering are:
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
18.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 25) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 28 and 29
Table 28.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 29.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 25.
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 25. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
19. Soldering: PCB footprints
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627
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Fig 26. PCB footprint for SOT1331-1 (HTSSOP38); reflow soldering
PCA9956B
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24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
20. Abbreviations
Table 30.
Abbreviations
Acronym
Description
ACK
Acknowledge
CDM
Charged-Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
FET
Field-Effect Transistor
HBM
Human Body Model
I2C-bus
Inter-Integrated Circuit bus
LED
Light Emitting Diode
LSB
Least Significant Bit
MSB
Most Significant Bit
NMOS
Negative-channel Metal-Oxide Semiconductor
PCB
Printed-Circuit Board
PMOS
Positive-channel Metal-Oxide Semiconductor
PWM
Pulse Width Modulation
RGB
Red/Green/Blue
RGBA
Red/Green/Blue/Amber
SMBus
System Management Bus
21. Revision history
Table 31.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9956B v.1.1
20151215
Product data sheet
-
PCA9956B v.1
Modifications:
PCA9956B v.1
PCA9956B
Product data sheet
•
•
•
Figure 1: Removed 200 k resistor
Table 3: Updated description for pin 35
Figure 20: Changed value for RESET resistor from 1.1 k to 10 k; added note [3].
20150831
Product data sheet
-
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-
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22. Legal information
22.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
22.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
22.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA9956B
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
22.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
23. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
52 of 53
PCA9956B
NXP Semiconductors
24-channel Fm+ I2C-bus 57 mA/20 V constant current LED driver
24. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.2
7.3
7.3.1
7.3.2
7.3.3
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 7
Device addresses . . . . . . . . . . . . . . . . . . . . . . . 7
Regular I2C-bus slave address. . . . . . . . . . . . . 7
LED All Call I2C-bus address . . . . . . . . . . . . . 11
LED Sub Call I2C-bus addresses . . . . . . . . . . 11
Control register . . . . . . . . . . . . . . . . . . . . . . . . 12
Register definitions . . . . . . . . . . . . . . . . . . . . . 13
MODE1 — Mode register 1 . . . . . . . . . . . . . . 16
MODE2 — Mode register 2 . . . . . . . . . . . . . . 16
LEDOUT0 to LEDOUT5, LED driver output
state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.3.4
GRPPWM, group duty cycle control . . . . . . . . 18
7.3.5
GRPFREQ, group frequency . . . . . . . . . . . . . 18
7.3.6
PWM0 to PWM23, individual brightness
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.3.7
IREF0 to IREF23, LED output current value
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.3.8
OFFSET — LEDn output delay offset register 20
7.3.9
LED Sub Call I2C-bus addresses for
PCA9956B . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.3.10
ALLCALLADR, LED All Call I2C-bus address. 22
7.3.11
PWMALL — brightness control for all LEDn
outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3.12
IREFALL register: output current value for
all LED outputs . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3.13
LED driver constant current outputs . . . . . . . . 23
7.3.13.1 Adjusting output current . . . . . . . . . . . . . . . . . 23
7.3.14
LED error detection . . . . . . . . . . . . . . . . . . . . 25
7.3.14.1 Open-circuit detection principle . . . . . . . . . . . 26
7.3.14.2 Short-circuit detection principle. . . . . . . . . . . . 27
7.3.15
Overtemperature protection . . . . . . . . . . . . . . 27
7.4
Active LOW output enable input . . . . . . . . . . . 28
7.5
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 28
7.6
Hardware reset recovery . . . . . . . . . . . . . . . . 28
7.7
Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 29
7.8
Individual brightness control with group
dimming/blinking . . . . . . . . . . . . . . . . . . . . . . . 30
8
8.1
8.1.1
8.2
8.3
9
10
10.1
11
12
13
14
15
16
17
18
18.1
18.2
18.3
18.4
19
20
21
22
22.1
22.2
22.3
22.4
23
24
Characteristics of the I2C-bus . . . . . . . . . . . .
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . .
START and STOP conditions. . . . . . . . . . . . .
System configuration . . . . . . . . . . . . . . . . . . .
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . .
Bus transactions . . . . . . . . . . . . . . . . . . . . . . .
Application design-in information. . . . . . . . .
Thermal considerations . . . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Thermal characteristics . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics. . . . . . . . . . . . . . . . .
Test information . . . . . . . . . . . . . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Handling information . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Soldering: PCB footprints . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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31
31
32
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37
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40
41
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Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 15 December 2015
Document identifier: PCA9956B
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