Application Notes

AN11404
Pin FMEA for NX5P/NX18P3001 bidirectional high-side power
switches for chargers and USB-OTG combined applications
Rev. 1 — 23 January 2014
Application note
Document information
Info
Content
Keywords
FMEA
Abstract
This application note provides a Failure Modes and Effects Analysis
(FMEA) for the device pins of NXP Semiconductors bidirectional high-side
power switches
AN11404
NXP Semiconductors
Pin FMEA for NX5P/NX18P3001 switches
Revision history
Rev
Date
Description
v.1
20140123
initial version
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
AN11404
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 23 January 2014
© NXP B.V. 2014. All rights reserved.
2 of 8
AN11404
NXP Semiconductors
Pin FMEA for NX5P/NX18P3001 switches
1. Introduction
The NX5P/NX18P3001 is an advanced bidirectional power switch and ESD-protection
device for combined USB-OTG and charger port applications. It includes under voltage
lockout, over voltage lockout and over temperature protection circuits designed to
automatically isolate the power switch terminals when a fault condition occurs.
The device features two power switch input/output terminals (VBUSI and VBUSO), an
open-drain acknowledge output (ACK), an enable input which includes logic level
translation (EN) and low capacitance transient voltage suppression (TVS) type ESD
clamps for USB data and ID pins.
When EN is set HIGH the device enters a low-power mode, disabling all protection
circuits. When used in combined charger and USB-OTG applications, the 30 V tolerant
VBUSI switch terminal is used as the supply and switch input when charging. For
USB-OTG the VBUSO switch terminal is used as the supply and switch input.
Designed for operation from 3.2 V to 6.35 V (17.5 V for NX18P3001), it is used in battery
charging and power domain isolation applications to reduce power dissipation and extend
battery life.
2. Pin FMEA
This chapter provides an FMEA (Failure Mode and Effect Analysis) for typical failure
situations, when the pins of bidirectional high-side power switch for charger and
USB-OTG combined applications family are short circuited to supply IO, GND or neighbor
pins or simply left open.
The individual failures are classified, according to their corresponding effects on a device
and the functionality; see Table 1.
Table 1.
Classification of failure effects
Class
Failure effect
A
damage to this device
functionality of application affected
B
no damage to this device
C
no damage to this device
functionality of application may be affected
functionality of application not affected
Table 2.
AN11404
Application note
FMEA matrix for pin short-circuit to supply IO
Pin
Class
Remarks
Input
A
When Supply IO is higher than 6.35 V, it causes device damage.
B
When Supply IO is lower than 6.35 V, no damage to this device.
Functionality is affected.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 23 January 2014
© NXP B.V. 2014. All rights reserved.
3 of 8
AN11404
NXP Semiconductors
Pin FMEA for NX5P/NX18P3001 switches
Table 2.
Pin
Class
Remarks
Output
C
If output defined HIGH and supply IO is lower than 6.35 V, the device
has no damage, no leakages.
A
If output defined HIGH and supply IO is higher than 6.35 V, it causes
device damage.
A
If output defined LOW, short circuited and high currents can damage
device. Output level changed.
B
No damage to this device if supply IO is lower than 6.35 V, increased
leakages. Functionality of application is affected. Functionality of the
device is not affected.
A
If supply IO is higher than 6.35 V, it causes device damage.
Functionality of application is affected.
A
Short circuited and high currents can damage device. Functionality is
affected.
ESD IO
GND
Table 3.
Class
Remarks
Input
B
No damage to this device, no leakages, functionality may be affected
Output
C
If output defined LOW, no damage, no leakages, same output level
A
If output defined HIGH, short circuited and high currents can damage
device. Output level changed.
ESD IO
B
No damage to this device. Functionality of application is affected.
Functionality of the device is not affected.
Supply IO
-
see Table 2
FMEA matrix for pin left open
Pin
Class
Remarks
Input
B
undefined operating condition, no damage, increased leakage,
functionality may be affected
Output
C
normal operating condition, no damage, no leakages.
GND
B
undefined operating condition, no damage, increased leakages.
functionality is affected.
ESD IO
C
normal operating condition, increased leakages. Functionality of
application not affected
Supply IO
B
If all supply IO’s are left open, undefined operating conditions, no
damage, increased leakages. functionality is affected
A
If part of supply IO’s are left open and part of supply IO is connected to
source, it causes device damage in case of large continuous current.
Table 5.
Application note
FMEA matrix for pin short-circuit to GND
Pin
Table 4.
AN11404
FMEA matrix for pin short-circuit to supply IO …continued
FMEA matrix for pin short-circuits between neighbor pins
Pin
Class
Remarks
Input to ESD IO
B
no damage to this device, increased leakages. functionality
may be affected.
Input to supply IO
-
see Table 2
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 23 January 2014
© NXP B.V. 2014. All rights reserved.
4 of 8
AN11404
NXP Semiconductors
Pin FMEA for NX5P/NX18P3001 switches
Table 5.
AN11404
Application note
FMEA matrix for pin short-circuits between neighbor pins …continued
Pin
Class
Remarks
Input to output
A
Different input and output voltage levels, causes circuit
high-currents and device damage. functionality is affected.
C
When input has same voltage level as output, no damage, no
leakages.
Output to ESD IO
B
no damage to this device, increased leakages. functionality
may be affected
Output to input
-
see “Input to output”
Output to GND
-
see Table 3
Output to supply IO -
see Table 2
GND to supply IO
-
see Table 2
GND to ESD IO
-
see Table 3
Supply input to
supply output
B
no damage to this device. functionality is affected.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 23 January 2014
© NXP B.V. 2014. All rights reserved.
5 of 8
AN11404
NXP Semiconductors
Pin FMEA for NX5P/NX18P3001 switches
2.1 Pin name mapping
Supply IO: VBUSI, VBUSO
ESD IO: D+, D, ID
Input: EN
Output: ACK
3. Abbreviations
Table 6.
AN11404
Application note
Abbreviations
Acronym
Description
FMEA
Failure Mode and Effect Analysis
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 23 January 2014
© NXP B.V. 2014. All rights reserved.
6 of 8
AN11404
NXP Semiconductors
Pin FMEA for NX5P/NX18P3001 switches
4. Legal information
4.1
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
4.2
Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
AN11404
Application note
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Evaluation products — This product is provided on an “as is” and “with all
faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates
and their suppliers expressly disclaim all warranties, whether express, implied
or statutory, including but not limited to the implied warranties of
non-infringement, merchantability and fitness for a particular purpose. The
entire risk as to the quality, or arising out of the use or performance, of this
product remains with customer.
In no event shall NXP Semiconductors, its affiliates or their suppliers be liable
to customer for any special, indirect, consequential, punitive or incidental
damages (including without limitation damages for loss of business, business
interruption, loss of use, loss of data or information, and the like) arising out
the use of or inability to use the product, whether or not based on tort
(including negligence), strict liability, breach of contract, breach of warranty or
any other theory, even if advised of the possibility of such damages.
Notwithstanding any damages that customer might incur for any reason
whatsoever (including without limitation, all damages referenced above and
all direct or general damages), the entire liability of NXP Semiconductors, its
affiliates and their suppliers and customer’s exclusive remedy for all of the
foregoing shall be limited to actual damages incurred by customer based on
reasonable reliance up to the greater of the amount actually paid by customer
for the product or five dollars (US$5.00). The foregoing limitations, exclusions
and disclaimers shall apply to the maximum extent permitted by applicable
law, even if any remedy fails of its essential purpose.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
4.3
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 23 January 2014
© NXP B.V. 2014. All rights reserved.
7 of 8
AN11404
NXP Semiconductors
Pin FMEA for NX5P/NX18P3001 switches
5. Contents
1
2
2.1
3
4
4.1
4.2
4.3
5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin FMEA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin name mapping . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . .
Legal information. . . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
6
6
7
7
7
7
8
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 23 January 2014
Document identifier: AN11404
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