Data Sheet

CBTL04082A; CBTL04082B
3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer
switch for PCI Express Gen2
Rev. 1 — 28 February 2011
Product data sheet
1. General description
CBTL04082A/B is an 8-to-4 bidirectional differential channel multiplexer/demultiplexer
switch for PCI Express Generation 2 (Gen2) applications. The CBTL04082A/B can switch
four differential signals to one of two locations. Using a unique design technique, NXP has
minimized the impedance of the switch such that the attenuation observed through the
switch is negligible, and also minimized the channel-to-channel skew as well as
channel-to-channel crosstalk, as required by the high-speed serial interface.
CBTL04082A/B allows expansion of existing high speed ports for extremely low power.
The devices’ pinouts are optimized to match different application layouts. CBTL04082A
has input and output pins on the opposite of the package, and is suitable for edge
connector(s) with different signal sources on the motherboard. CBTL04082B has outputs
on both sides of the package, and the device can be placed between two connectors to
multiplex differential signals from a controller. Please refer to Section 8 for layout
examples.
2. Features and benefits
„
„
„
„
„
„
„
„
„
„
„
„
„
4 bidirectional differential channel, 2 : 1 multiplexer/demultiplexer
High-speed signal switching for PCIe Gen2 5 Gbit/s
High bandwidth: 6 GHz at −3 dB
Insertion loss:
‹ −0.5 dB at 100 MHz
‹ −1.2 dB at 2.5 GHz
Low intra-pair skew: 5 ps typical
Low inter-pair skew: 35 ps maximum
Low crosstalk: −30 dB at 2.5 GHz
Low off-state isolation: −25 dB at 2.5 GHz
Low return loss: −20 dB at 2.5 GHz
VDD operating range: 3.3 V ± 10 %
Dual shutdown pins for channel 0/1 and 2/3 independently to minimize power
consumption
‹ Standby current less than 1 μA
ESD tolerance:
‹ 8 kV HBM
‹ 1 kV CDM
HVQFN42 package
CBTL04082A; CBTL04082B
NXP Semiconductors
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
3. Applications
„ Routing of high-speed differential signals with low signal attenuation
‹ PCIe Gen2
‹ DisplayPort 1.2
‹ USB 3.0
‹ SATA 6 Gbit/s
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
CBTL04082ABS
HVQFN42
plastic thermal enhanced very thin quad flat package; no leads;
42 terminals; body 3.5 × 9 × 0.85 mm[1]
SOT1144-1
CBTL04082BBS
HVQFN42
plastic thermal enhanced very thin quad flat package; no leads;
42 terminals; body 3.5 × 9 × 0.85 mm[1]
SOT1144-1
[1]
Total height after printed-circuit board mounting = 1.0 mm (maximum).
5. Functional diagram
A0_P
B0_P
A0_N
B0_N
A1_P
B1_P
A1_N
B1_N
C0_P
C0_N
XSD01
C1_P
C1_N
A2_P
B2_P
A2_N
B2_N
A3_P
B3_P
A3_N
B3_N
C2_P
C2_N
XSD23
C3_P
C3_N
SEL
002aaf752
Fig 1.
CBTL04082A_CBTL04082B
Product data sheet
Functional diagram of CBTL04082A; CBTL04082B
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 28 February 2011
© NXP B.V. 2011. All rights reserved.
2 of 18
CBTL04082A; CBTL04082B
NXP Semiconductors
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
6. Pinning information
6.1 Pinning
39 n.c.
40 XSD01
GND
1
38 B0_P
A0_P
1
38 GND
A0_P
2
37 B0_N
A0_N
2
37 B0_P
A0_N
3
36 B1_P
C0_P
3
36 B0_N
GND
4
35 B1_N
C0_N
4
35 GND
VDD
5
34 C0_P
A1_P
5
34 VDD
A1_P
6
33 C0_N
A1_N
6
33 B1_P
A1_N
7
32 C1_P
C1_P
7
32 B1_N
n.c.
8
31 C1_N
C1_N
8
31 VDD
SEL
9
30 VDD
VDD
9
30 SEL
GND 10
29 B2_P
A2_P 10
29 GND
A2_P 11
28 B2_N
A2_N 11
28 B2_P
A2_N 12
27 B3_P
C2_P 12
27 B2_N
VDD 13
26 B3_N
C2_N 13
26 VDD
GND 14
25 C2_P
A3_P 14
24 C2_N
A3_N 15
23 C3_P
C3_P 16
22 C3_N
C3_N 17
Transparent top view
23 B3_N
VDD 21
002aaf754
24 B3_P
22 GND
XSD23 20
VDD 20
GND 21
n.c. 18
XSD23 19
GND 17
VDD 19
A3_N 16
25 GND
GND
(exposed
thermal pad)
GND 18
GND
(exposed
thermal pad)
A3_P 15
002aaf710
Transparent top view
a. CBTL04082A
Fig 2.
41 VDD
42 GND
CBTL04082BBS
39 GND
40 VDD
41 XSD01
42 VDD
CBTL04082ABS
b. CBTL04082B
Pin configuration for HVQFN42
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
CBTL04082A
CBTL04082B
A0_P
2
A0_N
A1_P
Type
Description
1
I/O
channel 0, port A differential signal input/output
3
2
I/O
6
5
I/O
A1_N
7
6
I/O
A2_P
11
10
I/O
A2_N
12
11
I/O
A3_P
15
14
I/O
A3_N
16
15
I/O
CBTL04082A_CBTL04082B
Product data sheet
channel 1, port A differential signal input/output
channel 2, port A differential signal input/output
channel 3, port A differential signal input/output
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 28 February 2011
© NXP B.V. 2011. All rights reserved.
3 of 18
CBTL04082A; CBTL04082B
NXP Semiconductors
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
Table 2.
Pin description …continued
Symbol
Pin
Type
Description
37
I/O
channel 0, port B differential signal input/output
37
36
I/O
B1_P
36
33
I/O
B1_N
35
32
I/O
B2_P
29
28
I/O
B2_N
28
27
I/O
B3_P
27
24
I/O
B3_N
26
23
I/O
C0_P
34
3
I/O
C0_N
33
4
I/O
C1_P
32
7
I/O
C1_N
31
8
I/O
C2_P
25
12
I/O
C2_N
24
13
I/O
C3_P
23
16
I/O
C3_N
22
17
I/O
SEL
9
30
CMOS
single-ended
input
operation mode select
CBTL04082A
CBTL04082B
B0_P
38
B0_N
channel 1, port B differential signal input/output
channel 2, port B differential signal input/output
channel 3, port B differential signal input/output
channel 0, port C differential signal input/output
channel 1, port C differential signal input/output
channel 2, port C differential signal input/output
channel 3, port C differential signal input/output
SEL = LOW: A ↔ B
SEL = HIGH: A ↔ C
XSD01
41
40
CMOS
single-ended
input
Shutdown pin; should be driven LOW or connected to GND for
normal operation. When HIGH, channel 0 and channel 1 are
switched off (non-conducting high-impedance state), and
supply current consumption is minimized.
XSD23
19
20
CMOS
single-ended
input
Shutdown pin; should be driven LOW or connected to GND for
normal operation. When HIGH, channel 2 and channel 3 are
switched off (non-conducting high-impedance state), and
supply current consumption is minimized.
VDD
5, 13, 20, 30,
40, 42
9, 19, 21, 26,
31, 34, 41
power
positive supply voltage, 3.3 V (±10 %)
GND[1]
1, 4, 10, 14,
17, 21, 39,
center pad
18, 22, 25, 29, power
35, 38, 42,
center pad
supply ground
n.c.
8, 18
39
not connected; these pins can be connected to any signal
externally
[1]
-
HVQFN42 package die supply ground is connected to both GND pins and exposed center pad. GND pins and the exposed center pad
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the
exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through
the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region.
CBTL04082A_CBTL04082B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 28 February 2011
© NXP B.V. 2011. All rights reserved.
4 of 18
CBTL04082A; CBTL04082B
NXP Semiconductors
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
7. Functional description
Refer to Figure 1 “Functional diagram of CBTL04082A; CBTL04082B”.
7.1 Function selection
Table 3.
Function selection
X = Don’t care.
XSD01
XSD23
SEL
Function
HIGH
-
X
An, Bn and Cn pins are high-Z, n = 0, 1
LOW
-
LOW
An to Bn or vice versa, n = 0, 1
LOW
-
HIGH
An to Cn or vice versa, n = 0, 1
-
HIGH
X
An, Bn and Cn pins are high-Z, n = 2, 3
-
LOW
LOW
An to Bn or vice versa, n = 2, 3
-
LOW
HIGH
An to Cn or vice versa, n = 2, 3
7.2 Shutdown function
The CBTL04082A/B provides a shutdown function to minimize power consumption when
the application is not active, but power to the CBTL04082A/B is provided. Pin XSD01 and
XSD23 (active HIGH) places channel 0/1 and 2/3 (respectively) in high-impedance state
(non-conducting) while reducing current consumption to near-zero.
Table 4.
CBTL04082A_CBTL04082B
Product data sheet
Shutdown function
XSD01
XSD23
Channel 0
Channel 1
Channel 2
Channel 3
HIGH
-
high-Z
high-Z
-
-
LOW
-
active
active
-
-
-
HIGH
-
-
high-Z
high-Z
-
LOW
-
-
active
active
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 28 February 2011
© NXP B.V. 2011. All rights reserved.
5 of 18
CBTL04082A; CBTL04082B
NXP Semiconductors
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
8. Application design-in information
PCIe SLOT
PCI EXPRESS
CONTROLLER
PCIe SLOT
CBTL04082A
CBTL04082B
002aaf773
Fig 3.
CBTL04082A_CBTL04082B
Product data sheet
A/B pinout difference (layout)
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 28 February 2011
© NXP B.V. 2011. All rights reserved.
6 of 18
CBTL04082A; CBTL04082B
NXP Semiconductors
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VDD
supply voltage
Tcase
case temperature
VESD
electrostatic discharge voltage
Min
Max
Unit
−0.3
+4.6
V
−40
+85
°C
HBM
[1]
-
8000
V
CDM
[2]
-
1000
V
[1]
Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA.
[2]
Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device
Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
10. Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol
Parameter
VDD
supply voltage
VI
input voltage
Tamb
ambient temperature
Conditions
operating in free air
Min
Typ
Max
Unit
3.0
3.3
3.6
V
-
-
VDD
V
−40
-
+85
°C
11. Static characteristics
Table 7.
Static characteristics
VDD = 3.3 V ± 10 %; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
IDD
supply current
VDD = max.; VI = GND or VDD;
XSD01 = XSD23 = LOW
-
2.7
5
mA
Istb
standby current
VDD = max.; VI = GND or VDD;
XSD01 = XSD23 = HIGH
-
-
1
μA
IIH
HIGH-level input current
VDD = max.; VI = VDD
-
-
±5[2]
μA
IIL
LOW-level input current
VDD = max.; VI = GND
-
-
±5[2]
μA
VIH
HIGH-level input voltage
SEL, XSD01, XSD23 pins
0.65VDD
-
-
V
VIL
LOW-level input voltage
SEL, XSD01, XSD23 pins
-
-
0.35VDD
V
VI
input voltage
differential pins
-
-
2.4
V
SEL, XSD01, XSD23 pins
-
-
VDD
V
0
-
2.0
V
VIC
common-mode input
voltage
VID
differential input voltage
peak-to-peak
-
-
1.6
V
Ron
ON-state resistance
VDD = 3.3 V; VI = 2 V; II = 19 mA
-
6
-
Ω
[1]
Typical values are at VDD = 3.3 V, Tamb = 25 °C, and maximum loading.
[2]
Input leakage current is ±50 μA if differential pairs are pulled to HIGH and LOW.
CBTL04082A_CBTL04082B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 28 February 2011
© NXP B.V. 2011. All rights reserved.
7 of 18
CBTL04082A; CBTL04082B
NXP Semiconductors
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
12. Dynamic characteristics
Table 8.
Dynamic characteristics
VDD = 3.3 V ± 10 %; Tamb = −40 °C to +85 °C; unless otherwise specified.
Min
Typ[1]
Max
Unit
f = 100 MHz
-
−50
-
dB
f = 2.5 GHz
-
−25
-
dB
f = 100 MHz
-
−0.5
-
dB
f = 2.5 GHz
-
−1.2
-
dB
f = 100 MHz
-
−50
-
dB
f = 2.5 GHz
-
−30
-
dB
Symbol
Parameter
Conditions
DDIL
differential insertion loss
channel is OFF
channel is ON
DDNEXT differential near-end crosstalk
B−3dB
−3 dB bandwidth
DDRL
differential return loss
adjacent channels are ON
propagation delay
tPD
-
6.0
-
GHz
f = 100 MHz
-
−25
-
dB
f = 2.5 GHz
-
−20
-
dB
from Port A to Port B, or
Port A to Port C, or vice versa
-
80
-
ps
supply voltage valid or
XSD01/XSD23 going LOW to
channel specified operating
characteristics
-
-
10
ms
Switching characteristics
tstartup
start-up time
tPZH
OFF-state to HIGH propagation delay
-
-
300
ns
tPZL
OFF-state to LOW propagation delay
-
-
70
ns
tPHZ
HIGH to OFF-state propagation delay
-
-
50
ns
tPLZ
LOW to OFF-state propagation delay
-
-
50
ns
tsk(dif)
differential skew time
intra-pair
-
5
-
ps
tsk
skew time
inter-pair
-
-
35
ps
[1]
Typical values are at VDD = 3.3 V; Tamb = 25 °C, and maximum loading.
CBTL04082A_CBTL04082B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 28 February 2011
© NXP B.V. 2011. All rights reserved.
8 of 18
CBTL04082A; CBTL04082B
NXP Semiconductors
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
VDD
SEL
0.5VDD
0.5VDD
0V
tPZL
tPLZ
0.85VOH
output 1
0.25VOH
tPZH
output 2
VOH
VOL
tPHZ
VOH
0.85VOH
0.25VOH
VOL
002aag013
Output 1 is for an output with internal conditions such that the output is LOW except when disabled
by the output control.
Output 2 is for an output with internal conditions such that the output is HIGH except when disabled
by the output control.
The outputs are measured one at a time with one transition per measurement.
Fig 4.
CBTL04082A_CBTL04082B
Product data sheet
Voltage waveforms for enable and disable times
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 28 February 2011
© NXP B.V. 2011. All rights reserved.
9 of 18
CBTL04082A; CBTL04082B
NXP Semiconductors
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
13. Test information
VDD
VIC
PULSE
GENERATOR
RL
200 Ω
VO
2 × VIC
open
GND
DUT
CL
50 pF
RT
RL
200 Ω
002aag014
CL = load capacitance; includes jig and probe capacitance.
RT = termination resistance; should be equal to Zo of the pulse generator.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 5 MHz;
Zo = 50 Ω; tr ≤ 2.5 ns; tf ≤ 2.5 ns.
Fig 5.
Test circuitry for switching times
4-PORT, 20 GHz
NETWORK ANALYZER
PORT 2
PORT 3
PORT 1
PORT 4
DUT
002aae655
Fig 6.
Test circuit
Table 9.
Test data
Test
CBTL04082A_CBTL04082B
Product data sheet
Load
Switch
CL
RL
tPLZ, tPZL (output on B side)
50 pF
200 Ω
2 × VIC
tPHZ, tPZH (output on B side)
50 pF
200 Ω
GND
tPD
-
200 Ω
open
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 28 February 2011
© NXP B.V. 2011. All rights reserved.
10 of 18
CBTL04082A; CBTL04082B
NXP Semiconductors
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
14. Package outline
HVQFN42: plastic thermal enhanced very thin quad flat package; no leads;
42 terminals; body 3.5 x 9 x 0.85 mm
A
B
D
SOT1144-1
terminal 1
index area
A
E
A1
c
detail X
e1
1/2 e
e
L
18
21
C
C A B
C
v
w
b
y1 C
y
22
17
e
e2
Eh
38
1
terminal 1
index area
42
39
X
Dh
0
2.5
scale
Dimensions
Unit(1)
mm
5 mm
A
A1
b
max 1.00 0.05 0.30
nom 0.85 0.02 0.25
min 0.80 0.00 0.20
c
D
Dh
E
Eh
0.2
3.6
3.5
3.4
2.30
2.05
1.90
9.1
9.0
8.9
7.70
7.55
7.40
e
e1
0.5
1.5
e2
L
v
8.0
0.5
0.4
0.3
0.1
w
y
0.05 0.05
y1
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Fig 7.
References
Outline
version
IEC
JEDEC
JEITA
SOT1144-1
---
---
---
sot1144-1_po
European
projection
Issue date
09-08-26
09-08-28
Package outline SOT1144-1 (HVQFN42)
CBTL04082A_CBTL04082B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 28 February 2011
© NXP B.V. 2011. All rights reserved.
11 of 18
CBTL04082A; CBTL04082B
NXP Semiconductors
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
15. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
CBTL04082A_CBTL04082B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 28 February 2011
© NXP B.V. 2011. All rights reserved.
12 of 18
CBTL04082A; CBTL04082B
NXP Semiconductors
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
15.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 8) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 10 and 11
Table 10.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 11.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 8.
CBTL04082A_CBTL04082B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 28 February 2011
© NXP B.V. 2011. All rights reserved.
13 of 18
CBTL04082A; CBTL04082B
NXP Semiconductors
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 8.
Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
16. Abbreviations
Table 12.
CBTL04082A_CBTL04082B
Product data sheet
Abbreviations
Acronym
Description
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
I/O
Input/Output
PCI
Peripheral Component Interconnect
PCIe
PCI express
PRR
Pulse Repetition Rate
SATA
Serial Advanced Technology Attachment
USB
Universal Serial Bus
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 28 February 2011
© NXP B.V. 2011. All rights reserved.
14 of 18
CBTL04082A; CBTL04082B
NXP Semiconductors
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
17. Revision history
Table 13.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
CBTL04082A_CBTL04082B v.1
20110228
Product data sheet
-
-
CBTL04082A_CBTL04082B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 28 February 2011
© NXP B.V. 2011. All rights reserved.
15 of 18
CBTL04082A; CBTL04082B
NXP Semiconductors
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
CBTL04082A_CBTL04082B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 28 February 2011
© NXP B.V. 2011. All rights reserved.
16 of 18
NXP Semiconductors
CBTL04082A; CBTL04082B
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
CBTL04082A_CBTL04082B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 28 February 2011
© NXP B.V. 2011. All rights reserved.
17 of 18
NXP Semiconductors
CBTL04082A; CBTL04082B
3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
20. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.2
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
18
18.1
18.2
18.3
18.4
19
20
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 5
Function selection. . . . . . . . . . . . . . . . . . . . . . . 5
Shutdown function . . . . . . . . . . . . . . . . . . . . . . 5
Application design-in information . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Test information . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Soldering of SMD packages . . . . . . . . . . . . . . 12
Introduction to soldering . . . . . . . . . . . . . . . . . 12
Wave and reflow soldering . . . . . . . . . . . . . . . 12
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 12
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 28 February 2011
Document identifier: CBTL04082A_CBTL04082B
Similar pages