Data Sheet

PCF8802
Smartcard RTC; ultra low power oscillator with integrated
counter for initiating one time password generation
Rev. 1 — 30 June 2014
Product data sheet
1. General description
The PCF8802 is a CMOS integrated circuit for battery operation, typically supplied by
button cells or flexible polymer batteries. Incorporated is a 32.768 kHz quartz crystal
oscillator circuit including the two load capacitors. The circuit is optimized for a quartz with
6 pF load capacitance specification. Higher values can also be used with the addition of
external load capacitors.
The main function of the oscillator is to generate a 1⁄32 Hz clock signal which is used to
increment a 24 bit binary counter. The counter can be read over the serial interface and
can also be set to any desired value. Control over the divider chain also allows for
accurate starting of the counter. Incrementing of the counter value during read is
prevented by freezing of the counter during access.
An interrupt signal is also available and is triggered coincident with the counter updating.
This signal can be used as a wake-up for a microcontroller.
2. Features and benefits
 32.768 kHz quartz oscillator, amplitude regulated with excellent frequency stability and
high immunity to leakage currents
 Two integrated quartz crystal oscillator capacitors
 Very low current consumption: typically 130 nA
 Two-wire serial interface (I2C-bus)
 Integrated 24-bit counter with auto increment every 32 seconds
 Interrupt output for processor wake-up
 Stop function for accurate time setting and current saving during shelf life
 User test modes for accelerated application testing and development
3. Applications
 One time password function generators
 Ultra low-power time keeper circuit
PCF8802
NXP Semiconductors
Smartcard RTC
4. Ordering information
Table 1.
Ordering information
Type number
Package
PCF8802AUG
Name
Description
Version
WLCSP8
wafer level chip-size package; 8 bumps PCF8802AUG
4.1 Ordering options
Table 2.
Ordering options
Product type number
Orderable part number Sales item
(12NC)
Delivery form
IC
revision
PCF8802AUG/AB[1]
PCF8802AUG/ABZ
gold bumps; chips in tape and reel
1
[1]
935304226027
Bump hardness see Table 16.
5. Marking
Table 3.
Marking codes
Product type number
Marking code
PCF8802AUG/AB
PC8802-1
backside (non-active side) laser marking
3LQ
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6. Block diagram
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Fig 1.
PCF8802
Product data sheet
Block diagram of PCF8802
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Rev. 1 — 30 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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PCF8802
NXP Semiconductors
Smartcard RTC
7. Pinning information
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7.1 Pinning
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Viewed from active side. For mechanical details, see Figure 26.
Fig 2.
Pinning diagram of PCF8802AUG
7.2 Pin description
Table 4.
Pin description for PCF8802
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.
PCF8802
Product data sheet
Symbol
Pin
Description
INT
1
interrupt and test mode output, push-pull
VDD
2
supply voltage
TEST
3
test pin; must be connected to VSS
OSCO
4
oscillator output
OSCI
5
oscillator input
VSS
6
ground
SCL
7
serial interface, clock
SDA
8
serial interface, bidirectional data line; push-pull
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Rev. 1 — 30 June 2014
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PCF8802
NXP Semiconductors
Smartcard RTC
8. Functional description
The PCF8802 is an ultra low-power device for battery operations. The integrated oscillator
circuit generates a 1⁄32 Hz clock signal to increment a 24-bit counter. The communication
between the PCF8802 and other devices is made via point to point I2C-bus protocol.
The device is always running but for longer storage time it can be put in deep sleep and
enabled again in case of delivery.
The functions of the device can be controlled with the following instruction set:
Table 5.
Instruction set overview
Instruction
Description
Reference
wrt_cmd
device write access
Section 8.6.2
dvs_cmd
divider start or stop switch
Section 8.6.3
pwd_cmd
deep sleep mode switch
Section 8.6.4
32k_cmd
32.768 kHz clock signal on the pin INT switch
Section 8.6.5
fst_cmd
fast system development mode switch
Section 8.6.6
set_cmd
set counter instruction
Section 8.6.7
rd_cmd
counter read instruction
Section 8.6.8
8.1 Oscillator
The 32.768 kHz oscillator includes two integrated load capacitors and an automatic gain
control to ensure a reliable start-up.
For prototype development and system debugging, it is possible to output a 32.768 kHz
square wave on the INT pin with the 32k_cmd instruction.
8.1.1 Low-power operation
When the oscillator is running, a prime consideration for low power consumption is the
series resistance Rs of the quartz used. The series resistance acts as a loss element. Low
Rs reduces current consumption further.
PCF8802
Product data sheet
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Rev. 1 — 30 June 2014
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PCF8802
NXP Semiconductors
Smartcard RTC
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Fig 3.
IDD with respect to Rs
8.1.2 Deep sleep mode
With the deep sleep mode instruction (pwd_cmd) the oscillator can be stopped and the
device can be put into a deep sleep where power consumption is reduced to an absolute
minimum. An example sequence can be found in Table 8. In deep sleep mode, the
interface is still accessible.
8.2 Divider
The divider chain is responsible for reducing the 32.768 kHz oscillator frequency down to
1⁄ Hz.
32
The dividers (see Figure 4) divider_2 and divider_3 can be reset with the dvs_cmd
instruction. The 24-bit counter can be set when the dividers are held in reset, but this is
not a requirement. This allows for accurate setting and restarting of the counter.
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Divider_1 = dividing by 4.
Divider_2 = dividing by 8192.
Divider_3 = dividing by 32.
Fig 4.
PCF8802
Product data sheet
Divider chain
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Rev. 1 — 30 June 2014
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PCF8802
NXP Semiconductors
Smartcard RTC
The interface is asynchronous to the quartz oscillator and the state of divider_1 cannot be
known when the dvs_cmd is enabled. The 8.192 kHz clock could have just occurred and
hence a delay of 1⁄8192 seconds will occur before the next increment of the divider_2, or
the 8.192 kHz clock could be just about to occur and immediately increment the divider_2.
As a consequence, an uncertainty of between zero and one 8192 Hz clock period (that is,
a time uncertainty of about 0 s to 122 s) will be present when restarting the counter.
8.3 Binary counter
A 24-bit binary roll-over counter is implemented. The counter is reset at power-on.
The counter can be set to any value using the set_cmd instruction. The set_cmd
instruction allows partial writing of data. Partial writing of the data parameters results in
partial setting of the counter. For example, if data transfer is stopped after P1[23:16] (see
Table 6) is transmitted, then only bit 23 to bit 16 will be updated. The counter will not
increment while being set.
The counter can be halted by stopping the dividers using the dvs_cmd instruction.
The counter can be read at any time and the counter value remains stable during reading.
If the counter is due to increment during the read or write cycle, then the request to
increment will be held off until after the read has concluded. For this reason, it is important
to read the counter in bursts, ensuring that an interface STOP condition (see
Section 8.5.4) is present between read accesses. Reading for periods of more than
32 seconds at a time results in loss of counts.
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(1) Increment delayed until after the read has finished.
Fig 5.
Counter behavior during read access
8.4 Pulse generator
An interrupt pulse is available at the INT pin. This pulse is generated once every
32 seconds. It could be used to wake up a microcontroller to perform a periodic function,
for example, to calculate and update an LCD display with a new one-time password. A
pulse is generated coincident with the increment of the counter. The new counter value is
immediately available.
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Fig 6.
PCF8802
Product data sheet
Pulse generator
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PCF8802
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Smartcard RTC
8.5 I2C-bus interface
For a more detailed information about the I2C-interface, see Ref. 10 “UM10204”
8.5.1 Interface protocol
The serial interface is a point-to-point I2C-bus protocol. The I2C-bus protocol has the
advantage of being robust in terms of immunity to electrical noise. Although the PCF8802
does not have the signal filters inside the interface pins, the slave address and
acknowledge hand shaking is nevertheless implemented.
For power saving, the SDA output is a push-pull instead of the more traditional open-drain
output. Push-pull prevents the need for power consuming pull-up resistors, but requires
that the SDA line of the microcontroller is a push-pull as well1 and does limit the operation
to point-to-point only.
The following slave addresses plus a write and read bit are reserved for the PCF8802:
• write: 1010 0000
• read: 1010 0001
An incorrect slave address results in the device ignoring all bus data. A STOP or START
condition (see Section 8.5.4) is required before a new transfer can be made.
8.5.1.1
The writing protocol
The writing protocol is shown in Figure 7.
There is no restriction for the order of sending instructions. As many instructions as
needed can be sent in one access. The total duration of one access must not exceed
32 seconds (see Figure 9).
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Wrt_cmd is slave address plus write bit.
Fig 7.
1.
Writing protocol
If the SDA line on the microcontroller is open drain a pull-up resistor is needed.
PCF8802
Product data sheet
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Rev. 1 — 30 June 2014
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PCF8802
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Smartcard RTC
8.5.1.2
The reading protocol
The reading protocol is shown in Figure 8.
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Rd_cmd is slave address plus read bit.
Fig 8.
Reading protocol
8.5.1.3
Reading and writing limitations
As the counter is frozen during interface accesses, all accesses must be completed within
32 seconds (see Figure 9). If this rule is not adhered to, then counts are dropped.
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Wrt_cmd is slave address plus write bit.
Rd_cmd is slave address plus read bit.
Fig 9.
Access restrictions
8.5.2 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as a control signal. Bit transfer is shown in Figure 10.
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Fig 10. Bit transfer
PCF8802
Product data sheet
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PCF8802
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Smartcard RTC
8.5.3 Bit order
Data is transferred MSB first.
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Fig 11. Bit transfer
8.5.4 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P). The START and STOP conditions are shown in Figure 12.
The data on SDA is sampled with the rising edge of SCL. Data is output to SDA on the
falling edge of SCL.
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Fig 12. Definition of START and STOP conditions
8.5.5 System configuration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master and the device which is
controlled by the master is the slave.
8.5.6 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. But the duration of the access must not exceed
32 seconds. Each byte of 8 bits is followed by an acknowledge bit. The acknowledge bit is
a HIGH level signal put on the bus by the transmitter during which time the master
generates an extra acknowledge related clock pulse. A slave receiver which is addressed
must generate an acknowledge after the reception of each byte. Also a master receiver
must generate an acknowledge after the reception of each byte that has been clocked out
of the slave transmitter. The device that acknowledges must pull-down the SDA line
during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse (set-up and hold times must be
considered). A master receiver must signal an end of data to the transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
event, the transmitter must leave the data line HIGH to enable the master to generate a
STOP condition. Acknowledgement is shown in Figure 13.
PCF8802
Product data sheet
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Rev. 1 — 30 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
9 of 32
PCF8802
NXP Semiconductors
Smartcard RTC
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Fig 13. Acknowledgement on the I2C-bus
8.5.7 Data transfer
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Fig 14. A complete data transfer
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Fig 15. A master-transmitter addresses a slave receiver
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Fig 16. A master reads from a slave immediately after the first byte
PCF8802
Product data sheet
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Rev. 1 — 30 June 2014
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NXP Semiconductors
Smartcard RTC
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(1) Not shaded because transfer direction of data and acknowledge bits depends on R/W bits.
Fig 17. Combined format
8.5.7.1
Example data transfers
Example 1: Sending the instruction dvs_cmd followed by fst_cmd is shown in Figure 18.
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Wrt_cmd is slave address plus write bit.
Fig 18. Sending instructions
Example 2: Sending dvs_cmd followed by setting the counter to A90001h is shown in
Figure 19
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Wrt_cmd is slave address plus write bit.
Fig 19. Setting the counter
Example 3: Reading the counter (counter = 000011h) is shown in Figure 20.
PCF8802
Product data sheet
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Rev. 1 — 30 June 2014
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PCF8802
NXP Semiconductors
Smartcard RTC
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Rd_cmd is slave address plus read bit.
Fig 20. Reading the counter
8.6 Instructions
8.6.1 Instruction set
Table 6.
Write instructions
The writing protocol is illustrated in Figure 7.
First byte
Second byte
Further bytes Action
Instruction Instruction code Instruction Instruction code Parameters
wrt_cmd
1010 0000
-
device slave write address: slave address
plus write bit
-
stop and reset dividers
dvs_cmd
0001 0001
0001 0000
-
start dividers
pwd_cmd
0010 0001
-
shut down the device
0010 0000
-
enable the device
32k_cmd
0011 0001
-
enable output of 32.768 kHz on pin INT
0011 0000
-
disable output of 32.768 kHz on pin INT
fst_cmd
0100 0001
-
fast mode; increments counter every
second
0100 0000
-
fast mode disable
set_cmd
1000 0000
set the counter value
P1[23:16]
parameter with counter values
P2[15:8]
P3[7:0]
PCF8802
Product data sheet
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Smartcard RTC
Table 7.
Read instructions
The reading protocol is illustrated in Figure 8.
First byte
Further bytes Action
Instruction Instruction code Parameters
rd_cmd[1]
1010 0001
device slave read address: slave address plus
read bit
P1[23:16]
P2[15:8]
P3[7:0]
parameter with counter values;
continues to read until no ACK is received;
counter is not updated during this time
P4[23:16]
:
[1]
Read of the counter is implicit with an interface read.
8.6.2 Instruction wrt_cmd
The write instruction (wrt_cmd) precedes each write sequence. Details of the writing
protocol can be found in Section 8.5.1.1.
8.6.3 Instruction dvs_cmd
The divider stop instruction (dvs_cmd) can be used to freeze the divider chain and to put it
in a defined state. The first 2 bits of the divider chain cannot be influenced. With this
instruction, it is possible to control the time to the next increment of the counter. See
Table 9.
When the dividers are restarted, the first increment of the 24-bit counter will be after 32
seconds.
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Divider_1 = dividing by 4.
Divider_2 = dividing by 8192.
Divider_3 = dividing by 32.
Fig 21. Instruction dvs_cmd
PCF8802
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When the dividers are restarted, the 8192 Hz clock could have just occurred and hence a
delay of 1⁄8192 seconds will occur before the next increment of the divider_2. Or the
8192 Hz clock could be just about to occur and immediately increment the divider_2. As a
consequence, an uncertainty of one half clock period in the starting of the 24 bit counter is
present when restarting (see Figure 21).
8.6.4 Instruction pwd_cmd
The power down instruction (pwd_cmd) is intended to be used to put the system into a
low-power mode for storage. Static leakage current will be the only power consumed.
Storage at temperatures exceeding room temperature can increase leakage currents.
Entering deep sleep mode requires a specific sequence of events since under normal
circumstances stopping the oscillator would result in a chip reset.
Table 8.
Deep sleep mode sequence
Step Action
Code sequence Note
To enter deep sleep mode
1
initiate transfer
START condition -
2
send wrt_cmd
1010 0000
-
3
enable dvs_cmd
0001 0001
stop the divider
4
set counter with set_cmd
1000 0000
set the counter = AAAAAAh
1010 1010
P1[23:16]
1010 1010
P2[15:8]
1010 1010
P3[7:0]
5
enable pwd_cmd
0010 0001
stop the oscillator
6
end transfer
STOP condition
-
7
device is now in deep sleep mode
-
To exit deep sleep mode
1
initiate transfer
START condition -
2
send wrt_cmd
1010 0000
-
3
disable pwd_cmd
0010 0000
oscillator starts on the ACK cycle of this
instruction
4
disable dvs_cmd
0001 0000
enable the divider again
5
end transfer
STOP condition
-
8.6.5 Instruction 32k_cmd
The 32.768 kHz enable instruction (32k_cmd) is intended to aid with oscillator
characterization during system development. With this instruction, it is possible to obtain a
32.768 kHz clock on the INT pin which can be used for measurement.
This mode does not affect other operation of the chip except for the loss of interrupt
output.
8.6.6 Instruction fst_cmd
The fast mode instruction (fst_cmd) is intended to enable faster system development.
When enabled, the counter increments once every second instead of once every 32
seconds. Interrupt pulses are generated once every second as well.
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Rev. 1 — 30 June 2014
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PCF8802
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Smartcard RTC
When using fst_cmd, data access to the device must be completed within 1 second, if not
then counter increments are lost. The 1 second period is measured from the ACK cycle of
a valid slave address to the next STOP or repeated START. A repeated START is
sufficient to allow the counter to increment.
8.6.7 Instruction set_cmd
The counter can be set to any value using the set instruction (set_cmd). Partial writing of
the data parameters results in partial setting of the counter. For example, if data transfer is
stopped after P1[23:16] is transmitted, then only bit 23 to bit 16 will be updated.
This instruction takes only 3 parameters in one command. Data after the third parameter
are interpreted as the next instruction.
Accurate setting and start-up can be implemented using the dvs_cmd instruction in
cooperation with the set_cmd instruction. An example is shown in Table 9.
Table 9.
Example of accurate setting of the counter
Step
Action
Code sequence Note
1
initiate transfer
START condition -
2
send wrt_cmd
1010 0000
-
3
enable dvs_cmd
0001 0001
-
4
set counter with set_cmd
1000 0000
set the counter = 1
0000 0000
P1[23:16]
0000 0000
P2[15:8]
0000 0001
P3[7:0]
5
end transfer
STOP condition
-
6
wait for an external time
marker
-
-
7
initiate transfer
START condition -
8
send wrt_cmd
1010 0000
-
9
disable dvs_cmd
0001 0000
counter starts on the ACK cycle of this
instruction
10
end transfer
STOP condition
-
8.6.8 Instruction rd_cmd
With the read instruction (rd_cmd) the counter value can be read at any time. When the
counter value is read, the counter is frozen so that there are no changes during the read
back. After a read is terminated, the counter will be allowed to increment again. Any
increment that was scheduled during the frozen period will then be effected.
Reading the counter is cyclic, that is, the device repeatedly returns the present counter
value until the read is terminated. Reading the counter more than once can be useful in
the case that the application is subject to a strong Electromagnetic Interference (EMI)
environment, so that read-back values can be compared.
Read back must be terminated within 32 seconds else a count will be dropped.
PCF8802
Product data sheet
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E E E E E E E E E E E E E E
E
E
E
E
E
E
06%
E
E
E
E
/6%
DDM
Fig 22. Read bit order
8.7 Power-on reset
At initial power-on a reset is generated. The reset lasts not longer than 10 ms. During this
time, the serial interface will not respond when accessed. The state of the device after
power-on reset is shown in Table 10.
Table 10.
Reset state
Instruction name
PCF8802
Product data sheet
State after reset
dvs_cmd
disabled
pwd_cmd
disabled
32k_cmd
disabled
fst_cmd
disabled
24-bit counter
000000h
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9. Internal circuitry
966
26&,
6&/
26&2
6'$
7(67
,17
3&)
9''
DDD
Fig 23. Diode protection diagram
10. Safety notes
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
CAUTION
Semiconductors are light sensitive. Exposure to light sources can cause the IC to
malfunction. The IC must be protected against light. The protection must be applied to all
sides of the IC.
PCF8802
Product data sheet
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Rev. 1 — 30 June 2014
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11. Limiting values
Table 11. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
Min
Max
Unit
supply voltage
0.5
+6.5
V
IDD
supply current
50
+50
mA
VI
input voltage
0.5
+6.5
V
II
input current
10
+10
mA
VO
output voltage
0.5
+6.5
V
IO
output current
10
+10
mA
Ptot
total power dissipation
-
300
mW
Vesd
electrostatic
discharge voltage
Ilu
latch-up current
Tamb
ambient temperature
HBM
[1]
-
2500
V
MM
[2]
-
200
V
[3]
-
200
mA
40
+85
C
65
+150
C
[4]
storage temperature
Tstg
[1]
Conditions
Pass level; Human Body Model (HBM) according to JESD22-A114.
[2]
Pass level; Machine Model (MM), according to JESD22-A115.
[3]
Pass level; Latch-up testing, according to JESD78.
[4]
According to the store and transport requirements (see Ref. 11 “UM10569”) the devices have to be stored at a temperature of +8 C to
+45 C and a humidity of 25 % to 75 %.
PCF8802
Product data sheet
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Rev. 1 — 30 June 2014
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12. Static characteristics
Table 12. Static characteristics
VDD = 1.6 V to 5.5 V; VSS = 0 V; fosc = 32.768 kHz; Tamb = 40 C to +85 C; quartz crystal: Rs = 30 k, CL = 6.0 pF; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.6
-
5.5
V
Tamb = 25 C;
fSCL = 0 Hz
-
1.0
-
V
-
0.25
-
V
-
3
-
nA
fSCL = 0 Hz
-
-
400
nA
Tamb = 25 C;
VDD = 3 V;
fSCL = 0 Hz
-
130
-
nA
Supplies
VDD
supply voltage
VDD
supply voltage
variation
V/t = 1 V/s
IDD
supply current
deep sleep active
[1]
Tamb = 25 C;
VDD = 3 V;
fSCL = 0 Hz
device running
interface active
fSCL = 100 kHz
-
5
20
A
fSCL = 1 MHz
-
50
100
A
-
1.1
-
V
Oscillator
Vstart
start voltage
tstartup
start-up time
CL(itg)
integrated load
capacitance
[2]
-
0.2
-
s
-
6.0
-
pF
Inputs
VIL
LOW-level input
voltage
-
-
0.3VDD
V
VIH
HIGH-level input
voltage
0.7VDD
-
-
V
VI
input voltage
ILI
input leakage current
on pins SCL, OSCI, TEST
0.5
-
5.5
V
on pin SDA
0.5
-
VDD + 0.5
V
VI = VDD or VSS;
on pins SCL, SDA and TEST
200
0
+200
nA
0.5
-
VDD+0.5
V
VOH = 4.0 V;
VDD = 5 V;
on pins INT and SDA
-
5
2
mA
VOH = 1.28 V;
VDD = 1.6 V;
on pins INT and SDA
-
0.5
0.2
mA
Outputs
VO
output voltage
IOH
HIGH-level output
current
PCF8802
Product data sheet
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Smartcard RTC
Table 12. Static characteristics …continued
VDD = 1.6 V to 5.5 V; VSS = 0 V; fosc = 32.768 kHz; Tamb = 40 C to +85 C; quartz crystal: Rs = 30 k, CL = 6.0 pF; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IOL
LOW-level output
current
VOL = 1.0 V;
VDD = 5 V;
on pins INT and SDA
2
7
-
mA
VOL = 0.32 V;
VDD = 1.6 V;
on pins INT and SDA
0.4
1
-
mA
output leakage current VO = VDD or VSS;
on pins SDA and INT
200
0
+200
nA
ILO
[1]
Unless otherwise defined, IDD is measured with the reset state, see Section 8.7.
[2]
Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series: C L  itg  = -------------------------------------------- .
PCF8802
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 30 June 2014
 C OSCI  C OSCO 
 C OSCI + C OSCO 
© NXP Semiconductors N.V. 2014. All rights reserved.
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PCF8802
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Smartcard RTC
13. Dynamic characteristics
Table 13. Dynamic characteristics
VDD = 1.6 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. [1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Timing characteristics: serial bus
fSCL
SCL clock frequency
-
-
1
MHz
tLOW
LOW period of the
SCL clock
500
-
-
ns
tHIGH
HIGH period of the
SCL clock
260
-
-
ns
tBUF
bus free time between
a STOP and START
condition
500
-
-
ns
tHD;STA
hold time (repeated)
START condition
260
-
-
ns
tSU;STA
set-up time for a
repeated START
condition
260
-
-
ns
tr
rise time of both SDA
and SCL signals
[2]
-
10
-
ns
tf
fall time of both SDA
and SCL signals
[2]
-
10
-
ns
tSU;DAT
data set-up time
50
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
tSU;STO
set-up time for STOP
condition
260
-
-
ns
tVD;DAT
data valid time
75
-
450
ns
Cb
capacitive load for
each bus line
-
-
50
pF
20
40
80
s
Timing characteristics: INT
tw(int)
interrupt pulse width
[1]
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD.
[2]
Rise and fall times are not limited. Fast edges can lead to system EMI problems, while slow edges are susceptible to noise.
PCF8802
Product data sheet
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21 of 32
PCF8802
NXP Semiconductors
Smartcard RTC
W6867$
W/2:
W+,*+
I6&/
6&/
W%8)
WU
WI
6'$
W+'67$
W68'$7
W+''$7
W9''$7
W68672
DDM
Fig 24. Serial bus timing waveforms
,17
WZLQW
DDM
Fig 25. INT timing
PCF8802
Product data sheet
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Rev. 1 — 30 June 2014
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PCF8802
NXP Semiconductors
Smartcard RTC
14. Bare die outline
:/&63ZDIHUOHYHOFKLSVL]HSDFNDJHEXPSV
3&)$8*
$
'
$
3
3
H
[
;
3
(
\
3
H
GHWDLO;
H
H
PP
VFDOH
1RWHV
0DUNLQJFRGH3&
2XWOLQH
YHUVLRQ
SFIDXJBSR
5HIHUHQFHV
,(&
-('(&
(XURSHDQ
SURMHFWLRQ
-(,7$
,VVXHGDWH
3&)$8*
Fig 26. Bare die outline PCF8802AUG
Table 14. Dimensions of PCF8802AUG
Original dimensions are in mm.
Product data sheet
e
e1
e2
P1[2]
P2[3]
-
-
-
-
-
0.093 -
0.215 0.015 1.19
1.14
0.396 0.448 0.449 0.099 0.090 0.099 0.090
-
-
-
A
A1
max
-
0.018 -
nom
min
[1]
PCF8802
E[1]
D[1]
Unit (mm)
0.012 -
-
-
-
P3[2]
0.087 -
P4[3]
0.093
0.087
Including saw lane.
[2]
Pad size.
[3]
Bump size.
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Rev. 1 — 30 June 2014
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23 of 32
PCF8802
NXP Semiconductors
Smartcard RTC
5()
DDM
Pin 1 is identified by this symbol.
Fig 27. Pin 1 identifier
Table 15.
Bump and reference point locations of PCF8802AUG
Symbol
Pad
Coordinates[1]
x
y
INT
1
437
396
VDD
2
12
430
TEST
3
460
396
OSCO
4
460
1
OSCI
5
460
396
[2]
6
12
430
7
437
396
VSS
SCL
SDA
8
437
1
pin 1 identifier
-
474.7
472.0
-
594.8
568.2
-
594.7
568.3
bottom left die
top right die
corner[3]
corner[3]
[1]
All coordinates are referenced, in m, to the center of the die (see Figure 26).
[2]
The substrate (rear side of the die) is connected to VSS and should be electrically isolated.
[3]
Die size before dicing. Final dimensions will be 10 m to 20 m smaller.
Table 16.
Gold bump hardness of PCF8802AUG
Gold bump type
Min
Max
Unit[1]
soft gold bump
35
80
HV
[1]
Pressure of diamond head: 10 g to 50 g.
15. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
PCF8802
Product data sheet
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Rev. 1 — 30 June 2014
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24 of 32
PCF8802
NXP Semiconductors
Smartcard RTC
16. Packing information
16.1 Tape and reel information for PCF8802AUG
PP
:
$
.
%
3
GLUHFWLRQRIIHHG
DDL
Fig 28. Tape and reel details for PCF8802AUG
Table 17.
Tape and reel dimensions
Dimension
Description
Value
Unit
W
tape width
8.0 (0.1, +0.3)
mm
A0
pocked length
1.29 ( 0.05)
mm
B0
pocket width
1.34 ( 0.05)
mm
K0
pocket depth
0.37 ( 0.05)
mm
P1
pocket pitch
4.0 ( 0.1)
mm
SLQ
DDM
Die is placed in pocket bump side down.
The orientation of the IC in a pocket is indicated by the position of pin 1, with respect to the
sprocket holes (see Table 3 on page 2 for pin 1 indicator on the backside marking).
Fig 29. Pocket alignment for PCF8802AUG
PCF8802
Product data sheet
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PCF8802
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Smartcard RTC
17. Abbreviations
Table 18.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
EMI
ElectroMagnetic Interference
HBM
Human Body Model
IC
Integrated Circuit
LCD
Liquid Crystal Display
LSB
Least Significant Bit
MM
Machine Model
MSB
Most Significant Bit
PCB
Printed-Circuit Board
RTC
Real-Time Clock
WLCSP
Wafer Level Chip-Size Package
18. References
[1]
AN10439 — Wafer Level Chip Size Package
[2]
AN10706 — Handling bare die
[3]
AN10853 — ESD and EMC sensitivity of IC
[4]
IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[5]
IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[6]
JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[7]
JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model
(MM)
[8]
JESD78 — IC Latch-Up Test
[9]
JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[10] UM10204 — I2C-bus specification and user manual
[11] UM10569 — Store and transport requirements
PCF8802
Product data sheet
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Rev. 1 — 30 June 2014
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26 of 32
PCF8802
NXP Semiconductors
Smartcard RTC
19. Revision history
Table 19.
Revision history
Document ID
Release date
Data sheet status Change notice
Supersedes
PCF8802 v.1
20140630
Product data sheet -
-
PCF8802
Product data sheet
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© NXP Semiconductors N.V. 2014. All rights reserved.
27 of 32
PCF8802
NXP Semiconductors
Smartcard RTC
20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
20.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCF8802
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 30 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
28 of 32
PCF8802
NXP Semiconductors
Smartcard RTC
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCF8802
Product data sheet
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Rev. 1 — 30 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
29 of 32
PCF8802
NXP Semiconductors
Smartcard RTC
22. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Ordering information . . . . . . . . . . . . . . . . . . . . . .2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2
Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2
Pin description for PCF8802. . . . . . . . . . . . . . . .3
Instruction set overview . . . . . . . . . . . . . . . . . . .4
Write instructions . . . . . . . . . . . . . . . . . . . . . . .12
Read instructions . . . . . . . . . . . . . . . . . . . . . . .13
Deep sleep mode sequence . . . . . . . . . . . . . . .14
Example of accurate setting of the counter . . .15
Reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .18
Static characteristics . . . . . . . . . . . . . . . . . . . .19
Dynamic characteristics . . . . . . . . . . . . . . . . . .21
Dimensions of PCF8802AUG . . . . . . . . . . . . . .23
Bump and reference point locations of
PCF8802AUG . . . . . . . . . . . . . . . . . . . . . . . . .24
Gold bump hardness of PCF8802AUG . . . . . .24
Tape and reel dimensions . . . . . . . . . . . . . . . .25
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .26
Revision history . . . . . . . . . . . . . . . . . . . . . . .27a
PCF8802
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 30 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
30 of 32
PCF8802
NXP Semiconductors
Smartcard RTC
23. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Fig 26.
Fig 27.
Fig 28.
Fig 29.
Block diagram of PCF8802 . . . . . . . . . . . . . . . . . .2
Pinning diagram of PCF8802AUG . . . . . . . . . . . . .3
IDD with respect to Rs . . . . . . . . . . . . . . . . . . . . . . .5
Divider chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Counter behavior during read access . . . . . . . . . .6
Pulse generator . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Writing protocol . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Reading protocol . . . . . . . . . . . . . . . . . . . . . . . . . .8
Access restrictions . . . . . . . . . . . . . . . . . . . . . . . . .8
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Definition of START and STOP conditions. . . . . . .9
Acknowledgement on the I2C-bus . . . . . . . . . . . .10
A complete data transfer . . . . . . . . . . . . . . . . . . .10
A master-transmitter addresses a slave
receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
A master reads from a slave immediately after
the first byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Combined format . . . . . . . . . . . . . . . . . . . . . . . . . 11
Sending instructions . . . . . . . . . . . . . . . . . . . . . . 11
Setting the counter. . . . . . . . . . . . . . . . . . . . . . . . 11
Reading the counter . . . . . . . . . . . . . . . . . . . . . .12
Instruction dvs_cmd . . . . . . . . . . . . . . . . . . . . . . .13
Read bit order . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Diode protection diagram. . . . . . . . . . . . . . . . . . .17
Serial bus timing waveforms . . . . . . . . . . . . . . . .22
INT timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Bare die outline PCF8802AUG . . . . . . . . . . . . . .23
Pin 1 identifier . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Tape and reel details for PCF8802AUG. . . . . . . .25
Pocket alignment for PCF8802AUG . . . . . . . . . .25
PCF8802
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 30 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
31 of 32
PCF8802
NXP Semiconductors
Smartcard RTC
24. Contents
1
2
3
4
4.1
5
6
7
7.1
7.2
8
8.1
8.1.1
8.1.2
8.2
8.3
8.4
8.5
8.5.1
8.5.1.1
8.5.1.2
8.5.1.3
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.7.1
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
8.6.7
8.6.8
8.7
9
10
11
12
13
14
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Low-power operation . . . . . . . . . . . . . . . . . . . . 4
Deep sleep mode . . . . . . . . . . . . . . . . . . . . . . . 5
Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Binary counter . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pulse generator . . . . . . . . . . . . . . . . . . . . . . . . 6
I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . . 7
Interface protocol . . . . . . . . . . . . . . . . . . . . . . . 7
The writing protocol . . . . . . . . . . . . . . . . . . . . . 7
The reading protocol. . . . . . . . . . . . . . . . . . . . . 8
Reading and writing limitations . . . . . . . . . . . . . 8
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
START and STOP conditions . . . . . . . . . . . . . . 9
System configuration . . . . . . . . . . . . . . . . . . . . 9
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Example data transfers. . . . . . . . . . . . . . . . . . 11
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . 12
Instruction wrt_cmd . . . . . . . . . . . . . . . . . . . . 13
Instruction dvs_cmd . . . . . . . . . . . . . . . . . . . . 13
Instruction pwd_cmd. . . . . . . . . . . . . . . . . . . . 14
Instruction 32k_cmd . . . . . . . . . . . . . . . . . . . . 14
Instruction fst_cmd . . . . . . . . . . . . . . . . . . . . . 14
Instruction set_cmd . . . . . . . . . . . . . . . . . . . . 15
Instruction rd_cmd . . . . . . . . . . . . . . . . . . . . . 15
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 16
Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 17
Safety notes . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18
Static characteristics. . . . . . . . . . . . . . . . . . . . 19
Dynamic characteristics . . . . . . . . . . . . . . . . . 21
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 23
15
16
16.1
17
18
19
20
20.1
20.2
20.3
20.4
21
22
23
24
Handling information . . . . . . . . . . . . . . . . . . .
Packing information . . . . . . . . . . . . . . . . . . . .
Tape and reel information for PCF8802AUG .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
25
25
26
26
27
28
28
28
28
29
29
30
31
32
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 30 June 2014
Document identifier: PCF8802
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