CMOS 8-BIT MICROCONTROLLER LC870800 SERIES USER’S MANUAL http://onsemi.com REV : 1.01 ON Semiconductor Digital Solution Division Microcontroller & Flash Business Unit ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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Contents Chapter 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Overview ···································································· 1-1 Overview ··················································································· 1-1 Features ··················································································· 1-1 Pinout ······················································································· 1-6 System Block Diagram ································································· 1-7 Pin Functions ············································································· 1-8 On-chip Debugger Pin Connection Requirements ····························· 1-10 Recommended Unused Pin Connections ········································ 1-10 Port Output Types ······································································ 1-10 User Option Table ······································································ 1-11 Chapter 2 Internal Configuration ·················································· 2-1 2.1 Memory Space ··········································································· 2-1 2.2 Program Counter (PC) ································································· 2-1 2.3 Program Memory (ROM) ······························································ 2-2 2.4 Internal Data Memory (RAM) ························································· 2-2 2.5 Accumulator/A Register (ACC/A) ···················································· 2-3 2.6 B Register (B)············································································· 2-3 2.7 C Register (C) ············································································ 2-4 2.8 Program Status Word (PSW) ························································· 2-4 2.9 Stack Pointer (SP) ······································································· 2-5 2.10 Indirect Addressing Registers ························································ 2-5 2.11 Addressing Modes······································································· 2-6 2.11.1 Immediate Addressing (#) ······················································· 2-6 2.11.2 Indirect Register Indirect Addressing ([Rn]) ································ 2-7 2.11.3 Indirect Register + C Register Indirect Addressing ([Rn,C]) ············ 2-7 2.11.4 Indirect Register (R0) + Offset Value Indirect Addressing ([off]) ······ 2-8 2.11.5 Direct Addressing (dst) ·························································· 2-8 2.11.6 ROM Table Look-up Addressing ·············································· 2-9 2.11.7 External Data Memory Addressing················································· 2-9 2.12 Wait Sequence ·········································································· 2-10 2.12.1 Wait Sequence Occurrence ··················································· 2-10 2.12.2 What is a Wait Sequence? ····················································· 2-10 Chapter 3 Peripheral System Configuration···································· 3-1 3.1 Port 0 ························································································· 3-1 3.1.1 Overview ·············································································· 3-1 －1－ Contents 3.1.2 Functions ·············································································· 3-1 3.1.3 Related Registers ··································································· 3-2 3.1.4 Options ················································································ 3-4 3.1.5 HALT and HOLD Mode Operation ·············································· 3-4 3.2 Port 1 ························································································· 3-5 3.2.1 Overview ·············································································· 3-5 3.2.2 Functions ·············································································· 3-5 3.2.3 Related Registers ··································································· 3-6 3.2.4 Options ················································································ 3-8 3.2.5 HALT and HOLD Mode Operation ·············································· 3-8 3.3 Port 2 ························································································· 3-9 3.3.1 Overview ·············································································· 3-9 3.3.2 Functions ·············································································· 3-9 3.3.3 Related Registers ·································································· 3-10 3.3.4 Options ··············································································· 3-12 3.3.5 HALT and HOLD Mode Operation ············································· 3-12 3.4 Port 3 ························································································ 3-13 3.4.1 Overview ············································································· 3-13 3.4.2 Functions ············································································· 3-13 3.4.3 Related Registers ·································································· 3-13 3.4.4 Options ··············································································· 3-14 3.4.5 HALT and HOLD Mode Operation ············································· 3-14 3.5 Port 7 ························································································ 3-15 3.5.1 Overview ············································································· 3-15 3.5.2 Functions ············································································· 3-15 3.5.3 Related Registers ·································································· 3-16 3.5.4 Options ··············································································· 3-20 3.5.5 HALT and HOLD Mode Operation ············································· 3-20 3.6 Timer/Counter 0 (T0) ···································································· 3-21 3.6.1 Overview ············································································· 3-21 3.6.2 Functions ············································································· 3-21 3.6.3 Circuit Configuration······························································· 3-22 3.6.4 Related Registers ·································································· 3-27 3.7 Timer/Counter 1 (T1) ···································································· 3-30 3.7.1 Overview ············································································· 3-30 3.7.2 Functions ············································································· 3-30 3.7.3 Circuit Configuration······························································· 3-32 －2－ Contents 3.7.4 Related Registers ·································································· 3-37 3.8 Timer 6 and Timer 7 (T6, T7) ························································· 3-42 3.8.1 Overview ············································································· 3-42 3.8.2 Functions ············································································· 3-42 3.8.3 Circuit Configuration······························································· 3-42 3.8.4 Related Registers ·································································· 3-45 3.9 Base Timer (BT) ·········································································· 3-47 3.9.1 Overview ············································································· 3-47 3.9.2 Functions ············································································· 3-47 3.9.3 Circuit Configuration······························································· 3-48 3.9.4 Related Registers ·································································· 3-49 3.10 Serial Interface 0 (SIO0) ······························································ 3-51 3.10.1 Overview············································································ 3-51 3.10.2 Functions ··········································································· 3-51 3.10.3 Circuit Configuration ····························································· 3-51 3.10.4 Related Registers ································································ 3-53 3.10.5 SIO0 Communication Examples ·············································· 3-54 3.10.6 SIO0 HALT Mode Operation ·················································· 3-55 3.11 Serial Interface 1 (SIO1) ······························································ 3-56 3.11.1 Overview············································································ 3-56 3.11.2 Functions ··········································································· 3-56 3.11.3 Circuit Configuration ····························································· 3-57 3.11.4 SIO1 Communication Examples ·············································· 3-61 3.11.5 Related Registers ································································ 3-65 3.12 Asynchronous Serial Interface 1 (UART1) ······································ 3-67 3.12.1 Overview ············································································ 3-67 3.12.2 Functions ··········································································· 3-67 3.12.3 Circuit Configuration ····························································· 3-68 3.12.4 Related Registers ································································ 3-71 3.12.5 UART1 Continuous Communication Processing Examples ··········· 3-75 3.12.6 UART1 HALT Mode Operation ··············································· 3-77 3.13 AD Converter (ADC10) ······························································· 3-78 3.13.1 Overview············································································ 3-78 3.13.2 Functions ··········································································· 3-78 3.13.3 Circuit Configuration ····························································· 3-79 3.13.4 Related Registers ································································ 3-79 3.13.5 AD Conversion Example ······················································· 3-83 －3－ Contents 3.13.6 Hints on the Use of the ADC ·················································· 3-84 3.14 Motor Control PWM (MCPWM) ····················································· 3-86 3.14.1 Overview············································································ 3-86 3.14.2 Functions ··········································································· 3-86 3.14.3 Circuit Configuration ····························································· 3-87 3.14.4 Related Registers ································································ 3-90 3.14.5 PULSGi/PULSGi# Output Port Settings (i=0, 1, 2) ······················· 3-96 3.14.6 Timing Charts ····································································· 3-98 3.15 Analog Comparator/Amplifier (CMP/AMP) ····································· 3-102 3.15.1 Overview·········································································· 3-102 3.15.2 Functions ········································································· 3-102 3.15.3 Circuit Configuration ··························································· 3-102 3.15.4 Related Registers ······························································ 3-104 Chapter 4 Control Functions ························································ 4-1 4.1 Interrupt Function ········································································· 4-1 4.1.1 Overview ·············································································· 4-1 4.1.2 Functions ·············································································· 4-1 4.1.3 Circuit Configuration································································ 4-2 4.1.4 Related Registers ··································································· 4-3 4.2 System Clock Generator Function ···················································· 4-5 4.2.1 Overview ·············································································· 4-5 4.2.2 Functions ·············································································· 4-5 4.2.3 Circuit Configuration································································ 4-6 4.2.4 Related Registers ··································································· 4-8 4.3 CF Oscillation (Main Clock) Monitoring Function ································ 4-13 4.3.1 Overview ············································································· 4-13 4.3.2 Functions ············································································· 4-13 4.3.3 Circuit Configuration······························································· 4-13 4.3.4 Related Register ··································································· 4-13 4.3.5 CF Oscillation Monitoring Example ············································ 4-14 4.4 Standby Function ········································································ 4-15 4.4.1 Overview ············································································· 4-15 4.4.2 Functions ············································································· 4-15 4.4.3 Related Registers ·································································· 4-16 4.5 Reset Function············································································ 4-20 4.5.1 Overview ············································································· 4-20 －4－ Contents 4.5.2 Functions ············································································· 4-20 4.5.3 Reset State ·········································································· 4-21 4.6 Watchdog Timer (WDT) ································································ 4-22 4.6.1 Overview ············································································· 4-22 4.6.2 Functions ············································································· 4-22 4.6.3 Circuit Configuration······························································· 4-22 4.6.4 Related Registers ·································································· 4-24 4.6.5 Notes on the Use of the Watchdog Timer ··································· 4-26 4.7 Internal Reset Function ································································· 4-27 4.7.1 Overview ············································································· 4-27 4.7.2 Functions ············································································· 4-27 4.7.3 Circuit Configuration······························································· 4-27 4.7.4 Options ··············································································· 4-28 4.7.5 Sample Operating Waveforms of the Internal Reset Circuit ············· 4-30 4.7.6 Notes on the Use of the Internal Reset Circuit······························ 4-31 4.7.7 Notes to be Taken When Not Using the Internal Reset Circuit ········· 4-33 Appendixes A-I A-II Special Functions Register (SFR) Map ······································· AI-(1-7) Port Block Diagrams ······························································· AII-(1-8) －5－ LC870800 Chapter 1 1. Overview 1.1 Overview The LC870800 series is an 8-bit microcontroller that, centered around a CPU running at a minimum bus cycle time of 50.0 ns, integrates on a single chip a number of hardware features such as 8K-byte flash ROM (onboard programmable), 256-byte RAM, an on-chip debugger function, two 16-bit timer/counters (may be divided into 8-bit timers), an asynchronous/synchronous SIO interface, a 10-bit, 10-channel AD converter with 10-/8-bit resolution selector, an analog comparator, an AMP circuit, a motor control PWM, a watchdog timer, an internal reset circuit, a system clock frequency divider, and 21-source 10-vector interrupt feature. This series of microcomputers is optimal for small motor control devices. 1.2 ● Features Flash ROM • • • • ● Programmable onboard with a supply voltage range of 3.3 to 5.5V Block-erasable in 128-byte units Writes data in 2-byte units 8192 × 8 bits RAM • 256 × 9 bits ● Minimum bus cycle time • 50.0 ns (at 20 MHz) Note: The bus cycle time here refers to the ROM read speed. ● Minimum instruction cycle time (Tcyc) • 150 ns (at 20 MHz) ● Ports • Normal withstand voltage I/O ports • • • • ● Ports whose I/O direction can be designated in 1-bit units: Ports whose I/O direction can be designated in 4-bit units: Dedicated oscillator/input ports: Reset pin Power pins: Dedicated on-chip debugger port 20 (P1n, P20, P21, P30 to P35, P70 to P73) 8 (P0n) 2 (CF1/XT1, CF2/XT2) 1 (RES) 4 (VSS1, VSS2, VDD1, VDD2) 1 (OWP0) Timers ● Timer 0: 16-bit timer/counter with a capture register Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) 1-1 ● Timer 1: 16-bit timer/counter that supports PWM/toggle output Mode 0: 8-bit timer with an 8-bit prescaler (with toggle output) + 8-bit timer/counter (with toggle output) Mode 1: 8-bit PWM with an 8-bit prescaler 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle output) (toggle output also available from the low-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle output) (The low-order 8 bits can be used as a PWM module.) ● Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) ● Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) ● Base timer 1) 2) 3) ● SIO ● SIO0: 8-bit synchronous serial interface 1) LSB first / MSB first is selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock rate = 4/3 Tcyc) ● ● The clock is selectable from among a subclock (32.768 kHz crystal oscillator), system clock, and timer 0 prescaler output. Interrupts are programmable in 5 different time schemes. The base timer is not available when the CF oscillator circuit is selected. SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 Tcyc transfer clock) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048Tcyc baudrate) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 Tcyc transfer clock) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) UART1 • Full duplex • Data length: 7/8/9 bits selectable • Stop bit: 1 bit (2 bits in continuous data transmission) • Built-in baudrate generator ● AD converter: 10 bits 10 channels (2 channels are implemented on-chip) • 10-/8-bit AD converter resolution selectable • Automatic AD start function (associated with the motor control PWM interrupt source) ● Remote control receiver circuit (multiplexed with the P73/INT3/T0IN pin) • Noise rejection function (noise filter time constant selectable from 1Tcyc/32Tcyc/128Tcyc) ● ● Clock output function 1 1 1 1) Can output a clock with a frequency of 1 , 2 , 4 , selected as the system clock. 2) Can generate the source oscillator clock for the subclock. 1 8 , 1 16 , 1 32 , or 1 64 Analog comparator/amplifier: 2 channels • Switches between the analog comparator and the amplifier function (each channel). • Analog comparator interrupt ● Motor control PWM: 12 bits 6 channels • The dead time can be set. • Forced output stop function using an external input or analog comparator output • Edge-aligned or center-aligned mode select 1-2 of the source clock LC870800 Chapter 1 ● Watchdog timer • Capable of generating an internal reset on an overflow of a timer running on the WDT-dedicated lowspeed RC oscillator clock (30kHz). • The continuation, termination, or retaining (count value) of the WDT operation on entry into the standby mode is programmable. ● Interrupts ● 21 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt request of the level equal to or lower than the current interrupt is not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, an interrupt into the smallest vector address is given priority. No. 1 2 3 4 5 6 7 8 9 10 Vector 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L Interrupt Source INT0 INT1 INT2/T0L/INT4 INT3/ base timer T0H T1L/T1H SIO0/UART1 receive SIO1/UART1 transmit/MCPWM ADC/T6/T7 Port 0/CMP1/CMP2 • Priority levels X > H > L • When interrupts of the same level occur at the same time, the interrupt with the smallest vector address is given priority. ● Subroutine stack levels: Up to 128 levels (The stack is allocated in RAM.) ● High-speed multiplication/division instructions • 16 bits 8 bits (5 Tcyc execution time) • 24 bits 16 bits (12 Tcyc execution time) • 16 bits 8 bits (8 Tcyc execution time) • 24 bits 16 bits (12 Tcyc execution time) ● Oscillator circuits ● Internal oscillator circuits 1) Medium-speed RC oscillator circuit: 2) High-speed RC oscillator circuit: 3) Low-speed RC oscillator circuit 2: ● For system clock (1 MHz) For system clock (20 MHz) For watchdog timer (30 kHz) External oscillator circuits 1) High-speed CF oscillator circuit: For system clock, with internal Rf 2) Low-speed crystal oscillator circuit: For low-speed system clock, with internal Rf (1) The CF and crystal oscillator circuits share the same oscillation pin, the selection of which is programmable. (2) The CF and the crystal oscillator circuits stop operating in the system reset state and start oscillating when the oscillation is enabled with an instruction. 1-3 ● System clock divider function • Capable of running on low current. • The minimum instruction cycle can be selected from among 150ns, 300ns, 600ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, and 38.4 s (at a main clock rate of 20 MHz). ● Internal reset circuit ● Power-on reset (POR) function 1) POR reset is generated only at power-on time. 2) The POR release level can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, and 4.35V) by setting options. ● ● Low-voltage detection reset (LVD) function 1) LVD function, when used together with the POR function, can generate a reset when power is turned on and when the power level lowers. 2) The use/non-use of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V, 2.81V, 3.79V, and 4.28V) can be selected by setting options. Standby function ● HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not stopped automatically. 2) There are three ways of releasing HALT mode. <1> Setting the reset pin to a low level <2> Generating a reset by the watchdog timer or low-voltage detection <3> Generating an interrupt ● HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, high-/medium-speed RC, and crystal oscillators automatically stop operation. 2) There are four ways of releasing HOLD mode. <1> Setting the reset pin to a lower level <2> Generating a reset by the watchdog timer or low-voltage detection <3> Establishing an interrupt source at least one of INT0, INT1, INT2, and INT4 * INT0 and INT1 HOLD mode release is available only when level detection is set. <4> Establishing an interrupt source at port 0 ● X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer (when X'tal oscillator is selected). 1) The CF and high-/medium-speed RC oscillators automatically stop operation. 2) The state of the crystal oscillator when X'tal HOLD mode is entered is retained. 3) There are five ways of releasing X'tal HOLD mode. <1> Setting the reset pin to a low level. <2> Generating a reset by the watchdog timer or low-voltage detection <3> Establishing an interrupt source at least one of INT0, INT1, INT2, and INT4 * INT0 and INT1 X’tal HOLD mode release is available only when level detection is set. <4> Establishing an interrupt source at port 0. <5> Establishing an interrupt source in the base timer circuit. Note: Available only when X’tal oscillator is selected. 1-4 LC870800 Chapter 1 ● On-chip debugger function • Supports software debugging with the microcontroller mounted on the target board. ● Data security function (flash versions only) • Protects the program data stored in flash memory from unauthorized read or copy. Note: This data security function does not necessarily provide absolute data security. ● Package form • QFP36 (7 7) (lead-free product) ● Development tools • On-chip debugger: ● TCB87 Type C + LC87F0808A Programming board Package QFP36 Programming board W87F24Q 1-5 27 26 25 24 23 22 21 20 19 P03/AN3 P02/AN2 P01/AN1 P00/AN0 VSS2 VDD2 P17/T1PWMH/URX/CMP2O P16/T1PWML/UTX/CMP2IA P15/SCK1/CMP2IB Pinout 28 29 30 31 32 33 34 35 36 18 17 16 15 14 13 12 11 10 ＴOP VＩEW P14/SI1/SB1/CMP1O P13/SO1/CMP1IA P12/SCK0/CMP1IB P11/SI0/SB0 P10/SO0 P35/PULSG2# P34/PULSG2 P33/PULSG1# P32/PULSG1 1 2 3 4 5 6 7 8 9 P04/AN4 P05/AN5/CKO P06/AN6/T6O P07/AN7/T7O P20/INT4 P21/INT4/BUZ P70/INT0/T0LCP P71/INT1/T0HCP P72/INT2/T0LCP/T0IN P73/INT3/T0HCP/T0IN RES# OWP0 VSS1 CF1/XT1 CF2/XT2 VDD1 P30/PULSG0 P31/PULSG0# 1.3 SANYO: QFP36 (7x7) (lead-free product) QFP36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 NAME QFP36 NAME P73/INT3/T0HCP/T0IN RES# 19 20 P15/SCK1/CMP2IB(+) P16/T1PWML/UTX/CMP2IA(-) OWP0 VSS1 CF1/XT1 CF2/XT2 VDD1 P30/PULSG0 P31/PULSG0# P32/PULSG1 P33/PULSG1# P34/PULSG2 P35/PULSG2# P10/SO0 P11/SI0/SB0 P12/SCK0/CMP1IB(+) P13/SO1/CMP1IA(-) P14/SI1/SB1/CMP1O 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 P17/T1PWMH/URX/CMP2O VDD2 VSS2 P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5/CKO P06/AN6/T6O P07/AN7/T7O P20/INT4 P21/INT4/BUZ P70/INT0/T0LCP P71/INT1/T0HCP P72/INT2/T0LCP/T0IN 1-6 LC870800 Chapter 1 System Block Diagram Interrupt control IR Standby control RC Clock CF/ X’tal PLA Flash ROM generator PC MRC RES＃ WDT Reset circuit Reset control 1.4 ACC B register (LVD/POR) C register SIO0 Bus interface ALU SIO1 Port 0 Timer 0 Port 1 PSW Timer 1 Port 2/INT4 RAR Timer 6 Port 3 Timer 7 Port 7 Stack pointer Base timer ADC On-chip debugger MCPWM INT0-INT2 INT3 (w/noise filter) UART1 1-7 RAM 1.5 Pin Functions Name VSS1, VSS2 I/O － VDD1, VDD2 － Port 0 P00 to P07 I/O Port 1 P10 to P17 I/O Port 2 P20, P21 I/O Port 3 P30 to P35 I/O Description – Power supply + Power supply • 8-bit I/O port • I/O specifiable in 4-bit units • Pull-up resistors can be turned on and off in 4-bit units • HOLD release input • Port 0 interrupt input • Pin functions P05: System clock output P06: Timer 6 toggle output P07: Timer 7 toggle output P00 (AN0) to P07 (AN7): AD converter input • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units • Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1 PWML output/ UART transmit P17: Timer 1 PWMH output/ UART receive P12 to P17: AMP/CMP I/O P12: CMP1(+) input/AMP1(+) input P13: CMP1(–) input/AMP1(–) input P14: CMP1 output/AMP1 output P15: CMP2(+) input/AMP2(+) input P16: CMP2(–) input/AMP2(–) input P17: CMP2 output/AMP2 output • 2-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units • Pin functions P21: BUZ output P20, P21: INT4 input/HOLD release input/timer 1 event input /timer 0L capture input/timer 0H capture input Interrupt acknowledge type Rising Falling Rising & H level L level Falling ○ ○ ○ × × INT4 • 6-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units • Pin functions P30 to P35:Motor control PWM output P30: PULSG0 output P31: PULSG0# output P32: PULSG1 output P33: PULSG1# output P34: PULSG2 output P35: PULSG2# output Continued on next page. 1-8 Option No No Yes Yes Yes Yes LC870800 Chapter 1 Name Port 7 P70 to P73 I/O I/O Description • 4-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units • Pin functions P70:ＩNT0 input/HOLD release input/timer 0L capture input P71:ＩNT1 input/HOLD release input/timer 0H capture input P72:ＩNT2 input/HOLD release input/timer 0 event input /timer 0L capture input P73:ＩNT3 input (input with noise filtering)/timer 0 event input /timer 0H capture input Interrupt acknowledge type INT0 INT1 INT2 INT3 CF1/XT1 I/O I CF2/XT2 I/O OWP0 I/O RES Option No Rising Falling Rising & Falling H level L level ○ ○ ○ ○ ○ ○ ○ ○ × × ○ ○ ○ ○ × × ○ ○ × × External reset input/internal reset output • Ceramic resonator/32.768 kHz crystal resonator input • Pin functions General-purpose input Must be configured as a general-purpose port and connected to VSS1 if not to be used. • Ceramic resonator /32.768 kHz crystal resonator output • Pin functions General-purpose input Must be configured as a general-purpose port and connected to VSS1 if not to be used. On-chip debugger only 1-9 No No No No 1.6 On-chip Debugger Pin Connection Requirements The on-chip debugger pin OWPO must be pulled down with a 100 kΩ resistor. Connect to the TCB87 Type C with three wires (OWP0, VDD, and VSS). 1.7 Recommended Unused Pin Connections Pin Name P00 to P07 P10 to P17 P20 to P21 P30 to P35 P70 to P73 CF1/XT1 CF2/XT2 1.8 Recommended Unused Pin Connections Board Software Open Output low Open Output low Open Output low Open Output low Open Output low General-purpose input port Pulled low with a 100 kΩ resistor or less Pulled low with a 100 kΩ resistor or less General-purpose input port Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in output mode. Port P00 to P07 P10 to P17 P20, P21 P30 to P35 Option Selected in Option Type Output Type Units of 1 bit 1 CMOS 1 bit Pull-up Resistor Programmable (Note 1) 2 N-channel open drain No 1 CMOS Programmable 2 N-channel open drain Programmable P70 to P73 － No CMOS Programmable Note 1: The control of the presence or absence of the programmable pull-up resistors for port 0 and switching between low- and high-impedance pull-up connections is exercised in nibble (4- bit) units (P00 to 03 or P04 to 07). 1-10 LC870800 Chapter 1 1.9 User Option Table Option to be Applied on Flash-ROM Version Option Selected in Units of P00 to P07 ○ 1 bit P10 to P17 ○ 1 bit P20 to P21 ○ 1 bit P30 to P35 ○ 1 bit Program start address - ○ - Protect area (note 1) - ○ - Detection function ○ - Option Name Port output type Low-voltage detection reset function Power-on reset function Detection level Power-on reset level ○ ○ Option Selection CMOS N-channel open drain CMOS N-channel open drain CMOS N-channel open drain CMOS N-channel open drain 00000h 01E00h 00000h - 01BFFh 01C00h - 01EFFh Enable: Use Disable: Non-use - 7-level - 8-level Note 1 This option selects the area to be write-protected at the time of the onboard writing. *1 Be sure to electrically short-circuit between the VSS1 and VSS2 pins and between the VDD1 and VDD2 pins. 1-11 1-12 LC870800 Chapter 2 2. Internal Configuration 2.1 Memory Space This series of microcontrollers has the following three types of memory space: 1) 2) Program memory space: Internal data memory space: 3) External data memory space: Address 3FFFFH 256K bytes (128K bytes × 2 banks) 64K bytes (0000H to FDFFH out of 0000H to FFFFH is shared with the stack area.) 16M bytes Address FFFFFFH Program memory space ROM bank １ 128KB External data memory space Internal data memory space Address FFFFH RAM 16MB Reserved for system FF00H FEFFH SFR（8-bit） （some 9-bit） 1FFFFH FE00H ROM bank 0 128KB FDFFH RAM/Stack 64 KB （9-bit config.） 0000H 00000H 000000H Note: SFR is the area in which special function registers such as the accumulator are allocated (see Appendixes A-I). Figure 2.1.1 Types of Memory Space 2.2 Program Counter (PC) The program counter (PC) is made up of 17 bits and a bank flag BNK. The value of BNK determines the bank. The low-order 17 bits of the PC allows linear access to the 128K ROM space in the current bank. Normally, the PC advances automatically in the current bank on each execution of an instruction. Bank switching is accomplished by executing a Return instruction after pushing necessary addresses onto the stack. When executing a branch or subroutine instruction, when accepting an interrupt, or when a reset is generated, the value corresponding to each operation is loaded into the PC. Table 2.2.1 lists the values that are loaded into the PC when the respective operations are performed. 2-1 Table 2.2.1 Values Loaded in the PC Operation Inter- Reset (Note) PC Value BNK Value 0 0 0 0 0 0 0 0 0 0 0 0 Unchanged Unchanged Unchanged 00000H 01E00H rupt INT0 00003H INT1 0000BH INT2/T0L/INT4 00013H INT3 /Base timer 0001BH T0H 00023H T1L/T1H 0002BH SIO0/UART1 receive 00033H SIO1/UART1 transmit/MCPWM 0003BH ADC/T6/T7 00043H Port 0/CMP1/CMP2 0004BH Unconditional branch JUMP a17 PC=a17 instructions BR r12 PC=PC+2+r12[-2048 to +2047] Conditional branch BE, BNE, DBNZ, DBZ, BZ, BNZ, PC=PC+nb+r8[-128 to +127] instructions BZW, BNZW, BP, BN, BPC nb: Number of instruction bytes Call instructions CALL a17 PC=a17 Unchanged RCALL r12 PC=PC+2+r12[-2048 to +2047] Unchanged RCALLA PC=PC+1+Areg[0 to +255] Unchanged Return instructions RET, RETI PC16 to 08=(SP) BNK is set PC07 to 00=(SP-1) to bit 8 of (SP) denotes the contents of RAM (SP-1). address designated by the value of the stack pointer SP. Standard instructions NOP, MOV, ADD, … PC=PC+nb Unchanged nb: Number of instruction bytes Note: The reset-time program start address can be selected through a user option in the flash version of the microcontroller. In the mask version, the program start address is fixed at address 00000H. 2.3 Program Memory (ROM) This series of microcontrollers has a program memory space of 256K bytes but the size of the ROM that is actually incorporated in the microcontroller varies with the type of the microcontroller. The ROM table look-up instruction (LDC) can be used to reference all ROM data within the bank. Of the ROM space, the 256 bytes in ROM bank 0 (1FF00H to 1FFFFH for this series of microcontrollers) are reserved as the option area. Consequently, this area is not available as a program area. 2.4 Internal Data Memory (RAM) This series of microcontrollers has an internal data memory space of 64K bytes but the size of the RAM that is actually incorporated in the microcontroller varies with the type of the microcontroller. Nine bits are used to access addresses 0000H to FDFFH of the 128K ROM space and 8 or 9 bits are used to access addresses FE00H to FFFFH. The 9th bit of RAM is implemented by bit 1 of the PSW and can be read and written. The 128 bytes of RAM from 0000H to 007FH are paired to form 64 2-byte indirect address registers. The bit length of these indirect registers is normally 16 bits (8 bits 2). When they are used by the ROM table look-up instruction (LDC), however, their bit length is set to 17 bits (9 high-order bits + 8 low-order bits). As shown in Figure 2.4.1, the available instructions vary depending on the RAM address. The efficiency of the ROM used and a higher execution speed can be attempted using these instructions properly. 2-2 LC870800 Chapter 2 FFFFH Reserved for system FF00H FEFFH FE00H FDFFH 2000H 1FFFH *Note: Some registers are 9-bit SFR space * 8-bit RAM/ Stack space 9-bit 0200H 01FFH 0100H 00FFH 0000H Bit instruction direct (long) Bit instruction direct (short) Non-bit instruction direct (long)/indirect,16-bit operation instruction direct/indirect Non-bit instruction direct (short) Figure 2.4.1 RAM Addressing Map When the value of the PC is stored in RAM during the execution of a subroutine call instruction or interrupt, assuming that SP represents the current value of the stack pointer, the value of BNK and the low-order 8 bits of the (17-bit) PC are stored in RAM address SP + 1 and the high-order 9 bits in SP + 2, after which SP is set to SP + 2. 2.5 Accumulator/A Register (ACC/A) The accumulator (ACC), also called the A register, is an 8-bit register that is used for data computation, transfer, and I/O processing. It is allocated to address FE00H in the internal data memory space and initialized to 00H on a reset. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE00 0000 0000 R/W AREG AREG7 AREG6 AREG5 AREG4 AREG3 AREG2 AREG1 AREG0 2.6 B Register (B) The B register is combined with the ACC to form a 16-bit arithmetic register during the execution of a 16bit arithmetic instruction. During a multiplication or division instruction, the B register is used with the ACC and C register to store the results of computation. In addition, during an external memory access instruction (LDX or STX), the B register designates the high-order 8 bits of the 24-bit address. The B register is allocated to address FE01H of the internal data memory space and initialized to 00H on a reset. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE01 0000 0000 R/W BREG BREG7 BREG6 BREG5 BREG4 BREG3 BREG2 BREG1 BREG0 2-3 2.7 C Register (C) The C register is used with the ACC and B register to store the results of computation during the execution of a multiplication or division instruction. In addition, during a C register offset indirect instruction, the C register stores the offset data (-128 to +127) to the contents of an indirect register. The C register is allocated to address FE02H of the internal data memory space and initialized to 00H on a reset. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE02 0000 0000 R/W CREG CREG7 CREG6 CREG5 CREG4 CREG3 CREG2 CREG1 CREG0 2.8 Program Status Word (PSW) The program status word (PSW) is made up of flags that indicate the status of computation results, a flag to access the 9th bit of RAM, and a flag to designate the bank during the LDCW instruction. The PSW is allocated to address FE06H of the internal data memory space and initialized to 00H on a reset. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE06 0000 0000 R/W PSW CY AC PSWB5 PSWB4 LDCBNK OV P1 PARITY CY (bit 7): Carry flag CY is set (to 1) when a carry occurs as the result of a computation and cleared (to 0) when no carry occurs. There are following 4 types of carries: 1) 2) 3) 4) Carry resulting from an addition Borrow resulting from a subtraction Borrow resulting from a comparison Carry resulting from a rotation There are some instructions that do not affect this flag at all. AC (bit 6): Auxiliary carry flag AC is set (to 1) when a carry or borrow occurs in bit 3 (bit 3 of the high-order byte during a 16-bit computation) as the result of an addition or subtraction and cleared (to 0) otherwise. There are some instructions that do not affect this flag at all. PSWB5, PSWB4 (bits 5 and 4): User bits These bits can be read and written through instructions. They can be used by the user freely. LDCBNK (bit 3): Bank flag for the table look-up instruction (LDCW) This bit designates the ROM bank to be specified when reading the program ROM with a table look-up instruction. (0: ROM-ADR = 0 to 1FFFF, 1: ROM-ADR = 20000 to 3FFFF) OV (bit 2): Overflow flag OV is set (to 1) when an overflow occurs as the result of an arithmetic operation and cleared (to 0) otherwise. An overflow occurs in the following cases: 1) 2) When MSB is used as the sign bit and when the result of negative number + negative number or negative number – positive number is a positive When MSB is used as the sign bit and when the result of positive number + positive number or positive number – negative number is a negative number 2-4 LC870800 Chapter 2 When the high-order 8 bits of a 16 bits 8 bits multiplication is nonzero When the high-order 16 bits of a 24 bits 16 bits multiplication is nonzero When the divisor of a division is 0 3) 4) 5) There are some instructions that do not affect this flag at all. P1 (bit 1): RAM bit 8 data flag P1 is used to manipulate bit 8 of 9-bit internal data RAM (0000H to FDFFH). Its behavior varies depending on the instruction executed. See Table 2.4.1 for details. PARITY (bit 0): Parity flag This bit shows the parity of the accumulator (A register). The parity flag is set (to 1) when there is an odd number of 1’s in the A register. It is cleared (to 0) when there is an even number of 1’s. 2.9 Stack Pointer (SP) LC870000 series microcontrollers can use RAM addresses 0000H to FDFFH as a stack area. The size of RAM, however, varies depending on the microcontroller type. The SP is 16 bits long and made up of two registers: SPL (at address FE0A) and SPH (at address FE0B). It is initialized to 0000H on a reset. The SP is incremented by 1 before data is saved in stack memory and decremented by 1 after the data is restored from stack memory. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE0A 0000 0000 R/W SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 FE0B 0000 0000 R/W SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 The value of the SP changes as follows: 1) 2) 3) 4) When the PUSH instruction is executed: SP = SP + 1, RAM (SP) = DATA When the CALL instruction is executed: SP = SP + 1, RAM (SP) = ROMBANK + ADL SP = SP + 1, RAM (SP) = ADH When the POP instruction is executed: DATA = RAM (SP), SP = SP - 1 When the RET instruction is executed: ADH = RAM (SP), SP = SP - 1 ROM BANK + ADL = RAM(SP), SP = SP - 1 2.10 Indirect Addressing Registers LC870000 series microcontrollers are provided with three addressing schemes ([Rn], [Rn + C], [off]), which use the contents of indirect registers (indirect addressing modes). (See Section 2.11 for the addressing modes.) These addressing modes use 64 2-byte indirect registers (R0 to R63) allocated to RAM addresses 0 to 7EH. The indirect registers can also be used as general-purpose registers (e.g., for saving 2byte data). Naturally, these addresses can be used as ordinary RAM (in a 1-byte (9 bits) units) if they are not used as indirect registers. R0 to R63 are "system reserved words" to the assembler and need not be defined by the user. 2-5 RAM Reserved for system ･ Address 7FH R63(upper) 7EH R63(lower) R63 ＝ 7EH ･ ･ ・ ･ ･ ・ 03H R1(upper) 02H R1(lower) 01H R0(upper) 00H R0(lower) R1 = 2 R0 = 0 Figure 2.10.1 Allocation of Indirect Registers 2.11 Addressing Modes LC870000 series microcontrollers support the following seven addressing modes: 1) 2) 3) 4) 5) 6) 7) Immediate (immediate data refers to data whose value has been established at program preparation (assembly) time.) Indirect register (Rn) indirect (0 ≦ n ≦ 63) Indirect register (Rn) + C register indirect (0 ≦ n ≦ 63) Indirect register (R0) + Offset value indirect Direct ROM table look-up External data memory access The rest of this section describes these addressing modes. 2.11.1 Immediate Addressing (#) The immediate addressing mode allows 8-bit (1-byte) or 16-bit (1-word) immediate data to be handled. Examples are given below. Examples: LD L1: LDW PUSH ADD BE #12H; #1234H; #34H; #56H; #78H, L1; Loads the accumulator with byte data (12H). Loads the BA register pair with word data (1234H). Loads the stack with byte data (34H). Adds byte data (56H) to the accumulator. Compares byte data (78H) with the accumulator for a branch. 2-6 LC870800 Chapter 2 2.11.2 Indirect Register Indirect Addressing ([Rn]) In indirect register indirect addressing mode, it is possible to select one of the indirect registers (R0 to R63) and use its contents to designate an address in RAM or SFR. When the selected register contains, for example, "FE02H," it designates the C register. Example: When R3 contains "123H" (RAM address 6: 23H, RAM address 7: 01H) LD [R3]; Transfers the contents of RAM address 123H to the accumulator. L1: STW [R3]; Transfers the contents of the BA register pair to RAM address 123H. PUSH [R3]; Saves the contents of RAM address123H in the stack. SUB [R3]; Subtracts the contents of RAM address 123H from the accumulator. DBZ [R3], L1; Decrements the contents of RAM address 123H by 1 and causes a branch if zero. 2.11.3 Indirect Register + C Register Indirect Addressing ([Rn, C]) In the indirect register + C register indirect addressing mode, the result of adding the contents of one of the indirect registers (R0 to R63) to the contents of the C register (-128 to +127 with MSB being the sign bit) designates an address in RAM or SFR. For example, if the selected indirect register contains "FE02H" and the C register contains "FFH (-1)," the address "B register (FE02H + (-1) = FE01H" is designated. Examples: When R3 contains "123H" and the C register contains "02H" LD [R3, C]; Transfers the contents of RAM address 125H to the accumulator. L1: STW [R3, C]; Transfers the contents of the BA register pair to RAM address 125H. PUSH [R3, C]; Saves the contents of RAM address 125H in the stack. SUB [R3, C]; Subtracts the contents of RAM address 125H from the accumulator. DBZ [R3, C], L1; Decrements the contents of RAM address 125H by 1 and causes a branch if zero. <Notes on this addressing mode > The internal data memory space is divided into three closed functional areas as explained in Section 2.1, namely, 1) system reserved area (FF00H to FFFFH), 2) SFR area (FE00H to FEFFH), and 3) RAM/stack area (0000H to FDFFH). Consequently, it is not possible to point to a different area using the value of the C register from the basic area designated by the contents of Rn. For example, if the instruction "LD [R5,C]" is executed when R5 contains "0FDFFH" and the C register contains "1," since the basic area is 3) RAM/stack area (0000H to FDFFH), the intended address "0FDFFH+1 = 0FE00H" lies outside the basic area and "0FFH" is consequently placed in the ACC as the result of LD. If the instruction "LD [R5,C]" is executed when R5 contains "0FEFFH" and the C register contains "2," since the basic area is 2) SFR area (FE00H to FEFFH), the intended address "0FEFFH+2 = 0FF01H" lies outside the basic area. In this case, since SFR is confined in an 8-bit address space, the part of the address data addressing outside the 8-bit address space is ignored and the contents of 0FE01H (B register) are placed in the ACC as the result of the computation "0FF01H&0FFH+0FE00H = 0FE01H." 2-7 2.11.4 Indirect Register (R0) + Offset Value Indirect Addressing ([off]) In this addressing mode, the results of adding the 7-bit signed offset data off (-64 to + 63) to the contents of the indirect register R0 designate an address in RAM or SFR. If R0 contains "FE02H" and off has a value of "7EH(-2)," for example, the A register (FE02H + (-2) = FE00H) is designated. Examples: When R0 contains "123H" (RAM address 0: 23H, RAM address 1: 01H) LD [10H]; Transfers the contents of RAM address 133H to the accumulator. L1: STW [10H]; Transfers the contents of the BA register pair to RAM address 133H. PUSH [10H]; Saves the contents of RAM address 133H in the stack. SUB [10H]; Subtracts the contents of RAM address 133H from the accumulator. DBZ [10H], L1; Decrements the contents of RAM address 133H by 1 and causes a branch if zero. <Notes on this addressing mode> The internal data memory space is divided into three closed functional areas as explained in Section 2.1, namely, 1) system reserved area (FF00H to FFFFH), 2) SFR area (FE00H to FEFFH), and 3) RAM/stack area (0000H to FDFFH). Consequently, it is not possible to point to a different area using an offset value from the basic area designated by the contents of R0. For example, if the instruction "LD [1]" is executed when R0 contains "0FDFFH," since the basic area is 3) RAM/stack area (0000H to FDFFH), the intended address "0FDFFH+1 = 0FE00H" lies outside the basic area and "0FFH" is placed in the ACC as the results of LD. If the instruction "LD [2]" is executed when R0 contains "0FEFFH," since the basic area is 2) SFR (FE00H to FEFFH), the intended address "0FEFFH+2 = 0FF01H" lies outside the basic area. In this case, since SFR is confined in an 8-bit address space, the part of the address data addressing outside the 8-bit address space is ignored and the contents of 0FE01H (B register) are placed in the ACC as the result of computation "0FF01H&0FFH+0FE00H = 0FE01H." 2.11.5 Direct Addressing (dst) Direct addressing mode allows a RAM or SFR address to be specified directly in an operand. In this addressing mode, the assembler automatically generates the optimum instruction code from the address specified in the operand (the number of instruction bytes varies according to the address specified in the operand). Long (middle) range instructions (identified by an "L (M)" at the end of the mnemonic) are available to make the byte count of instructions constant (align instructions with the longest one). Examples: LD 123H; LDL 123H; STW PUSH SUB DBZ 123H; 123H; 123H; 123H, L1; L1: Transfers the contents of RAM address 123H to the accumulator (2-byte instruction). Transfers the contents of RAM address 123H to the accumulator (3-byte instruction). Transfers the contents of the BA register pair to RAM address 123H. Saves the contents of RAM address 123H in the stack. Subtracts the contents of RAM address 123H from the accumulator. Decrements the contents of RAM address 123H by 1 and causes a branch if zero. 2-8 LC870800 Chapter 2 2.11.6 ROM Table Look-up Addressing The LC870000 series microcontrollers can read 2-byte data into the BA register pair at once using the LDCW instruction. Three addressing modes [Rn], [Rn, C], and [off] are available for this purpose. (In this case only, Rn is configured as 17-bit registers (128K-byte space)). For models with banked ROM, it is possible to reference the ROM data in the ROM bank (128K bytes) identified by the LDCBNK flag (bit 3) in the PSW. Consequently, when looking into the ROM table on a series model with banked ROM, execute the LDCW instruction after switching the bank using the SET1 or CLR1 instruction so that the LDCBNK flag designates the ROM bank where the ROM table resides. Examples: TBL: DB DB DW • • LDW CHGP3 CHGP1 STW LDCW MOV LDCW INC LDCW 34H 12H 5678H • • #TBL; (TBL >> 17) & 1; (TBL >> 16) & 1; R0; [1]; #1, C; [R0, C]; C; [R0, C]: Loads the BA register pair with the TBL address. Loads LDCBNＫ in PSW with bit 17 of the TBL address. (Note 1) Loads P1 in PSW with bit 16 of the TBL address. Loads indirect register R0 with the TBL address (bits 16 to 0). Reads the ROM table (B=78H, ACC=12H). Loads the C register with "01H." Reads the ROM table (B=78H, ACC=12H). Increments the C register by 1. Reads the ROM table (B=56H, ACC=78H). Note 1: LDCBNK (bit 3) of PSW needs to be set up only for models with banked ROM. 2.11.7 External Data Memory Addressing LC870000 series microcontrollers can access external data memory spaces of up to 16M bytes (24 bits) using the LDX and STX instructions. To designate a 24-bit space, specify the contents of the B register (8 bits) as the highest-order byte of the address and the contents (16 bits) of (Rn), (Rn) + (C), or (R0) + off (either one) as the low-order bytes of the address. Examples: LDW STW MOV LDX #3456H; R5; #12H, B; [1]; Sets up the low-order 16 bits. Loads the indirect register R5 with the low-order 16 bits of the address. Sets up the high-order 8 bits of the address. Transfers the contents of external data memory (address 123456H) to the accumulator. 2-9 2.12 Wait Sequence 2.12.1 Wait Sequence Occurrence This series of microcontrollers does not have wait sequences that automatically suspends execution of instructions. 2.12.2 1) 2) 3) 4) 5) What is a Wait Sequence? When a wait request occurs out of a factor explained in Subsection 2.12.1, the CPU suspends the execution of the instruction for one cycle, during which the required data is transferred. This is called a wait sequence. The peripheral circuits such as timers and PWM continue processing during the wait sequence. A wait sequence extends over no more than two cycles. The microcontroller performs no wait sequence when it is in HALT or HOLD mode. Note that one cycle of discrepancy is introduced between the progress of the program counter and time once a wait sequence occurs. 2-10 LC870800 Chapter 2 Table 2.4.1 Chart of State Transitions of Bit 8 (RAM / SFR) and P1 Instruction Bit 8 (RAM/SFR) P1 (PSW Bit 1) LD#/LDW# － － Remarks LD － P1REG8 LDW － P1REGH8 ST REG8P1 － STW REGL8, REGH8P1 － MOV REG8P1 － PUSH# RAM8P1 － PUSH RAM8REG8 P1REG8 PUSHW RAMH8REGH8, RAML8REGL8 P1REGH8 PUSH_P RAM8Pl － PUSH_BA RAMH8P1, RAML8P1 － POP REG8RAM8 P1RAM8 P1bit1 when PSW is popped POPW REGH8RAMH8, REGL8RAML8 PlRAMH8 P1bit1 when highorder address of PSW is popped POP_P － P1RAMl (bit l) Bit 8 ignored POP_BA － P1RAMH8 XCH REG8P1 Same as left. XCHW REGH8P1, REGL8Pl, P1REGH8 Same as left. INC INC 9 bits P1REG8 after computation INC 9 bits INCW INC 17 bits, REGL8low byte of CY P1REGH8 after computation INC 17 bits DEC DEC 9 bits P1REG8 after computation DEC 9 bits DECW DEC 17 bits REGL8 low byte of CY inverted P1REGH8 after computation DEC 17 bits DBNZ DEC 9 bits P1REG8 DEC 9 bits, check loworder 8 bits DBZ DEC 9 bits P1REG8 DEC 9 bits, check loworder 8 bits SET1 － － NOT1 － － CLR1 － － BPC － － BP － － BN － － MUL24 /DIV24 RAM8"1" － FUNC － － Bit 8 of RAM address for storing results is set to 1. Note: A "1" is read if the processing target is an 8-bit register (no bit 8). Legends: REG8: REGH8/REGL8: RAM8: RAMH8/RAML8: Bit 8 of a RAM or SFR location Bit 8 of the high-order byte of a RAM location or SFR/bit 8 of the low-order byte Bit 8 of a RAM location Bit 8 of the high-order byte of a RAM location/bit 8 of the low-order byte 2-11 2-12 LC870800 Chapter 3 3. Peripheral System Configuration This chapter describes the internal functional blocks (peripheral system) of this series of microcontrollers, except the CPU core, RAM, and ROM. Port block diagrams are provided in Appendix A-II for reference. 3.1 Port 0 3.1.1 Overview Port 0 is an 8-bit I/O port equipped with programmable pull-up resistors. It is made up of a data latch, a data direction register, and a control circuit. The I/O direction and the pull-up resistor are set by the data direction register in 4-bit units. This port can also serve as a pin for external interrupts and can release HOLD mode. As a user option, either CMOS output with a programmable pull-up resistor or N-channel open drain output can be selected as the output type in 1-bit units. 3.1.2 1) Functions Input/output port (8 bits: P00-P07) • • • • The port output data is controlled by the port 0 data latch (P0: FE40) in 1-bit units. I/O control of P00 to P03 is performed by P0LDDR (P0DDR: FE41, bit 0). I/O control of P04 to P07 is performed by P0HDDR (P0DDR: FE41, bit 1). The port selected as a CMOS output by user option is provided with a programmable pull-up resistor. • The programmable pull-up resistors may be of either low impedance or high impedance type . • The programmable pull-up resistors for P00 to P03 are controlled by the P0LPU (P0DDR: FE41, bit 2). Their type (either low impedance or high impedance) is selected by P0LPUS (P0DDR: FE41, bit 6). • The programmable pull-up resistors for P04 to P07 are controlled by P0HPU (P0DDR: FE41, bit 3). Their type (either low impedance or high impedance) is selected by P0HPUS (P0DDR: FE41, bit 7). 2) Interrupt pin function P0FLG (P0DDR: FE41, bit 5) is set when an input port is specified and 0 level data is input to one of the port bits whose corresponding bit in the port 0 data latch (P0: FE40) is set to 1. In this case, if P0IE (P0DDR: FE41, bit 4) is 1, HOLD mode is released and an interrupt request to vector address 004BH is generated. 3) Multiplexed pin function Pin P05 is also used as the system clock output, pin P06 as the timer 6 toggle output, pin P07 as the timer 7 toggle output, and P00 to P07 as the analog input channel AN0 to AN7. Address Initial Value R/W Name BIT7 BIT6 FE40 0000 0000 R/W P0 P07 P06 P05 P04 P03 P02 P01 P00 FE41 0000 0000 R/W P0DDR P0HPUS P0LPUS P0FLG P0IE P0HPU P0LPU P0HDDR P0LDDR FE42 00HH 0000 R/W P0FCR T7OE T6OE - - 3-1 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 CLKOEN CKODV2 CKODV1 CKODV0 Port 0 3.1.3 Related Registers 3.1.3.1 1) 2) Port 0 data latch (P0) This latch is an 8-bit register for controlling port 0 output data and port 0 interrupts. When this register is read with an instruction, data at pins P00 to P07 is read in. If P0 (FE40) is manipulated using the NOT1, CLR1, SET1, DBZ, DBNZ, INC, or DEC instruction, the contents of the register are referenced instead of the data at the port pin. Port 0 data can always be read regardless of the I/O state of the port. 3) Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE40 0000 0000 R/W P0 P07 P06 P05 P04 P03 P02 P01 P00 3.1.3.2 Port 0 data direction register (P0DDR) 1) This register is an 8-bit register that controls the I/O direction of port 0 data in 4-bit units, the pull-up resistors in 4-bit units, and port 0 interrupts. Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 FE41 0000 0000 R/W P0DDR P0HPUS P0LPUS P0FLG P0IE P0HPU P0LPU BIT1 BIT0 P0HDDR P0LDDR P0HPUS (bit 7): P07 to P04 high/low impedance pull-up resistor select A 1 in this bit selects high impedance pull-up resistors for pins P07 to P04 and a 0 selects low impedance pull-up resistors. P0LPUS (bit 6): P03 to P00 high/low impedance pull-up resistor select A 1 in this bit selects high impedance pull-up resistors for pins P03 to P00 and a 0 selects low impedance pull-up resistors. P0FLG (bit 5): P0 interrupt source flag This flag is set when a low level is applied to port 0 that is set up for input and the corresponding P0 (FE40) bit is set. A HOLD mode release signal and an interrupt request to vector address 004BH are generated when this bit and the interrupt request enable bit (P0IE) are set to 1. This bit must be cleared with an instruction as it is not cleared automatically. P0IE (bit 4): P0 interrupt request enable Setting this bit and P0FLG to 1 generates a HOLD mode release signal and an interrupt request to vector address 004BH. P0HPU (bit 3): P07 to P04 pull-up resistor control When this bit is set to 1 and P0HDDR to 0, pull-up resistors are connected to port bits P07 to P04 that are selected as CMOS output by options. P0LPU (bit 2): P03 to P00 pull-up resistor control When this bit is set to 1 and P0LDDR to 0, pull-up resistors are connected to port bits P03 to P00 that are selected as CMOS output by options. P0HDDR (bit 1): P07 to P04 I/O control When this bit is set to 1, P07 to P04 are placed into output mode and the contents of the corresponding port 0 data latch (P0) are output from the port. When this bit is set to 0, P07 to P04 are placed into input mode and P0FLG is set when a low level is detected at the port whose corresponding port 0 data latch (P0) bit is set to 1. 3-2 LC870800 Chapter 3 P0LDDR (bit 0): P03 to P00 I/O control When this bit is set to 1, P03 to P00 are placed into output mode and the contents of the corresponding port 0 data latch (P0) are output from the port. When this bit is set to 0, P03 to P00 are placed into input mode and P0FLG is set when a low level is detected at the port whose corresponding port 0 data latch (P0) bit is set to 1. P07 to P04 pull-up resistor selection settings P0HPUS X P0HPU 0 Port for Which P0HDDR=0 and CMOS Option is Specified Pull-up resistor OFF X 0 Pull-up resistor OFF 0 1 Low impedance pull-up resistor ON 1 1 High impedance pull-up resistor ON P03 to P00 pull-up resistor selection settings 3.1.3.3 1) P0LPUS X P0LPU 0 Port for Which P0LDDR=0 and CMOS Option is Specified Pull-up resistor OFF X 0 Pull-up resistor OFF 0 1 Low impedance pull-up resistor ON 1 1 High impedance pull-up resistor ON Port 0 function control register (P0FCR) This register is a 6-bit register that controls the port 0 multiplexed output pins. Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 FE42 00HH 0000 R/W P0FCR T7OE T6OE - - BIT3 BIT2 CLKOEN CKODV2 BIT1 BIT0 CKODV1 CKODV0 T7OE (bit 7): This bit controls the output data of pin P07. It is disabled when P07 is in input mode. When P07 is in output mode: 0: Carries the value of the port data latch. 1: Carries the OR of the waveform that toggles at the interval determined by timer 7 and the value of the port data latch. T6OE (bit 6): This bit controls the output data of pin P06. It is disabled when P06 is in input mode. When P06 is in output mode: 0: Carries the value of the port data latch. 1: Carries the OR of the waveform that toggles at the interval determined by timer 6 and the value of the port data latch. CLKOEN (bit 3): This bit controls the output data of pin P05. It is disabled when P05 is in input mode. When P05 is in output mode: 0: Carries the value of the port data latch. 1: Carries the OR of the system clock output and the value of the port data latch. 3-3 Port 0 CKODV2 (bit 2): CKODV1 (bit 1): CKODV0 (bit 0): These bits define the frequency of the system clock to be placed at P05. 000: Frequency of source oscillator selected as system clock 001: 1/2 of frequency of source oscillator selected as system clock 010: 1/4 of frequency of source oscillator selected as system clock 011: 1/8 of frequency of source oscillator selected as system clock 100: 1/16 of frequency of source oscillator selected as system clock 101: 1/32 of frequency of source oscillator selected as system clock 110: 1/64 of frequency of source oscillator selected as system clock 111: Frequency of source oscillator selected as subclock <Notes on the use of the clock output function> Follow notes 1) to 3) given below when using the clock output function. Anomalies may be observed in the waveform of the port clock output if these notes are violated. 1) Do not change the frequency division setting of the clock output when CLKOEN (bit 3) is set to 1. Do not change the settings of CKODV2 to CKODV0 (bits 2 to 0). 2) Do not change the system clock selection when CLKOEN (bit 3) is set to 1. Do not change the settings of CLKB5 and CLKB4 (bits 5 and 4) of the OCR register. 3) CLKOEN will not go to 0 immediately even when the user executes an instruction that loads the P0FCR register with data that sets the state of CLKOEN bit from 1 to 0. CLKOEN is set to 0 at the end of the clock that is being output (on detection of the falling edge of the clock). Accordingly, when changing the clock divider setting or changing the system clock selection after setting CLKOEN to 0 with an instruction, be sure to read the CLKOEN value in advance and make sure that it is 0. 3.1.4 Options Two user options are available. 1) CMOS output (with a programmable pull-up resistor) 2) N-channel open drain output 3.1.5 HALT and HOLD Mode Operation When in HALT or HOLD mode, port 0 retains the state that is established when HALT or HOLD mode is entered. 3-4 LC870800 Chapter 3 3.2 Port 1 3.2.1 Overview Port 1 is an 8-bit I/O port with programmable pull-up resistors. It is made up of a data latch, a data direction register, a function control register, and a control circuit. The I/O direction is set by the data direction register in 1-bit units. Port 1 can also be used as a serial interface I/O port, a PWM output, an analog comparator/amplifier I/O, or a UART transmit/receive port by manipulating the function control register. As a user option, either CMOS output with a programmable pull-up resistor or N-channel open drain output with a programmable pull-up resistor can be selected as the output type in 1-bit units. 3.2.2 Functions 1) I/O port (8 bits: P10 to P17) • The port output data is controlled by the port 1 data latch (P1: FE44) and the I/O direction is controlled by the port 1 data direction register (P1DDR: FE45). • Each port bit is provided with a programmable pull-up resistor. 2) Multiplexed pin functions P17 is also used as the timer 1 PWMH/CMP2O output, P16 as the timer 1 PWML output, P15 to P13 as SIO1 I/O, P14 as the CMP1O output, and P12 to P10 as SIO0 I/O. Also P17 and P16 have UART1 I/O function. It is explained in the chapter on UART1. Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 P17 P16 P15 P14 P13 P12 P11 P10 FE44 0000 0000 R/W P1 FE45 0000 0000 R/W P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR FE46 0000 0000 R/W P1FCR P17FCR P16FCR P15FCR P14FCR P13FCR P12FCR P11FCR P10FCR FE47 000H HHH0 R/W P1TST FIX0 FIX0 MRCSFT - - - - FIX0 Bits 7, 6, and 0 of P1TST (FE47) are reserved for test purposes. They must always be set to 0. Bit 5 of P1TST (FE47) is used to control the high-speed RC oscillator. It is explained in the chapter on system clock generators. 3-5 Port 1 3.2.3 Related Registers 3.2.3.1 1) 2) Port 1 data latch (P1) This latch is an 8-bit register for controlling port 1 output data and pull-up resistors. When this register is read with an instruction, data at pins P10 to P17 is read in. If P1 (FE44) is manipulated using the NOT1, CLR1, SET1, DBZ, DBNZ, INC, or DEC instruction, the contents of the register are referenced instead of the data at the port pin. Port 1 data can always be read regardless of the I/O state of the port. 3) Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE44 0000 0000 R/W P1 P17 P16 P15 P14 P13 P12 P11 P10 3.2.3.2 Port 1 data direction register (P1DDR) 1) This register is an 8-bit register that controls the I/O direction of port 1 data in 1-bit units. Port P1n is placed in output mode when bit P1nDDR is set to 1 and in input mode when set to 0. 2) When bit P1nDDR is set to 0, and bit P1n of the port 1 data latch is set to 1, port P1n becomes an input with a pull-up resistor. Address Initial Value R/W Name FE45 0000 0000 R/W P1DDR Register Data P1n P1nDDR 0 0 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Port P1n State Output Internal Pull-up Resistor Input Enabled Open OFF 1 0 Enabled Internal pull-up resistor ON 0 1 Enabled Low OFF 1 1 Enabled High/open (CMOS/N-channel open drain) OFF 3-6 LC870800 Chapter 3 3.2.3.3 1) Port 1 function control register (P1FCR) This register is an 8-bit register that controls the multiplexed pin outputs of port 1. Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE46 0000 0000 R/W P1FCR P17FCR P16FCR P15FCR P14FCR P13FCR P12FCR P11FCR P10FCR n 7 CP2OUTEN CP1OUTEN CPAPCR2 CPAPCR1 (FEA1h), bit 5 (FEA0h), bit 5 0 0 0 1 1 1 6 5 4 3 2 1 0 0 0 0 1 1 1 P1nFCR P1n 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 － 0 1 0 1 － － 0 1 － 0 1 － 0 1 0 1 － － 0 1 － 0 1 － 0 1 － 0 １ P1n Pin Data in Output Mode (P1nDDR = 1) Value of port data latch (P17) Timer 1 PWMH PWMH inverted data of timer 1 Comparator 2 output Comparator 2 output inverted data Inhibited Value of port data latch (P16） Timer 1 PWML data Inverted data of timer 1 PWML Value of port data latch (P15） SIO1 clock output data High output Value of port data latch (P14) SIO1 output data High output Comparator 1 output High output Inhibited Value of port data latch (P13） SIO1 output data High output Value of port data latch (P12） SIO0 clock output data High output Value of port data latch (P11） SIO0 output data High output Value of port data latch (P10） SIO0 output data High output ・The high data output at the pins that are selected as N-channel open drain output by configuring options is represented by an open circuit. ・The comparator 1 and comparator 2 outputs are set low when the respective comparator is stopped. P17FCR (bit 7): P17 function control (timer 1 PWMH output control) This bit controls the output data at pin P17. When P17 is placed in output mode (P17DDR = 1), CP2OUTEN is set to 0, and P17FCR is set to 1, the EOR of the timer 1 PWMH output data and the port data latch is placed at pin P17. P16FCR (bit 6): P16 function control (timer 1 PWML output control) This bit controls the output data at pin P16. When P16 is placed in output mode (P16DDR = 1) and P16FCR is set to 1, the EOR of the timer 1 PWML output data and the port data latch is placed at pin P16. 3-7 Port 1 P15FCR (bit 5): P15 function control (SIO1 clock output control) This bit controls the output data at pin P15. When P15 is placed in output mode (P15DDR = 1) and P15FCR is set to 1, the OR of the SIO1 clock output data and the port data latch is placed at pin P15. P14FCR (bit 4): P14 function control (SIO1 data output control) This bit controls the output data at pin P14. When P14 is placed in output mode (P14DDR = 1), CP1OUTEN is set to 0, and P14FCR is set to 1, the OR of the SIO1 output data and the port data latch is placed at pin P14. When the SIO1 is active, SIO1 input data is read from P14 regardless of the I/O state of P14. P13FCR (bit 3): P13 function control (SIO1 data output control) This bit controls the output data at pin P13. When P13 is placed in output mode (P13DDR = 1) and P13FCR is set to 1, the OR of the SIO1 output data and the port data latch is placed at pin P13. P12FCR (bit 2): P12 function control (SIO0 clock output control) This bit controls the output data at pin P12. When P12 is placed in output mode (P12DDR = 1) and P12FCR is set to 1, the OR of the SIO0 clock output data and the port data latch is placed at pin P12. P11FCR (bit 1): P11 function control (SIO0 data output control) This bit controls the output data at pin P11. When P11 is placed in output mode (P11DDR = 1) and P11FCR is set to 1, the OR of the SIO0 output data and the port data latch is placed at pin P11. When the SIO0 is active, SIO0 input data is read from P11 regardless of the I/O state of P11. P10FCR (bit 0): P10 function control (SIO0 data output control) This bit controls the output data at pin P10. When P10 is placed in output mode (P10DDR = 1) and P10FCR is set to 1, the OR of the SIO0 output data and the port data latch is placed at pin P10. 3.2.4 Options Two user options are available. 1) CMOS output 2) N-channel open drain output 3.2.5 (with a programmable pull-up resistor) (with a programmable pull-up resistor) HALT and HOLD Mode Operation When in HALT or HOLD mode, port 1 retains the state that is established when HALT or HOLD mode is entered. 3-8 LC870800 Chapter 3 3.3 Port 2 3.3.1 Overview Port 2 is a 2-bit I/O port with programmable pull-up resistors. It is made up of a data latch, a data direction register, and a control circuit. The I/O direction is set by the data direction register in 1-bit units. Port 2 can also serve as an input port for external interrupts. It can also be used as an input port for the timer 1 count clock input, timer 0 capture signal input, and HOLD mode release signal input. As a user option, either CMOS output with a programmable pull-up resistor or N-channel open drain output with a programmable pull-up resistor can be selected as the output type in 1-bit units. 3.3.2 Functions 1) Input/output port (2 bits: P20 and P21) • The port output data is controlled by the port 2 data latch (P2: FE48) and the I/O direction is controlled by the port 2 data direction register (P2DDR: FE49). • Each port bit is provided with a programmable pull-up resistor. 2) Interrupt input pin function The port (INT4) selected from P20 and P21 is provided with a pin interrupt function. This function detects a low edge, a high edge, or both edges and sets the interrupt flag. This port can also serve as timer 1 count clock input or timer 0 capture signal input. 3) Hold mode release function • When the interrupt flag and interrupt enable flag are set by INT4, a HOLD mode release signal is generated, releasing HOLD mode. The CPU then enters HALT mode (main oscillation by CR). When the interrupt is accepted, the CPU switches from HALT mode to normal operating mode. • When a signal change that sets the INT4 interrupt flag is input in HOLD mode, that interrupt flag is set. In this case, HOLD mode is released if the corresponding interrupt enable flag is set. The interrupt flag, however, cannot be set by a rising edge occurring when INT4 data that is established when HOLD mode is entered is in the high state, or by a falling edge occurring when INT4 data that is established when HOLD mode is entered is in the low state. Consequently, to release HOLD mode with INT4, it is recommended that INT4 be used in the double edge interrupt mode. 4) Multiplexed pin function • Pin P21 is also used as the base timer BUZ output. It is explained in “3.9 Base Timer.” Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE48 HHHH HH00 R/W P2 - - - - - - P21 P20 FE49 HHHH HH00 R/W P2DDR - - - - - - P21DDR P20DDR FE4A HHHH 0000 R/W I45CR - - - - INT4IF INT4IE FE4B HHHH 0000 R/W I45SL - - - - I4SL1 I4SL0 3-9 INT4HEG INT4LEG I4SL3 I4SL2 Port 2 3.3.3 Related Registers 3.3.3.1 1) 2) Port 2 data latch (P2) This latch is a 2-bit register for controlling port 2 output data and pull-up resistors. When this register is read with an instruction, data at pins P20 and P21 is read in. If P2 (FE48) is manipulated using the NOT1, CLR1, SET1, DBZ, DBNZ, INC, or DEC instruction, the contents of the register are referenced instead of the data at the port pin. Port 2 data can always be read regardless of the I/O state of the port. 3) Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE48 HHHH HH00 R/W P2 - - - - - - P21 P20 3.3.3.2 1) Port 2 data direction register (P2DDR) This register is a 2-bit register that controls the I/O direction of the port 2 data in 1-bit units. Port P2n is placed in output mode when bit P2nDDR is set to 1 and in input mode when set to 0. 2) When bit P2nDDR is set to 0 and bit P2n of the port 2 data latch is set to 1, port P2n becomes an input with a pull-up resistor Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 FE49 HHHH HH00 R/W P2DDR - - - - - - Register Data P2n P2nDDR 0 0 Port P2n State Output BIT1 BIT0 P21DDR P20DDR Internal Pull-up Resistor Input Enabled Open OFF 1 0 Enabled Internal pull-up resistor ON 0 1 Enabled Low OFF 1 1 Enabled High/open (CMOS/N-channel open drain) OFF 3.3.3.3 1) External interrupt 4 control register (I45CR) This register is a 4-bit register for controlling external interrupt 4. Address Initial Value R/W FE4A HHHH 0000 R/W Name BIT7 BIT6 BIT5 BIT4 I45CR - - - - BIT3 BIT2 INT4HEG INT4LEG BIT1 BIT0 INT4IF INT4IE INT4HEG (bit 3): INT4 rising edge detection control INT4LEG (bit 2): INT4 falling edge detection control INT4HEG 0 INT4LEG 0 INT4 Interrupt Conditions (Pin Data) No edge detected 0 1 Falling edge detected 1 0 Rising edge detected 1 1 Both edges detected INT4IF (bit 1): INT4 interrupt source flag This bit is set when the conditions specified by INT4HEG and INT4LEG are satisfied. When this bit and the INT4 interrupt request enable bit (INT4IE) are set to 1, a HOLD mode release signal and an interrupt request to vector address 0013H are generated. 3-10 LC870800 Chapter 3 The interrupt flag, however, cannot be set by a rising edge occurring when INT4 data that is established when HOLD mode is entered is in the high state, or by a falling edge occurring when INT4 data that is established when HOLD mode is entered is in the low state. Consequently, to release HOLD mode with INT4, it is recommended that INT4 be used in the double edge interrupt mode. This bit must be cleared with an instruction as it is not cleared automatically. INT4IE (bit 0): INT4 interrupt request enable When this bit and INT4IF are set to 1, a HOLD mode release signal and an interrupt request to vector address 0013H are generated. 3.3.3.4 1) External interrupt 4 pin select register (I45SL) This register is a 4-bit register used to select pins for the external interrupt 4. Address Initial Value R/W Name BIT7 BIT6 BIT5 FE4B HHHH 0000 R/W I45SL - - - BIT4 BIT3 BIT2 BIT1 BIT0 I4SL3 I4SL2 I4SL1 I4SL0 I4SL3 (bit 3): INT4 pin select I4SL2 (bit 2): INT4 pin select I4SL3 0 I4SL2 0 Pin Assigned to INT4 Port pin P20 0 1 Port pin P21 1 0 Inhibited 1 1 Inhibited I4SL1 (bit 1): INT4 pin function select I4SL0 (bit 0): INT4 pin function select When the data change specified in the external interrupt 4 control register (I45CR) is given to the pin that is assigned to INT4, timer 1 count clock input and timer 0 capture signal are generated. I4SL1 0 I4SL0 0 Function Other Than INT4 Interrupt None 0 1 Timer 1 count clock input 1 0 Timer 0L capture signal input 1 1 Timer 0H capture signal input Notes: 1) When timer 0L capture signal input or timer 0H capture signal input is specified for INT4 together with in port 7, the signal from port 7 is ignored. 2) When INT4 is specified in duplicate for timer 1 count clock input, timer 0L capture signal input, or timer 0H capture signal input, both interrupts are accepted. If INT4 events occur at the same time, however, only one event is recognized. 3) When timer 1 count clock input is specified for INT4, timer 1L functions as an event counter. When timer 1 count clock input is not specified for INT4, the timer 1L counter counts on every 2Tcyc. 3-11 Port 2 3.3.4 Options Two user options are available. 1) CMOS output 2) N-channel open drain output 3.3.5 (with a programmable pull-up resistor) (with a programmable pull-up resistor) HALT and Hold Mode Operation When in HALT or HOLD mode, port 2 retains the state that is established when HALT or HOLD mode is entered. 3-12 LC870800 Chapter 3 3.4 Port 3 3.4.1 Overview Port 3 is a 6-bit I/O port with programmable pull-up resistors. It is made up of a data latch, a data direction register, and a control circuit. The I/O direction is set by the data direction register in 1-bit units. As a user option, either CMOS output with a programmable pull-up resistor or N-channel open drain output with a programmable pull-up resistor can be selected as the output type in 1-bit units. 3.4.2 Functions 1) Input/output port (6 bits: P30 to P35) • The port output data is controlled by the port 3 data latch (P3: FE4C) and the I/O direction is controlled by the port 3 data direction register (P3DDR: FE4D). • Each port bit is provided with a programmable pull-up resistor. 2) Multiplexed pin function • Pins P30 to P35 are also used as the MCPWM output. It is explained in “3.14 Motor Control PWM (MCPWM).” Address Initial Value R/W Name BIT7 BIT6 FE4C HH00 0000 R/W P3 - - FE4D HH00 0000 R/W P3DDR - - BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 P35 P34 P33 P32 P31 P30 P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR 3.4.3 Related Registers 3.4.3.1 1) 2) Port 3 data latch (P3) This latch is a 6-bit register for controlling the port 3 output data and its pull-up resistors. When this register is read with an instruction, the data at pins P30 to P35 is read in. If P3 (FE4C) is manipulated using the NOT1, CLR1, SET1, DBZ, DBNZ, INC or DEC instruction, the contents of the register is referenced instead of the data at the pins. Port 3 data can always be read regardless of the I/O state of the port. 3) Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE4C HH00 0000 R/W P3 - - P35 P34 P33 P32 P31 P30 3-13 Port 3 3.4.3.2 Port 3 data direction register (P3DDR) 1) This register is a 6-bit register for controlling the I/O direction of the port 3 data in 1-bit units. Port P3n is placed in output mode when bit P3nDDR is set to 1 and in input mode when set to 0. 2) When bit P3nDDR is set to 0 and bit P3n of port 3 data latch is set to 1, port P3n becomes an input with a pull-up resistor. Address Initial Value R/W Name BIT7 BIT6 FE4D HH00 0000 R/W P3DDR - - Register Data P3n P3nDDR 0 0 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Port P3n State Output Internal Pull-up Resistor Input Enabled Open OFF 1 0 Enabled Internal pull-up resistor ON 0 1 Enabled Low OFF 1 1 Enabled High/open (CMOS/N-channel open drain) OFF 3.4.4 Options Two user options are available. 1) CMOS output 2) N-channel open drain output 3.4.5 (with a programmable pull-up resistor) (with a programmable pull-up resistor) HALT and HOLD Mode Operation When in HALT or HOLD mode, port 3 retains the state that is established when HALT or HOLD mode is entered. 3-14 LC870800 Chapter 3 3.5 Port 7 3.5.1 Overview Port 7 is a 4-bit I/O port with programmable pull-up resistors. It is made up of a data control latch and a control circuit. The I/O direction is set by data direction register in 1-bit units. Port 7 can be used as an input port for external interrupts. It can also be used as an input port for the timer 0 count clock input, capture signal input, and HOLD mode release signal input. There is no user option for this port. 3.5.2 Functions 1) Input/output port (4 bits: P70 to P73) • The port output data is controlled by the low-order 4 bits of the port 7 control register (P7: FE5C) and the I/O direction is controlled by the high-order 4 bits. • P70 to P73 are CMOS output port. • Each port bit is provided with a programmable pull-up resistor. 2) Interrupt input pin function • P70 and P71 are assigned to INT0 and INT1, respectively, and are used to detect a low or high level, or a low or high edge and to set the interrupt flag. • P72 and P73 are assigned to INT2 and INT3, respectively, and are used to detect a low or high edge, or both edges and to set the interrupt flag. 3) Timer 0 count input function A count signal is sent to timer 0 each time a signal change that sets the interrupt flag is supplied to a port selected from P72 and P73. 4) Timer 0L capture input function A timer 0L capture signal is generated each time a signal change that sets the interrupt flag is supplied to a port selected from P70 and P72. When a selected level of signal is input to P70 that is specified for level-triggered interrupts, a timer 0L capture signal is generated at 1-cycle intervals for the duration of the input signal. 5) Timer 0H capture input function A timer 0H capture signal is generated each time a signal change that sets the interrupt flag is supplied to a port selected from P71 and P73. When a selected level of signal is input to P71 that is specified for level-triggered interrupts, a timer 0H capture signal is generated at 1-cycle intervals for the duration of the input signal. 3-15 Port 7 6) HOLD mode release function • When the interrupt flag and interrupt enable flag are set by INT0, INT1, or INT2, a HOLD mode release signal is generated, releasing HOLD mode. The CPU then enters HALT mode (main oscillation by CR). When the interrupt is accepted, the CPU switches from HALT mode to normal operating mode. • When a signal change that sets the interrupt flag is input to P70 or P71 in HOLD mode, the interrupt flag is set. In this case, HOLD mode is released if the corresponding interrupt enable flag is set. • When a signal change that sets the interrupt flag is input to P72 in HOLD mode, the interrupt flag is set. In this case, HOLD mode is released if the corresponding interrupt enable flag is set. The interrupt flag, however, cannot be set by a rising edge occurring when P72 data that is established when HOLD mode is entered is in the high state, or by a falling edge occurring when P72 data that is established when HOLD mode is entered is in the low state. Consequently, to release HOLD mode with P72, it is recommended that P72 be used in the double edge interrupt mode. Input P70 P71 P72 Output With programmable pull-up resistor CMOS Interrupt Input Timer 0 Signal Detection Count Input L level, H level, L edge, H edge - Capture Input Timer 0L Hold Mode Release Enabled (Note) Timer 0H Enabled (Note) L edge, H edge, Available Timer 0L both edges P73 Available Timer 0H Note: P70 and P71 HOLD mode release is available only when level detection is set. Address Initial Value R/W Name FE5C 0000 0000 R/W FE5D 0000 0000 R/W I01CR BIT8 P7 FE5E 0000 0000 R/W I23CR FE5F 00000 0000 R/W ISL BIT7 BIT6 BIT5 BIT4 BIT3 Enabled - BIT2 BIT1 - P73DDR P72DDR P71DDR P70DDR P73DT P72DT - INT1LH INT0LH INT0LV - INT1LV INT3HEG INT3LEG BUZDIV ST0HCP ST0LCP BIT0 P71DT P70DT INT1IF INT1IE INT0IF INT0IE INT3IF INT3IE INT2HEG INT2LEG INT2IF INT2IE BTIMC1 BTIMC0 BUZON NFSEL NFON ST0IN 3.5.3 Related Registers 3.5.3.1 1) 2) Port 7 control register (P7) This register is an 8-bit register for controlling the I/O of port 7 data and pull-up resistors. When this register is read with an instruction, data at pins P70 to P73 is read into bits 0 to 3. Bits 4 to 7 are loaded with bits 4 to 7 of register P7. If P7 (FE5C) is manipulated using the NOT1, CLR1, SET1, DBZ, DBNZ, INC, or DEC instruction, the contents of the register are referenced as bits 0 to 3 instead of the data at the port pin. Port 7 data can always be read regardless of the I/O state of the port. 3) Address Initial Value R/W Name FE5C 0000 0000 R/W P7 Register Data P7n P7nDDR 0 0 BIT7 BIT6 BIT5 BIT4 P73DDR P72DDR P71DDR P70DDR Input Enabled Port P7n State Output Open BIT3 BIT2 BIT1 BIT0 P73DT P72DT P71DT P70DT Internal Pull-up Resistor OFF 1 0 Enabled Internal pull-up resistor ON 0 1 Enabled CMOS-low OFF 1 1 Enabled CMOS-high ON 3-16 LC870800 Chapter 3 P73DDR (bit 7): P73 I/O control A 1 or 0 in this bit controls the output (CMOS) or input of pin P73. P72DDR (bit 6): P72 I/O control A 1 or 0 in this bit controls the output (CMOS) or input of pin P72. P71DDR (bit 5): P71 I/O control A 1 or 0 in this bit controls the output (CMOS) or input of pin P71. P70DDR (bit 4): P70 I/O control A 1 or 0 in this bit controls the output (CMOS) or input of pin P70. P73DT (bit 3): P73 data The value of this bit is output from pin P73 when P73DDR is set to 1. A 1 or 0 in this bit turns the internal pull-up resistor on or off for pin P73. P72DT (bit 2): P72 data The value of this bit is output from pin P72 when P72DDR is set to 1. A 1 or 0 in this bit turns the internal pull-up resistor on or off for pin P72. P71DT (bit 1): P71 data The value of this bit is output from pin P71 when P71DDR is set to 1. A 1 or 0 in this bit turns the internal pull-up resistor on or off for pin P71. P70DT (bit 0): P70 data The value of this bit is output from pin P70 when P70DDR is set to 1. A 1 or 0 in this bit turns the internal pull-up resistor on or off for pin P70. 3.5.3.2 1) External interrupt 0/1 control register (I01CR) This register is an 8-bit register for controlling external interrupts 0 and 1. Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE5D 0000 0000 R/W I01CR INT1LH INT1LV INT1IF INT1IE INT0LH INT0LV INT0IF INT0IE INT1LH (bit 7): INT1 detection polarity select INT1LV (bit 6): INT1 detection level/edge select INT1LH 0 INT1LV 0 INT1 Interrupt Conditions (P71 Pin Data) Falling edge detected 0 1 Low level detected 1 0 Rising edge detected 1 1 High level detected 3-17 Port 7 INT1IF (bit 5): INT1 interrupt source flag This bit is set when the conditions specified by INT1LH and INT1LV are satisfied. When this bit and the INT1 interrupt request enable bit (INT1IE) are set to 1, a HOLD mode release signal and an interrupt request to vector address 000BH are generated. This bit must be cleared with an instruction as it is not cleared automatically. INT1IE (bit 4): INT1 interrupt request enable When this bit and INT1IF are set to 1, a HOLD mode release signal and an interrupt request to vector address 000BH are generated. INT0LH (bit 3): INT0 detection polarity select INT0LV (bit 2): INT0 detection level/edge select INT0LH 0 INT0LV 0 INT0 Interrupt Conditions (P70 Pin Data) Falling edge detected 0 1 Low level detected 1 0 Rising edge detected 1 1 High level detected INT0IF (bit 1): INT0 interrupt source flag This bit is set when the conditions specified by INT0LH and INT0LV are satisfied. When this bit and the INT0 interrupt request enable bit (INT0IE) are set to 1, a HOLD mode release signal and an interrupt request to vector address 0003H are generated. This bit must be cleared with an instruction as it is not cleared automatically. INT0IE (bit 0): INT0 interrupt request enable When this bit and INT0IF are set to 1, a HOLD mode release signal and an interrupt request to vector address 0003H are generated. 3.5.3.3 1) External interrupt 2/3 control register (I23CR) This register is an 8 bit register for controlling external interrupts 2 and 3. Address Initial Value FE5E 0000 0000 R/W Name BIT7 BIT6 R/W I23CR INT3HEG INT3LEG BIT5 BIT4 INT3IF INT3IE BIT3 BIT2 INT2HEG INT2LEG BIT1 BIT0 INT2IF INT2IE INT3HEG (bit 7): INT3 rising edge detection control INT3LEG (bit 6): INT3 falling edge detection control INT3HEG 0 INT3LEG 0 INT3 Interrupt Conditions (P73 Pin Data) No edge detected 0 1 Falling edge detected 1 0 Rising edge detected 1 1 Both edges detected INT3IF (bit 5): INT3 interrupt source flag This bit is set when the conditions specified by INT3HEG and INT3LEG are satisfied. When this bit and the INT3 interrupt request enable bit (INT3IE) are set to 1, an interrupt request to vector address 001BH is generated. This bit must be cleared with an instruction as it is not cleared automatically. 3-18 LC870800 Chapter 3 INT3IE (bit 4): INT3 interrupt request enable When this bit and INT3IF are set to 1, an interrupt request to vector address 001BH is generated. INT2HEG (bit 3): INT2 rising edge detection control INT2LEG (bit 2): INT2 falling edge detection control INT2HEG 0 INT2LEG 0 INT2 Interrupt Conditions (P72 Pin Data) No edge detected 0 1 Falling edge detected 1 0 Rising edge detected 1 1 Both edges detected INT2IF (bit 1): INT2 interrupt source flag This bit is set when the conditions specified by INT2HEG and INT2LEG are satisfied. When this bit and the INT2 interrupt request enable bit (INT2IE) are set to 1, a HOLD mode release signal and an interrupt request to vector address 0013H are generated. The interrupt flag, however, cannot be set by a rising edge occurring when P72 data that is established when HOLD mode is entered is in the high state, or by a falling edge occurring when P72 data that is established when HOLD mode is entered is in the low state. Consequently, to release HOLD mode with P72, it is recommended that P72 be used in the double edge interrupt mode. This bit must be cleared with an instruction as it is not cleared automatically. INT2IE (bit 0): INT2 interrupt request enable When this bit and INT2IF are set to 1, a HOLD mode release signal and an interrupt request to vector address 0013H are generated. 3.5.3.4 1) Input signal select register (ISL) This register is a 9-bit register for controlling the timer 0 input, noise filter time constant, buzzer output, and base timer clock. Address Initial Value R/W Name FE5F 00000 0000 R/W ISL BIT8 BIT7 BUZDIV ST0HCP BIT6 ST0LCP BIT5 BIT4 BTIMC1 BTIMC0 BIT3 BIT2 BIT1 BIT0 BUZON NFSEL NFON ST0IN BUZDIV (bit 8): Buzzer output frequency division ratio select This bit selects the frequency division ratio for the buzzer output. When this bit is set to 1, the signal obtained by dividing the base timer clock by 256 is output. When this bit is set to 0, the signal obtained by dividing the base timer clock by 16 is output. ST0HCP (bit 7): Timer 0H capture signal input port select This bit selects the timer 0H capture signal input port. When this bit is set to 1, a timer 0H capture signal is generated when an input that satisfies the INT1 interrupt detection conditions is supplied to P71. If the INT1 interrupt detection mode is set to "level detection," capture signals are generated at the interval of 1 Tcyc as long as the detection level is present at P71. When this bit is set to 0, a timer 0H capture signal is generated when an input that satisfies the INT3 interrupt detection conditions is supplied to P73. ST0LCP (bit 6): Timer 0L capture signal input port select This bit selects the timer 0L capture signal input port. When this bit is set to 1, a timer 0L capture signal is generated when an input that satisfies the INT0 interrupt detection conditions is supplied to P70. If the INT0 interrupt detection mode is set to "level detection," capture signals are generated at the interval of 1 Tcyc as long as the detection level is present at P70. When this bit is set to 0, a timer 0L capture signal is generated when an input that satisfies the INT2 interrupt detection conditions is supplied to P72. 3-19 Port 7 BTIMC1 (bit 5): Base timer clock select BTIMC0 (bit 4): Base timer clock select BTIMC1 0 BTIMC0 0 Base Timer Input Clock Subclock 0 1 Cycle clock 1 0 Subclock 1 1 Timer/counter 0 prescaler output BUZON (bit 3): Buzzer output select This bit enables the buzzer output (fBST/16 or fBST/256). When this bit is set to 1, a signal that is obtained by dividing the base timer clock by 16 is sent to port P21 as buzzer output. When this bit is set to 0, the buzzer output is fixed at the high level. NFSEL (bit 2): Noise filter time constant select NFON (bit 1): Noise filter time constant select NFSEL 0 NFON 0 Noise Filter Time Constant 1 Tcyc 0 1 128 Tcyc 1 0 1 Tcyc 1 1 32 Tcyc ST0IN (bit 0): Timer 0 count clock input port select This bit selects the timer 0 count clock signal input port. When this bit is set to 1, a timer 0 count clock is generated when an input that satisfies the INT3 interrupt detection conditions is supplied to P73. When this bit is set to 0, a timer 0 count clock is generated when an input that satisfies the INT2 interrupt detection conditions is supplied to P72. Note: When timer 0L capture signal input or timer 0H capture signal input is specified for INT4 together with in port 7, the signal from port 7 is ignored. 3.5.4 Options There is no user option for port 7. 3.5.5 HALT and HOLD Mode Operation P70 to P73 retain the state that is established when HALT or HOLD mode is entered. 3-20 LC870800 Chapter 3 3.6 Timer / Counter 0 (T0) 3.6.1 Overview The timer/counter 0 (T0) incorporated in this series of microcontrollers is a 16-bit timer/counter that provides the following four functions: 1) Mode 0: 2) Mode 1: 3) Mode 2: 4) Mode 3: 3.6.2 8-bit programmable timer with a programmable prescaler (with an 8-bit capture register) 2 channels 8-bit programmable timer with a programmable prescaler (with an 8-bit capture register) + 8-bit programmable counter (with an 8-bit capture register) 16-bit programmable timer with a programmable prescaler (with a 16-bit capture register) 16-bit programmable counter (with a 16-bit capture register) Functions 1) Mode 0: 8-bit programmable timer with a programmable prescaler (with an 8-bit capture register) 2 channels • Two independent 8-bit programmable timers (T0L and T0H) run on the clock (with a period of 1 to 256 Tcyc) from an 8-bit programmable prescaler. • The contents of T0L are captured into the capture register T0CAL on external input detection signals from P70/INT0/T0LCP, P72/INT2/T0IN, P20, and P21 timer 0L capture input pins. • The contents of T0H are captured into the capture register T0CAH on external input detection signals from P71/INT1/T0HCP, P73/INT3/T0IN, P20, and P21 timer 0H capture input pins. T0L period = (T0LR + 1) (T0PRR + 1) Tcyc T0H period = (T0HR + 1) (T0PRR + 1) Tcyc Tcyc = Period of cycle clock 2) Mode 1: • • • • 8-bit programmable timer with a programmable prescaler (with an 8-bit capture register) + 8-bit programmable counter (with an 8-bit capture register) T0L serves as an 8-bit programmable counter that counts the number of external input detection signals from pins P72/INT2/T0IN and P73/INT3/T0IN. T0H serves as an 8-bit programmable timer that runs on the clock (with a period of 1 to 256 Tcyc) from an 8-bit programmable prescaler. The contents of T0L are captured into the capture register T0CAL on external input detection signals from P70/INT0/T0LCP, P72/INT2/T0IN, P20, and P21 timer 0L capture input pins. The contents of T0H are captured into the capture register T0CAH on external input detection signals from P71/INT1/T0HCP, P73/INT3/T0IN, P20, and P21 timer 0H capture input pins. T0L period = (T0LR + 1) T0H period = (T0HR + 1) (T0PRR +1) Tcyc 3-21 T0 3) Mode 2: 16-bit programmable timer with a programmable prescaler (with a 16-bit capture register) • Timer/counter 0 serves as a 16-bit programmable timer that runs on the clock (with a period of 1 to 256 Tcyc) from an 8-bit programmable prescaler. • The contents of T0L and T0H are captured into the capture registers T0CAL and T0CAH at the same time on external input detection signals from P71/INT1/T0HCP, P73/INT3/T0IN, P20, and P21 timer 0H capture input pins. T0 period = ([T0HR, T0LR] + 1) (T0PRR +1) Tcyc 16 bits 4) Mode 3: 16-bit programmable counter (with a 16-bit capture register) • Timer/counter 0 serves as a 16-bit programmable counter that counts the number of external input detection signals from pins P72/INT2/T0IN and P73/INT3/T0IN. • The contents of T0L and T0H are captured into the capture registers T0CAL and T0CAH at the same time on external input detection signals from P71/INT1/T0HCP, P73/INT3/T0IN, P20, and P21 timer 0H capture input pins. T0 period = [T0HR,T0LR] + 1 16 bits 5) Interrupt generation T0L or T0H interrupt request is generated at the counter interval for timer/counter T0L or T0H if the interrupt request enable bit is set. 6) It is necessary to manipulate the following special function registers to control timer/counter 0 (T0). • T0CNT, T0PRR, T0L, T0H, T0LR, T0HR • P7, TSL, ISL, I01CR, I23CR • P2, P2DDR, I45CR, I45SL Address Initial Value R/W Name FE10 0000 0000 R/W T0CNT T0HRUN T0LRUN T0LONG T0LEXT T0HCMP BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 T0HIE T0LCMP T0LIE FE11 0000 0000 R/W T0PRR T0PRR7 T0PRR6 T0PRR5 T0PRR4 FE12 0000 0000 R T0L T0L7 T0L6 T0L5 T0L4 T0PRR3 T0PRR2 T0PRR1 T0PRR0 T0L3 T0L2 T0L1 FE13 0000 0000 R T0H T0H7 T0H6 T0H5 T0H4 T0L0 T0H3 T0H2 T0H1 T0H0 FE14 0000 0000 R/W T0LR T0LR7 T0LR6 T0LR5 T0LR4 T0LR3 T0LR2 T0LR1 T0LR0 FE15 0000 0000 R/W T0HR T0HR7 T0HR6 T0HR5 T0HR4 T0HR3 T0HR2 T0HR1 T0HR0 FE16 XXXX XXXX R T0CAL T0CAL7 T0CAL6 T0CAL5 T0CAL4 T0CAL3 T0CAL2 T0CAL1 T0CAL0 FE17 XXXX XXXX R T0CAH T0CAH7 T0CAH6 T0CAH5 T0CAH4 T0CAH3 T0CAH2 T0CAH1 T0CAH0 3.6.3 Circuit Configuration 3.6.3.1 1) Timer/counter 0 control register (T0CNT) (8-bit register) This register controls the operation and interrupts of T0L and T0H. 3-22 LC870800 Chapter 3 3.6.3.2 1) Programmable prescaler match register (T0PRR) (8-bit register) This register stores the match data for the programmable prescaler. 3.6.3.3 1) 2) 3) Programmable prescaler (8-bit counter) Start/stop: This register runs in modes other than HOLD mode. Count clock: Cycle clock (period = 1 Tcyc). Match signal: A match signal is generated when the count value matches the value of register T0PRR (period: 1 to 256 Tcyc) Reset: The counter starts counting from 0 when a match signal occurs or when data is written into T0PRR. 4) 3.6.3.4 1) 2) 3) 4) 3.6.3.5 1) 2) 3) 4) 3.6.3.6 1) 2) 3.6.3.7 1) 2) Timer/counter 0 low byte (T0L) (8-bit counter) Start/stop: Stop/start is controlled by the 0/1 value of T0LRUN (timer 0 control register, bit 6). Count clock: Either a prescaler match signal or an external signal must be selected through the 0/1 value of T0LEXT (timer 0 control register, bit 4). Match signal: A match signal is generated when the count value matches the value of the match buffer register (16 bits of data needs to match in the 16-bit mode). Reset: This counter is reset when it stops operation or a match signal is generated. Timer/counter 0 high byte (T0H) (8-bit counter) Start/stop: Stop/start is controlled by the 0/1 value of T0HRUN (timer 0 control register, bit 7). Count clock: Either prescaler match signal or T0L match signal must be selected through the 0/1 value of T0LONG (timer 0 control register, bit 5). Match signal: A match signal is generated when the count value matches the value of the match buffer register (16 bits of data needs to match in the 16-bit mode). Reset: When the counter stops operation or a match signal is generated. Timer/counter 0 match data register low byte (T0LR) (8-bit register with a match buffer register) This register is used to store the match data for T0L. It has an 8-bit match buffer register. A match signal is generated when the value of this match buffer register matches the value of the low-order byte of timer/counter 0 (16 bits of data needs to match in the 16-bit mode). The match buffer register is updated as follows: • When it is inactive (T0LRUN=0), the match register matches T0LR. • When it is active (T0LRUN=1), the match buffer register is loaded with the contents of T0LR when a match signal is generated. Timer/counter 0 match data register high byte (T0HR) (8-bit register with a match buffer register) This register is used to store the match data for T0H. It has an 8-bit match buffer register. A match signal is generated when the value of this match buffer register matches the value of the high-order byte of timer/counter 0 (16 bits of data needs to match in the 16-bit mode). The match buffer register is updated as follows: • When it is inactive (T0HRUN=0), the match register matches T0HR. • When it is active (T0HRUN=1), the match buffer register is loaded with the contents of T0HR when a match signal is generated. 3-23 T0 3.6.3.8 1) 2) 3.6.3.9 1) 2) Timer/counter 0 capture register low byte (T0CAL) (8-bit register) Capture clock: External input detection signals from pins P70/INT0/T0LCP, P72/INT2/T0IN, P20, and P21 timer 0L capture input pins when T0LONG (timer 0 control register, bit 5) is set to 0. External input detection signals from pins P71/INT1/T0HCP, P73/INT3/T0IN, P20, and P21 timer 0H capture input pins when T0LONG (timer 0 control register, bit 5) is set to 1. Capture data: Contents of timer/counter 0 low byte (T0L). Timer/counter 0 capture register high byte (T0CAH) (8-bit register) Capture clock: External input detection signals from pins P71/INT1/T0HCP, P73/INT3/T0IN, P20, and P21 timer 0H capture input pins. Capture data: Contents of timer/counter 0 high byte (T0H) Table 3.6.1 Timer 0 (T0H, T0L) Count Clocks Mode T0LONG T0LEXT T0H Count Clock T0L Count Clock [T0H, T0L] Count Clock 0 0 0 T0PRR match signal T0PRR match signal – 1 0 1 T0PRR match signal External signal – 2 1 0 – – T0PRR match signal 3 1 1 – – External signal 3-24 LC870800 Chapter 3 Clock Tcyc Clear Prescaler Match Capture trigger Comparator Registers I01CR (FE5Dh), I23CR (FE5Eh), and ISL (FE5Fh), T0PRR need setting T0CAL T0CAH Capture Clock Capture Clear Clock T0L Match Comparator Clear Match Comparator Match buffer register Reload T0HCMP flag set Match buffer register T0LCMP flag set Reload T0LR T0HR 8-bit programmable timer with programmable prescaler Figure 3.6.1 T0H 8-bit programmable timer with programmable prescaler Mode 0 Block Diagram (T0LONG = 0 , T0LEXT = 0) Clock Tcyc Capture trigger Prescaler Registers I01CR (FE5Dh), Comparator I23CR(FE5Eh), and ISL (FE5Fh) need setting Clear Match T0PRR T0CAL External input Clock T0CAH Capture Clock Clear T0L Set in register ISL(FE5Fh) Match Comparator Match buffer register T0LCMP Relaod flag set T0LR Match buffer register Relaod ﾞ T0HCMP flag set T0HR 8-bit programmable timer with programmable prescaler 8-bit programmable counter Figure 3.6.2 Clear T0H Match Comparator Capture Mode 1 Block Diagram (T0LONG = 0, T0LEXT = 1) 3-25 T0 Clock Clear Prescaler Tcyc Match Comparator T0PRR Capture trigger T0CAH T0CAL Registers I01CR (FE5Dh), Capture Clock T0H T0L Clear I23CR (FE5Eh), and ISL (FE5Fh) need setting Match Comparator Match buffer register Reload T0HR T0LCMP T0HCMP flag set T0LR 16-bit programmable timer with programmable prescaler Figure 3.6.3 Mode 2 Block Diagram (T0LONG = 1, T0LEXT = 0) Capture trigger T0CAH T0CAL Register I01CR (FE5Dh), External input Capture Clock Clear T0H T0L Set in register ISL(FE5Fh) I23CR (FE5Eh), and ISL (FE5Fh) need setting Match Comparator Match buffer register T0HR T0LCMP T0HCMP Relaod flag set T0LR 16-bit programmable counter Figure 3.6.4 Mode 3 Block Diagram (T0LONG = 1, T0LEXT = 1) 3-26 LC870800 Chapter 3 3.6.4 Related Registers 3.6.4.1 1) Timer/counter 0 control register (T0CNT) This register is an 8-bit register that controls the operation and interrupts of T0L and T0H. Address Initial Value R/W Name FE10 0000 0000 R/W T0CNT BIT7 BIT6 BIT5 BIT4 BIT3 T0HRUN T0LRUN T0LONG T0LEXT T0HCMP BIT2 BIT1 BIT0 T0HIE T0LCMP T0LIE T0HRUN (bit 7): T0H count control When this bit is set to 0, timer/counter 0 high byte (T0H) stops on a count value of 0. The match buffer register of T0H has the same value as T0HR. When this bit is set to 1, timer/counter 0 high byte (T0H) performs the required counting operation. The match buffer register of T0H is loaded with the contents of T0HR when a match signal is generated. T0LRUN (bit 6): T0L count control When this bit is set to 0, timer/counter 0 low byte (T0L) stops on a count value of 0. The match buffer register of T0L has the same value as T0LR. When this bit is set to 1, timer/counter 0 low byte (T0L) performs the required counting operation. The match buffer register of T0L is loaded with the contents of T0LR when a match signal is generated. T0LONG (bit 5): Timer/counter 0 bit length select When this bit is set to 0, timer/counter 0 high- and low-order bytes function as independent 8-bit timers/counters. When this bit is set to 1, timer/counter 0 functions as a 16-bit timer/counter. A match signal is generated when the count value of the 16-bit counter comprising T0H and T0L matches the contents of the match buffer register of T0H and T0L. T0LEXT (bit 4): T0L input clock select When this bit is set to 0, the count clock for T0L is the match signal for the prescaler. When this bit is set to 1, the count clock for T0L is an external input signal. T0HCMP (bit 3): T0H match flag This bit is set when the value of T0H matches the value of the match buffer register for T0H and a match signal is generated while T0H is running (T0HRUN=1). Its state does not change if no match signal is generated. Consequently, this flag must be cleared with an instruction. In the 16-bit mode (T0LONG=1), a match needs to occur in all 16 bits of data for a match signal to occur. T0HIE (bit 2): T0H interrupt request enable control When this bit and T0HCMP are set to 1, an interrupt request to vector address 0023H is generated. 3-27 T0 T0LCMP (bit 1): T0L match flag This bit is set when the value of T0L matches the value of the match buffer register for T0L and a match signal is generated while T0L is running (T0LRUN=1). Its state does not change if no match signal is generated. Consequently, this flag must be cleared with an instruction. In the 16-bit mode (T0LONG=1), a match needs to occur in all 16 bits of data for a match signal to occur. T0LIE (bit 0): T0L interrupt request enable control When this bit and T0LCMP are set to 1, an interrupt request to vector address 0013H is generated. Notes: • T0HCMP and T0LCMP must be cleared to 0 with an instruction. • When the 16-bit mode is to be used, T0LRUN and T0HRUN must be set to the same value at the same time to control operation. • T0LCMP and T0HCMP are set at the same time in the 16-bit mode. 3.6.4.2 1) 2) 3) Timer 0 programmable prescaler match register (T0PRR) This register is an 8-bit register that is used to define the clock period (Tpr) of timer/counter 0. The count value of the prescaler starts at 0 when T0PRR is loaded with data. Tpr = (T0PRR + 1) Tcyc Tcyc = Period of cycle clock Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE11 0000 0000 R/W T0PRR T0PRR7 T0PRR6 T0PRR5 T0PRR4 T0PRR3 T0PRR2 T0PRR1 T0PRR0 3.6.4.3 1) Timer/counter 0 low byte (T0L) This is a read-only 8-bit timer/counter. It counts the number of match signals from the prescaler or external signals. Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE12 0000 0000 R T0L T0L7 T0L6 T0L5 T0L4 T0L3 T0L2 T0L1 T0L0 3.6.4.4 1) Timer/counter 0 high byte (T0H) This is a read-only 8-bit timer/counter. It counts the number of match signals from the prescaler or overflows occurring in T0L. Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE13 0000 0000 R T0H T0H7 T0H6 T0H5 T0H4 T0H3 T0H2 T0H1 T0H0 3.6.4.5 1) 2) Timer/counter 0 match data register low byte (T0LR) This register is used to store the match data for T0L. It has an 8-bit match buffer register. A match signal is generated when the value of this match buffer register matches the value of the low-order byte of timer/counter 0 (16 bits of data needs to match in the 16-bit mode). The match buffer register is updated as follows: • When it is inactive (T0LRUN=0), the match register matches T0LR. • When it is active (T0LRUN=1), the match buffer register is loaded with the contents of T0LR when a match signal is generated. Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE14 0000 0000 R/W T0LR T0LR7 T0LR6 T0LR5 T0LR4 T0LR3 T0LR2 T0LR1 T0LR0 3-28 LC870800 Chapter 3 3.6.4.6 Timer/counter 0 match data register high byte (T0HR) 1) This register is used to store the match data for T0H. It has an 8-bit match buffer register. A match signal is generated when the value of this match buffer register matches the value of the high-order byte of timer/counter 0 (16 bits of data needs to match in the 16-bit mode). 2) The match buffer register is updated as follows: • When it is inactive (T0HRUN=0), the match register matches T0HR. • When it is active (T0HRUN=1), the match buffer register is loaded with the contents of T0HR when a match signal is generated. Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE15 0000 0000 R/W T0HR T0HR7 T0HR6 T0HR5 T0HR4 T0HR3 T0HR2 T0HR1 T0HR0 3.6.4.7 1) Timer/counter 0 capture register low byte (T0CAL) This register is a read-only 8-bit register used to capture the contents of timer/counter 0 low byte (T0L) on an external input detection signal. Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE16 XXXX XXXX R T0CAL T0CAL7 T0CAL6 T0CAL5 T0CAL4 T0CAL3 T0CAL2 T0CAL1 T0CAL0 3.6.4.8 1) Timer/counter 0 capture register high byte (T0CAH) (8-bit register) This register is a read-only 8-bit register used to capture the contents of timer/counter 0 high byte (T0H) on an external input detection signal. Address Initial Value R/W Name FE17 XXXX XXXX R T0CAH BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 T0CAH7 T0CAH6 T0CAH5 T0CAH4 T0CAH3 T0CAH2 T0CAH1 T0CAH0 3-29 T1 3.7 Timer/Counter 1 (T1) 3.7.1 Overview The timer/counter 1 (T1) incorporated in this series of microcontrollers is a 16-bit timer/counter that provides the following four functions: 1) Mode 0: 2) 3) Mode 1: Mode 2: 4) Mode 3: 3.7.2 8-bit programmable timer with an 8-bit prescaler (with toggle output) + 8-bit programmable timer/counter (with toggle output) 8-bit PWM with an 8-bit prescaler 2 channels 16-bit programmable timer/counter with an 8-bit prescaler (with toggle output) (The low-order 8 bits may be used as a timer/counter with toggle output.) 16-bit programmable timer with an 8-bit prescaler (with toggle output) (The low-order 8 bits may be used as a PWM.) Functions 1) Mode 0: 8-bit programmable timer with an 8-bit prescaler (with toggle output) + 8-bit programmable timer/counter (with toggle output) • Two independent 8-bit programmable timers (T1L and T1H) run on a clock that is obtained by dividing the cycle clock by 2. • T1L functions as an 8-bit programmable timer/counter that counts the number of signals obtained by dividing the cycle clock by 2 or external events, while T1H functions as an 8-bit programmable timer that counts the number of signals obtained by dividing the cycle clock by 2. • T1PWML and T1PWMH generate a signal that toggles at the interval of T1L and T1H periods, respectively. (Note 1) T1L period = (T1LR + 1) (T1LPRC count) 2Tcyc or (T1LR + 1) (T1LPRC count) events detected T1PWML period = T1L period T1H period = (T1HR + 1) (T1HPRC count) 2Tcyc T1PWMH period = T1H period 2) Mode 1: 8-bit PWM with an 8-bit prescaler 2 channels • Two independent 8-bit PWMs (T1PWML and T1PWMH) run on the cycle clock. T1PWML period = 256 (T1LPRC count) Tcyc T1PWML low period = (T1LR + 1) (T1LPRC count) Tcyc T1PWMH period = 256 (T1HPRC count) Tcyc T1PWMH low period = (T1HR + 1) (T1HPRC count) Tcyc 3) Mode 2: 16-bit programmable timer/counter with an 8-bit prescaler (with toggle output) (The low-order 8 bits may be used as a timer/counter with toggle output.) • Functions as a 16-bit programmable timer/counter that counts the number of signals obtained by dividing the cycle clock by 2 or external events. Since interrupts can occur from the low-order 8-bit timer (T1L) at the interval of T1L period, the low-order 8 bits of this 16-bit programmable timer/counter can be used as the reference timer. 3-30 LC870800 Chapter 3 • T1PWML and T1PWMH generate a signal that toggles at the interval of T1L and T1 periods, respectively. (Note 1) T1L period = (T1LR + 1) (T1LPRC count) 2Tcyc or (T1LR + 1) T1LPRC count) events detected T1PWML period = T1L period T1 period = (T1HR + 1) (T1HPRC count) T1L period or (T1HR+1) (T1HPRC count) (T1LR+1) (T1LPRC count) events detected T1PWMH period = T1 period 2 4) Mode 3: 16-bit programmable timer with an 8-bit prescaler (with toggle output) (The low-order 8 bits may be used as a PWM.) • A 16-bit programmable timer runs on the cycle clock. • The low-order 8 bits run as a PWM (T1PWML) having a period of 256 Tcyc. • T1PWMH generates a signal that toggles at the interval of T1 period. (Note 1) T1PWML period = 256 (T1LPRC count) Tcyc T1PWML low period = (T1LR + 1) (T1LPRC count) Tcyc T1 period = (T1HR + 1) (T1HPRC count) T1PWML period T1PWMH period = T1 period 2 5) Interrupt generation A T1L or T1H interrupt request is generated at the counter period of the T1L or T1H timer if the interrupt request enable bit is set. 6) It is necessary to manipulate the following special function registers to control timer 1 (T1). • T1CNT, T1L, T1H, T1LR, T1HR, T1PRR • P1, P1DDR, P1FCR • P2, P2DDR, I45CR, I45SL Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE18 0000 0000 R/W T1CNT T1HRUN T1LRUN T1LONG T1PWM T1HCMP FE19 0000 0000 R/W T1PRR T1HPRE T1HPRC2 T1HPRC1 T1HPRC0 T1LPRE T1HIE T1LCMP T1LIE FE1A 0000 0000 R T1L T1L7 T1L6 T1L5 T1L4 T1L3 T1L2 T1L1 T1L0 FE1B 0000 0000 R T1H T1H7 T1H6 T1H5 T1H4 T1H3 T1H2 T1H1 T1H0 FE1C 0000 0000 R/W T1LR T1LR7 T1LR6 T1LR5 T1LR4 T1LR3 T1LR2 T1LR1 T1LR0 FE1D 0000 0000 R/W T1HR T1HR7 T1HR6 T1HR5 T1HR4 T1HR3 T1HR2 T1HR1 T1HR0 T1PRC2 T1LPRC1 T1LPRC0 Note 1: The output of T1PWML is fixed at a high level if T1L is stopped. If T1L is running, the output of T1PWML is fixed at a low level when T1LR = FFH. The output of T1PWMH is fixed at a high level if T1H is stopped. If T1H is running, the output of T1PWMH is fixed at a low level when T1HR = FFH. 3-31 T1 3.7.3 Circuit Configuration 3.7.3.1 1) Timer 1 control register (T1CNT) (8-bit register) This register controls the operation and interrupts of T1L and T1H. 3.7.3.2 1) Timer 1 prescaler control register (T1PRR) (8-bit counter) This register sets the clocks for T1L and T1H. 3.7.3.3 1) 2) Timer 1 prescaler low byte (8-bit counter) Start/stop: Stop/start is controlled by the 0/1 value of T1LRUN (timer 1 control register, bit 6). Count clock: Depends on the operating mode. Mode 0 1 2 3 T1LONG 0 0 1 1 T1PWM 0 1 0 1 T1L Prescaler Count Clock 2 Tcyc/events (Note 1) 1 Tcyc (Note 2) 2 Tcyc/events (Note 1) 1 Tcyc (Note 2) Note 1: T1L serves as an event counter when INT4 is specified as the timer 1 count clock input in the external interrupt 4 pin select register (I45SL). It serves as a timer that runs on 2 Tcyc as its count clock if INT4 is not specified as the timer 1 count clock input. Note 2: T1L will not run normally if INT4 is specified as the timer 1 count clock input when T1PWM = 1. When T1PWM = 1, do not specify INT4 as the timer 1 count clock input. 3) Prescaler count: Determined by the T1PRC value. The count clock for T1L is output at intervals determined by the prescaler count. T1LPRE 0 1 1 1 1 1 1 1 1 4) Reset: T1LPRC2 T1LPRC1 T1LPRC0 – – – 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 T1L Prescaler Count 1 2 4 8 16 32 64 128 256 When timer 1 stops operation or a T1L reset signal is generated. 3-32 LC870800 Chapter 3 3.7.3.4 1) 2) Timer 1 prescaler high byte (8-bit counter) Start/stop: Stop/start is controlled by the 0/1 value of T1HRUN (timer 1 control register, bit 7). Count clock: Depends on the mode. Mode 0 1 2 3 3) 3.7.3.5 1) 2) 3) 4) 3.7.3.6 1) 2) 3) 4) T1PWM 0 1 0 1 T1H Prescaler Count Clock 2 Tcyc 1 Tcyc T1L match signal 256 (T1LPRC count) Tcyc Prescaler count: Determined by the T1PRC value. The count clock for T1H is output at intervals determined by the prescaler count. T1HPRE 0 1 1 1 1 1 1 1 1 4) T1LONG 0 0 1 1 Reset: T1HPRC2 T1HPRC1 T1HPRC0 – – – 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 T1H Prescaler Count 1 2 4 8 16 32 64 128 256 When timer 1 stops operation or a T1H reset signal is generated. Timer 1 low byte (T1L) (8-bit counter) Start/stop: Stop/start is controlled by the 0/1 value of T1LRUN (timer 1 control register, bit 6). Count clock: T1L prescaler output clock Match signal: A match signal is generated when the count value matches the value of the match buffer register. Reset: When the counter stops operation or a match signal occurs in mode 0 or mode 2. Timer 1 high byte (T1H) (8-bit counter) Start/stop: Stop/start is controlled by the 0/1 value of T1HRUN (timer 1 control register, bit 7). Count clock: T1H prescaler output clock Match signal: A match signal is generated when the count value matches the value of the match buffer register. Reset: When the counter stops operation or a match signal occurs in mode 0, mode 2, or mode 3. 3-33 T1 3.7.3.7 1) 2) 3.7.3.8 1) 2) 3.7.3.9 1) 2) 3) 3.7.3.10 1) 2) 3) Timer 1 match data register low byte (T1LR) (8-bit register with a match buffer register) This register is used to store the match data for T1L. It has an 8-bit match buffer register. A match signal is generated when the value of this match buffer register matches the value of timer 1 low byte (T1L). The match buffer register is updated as follows: • When it is inactive (T1LRUN=0), the match register matches T1LR. • When it is active (T1LRUN=1), the match buffer register is loaded with the contents of T1LR when the value of T1L reaches 0. Timer 1 match data register high byte (T1HR) (8-bit register with a match buffer register) This register is used to store the match data for T1H. It has an 8-bit match buffer register. A match signal is generated when the value of this match buffer register matches the value of timer 1 high byte (T1H). The match buffer register is updated as follows: • When it is inactive (T1HRUN=0), the match register matches T1HR. • When it is active (T1HRUN=1), the match buffer register is loaded with the contents of T1HR when the value of T1H reaches 0. Timer 1 low byte output (T1PWML) The T1PWML output is fixed at a high level when T1L is inactive. If T1L is active, the T1PWML output is fixed at a low level when T1LR = FFH. When T1PWM (timer 1 control register, bit 4) is set to 0, timer 1 low byte output is a toggle output whose state changes on a T1L match signal. When T1PWM (timer 1 control register, bit 4) is set to 1, timer 1 low byte output is a PWM output that is cleared on a T1L overflow and set on a T1L match signal. Timer 1 high byte output (T1PWMH) The T1PWMH output is fixed at a high level when T1H is inactive. If T1H is active, the T1PWMH output is fixed at a low level when T1HR = FFH. When T1PWM is set to 0 or T1LONG is set to 1, the timer 1 high byte output is a toggle output whose state changes on a T1H match signal. When T1PWM is set to 1 and T1LONG is set to 0, timer 1 high byte output is a PWM output that is cleared on a T1H overflow and set on a T1H match signal. 3-34 LC870800 Chapter 3 2Tcyc Clock or external events Set in I45CR(FE4Ah) I45SL(FE4Bh) Clock registers Clock 2Tcyc T1L prescaler Clock Clear T1L Match Comparator T1H prescaler Invert Clear T1H Match Comparator Invert T1PWML output T1PWMH output Match buffer register Match buffer register Reload Reload T1LCMP flag set T1LR 8-bit programmable timer Figure 3.7.1 8-bit programmable timer Mode 0 Block Diagram (T1LONG = 0, T1PWM = 0) Clock 1Tcyc T1HCMP flag set T1HR Clock 1Tcyc T1L prescaler Clock Overflow T1L Match Comparator Reset T1H prescaler Clock T1H T1PWML output Set Match buffer register Match Comparator T1PWMH output Set Reload T1LCMP flag set 8-bit PWM Figure 3.7.2 Reset Match buffer register Reload T1LR Overflow T1HR 8-bit PWM Mode 1 Block Diagram (T1LONG = 0, T1PWM = 1) 3-35 T1HCMP flag set T1 2Tcyc Clock or external events Set in I45CR(FE4Ah) I45SL(FE4Bh) Clock registers Clock T1L prescaler Clock Clear T1L Comparator T1H prescaler Clear T1H Match Invert Comparator Match T1PWML output Invert T1PWMH output Match buffer register Match buffer register Reload Reload T1LCMP flag set T1LR T1HCMP flag set T1HR 16-bit programmable timer Figure 3.7.3 Mode 2 Block Diagram (T1LONG = 1, T1PWM = 0) Clock 1Tcyc Clock T1L prescaler Clock T1L Comparator T1H prescaler Overflow Match Reset Clock Clear T1H T1PWML output Comparator Set Match buffer register Reload T1LCMP flag set T1HR 16-bit programmable timer Figure 3.7.4 Invert T1PWMH output Match buffer register Reload T1LR Match Mode 3 Block Diagram (T1LONG = 1, T1PWM = 1) 3-36 T1HCMP flag set LC870800 Chapter 3 3.7.4 Related Registers 3.7.4.1 1) Timer 1 control register (T1CNT) This register is an 8-bit register that controls the operation and interrupts of T1L and T1H. Address Initial Value R/W Name FE18 0000 0000 R/W T1CNT BIT7 BIT6 BIT5 T1HRUN T1LRUN T1LONG BIT4 BIT3 BIT2 BIT1 BIT0 T1PWM T1HCMP T1HIE T1LCMP T1LIE T1HRUN (bit 7): T1H count control When this bit is set to 0, timer 1 high byte (T1H) stops on a count value of 0. The match buffer register of T1H has the same value as T1HR. When this bit is set to 1, timer 1 high byte (T1H) performs the required counting operation. T1LRUN (bit 6): T1L count control When this bit is set to 0, timer 1 low byte (T1L) stops on a count value of 0. The match buffer register of T1L has the same value as T1LR. When this bit is set to 1, timer 1 low byte (T1L) performs the required counting operation. T1LONG (bit 5): Timer 1 bit length select When this bit is set to 0, timer 1 high- and low-order bytes serve as independent 8-bit timers. When this bit is set to 1, timer 1 serves as a 16-bit timer since the timer 1 high byte (T1H) counts up at the interval of the timer 1 low byte (T1L). Independent match signals are generated from T1H and T1L when their count value matches the contents of the corresponding match buffer register, regardless of the value of this bit. T1PWM (bit 4): T1 output mode select This bit and T1LONG (bit 5) determine the output mode of T1 (T1PWMH and T1PWML) as summarized in Table 3.7.1. Table 3.7.1 Timer 1 Output (T1PWMH, T1PWML) Mode T1LONG T1PWM 0 0 0 1 0 1 2 1 0 3 1 1 T1PWMH T1PWML Toggle output Period:(T1HR+1) (T1HPRC count) 4 Tcyc Toggle output or PWM output Toggle output or Period: 256 (T1HPRC count) Tcyc PWM output Toggle output or Toggle output Period: (T1HR+1) (T1HPRC count) (T1PWML period) Period: 2(T1HR+1) (T1HPRC count) (T1LR+1) (T1LPRC ) events Period: (T1HR+1) (T1HPRC count) (T1PWML period) 2 PWM output T1HCMP (bit 3): T1H match flag This flag is set if T1H reaches 0 when T1H is active (T1HRUN = 1). This flag must be cleared with an instruction. 3-37 Period: (T1LR+1) (T1LPRC count) Tcyc Period: 2(T1LR+1) (T1LPRC count) events Period: 256 (T1LPRC count) Tcyc Period: (T1LR+1) (T1LPRC count) Tcyc Period: 2(T1LR+1) (T1LPRC count) events Period: 256 (T1LPRC count) Tcyc T1 T1HIE (bit 2): T1H interrupt request enable control An interrupt request is generated to vector address 002BH when this bit and T1HCMP are set to 1. T1LCMP (bit 1): T1L match flag This flag is set if T1L reaches 0 when T1L is active (T1LRUN = 1). This flag must be cleared with an instruction. T1LIE (bit 0): T1L interrupt request enable control An interrupt request is generated to vector address 002BH when this bit and T1LCMP are set to 1. Note: T1HCMP and T1LCMP must be cleared to 0 with an instruction. 3.7.4.2 1) 2) Timer 1 prescaler control register (T1PRR) This register sets up the count values for the timer 1 prescaler. When the register value is changed while the timer is running, the change is reflected in the prescaler operation at the same timing when the match buffer register for the timer (T1L, T1H) is updated. Address Initial Value R/W Name FE19 0000 0000 R/W T1PRR BIT7 BIT6 BIT5 BIT4 BIT3 T1HPRE T1HPRC2 T1HPRC1 T1HPRC0 T1LPRE BIT2 BIT1 T1HPRE (bit 7): Controls the timer 1 prescaler high byte. T1HPRC2 (bit 6): Controls the timer 1 prescaler high byte. T1HPRC1 (bit 5): Controls the timer 1 prescaler high byte. T1HPRC0 (bit 4): Controls the timer 1 prescaler high byte. T1HPRE 0 1 1 1 1 1 1 1 1 T1HPRC2 T1HPRC1 T1HPRC0 – – – 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 T1LPRE (bit 3): Controls the timer 1 prescaler low byte. T1LPRC2 (bit 2): Controls the timer 1 prescaler low byte. T1LPRC1 (bit 1): Controls the timer 1 prescaler low byte. T1LPRC0 (bit 0): Controls the timer 1 prescaler low byte. 3-38 BIT0 T1LPRC2 T1LPRC1 T1LPRC0 T1H Prescaler Count 1 2 4 8 16 32 64 128 256 LC870800 Chapter 3 T1LPRE 0 1 1 1 1 1 1 1 1 3.7.4.3 1) T1LPRC2 T1LPRC1 T1LPRC0 – – – 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 T1L Prescaler Count 1 2 4 8 16 32 64 128 256 Timer 1 low byte (T1L) This is a read-only 8-bit timer. It counts up on the T1L prescaler output clock. Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE1A 0000 0000 R T1L T1L7 T1L6 T1L5 T1L4 T1L3 T1L2 T1L1 T1L0 3.7.4.4 1) Timer 1 high byte (T1H) This is a read-only 8-bit timer. It counts up on the T1H prescaler output clock. Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE1B 0000 0000 R T1H T1H7 T1H6 T1H5 T1H4 T1H3 T1H2 T1H1 T1H0 3.7.4.5 1) 2) Timer 1 match data register low byte (T1LR) This register is used to store the match data for T1L. It has an 8-bit match buffer register. A match signal is generated when the value of this match buffer register matches the value of timer 1 low byte. The match buffer register is updated as follows: • When it is inactive (T1LRUN=0), the match register matches T1LR. • When it is active (T1LRUN=1), the match buffer register is loaded with the contents of T1LR when the value of T1L reaches 0. Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE1C 0000 0000 R/W T1LR T1LR7 T1LR6 T1LR5 T1LR4 T1LR3 T1LR2 T1LR1 T1LR0 3.7.4.6 1) 2) Timer 1 match data register high byte (T1HR) This register is used to store the match data for T1H. It has an 8-bit match buffer register. A match signal is generated when the value of this match buffer register matches the value of timer 1 high byte. The match buffer register is updated as follows: • When it is inactive (T1HRUN=0), the match register matches T1HR. • When it is active (T1HRUN=1), the match buffer register is loaded with the contents of T1HR when the value of T1H reaches 0. Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE1D 0000 0000 R/W T1HR T1HR7 T1HR6 T1HR5 T1HR4 T1HR3 T1HR2 T1HR1 T1HR0 3-39 T1 Match buffer register value Modes 0, 2 T1L,T1H Match signal Interrupt flag set T1PWML,T1PWMH Counter value=FFH Mode 1 Match T1L、T1H Match signal Counter value=FFH Interrupt flag set T1PWML,T1PWMH 3-40 LC870800 Chapter 3 Match buffer register value Mode 3 T1H Match signal Interrupt flag set T1PWMH Counter value=FFH Match T1L Match signal Counter value=FFH Interrupt flag set T1PWML 3-41 T6, T7 3.8 Timer 6 and Timer 7 (T6, T7) 3.8.1 Overview The timer 6 (T6) and timer 7 (T7) incorporated in this series of microcontrollers are 8-bit timers with two independently controlled 6-bit prescalers. 3.8.2 Functions 1) Timer 6 (T6) Timer 6 is an 8-bit timer that runs on 4Tcyc, 16Tcyc, or 64Tcyc clock. It can generate, at pin P06, toggle waveforms whose frequency is equal to the period of timer 6. T6 period = (T6R+1) 4ｎTcyc (n=1, 2, 3) Tcyc = Period of cycle clock 2) Timer 7 (T7) Timer 7 is an 8-bit timer that runs on 4Tcyc, 16Tcyc, or 64Tcyc clock. It can generate, at pin P07, toggle waveforms whose frequency is equal to the period of timer 7. T7 period = (T7R+1) 4ｎTcyc (n=1, 2, 3) Tcyc = Period of cycle clock 3) Interrupt generation An interrupt request to vector address 0043H is generated when the overflow flag is set at the interval of timer 6 or timer 7 period and the corresponding interrupt request enable bit is set. 4) It is necessary to manipulate the following special function registers to control the timer 6 (T6) and timer 7 (T7). • T67CNT, T6R, T7R, P0FCR Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE78 0000 0000 R/W T67CNT T7C1 T7C0 T6C1 T6C0 T7OV T7IE T6OV T6IE FE7A 0000 0000 R/W T6R T6R7 T6R6 T6R5 T6R4 T6R3 T6R2 T6R1 T6R0 T7R3 T7R2 T7R1 T7R0 FE7B 0000 0000 R/W T7R T7R7 T7R6 T7R5 T7R4 FE42 00HH 0000 R/W P0FCR T7OE T6OE - - 3.8.3 CLKOEN CKODV2 CKODV1 CKODV0 Circuit Configuration 3.8.3.1 Timer 6/7 control register (T67CNT) (8-bit register) 1) This register controls the operation and interrupts of T6 and T7. 3.8.3.2 Timer 6 counter (T6CTR) (8-bit counter) 1) This counter counts the number of clocks from the timer 6 prescaler (T6PR). The value of the timer 6 counter (T6CTR) reaches 0 on the clock following the clock that brought about the value specified in the timer 6 period setting register (T6R), when the interrupt flag (T6OV) is set. 2) When T6C0 and T6C1 (T67CNT: FE78, bits 4 and 5) are set to 0, the timer 6 counter stops at a count value of 0. In the other cases, the timer 6 counter continues operation. 3) When data is written into T6R while timer 6 is running, both the timer 6 prescaler and counter are cleared and start counting again. 3-42 LC870800 Chapter 3 3.8.3.3 Timer 6 prescaler (T6PR) (6-bit counter) 1) This prescaler is used to define the clock period for timer 6 determined by T6C0 and T6C1. (T67CNT: FE78, bits 4 and 5). Table 3.8.1 Timer 6 Count Clocks T6C1 T6C0 T6 Count Clock 0 0 0 1 4 Tcyc 1 0 16 Tcyc 1 1 64 Tcyc Timer 6 prescaler and timer/counter are in the reset state. 3.8.3.4 Timer 6 period setting register (T6R) (8-bit register) 1) This register defines the period of timer 6. 2) When data is written into T6R while timer 6 is running, both the timer 6 prescaler and counter are cleared and start counting again. 3.8.3.5 Timer 7 counter (T7CTR) (8-bit counter) 1) This counter counts the number of clocks from the timer 7 prescaler (T7PR). The value of timer 7 counter (T7CTR) reaches 0 on the clock following the clock that brought about the value specified in the timer 7 period setting register (T7R), when the interrupt flag (T7OV) is set. 2) When T7C0 and T7C1 (T67CNT: FE78, bits 6 and 7) are set to 0, the timer 7 counter stops at a count value of 0. In the other cases, the timer 7 counter continues operation. 3) When data is written into T7R while timer 7 is running, both the timer 7 prescaler and counter are cleared and start counting again. 3.8.3.6 Timer 7 prescaler (T7PR) (6-bit counter) 1) This prescaler is used to define the clock period for timer 7 determined by T7C0 and T7C1 (T67CNT: FE78, bits 6 and 7). Table 3.8.2 Timer 7 Count Clocks T7C1 T7C0 T7 Count Clock 0 0 0 1 4 Tcyc 1 0 16 Tcyc 1 1 64 Tcyc Timer 7 prescaler and timer/counter are in the reset state. 3.8.3.7 Timer 7 period setting register (T7R) (8-bit register) 1) This register defines the period of timer 7. 2) When data is written into T7R while timer 7 is running, both the timer 7 prescaler and counter are cleared and start counting again. 3-43 T6, T7 Timer 6 period setting register T6R(FE7Ah) Timer 6/7 control register T67CNT(FE78h) bit5 T6 overflow (T6R+1) count clock bit4 Comparator Load prescaler count value 1Tcyc Clock Clock Timer 6 prescaler (T6PR) Timer 6 counter (T6CTR) Clear Clear Timer 6/7 control register T67CNT(FE78h) bit3 bit2 Set bit1 bit0 Set T6 interrupt T7 interrupt Clear 1Tcyc Clock Clear Clock Timer 7 prescaler (T7PR) Timer 7 counter (T7CTR) Load prescaler count value bit7 bit6 Comparator T7 overflow (T7R+1) count clock Timer 6/7 control register T67CNT(FE78h) Timer 7 period setting register T7R(FE7Bh) Figure 3.8.1 Timers 6/7 Block Diagram 3-44 LC870800 Chapter 3 3.8.4 Related Registers 3.8.4.1 Timer 6/7 control register (T67CNT) 1) This register is an 8-bit register that controls the operation and interrupts of T6 and T7. Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE78 0000 0000 R/W T67CNT T7C1 T7C0 T6C1 T6C0 T7OV T7IE T6OV T6IE T7C1 (bit 7): T7 count clock control T7C0 (bit 6): T7 count clock control T7C1 T7C0 T7 Count Clock 0 0 0 1 Timer 7 prescaler and timer/counter are stopped in the reset state. 4 Tcyc 1 0 16 Tcyc 1 1 64 Tcyc T6C1 (bit 5): T6 count clock control T6C0 (bit 4): T6 count clock control T6C1 T6C0 T6 Count Clock 0 0 0 1 4 Tcyc 1 0 16 Tcyc 1 1 64 Tcyc Timer 6 prescaler and timer/counter are stopped in the reset state. T7OV (bit 3): T7 overflow flag This flag is set at the interval of timer 7 period when timer 7 is running. This flag must be cleared with an instruction. T7IE (bit 2): T7 interrupt request enable control An interrupt request to vector address 0043H is generated when this bit and T7OV are set to 1. T6OV (bit 1): T6 overflow flag This flag is set at the interval of timer 6 period when timer 6 is running. This flag must be cleared with an instruction. T6IE (bit 0): T6 interrupt request enable control An interrupt request to vector address 0043H is generated when this bit and T6OV are set to 1. 3.8.4.2 Timer 6 period setting register (T6R) 1) This register is an 8-bit register for defining the period of timer 6. Timer 6 period = (T6R value + 1) Timer 6 prescaler value (4, 16 or 64 Tcyc) 2) When data is written into T6R while timer 6 is running, both the timer 6 prescaler and counter are cleared and start counting again. Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE7A 0000 0000 R/W T6R T6R7 T6R6 T6R5 T6R4 T6R3 T6R2 T6R1 T6R0 3-45 T6, T7 3.8.4.3 Timer 7 period setting register (T7R) 1) This register is an 8-bit register for defining the period of timer 7. Timer 7 period = (T7R value + 1) Timer 7 prescaler value (4, 16 or 64 Tcyc) 2) When data is written into T7R while timer 7 is running, both the timer 7 prescaler and counter are cleared and start counting again. Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE7B 0000 0000 R/W T7R T7R7 T7R6 T7R5 T7R4 T7R3 T7R2 T7R1 T7R0 3.8.4.4 Port 0 function control register (P0FCR) 1) This register is a 6-bit register that controls the multiplexed output of port 0 pins. It controls the toggle outputs of timer 6 and timer 7. Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 FE42 00HH 0000 R/W P0FCR T7OE T6OE - - BIT3 BIT2 BIT1 BIT0 CLKOEN CKODV2 CKODV1 CKODV0 T7OE (bit 7): This flag is used to control the timer 7 toggle output at pin P07. This flag is disabled when pin P07 is set in the input mode. When pin P07 is set in the output mode: A 0 in this bit outputs the value of port data latch. A 1 in this bit outputs OR of the port data latch and the waveform that toggles at the interval of the timer 7 period. T6OE (bit 6): This flag is used to control the timer 6 toggle output at pin P06. This flag is disabled when pin P06 is set in the input mode. When pin P06 is set in the output mode: A 0 in this bit outputs the value of port data latch. A 1 in this bit outputs OR of the port data latch and the waveform that toggles at the interval of the timer 6 period. (Bits 5 and 4): These bits do not exist. They are always read as 1. CLKOEN (bit 3): CKODV2 (bit 2): CKODV1 (bit 1): CKODV0 (bit 0): These 4 bits have nothing to do with the control functions on timers 6 and 7. See the description of port 0 for details on these bits. 3-46 LC870800 Chapter 3 3.9 Base Timer (BT) 3.9.1 Overview The base timer (BT) incorporated in this series of microcontrollers is a 14-bit binary up-counter that provides the following five functions: 1) Clock timer 2) 14-bit binary up-counter 3) High-speed mode (when used as a 6-bit base timer) 4) Buzzer output 5) Hold mode release 3.9.2 Functions 1) Clock timer The base timer can count clocks at 0.5 second intervals when a 32.768 kHz subclock is used as the count clock for the base timer. In this case, one of the three clocks (cycle clock, timer/counter 0 prescaler output or subclock) must be loaded in the input signal select register (ISL) as the base timer count clock. 2) 14-bit binary up-counter A 14-bit binary up-counter can be constructed using an 8-bit binary up-counter and a 6-bit binary up-counter. These counters can be cleared under program control. 3) High-speed mode (when used as a 6-bit base timer) When the base timer is used as a 6-bit timer, it can clock at the interval of approximately 2 ms if the 32.768 kHz subclock is used as the count clock. The bit length can be specified using the base timer control register (BTCR). 4) Buzzer output function The base timer can generate a 2kHz buzzer when the 32.768 kHz subclock is used as the count clock. The buzzer output can be controlled using the input signal select register (ISL). The buzzer output can be transmitted via pin P21. 5) Interrupt generation An interrupt request to vector address 001BH is generated if an interrupt request is generated by the base timer when the interrupt request enable bit is set. The base timer can generate two types of interrupt requests: "base timer interrupt 0" and "base timer interrupt 1." 6) HOLD mode operation and HOLD mode release function The base timer is enabled for operation in HOLD mode when bit 2 of the power control register (PCON) is set. HOLD mode can be released by an interrupt from the base timer. This function allows the microcontroller to perform low-current intermittent operations. 7) It is necessary to manipulate the following special function registers to control the base timer. • BTCR, ISL, P1DDR, P1, P1FCR Address Initial Value R/W Name BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE7F 0000 0000 R/W BTCR - BTFST BTON BTC11 BTC10 BTIF1 BTIE1 BTIF0 BTIE0 FE5F 00000 0000 R/W ISL NFSEL NFON ST0IN BUZDIV ST0HCP ST0LCP BTIMC1 BTIMC0 BUZON 3-47 BT 3.9.3 Circuit Configuration 3.9.3.1 8-bit binary up-counter 1) 3.9.3.2 This counter is an up-counter that receives, as its input, the signal selected by the input signal select register (ISL). It generates a 2 kHz buzzer output and base timer interrupt 1 flag set signals. The overflow from this counter serves as the clock for the 6-bit binary counter. 6-bit binary up-counter 1) 3.9.3.3 This counter is a 6-bit up-counter that receives, as its input, the signal selected by the input signal select register (ISL) or the overflow signal from the 8-bit counter and generates set signals for base timer interrupts 0 and 1. The switching of the input clock is accomplished by the base timer control register (BTCR). Base timer input clock source 1) The clock input to the base timer (fBST) can be selected from among the cycle clock, timer 0 prescaler, and subclock via the input signal select register (ISL). 16TBST 256TBST Timer 0 prescaler Selector Tcyc 1TBST Selector Set in ISL(FE5Fh) register Buzzer output 8-bit counter Subclock 6-bit counter 16384/64TBST BTIF0 flag set 32TBST 128TBST 512/2TBST 2048/8TBST Figure 3.9.1 Base Timer Block Diagram 3-48 Selector Selector 256TBST BTIF1 flag set LC870800 Chapter 3 3.9.4 Related Registers 3.9.4.1 Base timer control register (BTCR) 1) This register is an 8-bit register that controls the operation of the base timer. Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE7F 0000 0000 R/W BTCR BTFST BTON BTC11 BTC10 BTIF1 BTIE1 BTIF0 BTIE0 BTFST (bit 7): Base timer interrupt 0 period control This bit is used to select the interval at which base timer interrupt 0 is to occur. When this bit is set to 1, the base timer interrupt 0 flag is set when an overflow occurs in the 6-bit counter. The interval at which overflows occur is 64fBST. When this bit is set to 0, the base timer interrupt 0 flag is set when an overflow occurs in the 14-bit counter. The interval at which overflows occur is 16384fBST. This bit must be set to 1 when high-peed mode is to be used. BTON (bit 6): Base timer operation control When this bit is set to 0, the base timer stops when the count value reaches 0. When this bit is set to 1, the base timer continues operation. BTC11 (bit 5): Base timer interrupt 1 period control BTC10 (bit 4): Base timer interrupt 1 period control BTFST BTC11 BTC10 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 Base Timer Interrupt 0 Period 16384fBST 64fBST 16384fBST 64fBST 16384fBST 16384fBST 64fBST 64fBST Base Timer Interrupt 1 Period 32fBST 32fBST 128fBST 128fBST 512fBST 2048fBST 2fBST 8fBST *fBST: The frequency of the input clock selected by the input signal select register (ISL) BTIF1 (bit 3): Base timer interrupt 1 flag This flag is set at the interval equal to the base timer interrupt 1 period that is defined by BTFST, BTC11, and BTC10. This flag must be cleared with an instruction. BTIE1 (bit 2): Base timer interrupt 1 request enable control Setting this bit and BTIF1 to 1 generates X'tal HOLD mode release signal and an interrupt request to vector address 001BH. BTIF0 (bit 1): Base timer interrupt 0 flag This flag is set at the interval equal to the base timer interrupt 0 period that is defined by BTFST, BTC11, and BTC10. This flag must be cleared with an instruction. 3-49 BT BTIE0 (bit 0): Base timer interrupt 0 request enable control Setting this bit and BTIF0 to 1 generates X'tal HOLD mode release signal and an interrupt request to vector address 001BH. Notes: • The system clock and base timer clock cannot be selected at the same time as the subclock when BTFST=BTC10=1 (high-speed mode). • Note that BTIF1 is likely to be set to 1 when BTC11 and BTC10 are rewritten. • If HOLD mode is entered while running the base timer when the cycle clock or subclock is selected as the base timer clock source, the base timer is subject to the influence of unstable oscillations caused by the main clock and subclock when they are started following the release of HOLD mode, resulting in an erroneous count from the base timer. When entering HOLD mode, therefore, it is recommended that the base timer be stopped. • This series of microcontrollers supports X'tal HOLD mode, which enables low-current intermittent operation. In this mode, only the base timer is allowed for operation. 3.9.4.2 Input signal select register (ISL) 1) This register is a 9-bit register that controls the timer 0 input, noise filter time constant, the buzzer output, and base timer clock. Address Initial Value FE5F 00000 0000 R/W Name R/W ISL BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BUZDIV ST0HCP ST0LCP BTIMC1 BTIMC0 BUZON BIT2 BIT1 BIT0 NFSEL NFON ST0IN BUZDIV (bit 8): Buzzer output frequency division ratio select When this bit is set to 1, the signal obtained by dividing the base timer clock by 256 is sent as the buzzer output. When this bit is set to 0, the signal obtained by dividing the base timer clock by 16 is sent as the buzzer output. ST0HCP (bit 7): Timer 0H capture signal input port select ST0LCP (bit 6): Timer 0L capture signal input port select These 2 bits have nothing to do with the control function of the base timer. BTIMC1 (bit 5): Base timer clock select BTIMC0 (bit 4): Base timer clock select BTIMC1 0 0 1 1 BTIMC0 0 1 0 1 Base Timer Input Clock Subclock Cycle clock Subclock Timer/counter 0 prescaler output BUZON (bit 3): Buzzer output This bit enables the buzzer output (fBST/16 or fBST/256). When this bit is set to 1, a signal that is obtained by dividing the base timer clock by 16 is sent to port P21 as the buzzer output. When this bit is set to 0, the buzzer output is fixed at a high level. NFSEL (bit 2): Noise filter time constant select NFON (bit 1): Noise filter time constant select ST0IN (bit 0): Timer 0 counter clock input port select These 3 bits have nothing to do with the control function of the base timer. 3-50 LC870800 Chapter 3 3.10 3.10.1 Serial Interface 0 (SIO0) Overview The serial interface 0 (SIO0) incorporated in this series of microcontrollers has the following function: 1) 3.10.2 Synchronous 8-bit serial I/O (2- or 3-wire system, 43 to 512 3 Tcyc transfer clock) Functions 1) Synchronous 8-bit serial I/O • Performs 2- or 3-wire synchronous serial communication. The clock may be an internal or external clock. • The period of the internal clock is programmable within the range of (n+1) 2 Tcyc (n = 1 to 3 255; Note: n = 0 is inhibited). 2) Interrupt generation An interrupt request is generated at the end of communication when the interrupt request enable bit is set. 3) It is necessary to manipulate the following special function registers to the control serial interface 0 (SIO0). • SCON0, SBUF0, SBR0, SCTR0, SWCON0 • P1, P1DDR, P1FCR Address Initial Value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE30 0000 0000 R/W SCON0 FIX0 FIX0 SI0RUN FIX0 SI0DIR SI0OVR SI0END SI0IE FE31 0000 0000 R/W SBUF0 SBUF07 SBUF06 SBUF05 SBUF04 SBUF03 SBUF02 SBUF01 SBUF00 FE32 0000 0000 R/W SBR0 SBRG07 SBRG06 SBRG05 SBRG04 SBRG03 SBRG02 SBRG01 SBRG00 FE33 0000 0000 R/W SCTR0 FIX0 FIX0 FIX0 FIX0 FIX0 FIX0 FIX0 FIX0 FE37 0000 0000 R/W SWCON0 FIX0 FIX0 FIX0 FIX0 FIX0 FIX0 FIX0 FIX0 3.10.3 Circuit Configuration 3.10.3.1 1) SIO0 control register (SCON0) (8-bit register) This register controls the operation and interrupts of SIO0. 3.10.3.2 1) SIO0 data shift register (SBUF0) (8-bit register) This register is an 8-bit shift register that performs data input and output operations at the same time. 3.10.3.3 1) SIO0 baudrate generator register (SBR0) (8-bit register) This register is an 8-bit register that defines the transfer rate for SIO0 serial transfer. 2) It can generate clocks at the interval of (n+1) 23 Tcyc (n = 1 to 255; Note: n = 0 is inhibited). 3-51 SIO0 3.10.3.4 1) Continuous data bit register (SCTR0) (8-bit register) This register is not available for this series of microcontrollers because they are provided with no continuous transfer function. 3.10.3.5 1) Continuous data transfer control register (SWCON0) (8-bit register) This register is not available for this series of microcontrollers because they are provided with no continuous transfer function. Data input LSB first 8-bit shift register Data output SIO0 output control P10 port latch P10 output control bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Clock P10 MSB first SBUF0 (FE31h) SIO0 output control P11 port latch P11 output control P11 Clock Clock generator circuit MSB,LSB first control Baudrate generator Serial transfer end flag SBR0 (FE32h) SIO0 overrun flag SIO0 output control P12 port latch P12 output control bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SCON0 (FE30h) Interrupt request Figure 3.10.1 SIO0 Synchronous 8-bit Serial I/O Block Diagram 3-52 P12 LC870800 Chapter 3 3.10.4 Related Registers 3.10.4.1 1) SIO0 control register (SCON0) This register is an 8-bit register that controls the operation and interrupts of SIO0. Address Initial Value FE30 0000 0000 R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 R/W SCON0 FIX0 FIX0 SI0RUN FIX0 SI0DIR SI0OVR SI0END SI0IE FIX0 (bit 7): Fixed bit This bit must always be set to 0. FIX0 (bit 6): Fixed bit This bit must always be set to 0. SI0RUN (bit 5): SIO0 operation flag 1) A 1 in this bit indicates that SIO0 is running. 2) This bit must be set with an instruction. 3) This bit is automatically cleared at the end of serial transfer (on the rising edge of the last clock involved in the transfer). FIX0 (bit 4): Fixed bit This bit must always be set to 0. SI0DIR (bit 3): MSB/LSB first select 1) A 1 in this bit places SIO0 into MSB first mode. 2) A 0 in this bit places SIO0 into LSB first mode. SI0OVR (bit 2): SIO0 overrun flag 1) This bit is set when a falling edge of the input clock is detected with SI0RUN=0. 2) Read this bit and judge if communication is performed normally at the end of the communication. 3) This bit must be cleared with an instruction. SI0END (bit 1): Serial transfer end flag 1) This bit is set at the end of serial transfer (on the rising edge of the last clock involved in the transfer). 2) This bit must be cleared with an instruction. SI0IE (bit 0): SI00 interrupt request enable control 1) When this bit and SI0END are set to 1, an interrupt request to vector address 0033H is generated. 3.10.4.2 1) 2) SIO0 data shift register (SBUF0) This register is an 8-bit shift register for serial transfer. Data to be transmitted/received is written to and read from this shift register directly. Address Initial Value FE31 0000 0000 R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 R/W SBUF0 SBUF07 SBUF06 SBUF05 SBUF04 SBUF03 SBUF02 SBUF01 SBUF00 3-53 SIO0 3.10.4.3 1) 2) Baudrate generator register (SBR0) This register is an 8-bit register that defines the transfer rate of SIO0 serial transfer. The transfer rate is computed as follows: TSBR0 = (SBR0 value + 1) 23 Tcyc SBR0 can take a value from 1 to 255 and the valid value range of TSBR0 is from 43 to 512 Tcyc. 3 * The SBR0 value of 00[H] is prohibited. Address Initial Value FE32 0000 0000 R/W Name BIT7 R/W SBR0 SBRG07 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 SBRG06 SBRG05 SBRG04 SBRG03 SBRG02 SBRG01 BIT0 SBRG00 3.10.4.4 Continuous data bit register (SCTR0) 1) This register must always be set to 0. Address Initial Value FE33 0000 0000 R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 R/W SCTR0 FIX0 FIX0 FIX0 FIX0 FIX0 FIX0 FIX0 FIX0 3.10.4.5 Continuous data transfer control register (SWCON0) 1) This register must always be set to 0. Address Initial Value FE37 0000 0000 R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 R/W SWCON0 FIX0 FIX0 FIX0 FIX0 FIX0 FIX0 FIX0 FIX0 3.10.5 SIO0 Communication Examples 3.10.5.1 1) Synchronous 8-bit mode Setting the clock • Set up SBR0 when using an internal clock. Setting the mode • Set as follows: SI0DIR = ? , SI0IE = 1 Setting up the ports 2) 3) Internal clock P12 Output External clock Input Data transmission only Data reception only Data transmission/reception (3-wire) Data transmission/reception (2-wire) P10 Output – Output – 3-54 P11 – Input Input N-channel open drain output LC870800 Chapter 3 4) 5) 6) Setting up output data • Write the output data into SBUF0 in the data transmission or data transmission/reception mode. Starting operation • Set SI0RUN. Reading data (after an interrupt) • Read SBUF0 (SBUF0 has been loaded with serial data from the data I/O port even in the transmission mode). • Clear SI0END. • Return to step 4) when repeating processing. 3.10.6 SIO0 HALT Mode Operation 3.10.6.1 1) 2) Synchronous 8-bit mode SIO0 synchronous 8-bit mode processing is enabled in HALT mode. HALT mode can be released by an interrupt that is generated during SIO0 synchronous 8-bit mode processing. 3-55 SIO1 3.11 3.11.1 Serial Interface 1 (SIO1) Overview The serial interface 1 (SIO1) incorporated in this series of microcontrollers is provided with the following four functions: 1) 2) 3) 4) 3.11.2 Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire system, 2 to 512 Tcyc transfer clock) Mode 1: Asynchronous serial (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 Tcyc baudrate) Mode 2: Bus-master (start bit, 8 data bits, 2 to 512 Tcyc transfer clock) Mode 3: Bus-slave (start detection, 8 data bits, stop detection) Functions 1) Mode 0: Synchronous 8-bit serial I/O • Performs 2- or 3-wire synchronous serial communication. The clock may be an internal or external clock. • The period of the internal clock is programmable within the range of 2 to 512 Tcyc. 2) Mode 1: Asynchronous serial (UART) • Performs half-duplex, 8 data bits, 1 stop bit asynchronous serial communication. • The baudrate is programmable within the range of 8 to 2048 Tcyc. 3) Mode 2: Bus-master • SIO1 is used as a bus master controller. • The start conditions are automatically generated but the stop conditions must be generated by manipulating ports. • Clock synchronization is used. Since it is possible to verify the transfer-time bus data at the end of transfer, this mode can be combined with mode 3 to provide support for multi-master configurations. • The period of the output clock is programmable within the range of 2 to 512 Tcyc. 4) Mode 3: Bus-slave • SIO1 is used as a slave device of the bus. • Start/stop condition detection processing is performed but the detection of an address match condition and the output of acknowledge require program intervention. • SIO1 can generate an interrupt by forcing the clock line to a low level on the falling edge of the 8th clock for recognition by a program. 5) Interrupt generation An interrupt request is generated at the end of communication if the interrupt request enable flag is set. 6) It is necessary to manipulate the following special function registers to control the serial interface 1 (SIO1). • SCON1, SBUF1, SBR1 • P1, P1DDR, P1FCR Address Initial Value R/W Name BIT8 BIT7 BIT6 FE34 0000 0000 R/W SCON1 - SI1M1 SI1M0 FE35 00000 0000 R/W SBUF1 SBUF18 SBUF17 SBUF16 SBUF15 SBUF14 SBUF13 SBUF12 SBUF11 SBUF10 FE36 0000 0000 R/W SBR1 - BIT5 BIT4 BIT3 BIT2 BIT1 SI1RUN SI1REC SI1DIR SI1OVR SI1END BIT0 SI1IE SBRG17 SBRG16 SBRG15 SBRG14 SBRG13 SBRG12 SBRG11 SBRG10 3-56 LC870800 Chapter 3 3.11.3 Circuit Configuration 3.11.3.1 1) SIO1 control register (SCON1) (8-bit register) This register controls the operation and interrupts of SIO1. 3.11.3.2 1) 2) SIO1 shift register (SIOSF1) (8-bit shift register) This register is a shift register used to transfer and receive SIO1 data. This register cannot be directly accessed with an instruction. It is accessed via SBUF1. 3.11.3.3 1) 2) SIO1 data register (SBUF1) (9-bit register) The low-order 8 bits of SBUF1 are transferred to SIOSF1 at the beginning of data transfer. At the end of data transfer, the contents of SIOSF1 are placed in the low-order 8 bits of SBUF1. In modes 1, 2, and 3, since the 9th input data is placed in bit 8 of SBUF1, it is possible to check for a stop bit, etc. 3.11.3.4 1) 2) SIO1 baudrate generator (SBR1) (8-bit reload counter) This is a reload counter for generating internal clocks. The generator can generate clocks of 2 to 512 Tcyc in modes 0 and 2 and generate clocks of 8 to 2048 Tcyc in mode 1. 3-57 SIO1 Table 3.11.1 SIO1 Operations and Operating Modes Synchronous (Mode 0) UART (Mode 1) Bus Master (Mode 2) Bus Slave (Mode 3) Transfer SI1REC=0 Receive SI1REC=1 Transfer SI1REC=0 Receive SI1REC=1 Transfer SI1REC=0 Transfer SI1REC=0 Receive SI1REC=1 Start bit None None Output (Low) Input (Low) See 1) and 2) Not required below Not required See 2) below Data output 8 8 (Shift data) (All 1’s) 8 (Shift data) 8 (All 1’s) 8 (Shift data) 8 (All 1’s) Data input 8 (Input pin) 8 (Input pin) 8 (Input pin) 8 (Input pin) Stop bit None Output (High) Input (H/L) Input (H/L) Output Input (SBUF1,bit8) (H/L) Output (L) Clock 8 9 (Internal) 9 Operation start SI1RUN↑ Period 2 to 512 Tcyc SI1RUN (bit 5) SI1END (bit 1) 8 8 (Shift data) (All 1’s) 1) Start bit SI1RUN↑ detected 2) Start bit detected Receive SI1REC=1 Low output on falling edge of 8th clock 1) 1) on left side 1) on right No start bit side on falling edge of SI1END when SI1RUN=1 2) With start bit on rising edge of SI1RUN when SI1END=0 1) Clock released on falling edge of SI1END when SI1RUN=1 2) Start bit detected when SI1RUN=0 and SI1END=0 8 to 2048 Tcyc 2 to 512Tcyc 2 to 512Tcyc Set Instruction 1) Instruction 2) Start bit detected Start bit detected Instruction Already set Start bit detected Clear End of processing End of stop bit 1) Stop condition detected 2) Ack=1 detected Set End of processing End of stop bit 1) Falling edge of 8th clock 2) Stop condition detected Clear Instruction Instruction Instruction Already set 1) Stop condition detected 2) When arbitration lost (Note 1) 1) Rising edge of 9th clock 2) Stop condition detected Instruction Note 1: If internal data output state="H" and data port state= "L" conditions are detected on the rising edges of the first to 8th clocks, the microcontroller recognizes a bus contention loss and clears SI1RUN (and also stops the generation of the clock at the same time). (Continued on next page) 3-58 LC870800 Chapter 3 Table 3.11.1 SIO1 Operations and Operating Modes (cont.) SI1OVR Set (bit 2) Synchronous (Mode 0) UART (Mode 1) Bus Master (Mode 2) Bus Slave (Mode 3) Transfer SI1REC=0 Transfer SI1REC=0 Receive SI1REC=1 Transfer SI1REC=0 Receive SI1REC=1 1) SI1END set conditions met when SI1END=1 Instruction 1) Falling edge of clock detected when SI1RUN=0 2) SI1END set conditions met when SI1END=1 3) Start bit detected Instruction Shifter SBUF1 (bits 0 to 7) Automatic update of SBUF1, bit 8 SBUF1→ shifter at beginning of operation Rising edge of 8th clock None Transfer SI1REC=0 Receive SI1REC=1 1) Falling edge of clock detected when SI1RUN=0 2) SI1END set conditions met when SI1END=1 1) Falling edge of clock detected when SI1RUN=0 2) SI1END set conditions met when SI1END=1 Clear Instruction Shifter data update Receive SI1REC=1 Instruction SBUF1→ shifter at beginning of operation When 8-bit data transferred Input data read in on stop bit SBUF1→ shifter at beginning of operation When 8-bit Rising edge data of 8th clock received Input data read in on rising edge of 9th clock SBUF1→ shifter at beginning of operation Rising edge of 8th clock Input data read in on rising edge of 9th clock Data input 8-bit shift register(SIOSF1) Data output Clock At time transfer ends At time operation starts SIO1 output control P13 port latch P13 output control bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SBUF1(FE35h) SIO1 output control P14 port latch P13 P14 P14 output control Clock Clock generator circuit SIO1 output control Baudrate generator P15 P15 port latch P15 output control MSB,LSB first select Serial transfer end flag SBR1(FE36h) Overrun flag bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SCON1(FE34h) Interrupt request Figure 3.11.1 SIO1 Mode 0: Synchronous 8-bit Serial I/O Block Diagram (SI1M1=0, SI1M0=0) 3-59 SIO1 Start bit additional circuit Shift input Shift input 8-bit shift register (SIOSF1) Start, stop bit additional circuit At time 8-bit transfer ends Shift clock At time operation starts LSB, MSB first select Stop bit data input bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SBUF1 (FE35h) Stop bit input clock SIO1 output control P13 port latch P13 output control P13 SIO1 output control P14 port latch P14 output control P14 BUS Clock generator circuit Baudrate generator SBR1 (FE36h) Set SI1END when stop bit data ends Overrun flag bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SCON1 (FE34h) Interrupt request Figure 3.11.2 SIO1 Mode 1: Asynchronous Serial [UART] Block Diagram (SI1M1=0, SI1M0=1) 3-60 LC870800 Chapter 3 3.11.4 SIO1 Communication Examples 3.11.4.1 1) Synchronous serial communication (mode 0) Setting the clock • Set up SBR1 when using an internal clock. Setting the mode • Set as follows: SI1M0 = 0, SI1M1= 0, SI1DIR, SI1IE = 1 Setting up the ports and SI1REC (bit 4) 2) 3) 4) 6) 3.11.4.2 1) 3) 4) External clock Input Data transmission only P13 Output P14 – SI1REC 0 Data reception only – Input 1 Data transmission/reception (3-wire) Output Input 0 Data transmission/reception (2-wire) – N-channel open drain output 0 Setting up output data • Write output data into SBUF1 in data transmission mode (SI1REC=0). Starting operation • Set SI1RUN. Reading data (after an interrupt) • Read SBUF1 (SBUF1 has been loaded with serial data from the data I/O port even in transmission mode). • Clear SI1END and exit interrupt processing. • Return to step 4) when repeating processing. 5) 2) Internal clock P15 Output Asynchronous serial communication (mode 1) Setting the baudrate • Set up SBR1. Setting the mode • Set as follows: SI1M0 = 1, SI1M1 = 0, SI1DIR, SI1IE = 1 Setting up the ports. Data transmission/reception (2-wire) P13 Output P14 Input Data transmission/reception (1-wire) – N-channel open drain output Starting transmission • Set SI1REC to 0 and write output data into SBUF1. • Set SI1RUN. 3-61 SIO1 Note: Use the SIO1 data I/O port(P14) when using the SIO1 transmission only in mode 1. In mode 1, transmission is automatically started when a falling edge of receive data is detected. While mode 1 is on, the falling edge of data is always detected at the data I/O port (P14). Consequently, if the transmit port is assigned to the data output port (P13), it is likely that data transmission is started unexpectedly according to the changes in the state of P14. 5) Starting receive operation • Set SI1REC to 1. (Once SI1REC is set to 1, do not attempt to write data to the SCON1 register until the SI1END flag is set.) • Detect the falling edge of receive data. Reading data (after an interrupt) • Read SBUF1. (SBUF1 has been loaded with serial data from the data I/O port even in transmission mode. When SBUF1 is read in, the data about the position of the stop bit is read into bit 1 of the PSW.) • Clear SI1END and exit interrupt processing. • Return to step 4) when repeating processing. 6) Note: Make sure that the following conditions are met when performing continuous receive operation in mode 1 (UART): • The number of stop bits is set to 2 or greater. • Clearing of SI1END during interrupt processing terminates before the next start bit arrives. 3.11.4.3 1) 2) 3) 4) 5) Bus-master mode (mode 2) Setting the clock • Set up SBR1. Setting the mode. • Set as follows: SI1M0=0, SI1M1=1, SI1DIR, SI1IE=1, SI1REC=0 Setting up the ports • Designate the clock and data ports as N-channel open drain output ports. Starting communication (sending an address) • Load SBUF1 with address data. • Set SI1RUN (transfer a start bit + SBUF1 (8 bits) + stop bit (H)). Checking address data (after an interrupt) • Read SBUF1. (SBUF1 has been loaded with serial data from the data I/O port even in transmission mode. When SBUF1 is read in, the data about the position of the stop bit is read into bit 1 of the PSW.) • Check for an acknowledge by reading bit 1 of the PSW. • If a condition for losing the bus contention occurs (see Note 1 in Table 3.11.1), no interrupt will be generated as SI1RUN is cleared in that case. If there is a possibility of a condition for losing the bus contention such as the presence of a separate master mode device, find out such condition by, for example, performing timeout processing using a timer module. 3-62 LC870800 Chapter 3 6) 7) 8) 9) 10) Sending data • Load SBUF1 with output data. • Clear SI1END and exit interrupt processing (transfer SBUF1 (8 bits) + stop bit (H)). Checking transmission data (after an interrupt) • Read SBUF1. (SBUF1 has been loaded with serial data from the data I/O port even in transmission mode. When SBUF1 is read in, the data about the position of the stop bit is read into bit 1 of the PSW.) • Check for an acknowledge by reading bit 1 of the PSW. • If a condition for losing the bus contention occurs (see Note 1 in Table 3.11.1), no interrupt will be generated as SI1RUN is cleared in that case. If there is a possibility of a condition for losing the bus contention such as the presence of a separate master mode device, find out such condition by, for example, performing timeout processing using a timer module. • Return to step 6) when continuing data transmission. • Go to step 10) to terminate communication. Receiving data • Set SI1REC to 1. • Clear SI1END and exit interrupt processing (receive (8 bits) + output SBUF1, bit 8 (acknowledge)). Reading received data (after an interrupt) • Read SBUF1. • Return to step 8) to continue reception of data. • Go to * in step 10) to terminate processing. At this moment, SBUF1, bit 8 data has already been output as acknowledge data and the clock for the master side has been released. Terminating communication • Manipulate the clock output port (P15FCR=0, P15DDR=1, P15=0) and set the clock output to 0. • Manipulate the data output port (P14FCR=0, P14DDR=1, P14=0) and set the data output to 0. • Restore the clock output port into the original state (P15FCR=1, P15DDR=1, P15=0) and release the clock output. * • Wait for all slaves to release the clock and for the clock to be set to 1. • Allow for a data setup time, then manipulate the data output port (P14FCR=0, P14DDR=1, P14=1) and set the data output to 1. In this case, the SIO1 overrun flag SI1OVR (SCON1:FE34, bit 2) is set but this will exert no influence on the operation of SIO1. • Restore the data output port into the original state (set P14FCR to 1, then P14DDR to 1 and P14 to 0). • Clear SI1END and SI1OVR, then exit interrupt processing. • Return to step 4) to repeat processing. 3-63 SIO1 3.11.4.4 1) 2) 3) 4) 5) 6) 7) Bus-slave mode (mode 3) Setting the clock • Set up SBR1 (to set the acknowledge data setup time). Setting the mode • Set as follows: SI1M0 = 1, SI1M1 = 1, SI1DIR, SI1IE = 1, SI1REC = 0 Setting up ports • Designate the clock and data ports as N-channel open drain output ports. Starting communication (waiting for an address) *1 • Set SI1REC. *2 • SI1RUN is automatically set on detection of a start bit. • Perform a receive operation (8 bits), then set the clock output to 0 on the falling edge of the 8th clock, after which an interrupt occurs. Checking for address data (after an interrupt) • Detecting a start condition sets SI1OVR. Check SI1RUN=1 and SI1OVR=1 to determine if the address has been received. (SI1OVR is not automatically cleared. Clear it by instruction.) • Read SBUF1 and check the address. • If no address match occurs, clear SI1RUN and SI1END and exit interrupt processing, then wait for a stop condition detection at * in step 8). Receiving data * • Clear SI1END and exit interrupt processing. (If a receive sequence has been performed, send an acknowledge and release the clock port after the lapse of (SBR1 value + 1) × Tcyc.) • When a stop condition is detected, SI1RUN is automatically cleared and an interrupt is generated. Then, clear SI1END to exit interrupt processing and return to *2 in step 4). • Perform a receive operation (8 bits), then set the clock output to 0 on the falling edge of the 8th clock, after which an interrupt occurs. The clock counter is cleared if a start condition is detected in the middle of receive processing, in which case another 8 clocks are required to generate an interrupt. • Read SBUF1 and store the read data. Note: Bit 8 of SBUF1 is not yet updated because the rising edge of 9th clock has not yet occurred. • Return to * in step 6) to continue receive processing. Sending data • Clear SI1REC. • Load SBUF1 with output data. • Clear SI1END and exit interrupt processing. (Send an acknowledge for the preceding receive operation and release the clock port after the lapse of (SBR1 value + 1) × Tcyc.) *1 • Perform a send operation (8 bits) and set the clock output to 0 on the falling edge of the 8th clock, after which an interrupt occurs. *2 • Go to *3 in step 7) when SI1RUN is set to 1. • When SI1RUN is set to 0, implying an interrupt from *4 in step 7), clear SI1END and SI1OVR and return to *1 in step 4). *3 • Read SBUF1 and check send data as required. 3-64 LC870800 Chapter 3 Note: Bit 8 of SBUF1 is not yet updated because the rising edge of 9th clock has not yet occurred. • Load SBUF1 with the next output data. • Clear SI1END and exit interrupt processing. (Release the clock port after the lapse of (SBR1 value + 1) × Tcyc). • Return to *1 in step 7) when an acknowledge from the master is present (L). • When there is no acknowledge presented from the master (H), SIO1, recognizing the end of data transmission, automatically clears SI1RUN and releases the data port. * However, in a case that restart condition comes just after the event, SI1REC must be set to 1 before exiting the interrupt (SI1REC is for detecting a start condition and is not set automatically). It may disturb the transmission of address from the master if there is an unexpected restart just after slave transmission (when SI1REC is not set to 1 by instruction). *4 • When a stop condition is detected, an interrupt is generated and processing returns to *2 in step 7). Terminating communication • Set SI1REC. • Return to * in step 6) to cause communication to automatically terminate. • To forcibly terminate the communication, clear SI1RUN and SI1END (release the clock port). * • An interrupt occurs when a stop condition is detected. Then, clear SI1END and SI1OVR and return to *2 in step 4). 8) 3.11.5 Related Registers 3.11.5.1 1) SIO1 control register (SCON1) This register is an 8-bit register that controls the operation and interrupts of SIO1. Address Initial Value FE34 0000 0000 R/W Name BIT8 BIT7 BIT6 R/W SCON1 - SI1M1 SI1M0 BIT5 BIT4 SI1RUN SI1REC BIT3 SI1M1 (bit 7): SIO1 mode control SI1M0 (bit 6): SIO1 mode control Table 3.11.2 SIO1 Operating Modes Mode SI1M1 SI1M0 Operating Mode 0 0 0 Synchronous 8-bit SIO 1 0 1 UART (1 stop bit, no parity) 2 1 0 Bus master mode 3 1 1 Bus slave mode SI1RUN (bit 5): SIO1 operation flag 1) A 1 in this bit indicates that SIO1 is running. 2) See Table 3.11.1 for the conditions for setting and clearing this bit. SI1REC (bit 4): SIO1 receive/transmit control 1) Setting this bit to 1 places SIO1 into receive mode. 2) Setting this bit to 0 places SIO1 into transmit mode. SI1DIR (bit 3): MSB/LSB first select 1) Setting this bit to 1 places SIO1 into MSB first mode. 2) Setting this bit to 0 places SIO1 into LSB first mode. 3-65 BIT2 BIT1 SI1DIR SI1OVR SI1END BIT0 SI1IE SIO1 SI1OVR (bit 2): SIO1 overrun flag 1) This bit is set when the falling edge of the input clock is detected with SI1RUN =0 in mode 1, 2, or 3. 2) This bit is set if the conditions for setting SI1END are established when SI1END=1. 3) In mode 3 this bit is set when the start condition is detected. 4) This bit must be cleared with an instruction. SI1END (bit 1): Serial transfer end flag 1) This bit is set when serial transfer terminates (see Table 3.11.1). 2) This bit must be cleared with an instruction. SI1IE (bit 0): SIO1 interrupt request enable control When this bit and SI1END are set to 1, an interrupt request to vector address 003BH is generated. 3.11.5.2 1) 2) 3) Serial buffer 1 (SBUF1) Serial buffer 1 is a 9-bit register used to store data to be handled during SIO1 serial transfer. The low-order 8 bits of SBUF1 are transferred to the data shift register for data transmission/ reception at the beginning of transfer processing and the contents of the shift register are placed in the low-order 8 bits of SBUF1 when 8-bit data is transferred. In modes 1, 2, and 3, bit 8 of SBUF1 is loaded with the 9th data bit that is received (data about the position of the stop bit). Address Initial Value FE35 3.11.5.3 1) 2) 3) 00000 0000 Name R/W SBUF1 BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 SBUF18 SBUF17 SBUF16 SBUF15 SBUF14 SBUF13 SBUF12 SBUF11 SBUF10 Baudrate generator register (SBR1) This register is an 8-bit register that defines the serial transfer rate of SIO1. Loading this register with data causes the baudrate generating counter to be initialized immediately. The transfer ragte varies from mode to mode (the baudrate generator is disabled in mode 3). Modes 0 and 2: TSBR1 = (SBR1 value + 1) 2 Tcyc (Value range = 2 to 512 Tcyc) Mode 1: TSBR1 = (SBR1 value + 1) 8 Tcyc (Value range = 8 to 2048 Tcyc) Address Initial Value FE36 R/W 0000 0000 R/W Name BIT8 R/W SBR1 - BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 SBRG17 SBRG16 SBRG15 SBRG14 SBRG13 SBRG12 SBRG11 SBRG10 3-66 LC870800 Chapter 3 3.12 Asynchronous Serial Interface 1 (UART1) 3.12.1 Overview This series of microcontrollers incorporates an asynchronous serial interface 1 (UART1) that has the following characteristics and features: 1) Data length: 7/8/9 bits (LSB first) 2) Stop bits: 1 bit (2 bits in continuous transmission mode) 3) Parity bits: None 16 3 2048 3 64 3 8192 3 4) Transfer rate: 5) Full duplex communication The independent transmitter and receiver blocks allow both transmit and receive operations to be performed at the same time. Both transmitter and receiver blocks adopt a double buffer configuration, so that data can be transmitted and received continuously. 3.12.2 1) to ) Tcyc or ( to ) Tcyc Functions Asynchronous serial (UART1) • Performs full duplex asynchronous serial communication using a data length of 7, 8, or 9 bits with 1 stop bit. • The transfer rate of the UART1 is programmable within the range of ( 16 to 2048 ) Tcyc or ( 2) Programmable within the range of ( 64 3 to 8192 3 3 3 ) Tcyc. Continuous data transmission/reception • Performs continuous transmission of serial data whose data length and transfer rate are fixed. (The data length and transfer rate that are identified at the beginning of transmission are used.) • The number of stop bits used in the continuous transmission mode is 2 (see Figure 3.12.4). • Performs continuous reception of serial data whose data length and transfer rate vary on each receive operation. • The transfer rate of the UART1 is programmable within the range of ( 16 to 2048 ) Tcyc or 64 3 8192 3 ( 3 to 3 ) Tcyc. • The transmit data is read from the transmit data register (TBUF) and the receive data is stored in the receive data register (RBUF). 3) Interrupt generation An interrupt request is generated at the beginning of transmit operation and at the end of receive operation if the interrupt request enable bit is set. 4) It is necessary to manipulate the following special function registers to control the asynchronous serial interface 1 (UART1). • UCON0, UCON1, UBR, TBUF, RBUF, P1, P1DDR Address Initial Value R/W Name BIT7 BIT6 FED0 0000 0000 R/W UCON0 UBRSEL STRDET FED1 0000 0000 R/W UCON1 TRUN BIT5 BIT4 RECRUN TDDR 8/9BIT BIT3 BIT2 BIT1 BIT0 STPERR U0B3 RBIT8 RECEND RECIE TCMOS 8/7BIT TBIT8 TEPTY TRNSIE FED2 0000 0000 R/W UBR UBRG7 UBRG6 UBRG5 UBRG4 UBRG3 UBRG2 UBRG1 UBRG0 FED3 0000 0000 R/W TBUF T1BUF7 T1BUF6 T1BUF5 T1BUF4 T1BUF3 T1BUF2 T1BUF1 T1BUF0 FED4 0000 0000 R/W RBUF R1BUF7 R1BUF6 R1BUF5 R1BUF4 R1BUF3 R1BUF2 3-67 R1BUF1 R1BUF0 UART1 3.12.3 Circuit Configuration 3.12.3.1 1) UART1 control register 0 (UCON0) (8-bit register) This register controls the receive operation and interrupts for the UART1. 3.12.3.2 1) UART1 control register 1 (UCON1) (8-bit register) This register controls the transmit operation, data length, and interrupts for the UART1. 3.12.3.3 1) UART1 baudrate generator (UBR) (8-bit reload counter) The UART1 baudrate generator is a reload counter for generating internal clocks. 2) 8 It can generate clocks at intervals of (n+1) 3 Tcyc or (n+1) inhibited). 32 3 Tcyc (n = 1 to 255; Note: n = 0 is 3.12.3.4 1) UART1 transmit data register (TBUF) (8-bit register) This register is an 8-bit register for storing the data to be transmitted. 3.12.3.5 1) 2) UART1 transmit shift register (TSFT) (11-bit shift register) This register is used to send serial data via the UART1. This register cannot be accessed directly with an instruction. It must be accessed through the transmit data register (TBUF). 3.12.3.6 1) UART1 receive data register (RBUF) (8-bit register) This register is an 8-bit register for storing receive data. 3.12.3.7 1) 2) UART1 receive shift register (RSFT) (11-bit shift register) This register is used to receive serial data via the UART1. This register cannot be accessed directly with an instruction. It must be accessed through the receive data register (RBUF). 3-68 LC870800 Chapter 3 Data input (LSB first) Start bit (Note: The position of the start bit differs depending on the bit length to be transferred.) Stop bit 11-bit shift register (RSFT) Clock When receive operation ends (RSFTRBUF) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 RBUF (FED4h) Data bit 8 (9-bit data receive mode only) Clock generator circuit Stop bit error flag Start bit detected Falling edge detector Baudrate circuit At beginning of receive operation generator UBR(FED2h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 UCON0 (FED0h) Interrupt request Note: Bit 7 of P1DDR (at FE49) must be set to 0 when the UART1 is to be used in receive mode. (The UART1 will not function normally if this bit is set to 1) Figure 3.12.1 UART1 Block Diagram (Receive Mode) 3-69 P17 (Note) UART1 Stop bit (Note: The position of the stop bit differs depending on the bit length to be transferred.) 11-bit shift register (TSFT) Clock “H” “H” bit8 Start bit Data output (LSB first) “H” bit7 “L” End of transfer to shift register When transmit operation starts (TBUFTSFT) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TBUF(FED3h) Data bit 8 (When data length to be transferred is 9 bits.) Clock generator circuit Baudrate generator UART1 output control UART1 output format control UBR (FED2h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 UCON1 (FED1h) Interrupt request UCON0 (FED0h) bit 7 Note: Bit 6 of P1DDR (at FE49) must be set to 0 when the UART1 transmit data is to be output. (Transmit data is not output if this bit is set to 1) Figure 3.12.2 UART1 Block Diagram (Transmit Mode) 3-70 P16 (Note) LC870800 Chapter 3 3.12.4 Related Registers 3.12.4.1 1) UART1 control register 0 (UCON0) This register is an 8-bit register that controls the receive operation and interrupts for the UART1. Address Initial Value FED0 0000 0000 R/W Name R/W UCON0 BIT7 BIT6 BIT5 BIT4 UBRSEL STRDET RECRUN STPERR BIT3 BIT2 BIT1 BIT0 U0B3 RBIT8 RECEND RECIE UBRSEL (bit 7): UART1 baudrate generator period control 1) When this bit is set to 1, the UART1 baudrate generator generates clocks having a period of (n+1) 32 3 2) Tcyc. When this bit is set to 0, the UART1 baudrate generator generates clocks having a period of (n+1) 8 3 Tcyc. * "n" represents the value of the UART baudrate generator UBR (at FED2). STRDET (bit 6): UART1 start bit detection control 1) When this bit is set to 1, the start bit detection (falling edge detection) function is enabled. 2) When this bit is set to 0, the start bit detection (falling edge detection) function is disabled. * This bit must always be set to 1 to enable the start bit detection function when the UART1 is to be used in continuous receive mode. * If this bit is set to 1 when the receive port (P17) is held at a low level, RECRUN is automatically set and the UART 1 starts the receive operation. RECRUN (bit 5): UART1 receive start flag 1) This bit is set and a receive operation starts when a falling edge of the signal at the receive port (P17) is detected when the start bit detection function is enabled (STRDET = 1). 2) This bit is automatically cleared at the end of the receive operation. (If this bit is cleared during the receive operation, the operation is aborted in the middle of the processing.) * When a receive operation is forced to terminate prematurely, RECEND is set to 1 and the contents of the receive shift register are transferred to RBUF. STPERR is set to 1 if the state of the last data bit that is received on the forced termination is low. STPERR (bit 4): UART1 stop bit error flag 1) This bit is set at the end of a receive operation if the state of the received stop bit (the last data bit received) is low. 2) This bit must be cleared with an instruction. U0B3 (bit 3): General-purpose flag 1) This bit can be used as a general-purpose flag bit. Any attempt to manipulate this bit exerts no influence on the operation of the functional block. RBIT8 (bit 2): UART1 receive data bit 8 storage bit 1) This bit position is loaded with bit 8 of the received data at the end of receive operation when the data length is set to 9 bits (UCON1: 8/9BIT=1, 8/7BIT=0). (If the receive operation is terminated prematurely, this bit position is loaded with the last received bit but one.) 2) This bit must be cleared with an instruction. 3-71 UART1 RECEND (bit 1): UART1 receive end flag 1) This bit is set at the end of a receive operation. (When this bit is set, the received data is transferred from the receive shift register (RSFT) to the receive data register (RBUF).) 2) This bit must be cleared with an instruction. * In the continuous receive mode, the next receive operation is not performed even when the UART1 detects data that sets the receive start flag (RECRUN) before this bit is set. RECIE (bit 0): UART1 receive interrupt request enable control 1) When this bit and RECEND are set to 1, an interrupt request to vector address 0033H is generated. 3.12.4.2 1) UART1 control register 1 (UCON1) This register is an 8-bit register that controls the transmit operation, data length, and interrupts for the UART1. Address Initial Value FED1 0000 0000 R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 R/W UCON1 TRUN 8/9BIT TDDR TCMOS 8/7BIT TBIT8 TEPTY TRNSIE TRUN (bit 7): UART1 transmit control 1) When this bit is set to 1, the UART1 starts a transmit operation. 2) This bit is automatically cleared at the end of the transmit operation. (If this bit is cleared during the transmit operation, the operation is aborted in the middle of the processing.) * In continuous transmit mode, this bit is cleared at the end of a transmit operation, but is automatically set within the same cycle (Tcyc). Consequently, transmit operations occur with intervening 1-Tcyc delays. * In continuous transmit mode, TRUN will not be set automatically if a bit-manipulation instruction (NOT1, CLR1, or SET1) is executed to the UCON1 register in the same cycle in which TRUN is to be automatically cleared. 8/9 BIT (bit 6): UART1 transfer data length control 1) This bit and 8/7 BIT (bit 3) are used to control the transfer data length of the UART1. 8/9 BIT 1 8/7 BIT 0 Data Length (in bits) 9 0 0 8 0 1 7 1 1 Inhibited * The UART1 will not run normally if the data length is changed in the middle of a transfer operation. Be sure to manipulate this bit after confirming completion of the transfer operation. * The same data length is used when both transmit and receive operations are to be performed at the same time. TDDR (bit 5): UART1 transmit port output control 1) When this bit is set to 1, the transmit data is placed at the transmit port (P16). No transmit data is output if bit 6 of P1DDR (at FE45) is set to 1. 2) When this bit is set to 0, no transmit data is placed at the transmit port (P16). * The transmit port is placed in "high/open (CMOS/N-channel open-drain)" mode if this bit is set to 1 when the UART1 has stopped a transmit operation (TRUN = 0). * This bit must always be set to 0 when the UART transmit function is not to be used. 3-72 LC870800 Chapter 3 TCMOS (bit 4): UART1 transmit port output type control 1) When this bit is set to 1, the output type of the transmit port (P16) is set to CMOS. 2) When this bit is set to 0, the output type of the transmit port (P16) is set to N-channel open drain. 8/7 BIT (bit 3): UART1 transfer data length control 1) This bit and 8/9 BIT (bit 6) are used to control the transfer data length of the UART1. TBIT8 (bit 2): UART1 transmit data bit 8 storage bit 1) This bit stores bit 8 of the transmit data when the data length is set to 9 bits (8/9BIT = 1 and 8/7BIT = 0). TEPTY (bit 1): UART1 transmit shift register transfer flag 1) This bit is set when the data transfer from the transmit data register (TBUF) to the transmit shift register (TSFT) ends at the beginning of the transmit operation. (This bit is set in the cycle following the one (Tcyc) in which the transmit control bit (TRUN) is set to 1.) 2) This bit must be cleared with an instruction. * When performing a continuous transmit operation, make sure that this bit is set before each loading of the next transmit data into the transmit data register (TBUF). When this bit is subsequently cleared, the transmit control bit (TRUN) is automatically set at the end of the transmit operation. TRNSIE (bit 0): UART1 transmit interrupt request enable control 1) An interrupt request to vector address 003BH is generated when this bit and TEPTY are set to 1. 3.12.4.3 1) 2) * * * * * UART1 baudrate generator (UBR) The UART1 baudrate generator is an 8-bit register that defines the transfer rate of the UART1 transfer. The counter for the baudrate generator is initialized when a UART1 transfer operation is suspended or terminated (UCON0:RECRUN = UCON1:TRUN=0). Do not change the transfer rate in the middle of a UART1 transfer operation. The UART1 will not function normally if the baudrate is changed during operation. Always make sure that the transfer operation has ended before changing the baudrate. The same transfer rate is used when both transmit and receive operations are to be performed at the same time. (This also holds true when continuous transmit and receive operations are to be performed at the same time.) When (UCON0:UBRSEL = 0) 2048 16 TUBR = (UBR value + 1) 8 Tcyc (value range: 3 to 3 Tcyc) 3 When (UCON0:UBRSEL = 1) 8192 64 TUBR = (UBR value + 1) 32 Tcyc (value range: 3 to 3 Tcyc) 3 Setting the UBR to 00[H] is inhibited. Address Initial Value FED2 0000 0000 R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 R/W UBR UBRG7 UBRG6 UBRG5 UBRG4 UBRG3 UBRG2 UBRG1 UBRG0 3-73 UART1 3.12.4.4 1) 2) UART1 transmit data register (TBUF) This register is an 8-bit register that stores the data to be transmitted through the UART1. Data from the TBUF is transferred to the transmit shift register (TSFT) at the beginning of a transmit operation. (Load the next data after checking the transmit shift register transfer flag (UCON1:TEPTY).) * Bit 8 of the transmit data must be loaded into the transmit data bit 8 storage bit (UCON1:TBIT8). Address Initial Value FED3 0000 0000 R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 R/W TBUF T1BUF7 T1BUF6 T1BUF5 T1BUF4 T1BUF3 T1BUF2 T1BUF1 T1BUF0 3.12.4.5 1) 2) UART1 receive data register (RBUF) This register is an 8-bit register that stores the data that is received through the UART1. The data from the receive shift register (RSFT) is transferred to this RBUF at the end of a receive operation. * Bit 8 of the received data is transferred to the receive data bit 8 storage bit (UCON0:RBIT8). * Bit 7 of RBUF is set to 0 when the receive data length is 7 bits. Address Initial Value FED4 0000 0000 R/W Name R/W RBUF BIT7 BIT6 BIT5 R1BUF7 R1BUF6 R1BUF5 3-74 BIT4 BIT3 BIT2 BIT1 BIT0 R1BUF4 R1BUF3 R1BUF2 R1BUF1 R1BUF0 LC870800 Chapter 3 3.12.5 3.12.5.1 UART1 Continuous Communication Processing Examples Continuous 8-bit data receive mode (first received data = 55H) Start bit Beginning of receive Next start bit End of receive Receive data (LSB first) P17 input 1) TUBR1 Stop bit 2) Figure 3.12.3 1) 2) 3) 4) 5) 4), 5) 3) Example of Continuous 8-bit Data Receive Mode Processing Setting the clock • Set the transfer rate (UBR). Setting the data length • Clear UCON1:8/9BIT and 8/7BIT. Configuring the UART1 for receive processing and setting up the receive port and interrupts • Set up the receive control register (UCON0 = 41H). * Set P17DDR (P1DDR:bit 7) to 0 and P17 (P1:bit 7) to 0. Starting a receive operation • UCON0:RECRUN is set when a falling edge of the signal at the receive port (P17) is detected. End of a receive operation • When the receive operation ends, UCON0:RECRUN is automatically cleared and UCON0: RECEND is set. The UART1 then waits for the start bit of the next receive data. Receive interrupt processing • Read the receive data (RBUF). • Clear UCON0:RECEND and STPERR and exit the interrupt routine. * When changing the data length and baudrate for the next receive operation, do so before the start bit (falling edge of the signal) is detected at the receive port (P17). Receiving the next data • Subsequently, repeat steps 2), 3), and 4) above. • To end a continuous receive operation, clear UCON0:STRDET during a receive operation, and this receive operation will be the last receive operation that the UART1 executes. 3-75 UART1 3.12.5.2 Continuous 8-bit data transmit mode (first transmit data = 55H) Stop bit Beginning of transmit Start bit Transmit data (LSB first) Next start bit Beginning of transmit End of transmit P16 output TUBR1 5) 3) 1) 2) 4) Figure 3.12.4 1) 2) 3) 4) 5) Example of Continuous 8-bit Data Transmit Mode Processing Setting the clock • Set the transfer rate (UBR). Setting up transmit data • Load the transmit data (TBUF =55H). Setting the data length, transmit port, and interrupts • Set up the transmit control register (UCON1 = 31H). * Set P16DDR (P1DDR:bit 6) to 0 and P16 (P1:bit 6) to 0. Starting a transmit operation • Set UCON1:TRUN. Transmit interrupt processing • Load the next transmit data (TBUF = xxH). • Clear UCON1:TEPTY and exit the interrupt routine. End of a transmit operation • When the transmit operation ends, UCON1:TRUN is automatically cleared and automatically set in the same cycle (Tcyc) (continuous data transmit mode only; this processing takes 1 Tcyc of time). The UART1 then starts to transmit the next data. Transmitting the next data • Subsequently, repeat steps 3) and 4) above. • To end a continuous transmit operation, clear UCON1:TRNSIE while not clearing UCON1: TEPTY and exit the interrupt in the step 3) processing, and the transmit operation that is being performed at that time will be the last transmit operation that the UART1 executes . 3-76 LC870800 Chapter 3 3.12.5.3 Setting up the UART1 communication ports (1) When using port 1 as the UART1 port 1) Setting up the receive port (P17) Register Data P17DDR 0 P17 0 1 Receive Port (P17) State Internal Pull-up Resistor Input Off Input On 0 * The UART1 receives no data normally if P17DDR is set to 1. 2) Setting up the transmit port (P16) P16 0 Register Data P16DDR TDDR 0 1 TCMOS 1 Transmit Port (P16) State Internal Pull-up Resistor CMOS output Off 0 0 1 0 N-channel open drain output Off 1 0 1 0 N-channel open drain output On * The UART1 transmits no data if P16DDR is set to 1. 3.12.6 UART1 HALT Mode Operation 3.12.6.1 1) Receive mode A UART1 receive mode operation is enabled in HALT mode. (If UCON0:STRDET is set to 1 when the microcontroller enters HALT mode, the receive processing will be restarted if data that sets UCON0:RECRUN is input at the end of a receive operation.) HALT mode can be released using the UART1 receive interrupt. 2) 3.12.6.2 1) 2) Transmit mode A UART1 transmit mode operation is enabled in HALT mode. (If the continuous transmit mode is specified when the microcontroller enters HALT mode, the UART1 will restart transmit processing after terminating a transmit operation. Since UCON1:TEPTY cannot be cleared in this case, the UART1 stops processing after completing that transmit operation.) HALT mode can be released using the UART1 transmit interrupt. 3-77 ADC10 3.13 3.13.1 AD Converter (ADC10) Overview This series of microcontrollers incorporates a 10-bit resolution AD converter that has the features listed below. It allows the microcontroller to capture analog signals easily. 1) 10-bit resolution 2) Successive approximation 3) AD conversion mode selection (resolution switching) 4) 10-channel analog input (2 channels are implemented on-chip.) 5) Conversion time selection 6) Automatic reference voltage generation control 3.13.2 Functions 1) Successive approximation • The AD converter has a resolution of 10 bits. • Some conversion time is required after starting conversion processing. • The conversion results are transferred to the AD conversion result registers (ADRLC, ADRHC). 2) AD conversion selection (resolution switching) The AD converter supports two AD conversion modes (10- and 8-bit conversion modes), so that the appropriate conversion resolution can be selected according to the operating conditions of the application. The AD mode register (ADMRC) is used to select the AD conversion mode. 3) 10-channel analog input The signal to be converted is selected using the AD control register (ADCRC) from 8 types of analog signals that are input from pin P0 and 2 types of analog signals that are the outputs of on-chip AMP1 and AMP2. 4) Conversion time selection The AD conversion time can be set from 1/1 to 1/128 (frequency division ratio). The AD mode register (ADMRC) and AD conversion result register low byte (ADRLC) are used to select the conversion time for appropriate AD conversion. 5) Automatic reference voltage generation control The AD converter incorporates a reference voltage generator circuit that automatically generates the reference voltage when an AD conversion starts, and stops generation when the conversion ends. For this reason, set/reset control of reference voltage generation is not necessary. Also, there is no need to supply the reference voltage externally. 3-78 LC870800 Chapter 3 6) It is necessary to manipulate the following special function registers to control the AD converter. • ADCRC, ADMRC, ADRLC, ADRHC Address Initial value R/W Name FE58 0000 0000 R/W ADCRC BIT7 BIT6 BIT5 BIT4 AD AD AD AD CHSEL3 CHSEL2 CHSEL1 CHSEL0 ADMD4 BIT1 AD ENDF BIT0 ADIE FE59 0000 0000 R/W ADMRC ADMD1 ADMD0 ADMR2 ADTM1 ADTM0 0000 0000 R/W ADRLC DATAL3 DATAL2 DATAL1 DATAL0 ADRL3 ADRL2 ADRL1 ADTM2 FE5B 0000 0000 R/W ADRHC DATA3 DATA2 DATA1 DATA0 DATA6 ADMD2 ADCR3 BIT2 AD START FE5A DATA7 ADMD3 BIT3 DATA5 DATA4 3.13.3 Circuit Configuration 3.13.3.1 1) AD conversion control circuit This circuit runs in two modes: 10- and 8-bit AD conversion modes. 3.13.3.2 1) Comparator circuit The comparator circuit consists of a comparator that compares the analog input with the reference voltage and a control circuit that controls the reference voltage generator circuit and the conversion results. The conversion end flag (ADENDF) of the AD control register (ADCRC) is set when an analog input channel is selected and the AD conversion terminates in the conversion time designated by the conversion time control register. The conversion results are placed in the AD conversion result registers (ADRHC, ADRLC). 3.13.3.3 1) Multiplexer 1 (MPX1) Multiplexer 1 is used to select the analog signal to be subject to AD conversion from 10 channels of analog signals. 3.13.3.4 1) Automatic reference voltage generator circuit The automatic reference voltage generator circuit consists of a ladder resistor network and a multiplexer (MPX2) and generates the reference voltage that is supplied to the comparator circuit. Generation of the reference voltage is automatically started when an AD conversion starts and stopped when the conversion ends. The reference voltage output ranges from VDD to VSS. 3.13.4 Related Registers 3.13.4.1 1) AD control register (ADCRC) This register is an 8-bit register that controls the operation of the AD converter. Address FE58 Initial value 0000 0000 ADCHSEL3 (bit 7): ADCHSEL2 (bit 6): ADCHSEL1 (bit 5): ADCHSEL0 (bit 4): R/W R/W Name ADCRC BIT7 BIT6 BIT5 BIT4 AD AD AD AD CHSEL3 CHSEL2 CHSEL1 CHSEL0 AD conversion input signal select These 4 bits are used to select the signal to be subject to AD conversion. 3-79 BIT3 BIT2 BIT1 BIT0 ADCR3 AD START AD ENDF ADIE ADC10 AD CHSEL3 AD CHSEL2 AD CHSEL1 AD CHSEL0 Signal Input Pin 0 0 0 0 P00/AN0 0 0 0 1 P01/AN1 0 0 1 0 P02/AN2 0 0 1 1 P03/AN3 0 1 0 0 P04/AN4 0 1 0 1 P05/AN5 0 1 1 0 P06/AN6 0 1 1 1 P07/AN7 1 0 0 0 AMP1/AN8 1 0 0 1 AMP2/AN9 ADCRC3 (bit 3): Fixed bit This bit must always be set to 0. ADSTART (bit 2): AD converter operation control This bit starts (1) or stops (0) AD conversion processing. Setting this bit to 1 starts AD conversion. The bit is reset automatically when the AD conversion ends. The amount of time specified by the conversion time control register is required to complete the conversion. The conversion time is defined using three bits, i.e., the ADTM2 (bit 0) of the AD conversion result register low byte (ADRLC) and the ADTM1 (bit 1) and ADTM0 (bit 0) of the AD mode register (ADMRC). If ADMD0 (ADMRC register, bit 3) is set to 1 (automatic start mode), this bit is set when an AD automatic start signal from the MCPWM circuit is detected (automatic start). Setting this bit to 0 stops the AD conversion. No correct conversion results can be obtained if this bit is cleared when AD conversion is in progress. Never clear this bit or place the microcontroller in HALT or HOLD mode when AD conversion is in progress. ADENDF (bit 1): AD conversion end flag This bit identifies the end of AD conversion. It is set (1) when AD conversion is terminated. Then an interrupt request to vector address 0043H is generated if ADIE is set to 1. If ADENDF is set to 0, it indicates that no AD conversion is in progress. This flag must be cleared with an instruction. ADIE (bit 0): AD conversion interrupt request enable control An interrupt request to vector address 0043H is generated when this bit and ADENDF are set to 1. Notes: • Setting ADCHSEL3 to ADCHSEL0 to any value from '1010' to '1111' is prohibited. • Do not place the microcontroller in HALT or HOLD mode with ADSTART set to 1. Make sure that ADSTART is set to 0 before putting the microcontroller into HALT or HOLD mode. 3-80 LC870800 Chapter 3 3.13.4.2 AD mode register (ADMRC) 1) This register is an 8-bit register for controlling the operating mode of the AD converter. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE59 0000 0000 R/W ADMRC ADMD4 ADMD3 ADMD2 ADMD1 ADMD0 ADMR2 ADTM1 ADTM0 ADMD4 (bit 7): Fixed bit This bit must always be set to 0. ADMD3 (bit 6): AD conversion mode control (resolution select) This bit selects the AD converter resolution between 10-bit AD conversion mode (0) and 8-bit AD conversion mode (1). When this bit is set to 1, the AD converter operates as an 8-bit AD converter. The conversion results are placed only in the AD conversion result register high byte (ADRHC); the contents of the AD conversion result register low byte (ADRLC) remain unchanged. When this bit is set to 0, the AD converter operates as a 10-bit AD converter. The conversion results are placed in the AD conversion result register high byte (ADRHC) and the high-order 2 bits of the AD conversion result register low byte (ADRLC). ADMD2 (bit 5): Fixed bit This bit must always be set to 0. ADMD1 (bit 4): Fixed bit This bit must always be set to 0. ADMD0 (bit 3): AD start mode select This bit sets the AD start mode to either soft start (0) or automatic start mode (1). When this bit is set to 1, AD conversion is started when an AD automatic start signal from the MCPWM circuit is detected. When this bit is set to 0, AD conversion is started by setting bit 2 (ADSTART) of the AD control register (ADCRC). The automatic start mode is described in section 3.14, "Motor Control PWM." ADMR2 (bit 2): Fixed bit This bit must always be set to 0. ADTM1 (bit 1): AD conversion time control ADTM0 (bit 0): These bits and ADTM2 (bit 0) of the AD conversion result register low byte (ADRLC) define the conversion time. ADRLC Register ADTM2 ADTM1 ADTM0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ADMRC Register AD Frequency Division Ratio 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/128 3-81 ADC10 Conversion time calculation formulas • 10-bit AD conversion mode: Conversion time = ((42/(AD division ratio)) + 2)(1/3)Tcyc • 8-bit AD conversion mode: Conversion time = ((28/(AD division ratio)) + 2)(1/3) Tcyc Notes: • The conversion time is doubled in the following cases: 1) The AD conversion is performed in the 10-bit AD conversion mode for the first time after a system reset. 2) The AD conversion is performed for the first time after the AD conversion mode is switched from 8-bit to 10-bit AD conversion mode. • The conversion time determined by the above formula is required in the second and subsequent conversions or in AD conversions that are performed in the 8-bit AD conversion mode. 3.13.4.3 1) 2) AD conversion result register low byte (ADRLC) The AD conversion result register low byte is used to hold the low-order 2 bits of the results of an AD conversion performed in the 10-bit AD conversion mode and to control the conversion time. Since the data in this register is not established during an AD conversion, the conversion results must be read out only after the AD conversion is completed. Address Initial value R/W Name FE5A 0000 0000 R/W ADRLC DATAL3 (bit 7): DATAL2 (bit 6): BIT7 BIT6 BIT5 BIT4 DATAL3 DATAL2 DATAL1 DATAL0 BIT3 BIT2 BIT1 BIT0 ADRL3 ADRL2 ADRL1 ADTM2 Low-order 2 bits of AD conversion results DATAL1 (bit 5): Fixed bit This bit must always be set to 0. DATAL0 (bit 4): Fixed bit This bit must always be set to 0. ADRL3 (bit 3): Fixed bit This bit must always be set to 0. ADRL2 (bit 2): Fixed bit This bit must always be set to 0. ADRL1 (bit 1): Fixed bit This bit must always be set to 0. ADTM2 (bit 0): AD conversion time control This bit and AD mode register (ADMRC) bits ADTM1 (bit 1) and ADTM0 (bit 0) are used to control the conversion time. See the Subsection on the AD mode register for the procedure to set up the conversion time. Note: • The conversion result data contains some errors (quantization error + combination error). Be sure to use only valid conversion results based on the specifications provided in the latest "SANYO Semiconductor Data Sheet.” 3.13.4.4 1) 2) AD conversion result register high byte (ADRHC) This register is used to hold the high-order 8 bits of the results of an AD conversion that is performed in the 10-bit AD conversion mode. The register stores the entire 8 bits of an AD conversion that is performed in 8-bit AD conversion mode. Since the data in this register is not established during an AD conversion, the conversion results must be read out only after the AD conversion is completed. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE5B 0000 0000 R/W ADRHC DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 3-82 LC870800 Chapter 3 3.13.5 AD Conversion Example 3.13.5.1 1) 10-bit AD conversion mode Setting up the 10-bit AD conversion mode • Set the ADMD3 (bit 6) of the AD mode register (ADMRC) to 0. 2) Setting up the conversion time • To set the conversion time to 1/32 frequency division, set ADTM2 (bit 0) of the AD conversion result register low byte (ADRLC) to 1, ADTM1 (bit 1) of the AD mode register (ADMRC) to 0, and ADTM0 (bit 0) of the AD mode register (ADMRC) to 1. 3) Setting up the input channel • When using AD channel input AN5, set ADCHSEL3 (bit 7) of the AD control register (ADCRC) to 0, ADCHSEL2 (bit 6) to 1, ADCHSEL1 (bit 5) to 0, and ADCHSEL0 (bit 4) to 1. 4) Starting AD conversion • Set ADSTART (bit 2) of the AD control register (ADCRC) to 1. • The conversion time is doubled when the AD conversion is performed for the first time after a system reset or after the AD conversion mode is switched from 8-bit to 10-bit AD conversion mode. The conversion time determined by the formula is required in the second and subsequent conversions. 5) Detecting AD conversion end flag • Monitor ADENDF (bit 1) of the AD control register (ADCRC) until it is set to 1. • Clear the conversion end flag (ADENDF) to 0 after confirming that the ADENDF flag (bit 1) is set to 1. 6) Reading the AD conversion results • Read the AD conversion result register high byte (ADRHC) and AD conversion result register low byte (ADRLC). Since the conversion result data contains errors (quantization error + combination error), be sure to use only valid conversion results based on the specifications provided in the latest "SANYO Semiconductor Data Sheet.” • Send the above read data to application software processing. • Return to step 4) to repeat conversion processing. 3-83 ADC10 3.13.6 Hints on the Use of the ADC 1) The conversion time that the user can select varies depending on the frequency of the cycle clock. When preparing a program, refer to the latest edition of "SANYO Semiconductor Data Sheet" to select an appropriate conversion time. 2) Setting ADSTART to 0 while conversion is in progress will stop the conversion function. 3) Do not place the microcontroller in HALT or HOLD mode while AD conversion processing is in progress. Make sure that ADSTART is set to 0 before putting the microcontroller into HALT or HOLD mode. 4) ADSTART is automatically reset and the AD converter stops operation if a reset is triggered while AD conversion processing is in progress. 5) When conversion is finished, the AD conversion end flag (ADENDF) is set and, at the same time, the AD conversion operation control bit (ADSTART) is reset. The end of conversion condition can be identified by monitoring ADENDF. An interrupt request to vector address 0043H is generated at the end of conversion by setting ADIE. 6) The conversion time is doubled in the following cases: • The AD conversion is performed in the 10-bit AD conversion mode for the first time after a system reset. • The AD conversion is performed for the first time after the AD conversion mode is switched from 8-bit to 10-bit AD conversion mode. The conversion time determined by the formula given in the paragraph entitled "Conversion time calculation formulas" is required in the second and subsequent conversions or in AD conversions that are performed in the 8-bit AD conversion mode. 7) The conversion result data contains some errors (quantization error + combination error). Be sure to use only valid conversion results based on the specifications provided in the latest "SANYO Semiconductor Data Sheet.” 8) Make sure that only input voltages that fall within the specified range are supplied to pins P00/AN0 to P07/AN7, AMP1/AN8, and AMP2/AN9. Application of a voltage higher than VDD or lower than VSS to an input pin may exert an adverse influence on the conversion value of the channel in question or of other channels. 9) Take the following measures to prevent a reduction in conversion accuracy due to noise interferences: • Add external bypass capacitors of several µF plus thousands of pF near the VDD1 and VSS1 pins (as close as possible, desirably 5 mm or less). • Add external low-pass filters (RC) or capacitors, most suitable for noise reduction, very close to the analog input pins. To avoid any adverse coupling influence, use a ground that is free of noise interference as the ground for the capacitors (rough standard values are: R = less than 5 kΩ, C=1000 pF to 0.1µF). • Do not lay analog signal lines close to, in parallel with, or in a crossed arrangement with digital pulse signal lines or signal lines in which large current changes can occur. Shield both ends of analog signal lines with noise-free ground shields. • Make sure that no digital pulses are applied to or generated out of the pins adjacent to the analog input pin that is being subject to conversion. 3-84 LC870800 Chapter 3 • Correct conversion results may not be obtained because of noise interference if the state of port outputs is changing. To minimize the adverse influences of noise interference, it is necessary to keep line resistance across the power supply and the VDD pins of the microcontroller at a minimum. This should be kept in mind when designing an application circuit. • Adjust the amplitudes of the voltage at the oscillator pin and the I/O voltages at the other pins so that they fall within the voltage range between VDD and VSS. 10) To obtain valid conversion data, perform conversion operations several times, discard the maximum and minimum values of the conversion results, and use an average of the remaining data. 11) When the state of bit 3 of the ADMRC register (automatic AD start mode/AD soft start mode) is changed during conversion processing, the AD converter switches into the new mode after the conversion processing is finished. 12) The AD converter will accept no automatic AD start signal while it is in the automatic AD start mode. 13) To initiate the next automatic start sequence after the end of an AD conversion when the automatic AD start mode is on, clear bit 1 of the ADCRC register (AD conversion end flag). The AD converter will not accept any next automatic AD start signal if bit 1 of the ADCRC register is set to 1. 14) The AD converter can be subjected to soft AD start or forced stop control even when the automatic AD start mode is set. 3-85 MCPWM 3.14 3.14.1 Motor Control PWM (MCPWM) Overview The motor control PWM (MCPWM) incorporated in this series of microcontrollers is provided with a 12bit counter and generates 3 channels of positive/negative PWM outputs with dead time (PULSG0/ PULSG0#/PULSG1/PULSG1#/PULSG2/PULSG2#) set by a register. It can be forced to stop output by an external input (INT0/INT1/comparator 1/comparator 2). 3.14.2 1) Functions MCPWM0 output • The PWM period is controlled by the 12-bit counter that runs on the system clock and by the value of the PWM period setting register. • The low-level width of MCPWM0 is controlled by the MCPWM0 match count setting register. • NMCPWM0 is an inverted MCPWM0 signal with dead time. The dead time is controlled by the dead time setting register. • MCPWM0 and NMCPWM0 signals are output from pins P30 and P31 as PULSG0 and PULSG0#, respectively. PULSG0 and PULSG0# are controlled by the MCPWM0 output mode select register. • PULSG0 and PULSG0# are forced to stop output by an external input (INT0/INT1/ comparator 1/comparator 2). 2) MCPWM1 output • The PWM period is controlled by the 12-bit counter that runs on the system clock and by the value of the PWM period setting register. • The low-level width of MCPWM1 is controlled by the MCPWM1 match count setting register. • NMCPWM1 is an inverted MCPWM1 signal with dead time. The dead time is controlled by the dead time setting register. • MCPWM1 and NMCPWM1 signals are output from pins P32 and P33 as PULSG1 and PULSG1#, respectively. PULSG1 and PULSG1# are controlled by the MCPWM1 output mode select register. • PULSG1 and PULSG1# are forced to stop output by an external input (INT0/INT1/comparator 1/comparator 2). 3) MCPWM2 output • The PWM period is controlled by the 12-bit counter that runs on the system clock and by the value of the PWM period setting register. • The low-level width of MCPWM2 is controlled by the MCPWM2 match count setting register. • NMCPWM2 is an inverted MCPWM2 signal with dead time. The dead time is controlled by the dead time setting register. • The MCPWM2 and NMCPWM2 signals are output from pins P34 and P35 as PULSG2 and PULSG2#, respectively. PULSG2 and PULSG2# are controlled by the MCPWM2 output mode select register. • PULSG2 and PULSG2# are forced to stop output by an external input (INT0/INT1/ comparator 1/comparator 2). 3-86 LC870800 Chapter 3 4) 5) Interrupt generation • An end-of-cycle interrupt request is generated at the end of each cycle if the end-of-cycle interrupt enable bit is set. • An end-of-half-cycle interrupt request is generated at the end of each half cycle if the end-ofhalf- cycle interrupt enable bit is set. • End-of-cycle and end-of-half-cycle interrupt sources are used for automatic start mode operation of the AD converter. It is necessary to manipulate the following special function registers to control the motor control PWM. ・PWMCR, PINTCR, POMD0, POMD1, PPRDL, PPRDH, P0MTL, P0MTH, P1MTL, P1MTH, P2MTL, P20MTH, DTIM, PIOCR Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE90 0000 0000 R/W PWMCR PWMEN PWMMD OPOL OPOLB ATRGEN PCKDV2 PCKDV1 PCKDV0 FE91 0000 0000 R/W PINTCR CRTSEL CRTEN ERTSEL ERTEN HPRDRQ HPRDEN PRDRQ PRDEN FE92 H000 H000 R/W POMD0 - P1OMD2 P1OMD1 P1OMD0 - P0OMD2 P0OMD1 P0OMD0 FE93 HHHH H000 R/W POMD1 - - - - - P2OMD2 P2OMD1 P2OMD0 FE94 0000 0000 R/W PPRDL PPRD7 PPRD6 PPRD5 PPRD4 PPRD3 PPRD2 PPRD1 PPRD0 FE95 HHHH 0000 R/W PPRDH - - - - PPRDB PPRDA PPRD9 PPRD8 FE96 0000 0000 R/W P0MTL P0MT7 P0MT6 P0MT5 P0MT4 P0MT3 P0MT2 P0MT1 P0MT0 FE97 HHHH 0000 R/W P0MTH - - - - P0MTB P0MTA P0MT9 P0MT8 FE98 0000 0000 R/W P1MTL P1MT7 P1MT6 P1MT5 P1MT4 P1MT3 P1MT2 P1MT1 P1MT0 FE99 HHHH 0000 R/W P1MTH - - - - P1MTB P1MTA P1MT9 P1MT8 FE9A 0000 0000 R/W P2MTL P2MT7 P2MT6 P2MT5 P2MT4 P2MT3 P2MT2 P2MT1 P2MT0 FE9B HHHH 0000 R/W P2MTH - - - - P2MTB P2MTA P2MT9 P2MT8 FE9C 0000 0000 R/W DTIM DTIM7 DTIM6 DTIM5 DTIM4 DTIM3 DTIM2 DTIM1 DTIM0 FE9D HH00 0000 R/W PIOCR - - POEN2B POEN2 POEN1B POEN1 POEN0B POEN0 3.14.3 Circuit Configuration 3.14.3.1 MCPWM control register (PWMCR) (8-bit register) 1) This register controls the operation of the MCPWM, the output polarity, the AD converter automatic start mode, and the frequency division ratio of the operation clock. 3.14.3.2 MCPWM interrupt control register (PINTCR) (8-bit register) 1) This register controls MCPWM interrupt processing. 2) The register also controls the forced output stop of MCPWM. 3.14.3.3 Operation clock generator circuit 1) This circuit generates an operation clock whose frequency is a 1/1, 1/2, 1/4, 1/8, 1/16, or 1/32 frequency division of the system clock under control of the PWM clock frequency division ratio select register. 3.14.3.4 PWM period setting register (PPRDL, PPRDH) (12-bit register with a match buffer register) 1) This register holds the match data that sets the PWM period. It is provided with a 12-bit match buffer register. An end-of-cycle or end-of-half-cycle interrupt request source is set when the value of this register matches the value of the 12-bit counter. 2) Update of the match buffer register is performed as follows: The match buffer register is loaded with the contents of PPRDL and PPRDH when the state of the PWMEN bit (MCPWM control register, bit 7) is switched from 0 to 1. 3-87 MCPWM 3.14.3.5 1) 2) 3) 3.14.3.6 1) 2) 12-bit counter Start/stop: Stop/start operation of the 12-bit counter is controlled by the 0/1 state of the PWMEN bit (MCPWM control register, bit 7). Count clock: The output of the operation clock generator circuit. Reset: When the value of the PWM period setting match buffer register matches the value of the 12-bit counter. MCPWM0 match count setting register (P0MTL, P0MTH) (12-bit register with a match buffer register) This register holds the match data that sets the MCPWM0 match count. It is provided with a 12-bit match buffer register. The state of the MCPWM0 signal changes when the value of this match buffer register matches the value of the 12-bit counter. Update of the match buffer register is performed as follows: • It is loaded with the contents of P0MTL and P0MTH when the state of the PWMEN bit (MCPWM control register, bit 7) is switched from 0 to 1. • It is loaded with the contents of P0MTL and P0MTH at the end of a cycle. 3.14.3.7 1) 2) MCPWM1 match count setting register (P1MTL, P1MTH) (12-bit register with a match buffer register) This register holds the match data that sets the MCPWM1 match count. It is provided with a 12-bit match buffer register. The state of the MCPWM1 signal changes when the value of this match buffer register matches the value of the 12-bit counter. Update of the match buffer register is performed as follows: • It is loaded with the contents of P1MTL and P1MTH when the state of the PWMEN bit (MCPWM control register, bit 7) is switched from 0 to 1. • It is loaded with the contents of P1MTL and P1MTH at the end of a cycle. 3.14.3.8 1) 2) MCPWM2 match count setting register (P2MTL, P2MTH) (12-bit register with a match buffer register) This register holds the match data that sets the MCPWM2 match count. It is provided with a 12-bit match buffer register. The state of the MCPWM2 signal changes when the value of this match buffer register matches the value of the 12-bit counter. Update of the match buffer register is performed as follows: • It is loaded with the contents of P2MTL and P2MTH when the state of the PWMEN bit (MCPWM control register, bit 7) is switched from 0 to 1. • It is loaded with the contents of P2MTL and P2MTH at the end of a cycle. 3.14.3.9 1) 2) Dead time setting register (DTIM) (8-bit register with a buffer register) This register holds the data that sets the dead time. It is provided with an 8-bit buffer register. The NMCPWMi (i=0, 1, 2) signal is generated by the buffer register, 12-bit counter, and MCPWMi match buffer registers. Update of the buffer register is performed as follows: It is loaded with the contents of DTIM when the state of the PWMEN bit (MCPWM control register, bit 7) is switched from 0 to 1. 3-88 LC870800 Chapter 3 3.14.3.10 PWM signal generator circuit (3 channels) 1) The MCPWMi/NMCPWMi (i=0, 1, 2) signals are generated by the values of the 12-bit counter, the dead time setting buffer register, and the MCPWMi match count setting match buffer register. 3.14.3.11 1) 2) MCPWM output mode select register (POMD0, POMD1) (9-bit register with a buffer register) This register holds the data that selects the output mode of MCPWMi. It is provided with a 9-bit buffer register. This buffer register is used to control the PULSGi/PULSGi# (i=0, 1, 2) outputs. Update of the buffer register is performed as follows: • It is loaded with the contents of POMD0 and POMD1 when the state of the PWMEN bit (MCPWM control register, bit 7) is switched from 0 to 1. • It is loaded with the contents of POMD0 and POMD1 at the end of a cycle. • All bits are cleared when an external input (INT0/INT1/comparator 1/comparator 2) that is selected by the MCPWM interrupt control register is detected. 3.14.3.12 PWM output generator circuit (3 channels) 1) The PULSGi/PULSGi# signals are generated by the MCPWMi/NMCPWMi signals, and by the values of the dead time setting buffer register and the MCPWM output mode select buffer register. (i=0, 1, 2) Dead time setting register Load To MCPWMi output block Buffer register PWM period setting register Load Match buffer register Comparator System clock Operation clock generator circuit INT0 interrupt source INT1 interrupt source Comparator 1 interrupt source Comparator 2 interrupt source Match 12-bit counter Forced output stop signal generator circuit Select MCPWM interrupt control register Figure 3.14.1 MCPWM Common Block Diagram 3-89 To period interrupt AD converter To MCPWMｉ output block To MCPWMｉ output block MCPWM MCPWMｉ match count setting register Load Match buffer register MCPWMｉ PWM signal NMCPWMｉ generator circuit PWM output PULSGｉ generator circuit PULSGｉ# 12-bit counter value Dead time setting buffer register value MCPWM output mode select register Load Clear all bits Buffer register Clear all bits Forced output stop signal Figure 3.14.2 MCPWMi Output Block (i=0, 1, 2) Block Diagram 3.14.4 Related Registers 3.14.4.1 1) MCPWM control register (PWMCR) This register is an 8-bit register that controls the operation of the MCPWM, the output polarity, the AD converter automatic start mode, and the frequency division ratio of the operation clock. Address Initial value R/W FE90 0000 0000 R/W Name BIT7 BIT6 PWMCR PWMEN PWMMD BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 OPOL OPOLB ATRGEN PCKDV2 PCKDV1 PCKDV0 PWMEN (bit 7): MCPWM operation control Setting this bit to 0 stops the MCPWM operation. Setting this bit to 1 starts the MCPWM operation. PWMMD (bit 6): MCPWM mode control Setting this bit to 0 causes the MCPWM to run in edge-aligned PWM mode (mode 0). Setting this bit to 1 causes the MCPWM to run in center-aligned PWM mode (mode 1). OPOL (bit 5): PULSGi output polarity control (i=0, 1, 2) When this bit is set to 0, positive polarity PULSGi signals are output. When this bit is set to 1, negative polarity PULSGi signals are output. OPOLB (bit 4): PULSGi# output polarity control (i=0, 1, 2) When this bit is set to 0, positive polarity PULSGi# signals are output. When this bit is set to 1, negative polarity PULSGi# signals are output. ATRGEN (bit 3): AD converter automatic start mode control Setting this bit to 0 disables automatic start mode operation of the AD converter by the PWM period. Setting this bit to 1 enables automatic start mode operation of the AD converter by the PWM period. The AD automatic start signal is generated at the timing when the end-of-cycle interrupt source is set in mode 0 and when the end-of-half-cycle interrupt source is set in mode 1. 3-90 LC870800 Chapter 3 PCKDV2 to PCKDV0 (bits 2 to 0): PWM clock frequency division ratio select These bits select the clock frequency of the 12-bit counter. 12-bit Counter Clock PCKDV2 to PCKDV0 000 1/1 system clock 001 1/2 system clock 010 1/4 system clock 011 1/8 system clock 100 1/16 system clock 101 1/32 system clock 110 Inhibited 111 Inhibited Notes: • The settings of PWMMD and PCKDV2 to PCKDV0 cannot be changed while the MCPWM is running (PWMEN=1). 3.14.4.2 1) MCPWM interrupt control register (PINTCR) This register is an 8-bit register that controls PWM interrupt processing and forced output stop processing. Address Initial value FE91 0000 0000 R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 R/W PINTCR CRTSEL CRTEN ERTSEL ERTEN HPRDRQ HPRDEN PRDRQ PRDEN CRTSEL (bit 7): Comparator-triggered forced output stop event select Setting this bit to 0 selects the comparator 1 interrupt source as the trigger for forced output stop processing. Setting this bit to 1 selects the comparator 2 interrupt source as the trigger for forced output stop processing. CRTEN (bit 6): Comparator-triggered forced output stop control Setting this bit to 0 disables comparator-triggered forced output stop operation. Setting this bit to 1 enables comparator-triggered forced output stop operation. ERTSEL (bit 5): External interrupt-triggered forced output stop event select Setting this bit to 0 selects the INT0 interrupt source as the trigger for forced output stop processing. Setting this bit to 1 selects the INT1 interrupt source as the trigger for forced output stop processing. ERTEN (bit 4): External interrupt-triggered forced output stop control Setting this bit to 0 disables external interrupt-triggered forced output stop operation. Setting this bit to 1 enables external interrupt-triggered forced output stop operation. HPRDRQ (bit 3): End-of-half-cycle interrupt source This bit is set when a match is detected between the values of the PWM period setting register and the 12-bit counter in mode 1. This bit is not set in mode 0. This flag must be cleared with an instruction. HPRDEN (bit 2): End-of-half-cycle interrupt enable control An interrupt request to vector address 003BH is generated when this bit and HPRDRQ are set to 1. 3-91 MCPWM PRDRQ (bit 1): End-of-cycle interrupt source This bit is set when a match is detected between the values of the PWM period setting register and the 12-bit counter in mode 0. In mode 1, this bit is set when two match occurrences between the values of the PWM period setting register and the 12-bit counter are detected. This flag must be cleared with an instruction. PRDEN (bit 0): End-of-cycle interrupt enable control An interrupt request to vector address 003BH is generated when this bit and PRDRQ are set to 1. Note: • Both comparator-triggered forced output stop processing and external interrupt-triggered forced output stop processing can be used at the same time. 3.14.4.3 1) MCPWM output mode setting register 0 (POMD0) This register is a 6-bit register that sets up the output mode of MCPWM. Address Initial value R/W Name BIT7 FE92 H000 H000 R/W POMD0 - BIT6 BIT5 P1OMD2 P1OMD1 BIT4 BIT3 P1OMD0 - P1OMD2 to P1OMD0 (bits 6 to 4): MCPWM1 output mode setting P1OMD2 to P1OMD0 PULSG1 Output PULSG1# Output 000 Low Low 001 Low High 010 High Low 011 High High 100 NMCPWM1 MCPWM1 101 Low MCPWM1 110 MCPWM1 Low 111 MCPWM1 NMCPWM1 P0OMD2 to P0OMD0 (bits 2 to 0): MCPWM0 output mode setting P0OMD2 to P0OMD0 000 PULSG0 Output Low PULSG0# Output Low 001 Low High 010 High Low 011 High High 100 NMCPWM0 MCPWM0 101 Low MCPWM0 110 MCPWM0 Low 111 MCPWM0 NMCPWM0 3-92 BIT2 BIT1 P0OMD2 P0OMD1 BIT0 P0OMD0 LC870800 Chapter 3 Notes: • The inversion of PULSGi (i=0, 1) is output when OPOL=1. • The inversion of PULSGi# (i=0, 1) is output when OPOLB=1. • Bits P1OMD2 to P1OMD0 and P0OMD2 to P0OMD0 are loaded into the respective buffer registers when the state of the PWMEN bit (MCPWM control register, bit 7) is switched from 0 to 1 and at the end of every cycle. • All of bits P1OMD2 to P1OMD0 and P0OMD2 to P0OMD0 are cleared when MCPWM is forced to stop output operation by an external input (INT0/INT1/comparator 1/comparator 2). 3.14.4.4 1) MCPWM output mode setting register 1 (POMD1) This register is a 3-bit register that sets up the output mode of MCPWM. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 FE93 HHHH H000 R/W POMD1 - - - - - BIT2 BIT1 BIT0 P2OMD2 P2OMD1 P2OMD0 P2OMD2 to P2OMD0 (bits 2 to 0): MCPWM2 output mode setting P2OMD2 to P2OMD0 000 PULSG2 Output Low PULSG2# Output Low 001 Low High 010 High Low 011 High High 100 NMCPWM2 MCPWM2 101 Low MCPWM2 110 MCPWM2 Low 111 MCPWM2 NMCPWM2 Notes: • The inversion of PULSG2 is output when OPOL=1. • The inversion of PULSG2# is output when OPOLB=1. • Bits P2OMD2 to P2OMD0 are loaded into the buffer register when the state of the PWMEN bit (MCPWM control register, bit 7) is switched from 0 to 1 and at the end of every cycle. • All of bits P2OMD2 to P2OMD0 are cleared when MCPWM is forced to stop output operation by an external input (INT0/INT1/comparator 1/comparator 2). 3.14.4.5 1) PWM period setting register low byte (PPRDL) This register is an 8-bit register that is used to set the PWM period. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE94 0000 0000 R/W PPRDL PPRD7 PPRD6 PPRD5 PPRD4 PPRD3 PPRD2 PPRD1 PPRD0 3.14.4.6 1) PWM period setting register high byte (PPRDH) This register is a 4-bit register that is used to set the PWM period. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE95 HHHH 0000 R/W PPRDH - - - - PPRDB PPRDA PPRD9 PPRD8 3-93 MCPWM PPRDB to PPRD0: PWM period setting These bits define the PWM period. PWM period= Set value 12-bit counter clock frequency Note: • Bits PPRDB to PPRD0 are loaded into the buffer register when the state of the PWMEN bit (MCPWM control register, bit 7) is switched from 0 to 1. • Setting these bits to 000h is inhibited. 3.14.4.7 1) MCPWM0 match count setting register low byte (P0MTL) This register is an 8-bit register that is used to set the MCPWM0 match count value. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE96 0000 0000 R/W P0MTL P0MT7 P0MT6 P0MT5 P0MT4 P0MT3 P0MT2 P0MT1 P0MT0 3.14.4.8 1) MCPWM0 match count setting register high byte (P0MTH) This register is a 4-bit register that is used to set the MCPWM0 match count value. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE97 HHHH 0000 R/W P0MTH - - - - P0MTB P0MTA P0MT9 P0MT8 P0MTB to P0MT0: MCPWM0 match count setting These bits define the MCPWM0 match count value. MCPWM0 match count value = Set value 12-bit counter clock frequency Note: • Bits P0MTB to P0MTB0 are loaded into the buffer register when the state of the PWMEN bit (MCPWM control register, bit 7) is switched from 0 to 1 and at the end of every cycle. 3.14.4.9 1) MCPWM1 match count setting register low byte (P1MTL) This register is an 8-bit register that is used to set the MCPWM1 match count value. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE98 0000 0000 R/W P1MTL P1MT7 P1MT6 P1MT5 P1MT4 P1MT3 P1MT2 P1MT1 P1MT0 3.14.4.10 MCPWM1 match count setting register high byte (P1MTH) 1) This register is a 4-bit register that is used to set the MCPWM1 match count value. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE99 HHHH 0000 R/W P1MTH - - - - P1MTB P1MTA P1MT9 P1MT8 P1MTB to P1MT0: MCPWM1 match count setting These bits define the MCPWM1 match count value. MCPWM1 match count value = Set value 12-bit counter clock frequency Note: • Bits P1MTB to P1MTB0 are loaded into the buffer register when the state of the PWMEN bit (MCPWM control register, bit 7) is switched from 0 to 1 and at the end of every cycle. 3-94 LC870800 Chapter 3 3.14.4.11 MCPWM2 match count setting register low byte (P2MTL) 1) This register is an 8-bit register that is used to set the MCPWM2 match count value. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE9A 0000 0000 R/W P2MTL P2MT7 P2MT6 P2MT5 P2MT4 P2MT3 P2MT2 P2MT1 P2MT0 3.14.4.12 MCPWM2 match count setting register high byte (P2MTH) 1) This register is a 4-bit register that is used to set the MCPWM2 match count value. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE9B HHHH 0000 R/W P2MTH - - - - P2MTB P2MTA P2MT9 P2MT8 P2MTB to P2MT0: MCPWM2 match count setting These bits define the MCPWM2 match count value. MCPWM2 match count value = Set value 12-bit counter clock frequency Note: • Bits P2MTB to P2MT0 are loaded into the buffer register when the state of the PWMEN bit (MCPWM control register, bit 7) is switched from 0 to 1 and at the end of every cycle. 3.14.4.13 Dead time setting register (DTIM) 1) This register is an 8 bit register that is used to set the dead time. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE9C 0000 0000 R/W DTIM DTIM7 DTIM6 DTIM5 DTIM4 DTIM3 DTIM2 DTIM1 DTIM0 DTIM7 to DTIM0: Dead time setting These bits define the dead time. Dead time=Set value 12-bit counter clock frequency Note: • Bits DTIM7 to DTIM0 are loaded into the buffer register when the state of the PWMEN bit (MCPWM control register, bit 7) is switched from 0 to 1. • Set as follows: DTIM7 to DTIM0 < PPRDB to PPRD0. 3.14.4.14 PWM output pin control register (PIOCR) 1) This register is a 6-bit register that controls the PWM output pins. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE9D HH00 0000 R/W PIOCR - - POEN2B POEN2 POEN1B POEN1 POEN0B POEN0 POEN2B (bit 5): PULSG2# output pin control Setting this bit to 0 disables the PULSG2# output. Setting this bit to 1 enables the PULSG2# output from pin P35. POEN2 (bit 4): PULSG2 output pin control Setting this bit to 0 disables the PULSG2 output. Setting this bit to 1 enables the PULSG2 output from pin P34. 3-95 MCPWM POEN1B (bit 3): PULSG1# output pin control Setting this bit to 0 disables the PULSG1# output. Setting this bit to 1 enables the PULSG1# output from pin P33. POEN1 (bit 2): PULSG1 output pin control Setting this bit to 0 disables the PULSG1 output. Setting this bit to 1 enables the PULSG1 output from pin P32. POEN0B (bit 1): PULSG0# output pin control Setting this bit to 0 disables the PULSG0# output. Setting this bit to 1 enables the PULSG0# output from pin P31. POEN0 (bit 0): PULSG0 output pin control Setting this bit to 0 disables the PULSG0 output. Setting this bit to 1 enables the PULSG0 output from pin P30. Note: • Since PULSGi and PULSGi# (i=0, 1, 2) are logically ORed with the port latch data on output, the port latch data must be set to 0. 3.14.5 1) PULSGi / PULSGi# Output Port Settings (i=0, 1, 2) The relationship between the port settings and pin states for enabling the PULSG0 output from pin P30 is summarized below. Register Data P30 2) P30DDR P30 State POEN0 0 1 0 Low 0 1 1 PULSG0 1 1 X High/open (CMOS/N-channel open drain) The relationship between the port settings and pin states for enabling the PULSG0# output from pin P31 is summarized below. Register Data P31 3) P31DDR P31 State POEN0# 0 1 0 Low 0 1 1 PULSG0# 1 1 X High/open (CMOS/N-channel open drain) The relationship between the port settings and pin states for enabling the PULSG1 output from pin P32 is summarized below. Register Data P32 P32DDR P32 State POEN1 0 1 0 Low 0 1 1 PULSG1 1 1 X High/open (CMOS/N-channel open drain) 3-96 LC870800 Chapter 3 4) The relationship between the port settings and pin states for enabling the PULSG1# output from pin P33 is summarized below. Register Data P33DDR POEN1# 0 1 0 0 1 1 PULSG1# X High/open (CMOS/N-channel open drain) 1 5) P33 State P33 1 Low The relationship between the port settings and pin states for enabling the PULSG2 output from pin P34 is summarized below. Register Data 6) P34 State P34 P34DDR POEN2 0 1 0 Low 0 1 1 PULSG2 1 1 X High/open (CMOS/N-channel open drain) The relationship between the port settings and pin states for enabling the PULSG2# output from pin P35 is summarized below. Register Data P35 State P35 P35DDR POEN2# 0 1 0 Low 0 1 1 PULSG2# 1 1 X High/open (CMOS/N-channel open drain) 3-97 MCPWM 3.14.6 Timing Charts 3.14.6.1 Mode 0 The polarity of PULSGi/PULSGi# outputs is positive (OPOL=OPOLB=0). PWMEN MCPWMi NMCPWMi (i=0,1,2) PiMTB-0 DTIM7-0 DTIM7-0 PPRDB-0 1 cycle <PiOMD2-0=100→000> PiOMD2-0 Buffer register 100 000 101 001 110 010 111 001 PULSGi PULSGi# <PiOMD2-0=101→001> PiOMD2-0 Buffer register PULSGi PULSGi# <PiOMD2-0=110→010> PiOMD2-0 Buffer register PULSGi PULSGi# <PiOMD2-0=111→001> PiOMD2-0 Buffer register PULSGi PULSGi# DTIM7-0 DTIM7-0 <Automaic AD start mode timing> ADMD0 (ADMRC, bit 3)=1 PRDRQ Soft processing Soft processing Soft processing ATRGEN ADSTART （ADCRC, bit 2） Automatic AD conversion started 3-98 Automatic AD conversion started LC870800 Chapter 3 Notes: • The PWM period (PPRDB to PPRD0) is set to 1 cycle. • The dead time (PULSGi=PULSGi#=0)(i=0,1,2) is inserted at the following timings: 1) An MCPWM operation is started. 2) The MCPWMi output mode is changed. • If the MCPWMi output mode is set to 100 or 111, the dead time is inserted at the timings 3), 4), and 5) below in addition to the above-mentioned timings 1) and 2). 3) Immediately before the rising edge of MCPWMi and immediately after the falling edge. 4) The duty cycle is changed from 0％ (PiMTB0≧PPRDB0) to around 100％ (PiMTB0<DTIM70). PiMTB-0 Match buffer register MCPWMi PiMTB-0≧PPRDB-0 PiMTB-0＜DTIM7-0 NMCPWMi (i=0,1,2) DTIM7-0 PiMTB-0 PiMTB-0 PiMTB-0 PPRDB-0 5) The duty cycle is changed from 0％ (PiMTB0≧PPRDB-0) to a point other than 0％ (DTIM7-0<PiMTB-0<PPRDB-0). PiMTB-0 Match buffer register MCPWMi PiMTB-0≧PPRDB-0 PiMTB-0＜DTIM7-0 NMCPWMi (i=0,1,2) PPRDB-0 DTIM7-0 DTIM7-0 DTIM7-0 PiMTB-0 PiMTB-0 PiMTB-0 • When the automatic AD start mode is set, the next automatic AD start signal issued while AD conversion is in progress cannot be accepted. • To start the next automatic start processing after terminating the existing AD conversion when the automatic AD start mode is set, clear bit 1 (AD conversion end flag) of the ADCRC register in advance. No further automatic start signals can be accepted when bit 1 of the ADCRC register is set to 1. 3-99 MCPWM 3.14.6.2 Mode 1 The polarity of PULSGi/PULSGi# outputs is positive (OPOL=OPOLB=0). PWMEN MCPWMi NMCPWMi (i=0,1,2) DTIM7-0 DTIM7-0 PiMTB-0 PPRDB-0 1/2 cycle PiMTB-0 PPRDB-0 1/2 cycle 1 cycle <PiOMD2-0=100→000> PiOMD2-0 Buffer register 100 000 101 001 110 010 111 001 PULSGi PULSGi# <PiOMD2-0=101→001> PiOMD2-0 Buffer register PULSGi PULSGi# <PiOMD2-0=110→010> PiOMD2-0 Buffer register PULSGi PULSGi# <PiOMD2-0=111→001> PiOMD2-0 Buffer register PULSGi PULSGi# DTIM7-0 DTIM7-0 <Automatic AD start mode timing> ADMD0 (ADMRC, bit 3)=1 HPRDRQ Soft processing Soft processing Soft processing PRDRQ ATRGEN ADSTART (ADCRC, bit 2） 3-100 Automatic AD conversion started LC870800 Chapter 3 Notes: • The PWM period (PPRDB to PPRD0) is set to 1/2 cycle. • The dead time (PULSGi=PULSGi#=0)(i=0,1,2) is inserted at the following timings: 1) An MCPWM operation is started. 2) The MCPWMi output mode is changed. • If the MCPWMi output mode is set to 100 or 111, the dead time is inserted at the timings 3), 4), and 5) below in addition to the above-mentioned timings 1) and 2). 3) Immediately before the rising edge of MCPWMi and immediately after the falling edge. 4) The duty cycle is changed from a point other than around 100% (PiMTB0≧DTIM70) to around 100% (PiMTB0<DTIM70). PiMTB-0 Match buffer register PiMTB-0≧DTIM7-0 PiMTB-0＜DTIM7-0 MCPWMi NMCPWMi (i=0,1,2) DTIM7-0 PiMTB-0 DTIM7-0 DTIM7-0 PiMTB-0 PiMTB-0 PiMTB-0 PPRDB-0 5) The dead time is inserted when the duty cycle is changed from around 100% (PiMTB0<DTIM70) to a point other than around 100% (PiMTB0≧DTIM70). In the case of 5), the dead time may be longer than in normal cases (2 times maximum). PiMTB-0 Match buffer register PiMTB-0＜DTIM7-0 PiMTB-0≧DTIM7-0 MCPWMi NMCPWMi (i=0,1,2) PiMTB-0 PiMTB-0 DTIM7-0 DTIM7-0 PiMTB-0 PiMTB-0 PPRDB-0 • When the automatic AD start mode is set, the next automatic AD start signal issued while AD conversion is in progress cannot be accepted. • To start next automatic start processing after terminating the existing AD conversion when the automatic AD start mode is set, clear bit 1 (AD conversion end flag) of the ADCRC register in advance. No further automatic start signals can be accepted when bit 1 of the ADCRC register is set to 1. 3-101 CMP/AMP 3.15 Analog Comparator/Amplifier (CMP/AMP) 3.15.1 Overview This series of microcontrollers is provided with two channels of internal analog comparator/amplifier circuits that accept external inputs. The output of the analog comparator can be used to force the MCPWM output to be stopped. The output from the amplifier can be used as input to the AD converter. 3.15.2 Functions 1) Analog comparator • Generates, out of pin P14, the result of comparing the minus input from pin P13 with the plus input from pin P12. • Generates, out of pin P17, the result of comparing the minus input from pin P16 with the plus input from pin P15. 2) Amplifier • Takes in the minus input from pin P13 and plus input from P12 and generates the amplified output from pin P14. • Takes in the minus input from pin P16 and plus input from P15 and generates the amplified output from pin P17. • The amplifier output can be selected as an input signal to the AD converter. 3) Interrupt generation • Generates a comparator 1 interrupt request on detection of the rising/falling edge of the comparator 1 output if the comparator 1 interrupt enable bit is set. • Generates a comparator 2 interrupt request on detection of the rising/falling edge of the comparator 2 output if the comparator 2 interrupt enable bit is set. • The comparator 1 and comparator 2 interrupt sources are used to force the MCPWM output to be stopped. 4) It is necessary to manipulate the following special function registers to control the analog comparator/ amplifier. • CPAPCR1, CPAPCR2 Address Initial value R/W Name FEA0 000H 0000 R/W CPAPCR1 FEA1 000H 0000 R/W CPAPCR2 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 CPAP1EN CPAP1SL CP1OUTEN - CMP1OUT CMP1EG CMP1IF CMP1IE CPAP2EN CPAP2SL CP2OUTEN - CMP2OUT CMP2EG CMP2IF CMP2IE * Bit 3 (CMP1OUT, CMP2OUT) is read-only. 3.15.3 Circuit Configuration 3.15.3.1 1) Comparator 1/amplifier 1 control register (CPAPCR1) (7-bit register) This register controls the operation and interrupts of the comparator 1/amplifier 1. 3.15.3.2 1) Comparator 2/amplifier 2 control register (CPAPCR2) (7-bit register) This register controls the operation and interrupts of the comparator 2/amplifier 2. 3-102 LC870800 Chapter 3 3.15.3.3 1) Comparator (2 channels) These analog comparator circuits take in external inputs as their input signals. 3.15.3.4 1) Amplifier (2 channels) These amplifier circuits take in external inputs as their input signals. Comparator 1 P12 P13 ＋ Comparator 1 interrupt － CMP1OUT To P14 ＋ Amplifier 1 To AD converter To P14 － Comparator 1/amplifier 1 control register Comparator 2 P15 P16 ＋ Comparator 2 interrupt CMP2OUT To P17 － ＋ Amplifier 2 To AD converter To P17 － Comparator 2/amplifier 2 control register Figure 3.15.1 Analog Comparator/Amplifier Block Diagram 3-103 CMP/AMP 3.15.4 Related Registers 3.15.4.1 1) Comparator 1/amplifier 1 control register (CPAPCR1) This register is a 7-bit register that is used to control the operation and interrupts of the comparator 1/ amplifier 1. Address Initial value FEA0 000H 0000 R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 R/W CPAPCR1 CPAP1EN CPAP1SL CP1OUTEN - CMP1OUT CMP1EG CMP1IF CMP1IE * Bit 3 (CMP1OUT) is read-only. CPAP1EN (bit 7): Comparator 1/amplifier 1 operation control CPAP1SL (bit 6): Comparator 1/amplifier 1 select CPAP1EN 0 CPAP1SL 0 Comparator 1 Stop Amplifier 1 Stop 0 1 Stop Stop 1 0 Start Stop 1 1 Stop Start When the amplifier 1 is started, the output buffer for pin P14 is disabled and the amplifier 1 output is transmitted from pin P14. CP1OUTEN (bit 5): Comparator 1 output (P14) control When this bit is set to 0, the comparator 1 output (P14) is not output. When this bit is set to 1, the comparator 1 output (P14) is output. The output, however, is held low when the comparator 1 is stopped. CP1OUTEN P14FCR P14 0 0 － P14 Pin Data in Output Mode (P14DDR＝1） Value of port data latch (P14) 0 1 0 SIO1 output data 0 1 1 High output 1 0 0 Comparator 1 output 1 0 1 High output 1 1 － Inhibited CMP1OUT (bit 3): Comparator 1 output data Reading this bit makes the comparator 1 output data available. This bit is read-only. A 0 is read when the comparator 1 is stopped. CMP1EG (bit 2): Comparator 1 interrupt source control Setting this bit to 0 selects the falling edge detection mode for the comparator 1 interrupt source. Setting this bit to 1 selects the rising edge detection mode for the comparator 1 interrupt source. The setting in this bit is invalid when the comparator 1 is stopped. CMP1IF (bit 1): Comparator 1 interrupt source This bit is set when the comparator 1 output edge set by the comparator 1 interrupt source control is detected. The bit is not set, however, if the comparator 1 is stopped. This flag must be cleared with an instruction. 3-104 LC870800 Chapter 3 CMP1IE (bit 0): Comparator 1 interrupt enable control An interrupt request to vector address 004BH is generated when this bit and CMP1IF are set to 1. 3.15.4.2 1) Comparator 2/amplifier 2 control register (CPAPCR2) This register is a 7-bit register that is used to control the operation and interrupts of the comparator 2/ amplifier 2. Address Initial value FEA1 000H 0000 R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 R/W CPAPCR2 CPAP2EN CPAP2SL CP2OUTEN - CMP2OUT CMP2EG CMP2IF CMP2IE * Bit 3 (CMP2OUT) is read-only. CPAP2EN (bit 7): Comparator 2/amplifier 2 operation control CPAP2SL (bit 6): Comparator 2/amplifier 2 select CPAP2EN 0 CPAP2SL 0 Comparator 2 Stop Amplifier 2 Stop 0 1 Stop Stop 1 0 Start Stop 1 1 Stop Start When the amplifier 2 is started, the output buffer for pin P17 is disabled and the amplifier 2 output is transmitted from pin P17. CP2OUTEN (bit 5): Comparator 2 output (P17) control When this bit is set to 0, the comparator 2 output (P17) is not output. When this bit is set to 1, the comparator 2 output (P17) is output. The output, however, is held low when the comparator 2 is stopped. CP2OUTEN P17FCR P17 0 0 － P1n Pin Data in Output Mode (P1nDDR＝1） Value of port data latch (P17） 0 1 0 Timer 1 PWMH 0 1 1 PWMH inverted data of timer 1 1 0 0 Comparator 2 output 1 0 1 Comparator 2 output inverted data 1 1 － Inhibited CMP2OUT (bit 3): Comparator 2 output data Reading this bit makes the comparator 2 output data available. This bit is read-only. A 0 is read when the comparator 2 is stopped. CMP2EG (bit 2): Comparator 2 interrupt source control Setting this bit to 0 selects the falling edge detection mode for the comparator 2 interrupt source. Setting this bit to 1 selects the rising edge detection mode for the comparator 2 interrupt source. The setting in this bit is invalid when the comparator 2 is stopped. CMP2IF (bit 1): Comparator 2 interrupt source This bit is set when the comparator 2 output edge set by the comparator 2 interrupt source control is detected. The bit is not set, however, if the comparator 2 is stopped. This flag must be cleared with an instruction. CMP2IE (bit 0): Comparator 2 interrupt enable control An interrupt request to vector address 004BH is generated when this bit and CMP2IF are set to 1. 3-105 CMP/AMP 3-106 LC870800 Chapter 4 4. Control Functions 4.1 Interrupt Function 4.1.1 Overview This series of microcontrollers has the capacity to control three levels of multiple interrupts, i.e., low level (L), high level (H), and highest level (X). The master interrupt enable and interrupt priority control registers are used to enable or disable interrupts and determine the priority of interrupts. 4.1.2 Functions 1) Interrupt processing • Peripheral modules generate an interrupt request to the predetermined vector address when the interrupt request and interrupt request enable flags are set to 1. • When the microcontroller receives an interrupt request from a peripheral module, it determines the interrupt level, priority and interrupt enable status. If the interrupt request is legitimate for processing, the microcontroller saves the value of PC in the stack and causes a branch to the predetermined vector address. • The return from the interrupt routine is accomplished by the RETI instruction, which restores the old state of the PC and interrupt level. 2) Multilevel interrupt control • The interrupt function supports three levels of interrupts, that is, the low level (L), high level (H), and highest level (X). The interrupt function will not accept any interrupt request of the same level or lower level than that of the interrupt that is currently being processed. 3) Interrupt priority • When interrupt requests to two or more vector addresses occur at the same time, the interrupt request of the highest level takes precedence over the other interrupt requests. Among the interrupt requests of the same level, the one whose vector address is the smallest has priority. 4) Interrupt request enable control • The master interrupt enable register can be used to control the enabling/disabling of H- and L-level interrupt requests. • Interrupt requests of the X level cannot be disabled. 5) Interrupt disable period • Interrupts are held disabled for a period of 2Tcyc after a write is made to the IE (FE08H) or IP (FE09H) register, or HOLD mode is released. • No interrupt can occur during the interval between the execution of an instruction that loads the PCON (FE07H) register and the execution of the next instruction. • No interrupt can occur during the interval between the execution of a RETI instruction and the execution of the next instruction. 4-1 Interrupt 6) Interrupt level control • Interrupt levels can be selected on a vector address basis. Table of Interrupts No. 1 Vector Address 00003H Selectable Level X or L Interrupt Sources 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4 4 0001BH H or L INT3/base timer 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0/UART1 receive/MCPWM 8 0003BH H or L SIO1/UART1 transmit 9 00043H H or L ADC/T6/T7 10 0004BH H or L Port 0/CMP1/CMP2 INT0 • Priority levels: X H L • When interrupts of the same level occur at the same time, the interrupt with the smallest vector address is given priority. 7) It is necessary to manipulate the following special function registers to enable interrupts and to specify their priority. • IE, IP Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE08 0000 HH00 R/W IE IE7 XFLG HFLG LFLG - - XCNT1 XCNT0 FE09 0000 0000 R/W IP IP4B IP43 IP3B IP33 IP2B IP23 IP1B IP13 4.1.3 Circuit Configuration 4.1.3.1 1) 2) 3) Master interrupt enable control register (IE) (6-bit register) This register enables and disables H- and L-level interrupts. The interrupt level flag of the register can be read. The register selects the level (L or X) of interrupts to vector addresses 00003H and 0000BH. 4.1.3.2 1) Interrupt priority control register (IP) (8-bit register) This register selects the level (H or L) of interrupts to vector addresses 00013H to 0004BH. 4-2 LC870800 Chapter 4 4.1.4 4.1.4.1 1) Related Registers Master interrupt enable control register (IE) This register is a 6-bit register for controlling the interrupts. Bits 6 to 4 are read only. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE08 0000 HH00 R/W IE IE7 XFLG HFLG LFLG - - XCNT1 XCNT0 IE7 (bit 7): H-/L-level interrupt enable/disable control • A 1 in this bit enables H- and L-level interrupt requests to be accepted. • A 0 in this bit disables H- and L-level interrupt requests to be accepted. • X-level interrupt requests are always enabled regardless of the state of this bit. XFLG (bit 6): X-level interrupt flag (R/O) • This bit is set when an X-level interrupt is accepted and reset when execution returns from the processing of the X-level interrupt. • This bit is read only. No instruction can rewrite the value of this bit directly. HFLG (bit 5): H-level interrupt flag (R/O) • This bit is set when an H-level interrupt is accepted and reset when execution returns from the processing of the H-level interrupt. • This bit is read only. No instruction can rewrite the value of this bit directly. LFLG (bit 4): L-level interrupt flag (R/O) • This bit is set when an L-level interrupt is accepted and reset when execution returns from the processing of the L-level interrupt. • This bit is read only. No instruction can rewrite the value of this bit directly. (Bits 3, 2): These bits do not exist. They are always read as 1. XCNT1 (bit 1): 0000BH interrupt level control flag • A 1 in this bit sets all interrupts to vector address 0000BH to the L-level. • A 0 in this bit sets all interrupts to vector address 0000BH to the X-level. XCNT0 (bit 0): 00003H interrupt level control flag • A 1 in this bit sets all interrupts to vector address 00003H to the L-level. • A 0 in this bit sets all interrupts to vector address 00003H to the X-level. 4-3 Interrupt 4.1.4.2 1) Interrupt priority control register (IP) This register is an 8-bit register that selects the interrupt level (H/L) of interrupts to vector addresses 00013H to 0004BH. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE09 0000 0000 R/W IP IP4B IP43 IP3B IP33 IP2B IIP23 IP1B IP13 7 6 5 4 3 2 1 0 Interrupt Vector Address IP Bit 0004BH IP4B 00043H 0003BH 00033H 0002BH 00023H 0001BH 00013H Value 0 IP43 IP3B IP33 IP2B IP23 IP1B IP13 4-4 Interrupt Level L 1 H 0 L 1 H 0 L 1 H 0 L 1 H 0 L 1 H 0 L 1 H 0 L 1 H 0 L 1 H LC870800 Chapter 4 4.2 System Clock Generator Function 4.2.1 Overview This series of microcontrollers incorporates four systems of oscillator circuits, i.e., a main clock oscillator, a subclock oscillator, a medium-speed RC oscillator, and a high-speed RC oscillator as system clock generator circuits. The medium-speed RC and high-speed RC oscillator circuits have internal resistors and capacitors, so that no external circuit is required. The system clock can be selected from these four types of clock sources under program control. 4.2.2 Functions 1) System clock select • Allows the system clock to be selected under program control from four types of clocks generated by the main clock oscillator, subclock oscillator, medium-speed RC oscillator, and high-speed RC oscillator. 2) System clock frequency division • Divides the frequency of the oscillator clock selected as the system clock and supplies the resultant clock to the system as the system clock. • The frequency divider circuit has two stages 1 1 and . The first stage allows the selection of division ratios of 1 The second stage allows the selection of division ratios of 1 . and 2 1 1 , 1 2 , 1 4 , 1 , 1 8 16 , 1 32 , 1 64 , 128 3) Oscillator circuit control • Allows the start/stop control of the four systems of oscillators to be executed independently through microcontroller instructions. The main clock and subclock oscillator circuits share pins (CF1/XT1 and CF2/XT2) and cannot be used at the same time. 4) Multiplexed input pin function • The CF oscillation/crystal oscillation pins (CF1/XT1 and CF2/XT2) can also be used as general-purpose input ports. 5) Oscillator circuit states and operating modes Mode/Clock Main Clock Mediumspeed RC Oscillator Subclock High-speed RC System Clock Oscillator Reset Stopped Stopped Running Stopped Reset released Stopped Stopped Running Stopped Normal mode HALT Programmable State established at entry time Stopped State established at entry time Programmable State established at entry time Stopped State established at entry time Programmable State established at entry time Stopped Running Programmable State established at entry time Stopped Stopped HOLD Immediately after exit from HOLD mode X'tal HOLD Immediately after exit from X'tal HOLD mode Stopped State established Stopped Stopped at entry time State established State established State established State established at at entry time at entry time at entry time entry time Medium-speed RC oscillator Medium-speed RC oscillator Programmable State established at entry time Stopped Medium- speed RC oscillator Stopped State established at entry time See Section 4.4,"Standby Function," for the procedures to enter and exit the microcontroller operating modes. 4-5 System Clock ● Reset ・Main clock stopped. ●リセット ・Subclock stopped ・メインクロック動作 ・Medium-speed RC oscillator ・サブクロック停止 started ・RC 発振動作 ・High-speed ・周波数可変RC RCoscillator 発振停止 stopped ● HOLD mode ・All oscillators stopped. ・Since the OCR register, bits 1, 4, and 5 are cleared, the medium-speed RC oscillator is activated and designated as the system clock when HOLD mode is released. ・Since the OCR2 register bit 6 is cleared, the high-speed RC oscillator is stopped when HOLD mode is released. 6) ● X'tal HOLD mode ・The main clock, medium-speed RC oscillator, and high-speed RC oscillator are stopped. The subclock retains the state established when X'tal HOLD mode is entered. ・The contents of the OCR and OCR2 registers remain unchanged. ・The microcontroller enters this mode after selecting the subclock or medium-speed RC oscillator as the system clock source. ・When X'tal HOLD mode is exited, the oscillators return to the state established when the mode is entered. ● Normal operating mode ・Start/stop of oscillators programmable ● HALT mode ・All oscillators retain the state established when HALT mode is entered. It is necessary to manipulate the following special function registers to control the system clock. • PCON, OCR, CLKDIV, XT2PC, P1TST, CFLVM, OCR2 Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE07 HHHH H000 R/W PCON - - - - - XTIDLE PDN IDLE FE0C HHHH H000 R/W CLKDIV - - - - - CLKDV2 CLKDV1 CLKDV0 FE0E 0000 XX00 R/W OCR FE43 HHHH 0H00 R/W XT2PC - - - FE47 000H HHH0 R/W P1TST FIX0 FIX0 FE57 HHH0 HH00 R/W CFLVM - - FE7C 00HH HHHH R/W OCR2 4.2.3 4.2.3.1 1) 2) 3) 4.2.3.2 1) 2) 3) CLKSGL EXTOSC CLKCB5 CLKCB4 FRCSEL FRCSTART XT2IN XT1IN - XTCFSEL - RCSTOP CFSTOP MRCSFT - - - - FIX0 - CFMON - - FIX0 FIX0 - - - - - - XT2PCB1 XT2PCB0 Circuit Configuration Main clock oscillator circuit The main clock oscillator circuit is prepared for oscillation by connecting a ceramic resonator and a capacitor to the CF1/XT1 and CF2/XT2 pins and controlling the OCR and XT2PC registers. The data at the CF1/XT1 and CF2/XT2 pins can be read as bits 2 and 3 of the OCR register. The general-purpose input port configuration must be selected and the CF1/XT1 and CF2/XT2 pins must be connected to VSS1 when neither the main clock nor the subclock is to be used or these pins are not to be used as general-purpose input ports. Subclock oscillator circuit The subclock oscillator circuit is prepared for oscillation by connecting a crystal resonator (32.768 kHz standard), a capacitor and a damping resistor to the CF1/XT1 and CF2/XT2 pins and controlling the OCR and XT2PC registers. The data at the CF2/XT2 pin can be read as bit 3 of the OCR register. The data at the CF1/XT1 pin is not read as bit 2 of the OCR register. The general-purpose input port configuration must be selected and the CF1/XT1 and CF2/XT2 pins must be fixed to a high or low level when neither the main clock nor the subclock is to be used or these pins are not to be used as general-purpose input ports. 4-6 LC870800 Chapter 4 4.2.3.3 1) 2) 4.2.3.4 1) 2) 3) 4) Internal medium-speed RC oscillator circuit (conventional RC oscillator circuit) The medium-speed RC oscillator circuit oscillates according to the internal resistor and capacitor (at 1 MHz standard). The clock from the medium-speed RC oscillator is designated as the system clock after the reset is released or HOLD mode is exited . High-speed RC oscillator circuit The high-speed RC oscillator circuit oscillates according to the internal resistor and capacitor. The source oscillation frequency is 40 MHz. The highest clock rate setting is 20 MHz that is obtained by dividing the source oscillation frequency by 2. The circuit toggles out a clock each time the counter value matches the preset count value. The high-speed RC oscillator circuit is suited to generate a main clock that does not require the precision in frequency that the external CF oscillator would provide. 4.2.3.5 1) Power control register (PCON) (3-bit register) This register specifies the operating mode (normal/HALT/HOLD/X'tal HOLD). 4.2.3.6 1) 2) 3) 4) Oscillation control register (OCR) (8-bit register) This register controls the start/stop operations of the oscillator circuits. This register selects the system clock. The register sets the division ratio of the oscillator clock to be used as the system clock to The data at the CF1/XT1 and CF2/XT2 pins can be read as bits 2 and 3 of this register. 4.2.3.7 1) CF1/XT1 and CF2/XT2 general-purpose port input control register (XT2PC) (8-bit register) This register controls the general-purpose input at the CF1/XT1 and CF2/XT2 pins. 4.2.3.8 1) 2) 3) High-speed RC oscillation control register (OCR2) (2-bit register) This register controls the start/stop operations of the high-speed RC oscillator circuit. The register selects either CF or high-speed RC oscillator as the main clock source. The register also defines the frequency of the high-speed RC oscillator clock. 4.2.3.9 1) System clock frequency division control register (CLKDIV) (3-bit register) This register controls the operation of the system clock divider circuit. 1 1 1 1 1 1 1 1 , , , and are available. The division ratios of , , , , 1 2 4 8 16 32 4-7 64 128 1 1 or 1 2 . System Clock CLKCB5, 4 FRCSEL CF oscillator 2 CF clock Selector CFSTOP High-speed RC oscillator FRCSTART MRCSFT Main clock CLKSGL CLKDV2 to 0 RC clock Subclock Subclock oscillator System clock SCLK fSCLK : System clock frequency fCYC : Cycle clock frequency （Minimum instruction cycle） fCYC = fSCLK /3 To base timer EXTOSC Divider (2) Internal mediumspeed RC oscillator Selector RCSTOP Divider (1) 3 Fig. 4.2.1 System Clock Generator Block Diagram 4.2.4 Related Registers 4.2.4.1 1) Power control register (PCON) (3-bit register) This register is a 3-bit register used to specify the operating mode (normal/HALT/HOLD/X'tal HOLD). • See Section 4.4, "Standby Function," for the procedures to enter and exit the microcontroller operating modes. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE07 HHHH H000 R/W PCON - - - - - XTIDLE PDN IDLE (Bits 7 to 3): These bits do not exist. They are always read as 1. XTIDLE (bit 2): X'tal HOLD mode setting flag PDN (bit 1): HOLD mode setting flag 1) XTIDLE - PDN 0 Operating mode Normal or HALT mode 0 1 HOLD mode 1 1 X'tal HOLD mode These bits must be set with an instruction. • When the microcontroller enters HOLD mode, all oscillations (main clock, subclock, mediumspeed RC) are suspended and bits 1, 4, and 5 of the OCR are cleared. • When the microcontroller exits HOLD mode, medium-speed RC oscillator starts operation and is designated as the system clock source. The main clock and subclock returns to the state that is established before the microcontroller enters HOLD mode. The high-speed RC oscillator stops operation. 4-8 LC870800 Chapter 4 2) 3) 4) • When the microcontroller enters X'tal HOLD mode, all oscillations except XT (i.e., main clock and medium-speed RC) are suspended but the state of the OCR register remains unchanged. • Since X'tal HOLD mode is used usually for low-current clock counting, less current will be consumed if the system clock is switched to the subclock and medium-speed RC oscillation is suspended before X'tal HOLD mode is entered. XTIDLE must be cleared with an instruction. PDN is cleared when a HOLD mode release signal (INT0, INT1, INT2, INT4, or P0INT) or a reset signal occurs. Bit 0 is automatically set when PDN is set. IDLE (bit 0): HALT mode setting flag 1) Setting this bit places the microcontroller into HALT mode. 2) This bit is automatically set when bit 1 is set. 3) This bit is cleared on acceptance of an interrupt request or on receipt of a reset signal. 4.2.4.2 1) Oscillation control register (OCR) (8-bit register) This register is an 8-bit register that controls the operation of the oscillator circuits, selects the system clock, and reads data from the CF1/XT1 and CF2/XT2 pins. Except for read-only bits 3 and 2, all bits of this register can be read or written. Address Initial value R/W Name FE0E 0000 XX00 R/W OCR BIT7 BIT6 BIT5 BIT4 CLKSGL EXTOSC CLKCB5 CLKCB4 BIT3 BIT2 XT2IN XT1IN BIT1 BIT0 RCSTOP CFSTOP CLKSGL (bit 7): Clock division ratio select 1) When this bit is set to 1, the clock selected by bits 4 and 5 is used as the system clock as is. 1 of the clock selected by bits 4 and 5 is 2) When this bit is set to 0, the clock having a clock rate of 2 used as the system clock. EXTOSC (bit 6): CF1/XT1 and CF2/XT2 function control 1) When this bit is set to 1 and CFSTOP (bit 0) is set to 1, the CF1/XT1 and CF2/XT 2 pins serve as the pins for subclock oscillation and prepare for oscillation when a crystal resonator (32.768 kHz standard), capacitors, and damping resistors are connected. When the OCR register is read in this case, bit 3 reads the data at the CF2/XT2 pin, and bit 2 does not read the data at the CF1/XT1 pin but reads 0. 2) When this bit is set to 0 and XTCFSEL (XT2PC register, bit 3) is set to 1, the CF1/XT1 and CF2/XT2 pins serve as the pins for main clock oscillation and prepare for oscillation when a ceramic resonator, capacitors, feedback resistors, and damping resistors are connected. Start/stop control of the main clock oscillation is provided by CFSTOP (bit 0). When the OCR register is read in this case, bit 3 reads the data at the CF2/XT2 pin and bit 2 reads the data at the CF1/XT1 pin. CLKCB5 (bit 5): System clock select CLKCB4 (bit 4): System clock select 1) CLKCB5 and CLKCB4 are used to select the system clock. 2) CLKCB5 and CLKCB4 are cleared at reset time or when HOLD mode is entered. 4-9 System Clock CLKCB5 0 CLKCB4 0 System clock Medium-speed RC oscillator 0 1 Main clock 1 0 Subclock 1 1 Main clock XT2IN (bit 3): CF2/XT2 pin data (read-only) XT1IN (bit 2): CF1/XT1 pin data (read-only) 1) Data that can be read via XT1IN varies as shown in the table below according to the value of EXTOSC (bit 6). RCSTOP (bit 1): Internal medium-speed RC oscillator circuit control 1) Setting this bit to 1 stops the oscillation of the internal medium-speed RC oscillator circuit. 2) Setting this bit to 0 starts the oscillation of the internal medium-speed RC oscillator circuit. 3) When a reset occurs, this bit is cleared and the internal RC oscillator circuit is enabled for oscillation. 4) When the microcontroller enters HOLD mode, this bit is cleared and the oscillator starts oscillation and is designated as the system clock source when the microcontroller exits HOLD mode. CFSTOP (bit 0): Main clock oscillator circuit control 1) Setting this bit to 1 stops the oscillation of the main clock oscillator circuit. 2) Setting this bit to 0 starts the oscillation of the main clock oscillator circuit. 3) This bit is cleared on a reset. EXTOSC CFSTOP XT2PC Register XTCFIN 0 0 1 Main clock oscillator running 0 1 1 Main clock oscillator stopped 1 1 X Subclock oscillator running 1 0 X Inhibited 0 0 0 General-purpose input OCR Register 4.2.4.3 1) OCR Register CF1/XT1， CF2/XT2 State XT2IN CF2/XT2 pin data CF2/XT2 pin data CF2/XT2 pin data CF2/XT2 pin data CF2/XT2 pin data XT1IN CF1/XT1 pin data CF1/XT1 pin data 0 is read 0 is read CF1/XT1 pin data Main clock oscillation control register (XT2PC) (3-bit register) This register is a 3-bit register that controls the main clock oscillation. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 FE43 HHHH 0H00 R/W XT2PC - - - - XTCFSEL - BIT1 BIT0 XT2PCB1 XT2PCB0 XTCFSEL (bit 3): CF1/XT1 and CF2/XT2 input control 1) This bit and EXTOSC (OCR register: FE0EH, bit 6) and CFSTOP (OCR register: FE0EH, bit 0) are used to select the function of the CF1/XT1 and CF2/XT2 pins from among the main clock, subclock, and general-purpose input port pins. (See 4.2.4.2, "Oscillation control register," for details.) XT2PCB1 to XT2PCB0 (bits 1 to 0): General-purpose flags These bits can be used as general-purpose flag bits. Any manipulation of these bits exerts no influence on the operation of this function block. 4-10 LC870800 Chapter 4 4.2.4.4 1) High-speed RC oscillation control register (OCR2) (2-bit register) This register is a 2-bit register that controls the operation of the high-speed RC oscillator circuit and selects the main clock. Address Initial value R/W Name FE7C 00HH HHHH R/W OCR2 BIT7 BIT6 FRCSEL FRCSTART BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 - - - - - - FRCSEL (bit 7): High-speed RC oscillator clock select 1) When this bit is set to 1, the clock output from the high-speed RC oscillator is selected as the main clock. The high-speed RC oscillator clock will be the system clock if the main clock is selected as the system clock in the above-mentioned OCR register. 2) When this bit is set to 0, the high-speed RC oscillator clock is not selected as the main clock; CF is designated as the main clock. 3) This bit is cleared when the microcontroller enters HOLD mode. FRCSTART (bit 6): High-speed RC oscillation start control 1) A 1 in this bit starts the high-speed RC oscillator circuit. 2) A 0 in this bit stops the high-speed RC oscillator circuit. 3) This bit is cleared when the microcontroller enters HOLD mode. Note: When switching the system clock, secure an oscillation stabilization time of 100 μs or longer after the high-speed RC oscillator circuit switches from the "oscillation stopped" to "oscillation enabled" state. 4.2.4.5 1) 2) P1TST register (P1TST) (4-bit register) MRCSFT, bit 5 of the P1TST register, controls the frequency shifting of the source oscillator clock from the high-speed RC oscillator circuit. This register is used to avoid adverse influences of radiation noise caused by the source oscillator clock. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE47 000H HHH0 R/W P1TST FIX0 FIX0 MRCSFT - - - - FIX0 FIX0 (bits 7, 6, and 0): These bits are used for testing only. They must always be set to 0. MRCSFT (bit 5): Controls the frequency shift of the source oscillator clock from the high-speed RC oscillator circuit 1) A 0 in this bit initializes the source oscillator clock frequency. 2) A 1 in this bit shifts the frequency of the source oscillator clock slightly to a lower frequency. (Bits 4, 3, and1): These bits do not exist. They are always read as 1. 4-11 System Clock 4.2.4.6 1) System clock divider control register (CLKDIV) (3-bit register) This register controls the frequency division processing of the system clock. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 FE0C HHHH H000 R/W CLKDIV - - - - - BIT2 (Bits 7 to 3): These bits do not exist. They are always read as 1. CLKDV2 (bit 2): CLKDV1 (bit 1): CLKDV0 (bit 0): Define the division ratio of the system clock. CLKDV2 CLKDV1 CLKDV0 0 0 0 0 0 1 1 1 1 2 0 1 0 1 4 0 1 1 1 8 1 0 0 1 16 1 0 1 1 32 1 1 0 1 64 1 1 1 1 128 4-12 BIT1 BIT0 CLKDV2 CLKDV1 CLKDV0 Division Ratio LC870800 Chapter 4 4.3 CF Oscillation (Main Clock) Monitoring Function 4.3.1 Overview The CF oscillation monitor function checks the CF oscillator circuit for normal oscillation when the microcontroller switches the system clock source to the CF oscillator for the main clock. This precludes system deadlock and other system malfunctions from being incurred by any abnormalities that occur in the CF oscillator circuit. 4.3.2 Functions 1) Main clock oscillation counter • 9-bit binary counter to monitor the operating state of the CF oscillator circuit 2) CF oscillation monitor register • Used to start and stop CF oscillation monitoring and to check the operating state of the oscillator circuit 3) It is necessary to manipulate the following special function register to control the CF oscillation monitoring function. • CFLVM Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE57 HHH0 HH00 R/W CFLVM - - - CFMON - - FIX0 FIX0 4.3.3 Circuit Configuration The CF oscillation monitor circuit consists of a 9-bit binary counter for monitoring CF oscillation and the CF oscillation monitor register (CFLVM) that controls the binary counter. When the monitor bit of the CF oscillation monitor register is set, the 9-bit binary counter starts counting the number of CF oscillator clocks. As CF oscillation continues normally, an overflow eventually occurs in the counter, which resets the monitor bit, indicating that oscillation is continuing normally. 4.3.4 Related Register 4.3.4.1 CF oscillation monitor register (CFLVM) 1) (3-bit register) This register is a 3-bit register that is used to control CF oscillation monitoring operation. Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE57 HHH0 HH00 R/W CFLVM - - - CFMON - - FIX0 FIX0 (Bits 7 to 5, 3, 2): These bits do not exist. They are always read as 1. 4-13 CF Oscillation Monitor CFMON (bit 4): CF oscillation monitoring control Setting this bit to 1 starts monitoring CF oscillation. This bit is eventually reset to 0 if the CF oscillation continues normally. This bit must be reset to 0 to stop monitoring CF oscillation. The period during which CF oscillator clocks are to be counted is calculated as follows: CF monitoring count time= Source oscillation period 512 FIX0 (bit 1): Fixed bit This bit must always be set to 0. FIX0 (bit 0): Fixed bit This bit must always be set to 0. 4.3.5 1) 2) 3) 4) CF Oscillation Monitoring Example When the power is turned on, at system reset time, or exit from HOLD mode • Switch the system clock to internal RC oscillation and start monitoring. Oscillation start time of the CF oscillator circuit • Wait for several to several scores of milliseconds until the CF oscillator circuit for the main clock starts oscillation stably. Configuring for the initiation of CF oscillation monitoring and polling • Set the CFMON bit (bit 4) of the CF oscillation monitor register (CFLVM) to 1. • Poll the CFMON bit (bit 4); it will be reset to 0 in source oscillation period 512 if oscillation is continuing normally. • It is recommended that step 3) be repeated several times even when normal oscillation is once confirmed. If the confirmation of normal oscillation fails, the application in the set should recognize this condition as an oscillation error and take error recovery actions including error handling processing and continuation of step 3). Switching the system clock source to CF oscillation for the main clock. * Proceed with the next processing by the application. 4-14 LC870800 Chapter 4 4.4 Standby Function 4.4.1 Overview This series of microcontrollers supports three standby modes, i.e., HALT, HOLD, and X'tal HOLD modes, that are used to reduce current consumption at power-failure time or in program standby mode. In standby mode, the execution of all instructions is suspended. 4.4.2 Functions 1) HALT mode • The microcontroller suspends the execution of instructions but its peripheral circuits continue processing. Some serial transfer functions are suspended. • HALT mode is entered by setting bit 0 of the PCON register to 1. • Bit 0 of the PCON register is cleared and the microcontroller returns to the normal operating mode when a reset occurs or an interrupt request is accepted. 2) HOLD mode • All oscillations are suspended. The microcontroller suspends the execution of instructions and its peripheral circuits stop processing. • HOLD mode is entered by setting bit 1 of the PCON register to 1 when bit 2 is set to 0. In this case, bit 0 of the PCON register (HALT mode setting flag) is automatically set. • When a reset occurs or a HOLD mode release signal (INT0, INT1, INT2, INT4, or P0INT) occurs, bit 1 of the PCON register is cleared and the microcontroller switches into HALT mode. 3) X'tal HOLD mode • All oscillations except the subclock oscillation are suspended. The microcontroller suspends the execution of instructions and all the peripheral circuits except the base timer stop processing. • X’tal HOLD mode is entered by setting bit 1 of the PCON register to 1 when bit 2 is set to 1. In this case, bit 0 of the PCON register (HALT mode setting flag) is automatically set. • When a reset occurs or a HOLD mode release signal (base timer interrupt, remote control receiver interrupt, INT0, INT1, INT2, INT4, or P0INT) occurs, bit 1 of the PCON register is cleared and the microcontroller switches into HALT mode. Note: Do not allow the microcontroller to enter HALT, HOLD, or X'tal HOLD mode while AD conversion is in progress. Make sure that ADSTART is set to 0 before placing the microcontroller into one of the above-mentioned standby modes. 4-15 Standby 4.4.3 4.4.3.1 1) Related Registers Power control register (PCON) (3-bit register) This register is a 3-bit register that specifies the operating mode (normal/HALT/HOLD/X'tal HOLD). Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE07 HHHH H000 R/W PCON - - - - - XTIDLE PDN IDLE (Bits 7 to 3): These bits do not exist. They are always read as 1. XTIDLE (bit 2): X'tal HOLD mode setting flag PDN (bit 1): HOLD mode setting flag XTIDLE 1) 2) 3) 4) － PDN 0 Operating Mode Normal or HALT mode 0 1 HOLD mode 1 1 X'tal HOLD mode These bits must be set with an instruction. • When the microcontroller enters HOLD mode, all oscillations (main clock, subclock, medium-speed RC, and high-speed RC) are suspended and bits 1, 4 and 5 of the OCR register are cleared. • When the microcontroller exits HOLD mode, medium-speed RC oscillator resumes oscillation and is designated as the system clock source. The main clock and the subclock oscillator return to the states that are established before HOLD mode is entered. • When the microcontroller enters X’tal HOLD mode, all oscillations except XT (i.e., main clock, medium-speed RC, and high-speed RC) are suspended but the state of the OCR register remains unchanged. • Since X’tal HOLD mode is used usually for low-current clock counting or infrared remote control reception standby mode, less current will be consumed if the system clock is switched to the subclock and RC oscillation is suspended before X’tal HOLD mode is entered. XTIDLE must be cleared with an instruction. PDN is cleared when a HOLD mode release signal (INT0, INT1, INT2, INT4, or P0INT) or a reset occurs. Bit 0 is automatically set when PDN is set. IDLE (bit 0): HALT mode setting flag 1) Setting this bit places the microcontroller into HALT mode. 2) When bit 1 is set, this bit is automatically set. 3) This bit is cleared on acceptance of an interrupt request or on receipt of a reset signal. 4-16 LC870800 Chapter 4 Table 4.4.1 Standby Mode Operations Reset State HALT Mode Item/Mode HOLD Mode X'tal HOLD Mode Entry conditions RES applied Reset from watchdog timer PCON register Bit 1=0 Bit 0=1 Data changed on entry Initialized as shown in separate table. Main clock oscillation Stopped • If WDT register (FE79h), • If WDT register (FE79h), bits 4/3=0/1, WDTCNT, bits 4/3=0/1, WDTCNT, bit 5 is cleared. bit 5 is cleared. • PCON, bit 0 turns to 1. • PCON, bit 0 turns to 1. • OCR register (FE0E), bits 5 and 4 are cleared. State established at entry Stopped Stopped time PCON register Bit 2=0 Bit 1=1 PCON register Bit 2=1 Bit 1=1 If WDT register (FE79h), bits 4/3=0/1, WDTCNT, bit 5 is cleared. Running Internal medium-speed RC oscillation State established at entry Stopped time Stopped Subclock oscillation Stopped State established at entry Stopped time State established at entry time High-speed RC oscillation CPU I/O pin state RAM Stopped State established at entry time Stopped ← Data preserved Stopped Stopped Stopped ← Data preserved Stopped ← Data preserved Stopped State established at entry time Base timer and remote control receiver circuit Peripheral modules except base timer and remote control receiver circuit Exit conditions Returned mode Data changed on exit Initialized See Table 4.4.2. RES: Undefined When watchdog timer reset: Data preserved Stopped State established at entry time Stopped State established at entry Stopped time (Note 2) Stopped Entry conditions cancelled. • Interrupt request from • Interrupt request INT0 to INT2, INT4, or accepted. P0INT • Reset/entry conditions established • Reset/entry conditions established Normal mode None Normal mode (Note1) HALT (Note1) PCON register, bit 0＝0 PCON register, bit 1＝0 • Interrupt request from INT0 to INT2, INT4, P0INT, base timer, or remote control receiver circuit • Reset/entry conditions established HALT (Note1) PCON register, bit 1＝0 Note 1: The microcontroller switches into the reset state if it exits the current mode on the establishment of reset/entry conditions. Note 2: Some serial transfer functions are suspended. 4-17 Standby Table 4.4.2 Pin States and Operating Modes (This series) Pin Reset Time Normal Mode HALT Mode Name RES CF1 /XT1 • Input • CF oscillation inverter input • Oscillation not started • CF feedback resistor and XT feedback resistor off • CF oscillation inverter input/general-purpose input selected by bit 3 of register XT2PC (FE43H). • Oscillation enabled or disabled by register OCR (FE0EH). • Feedback resistor between CF1 and CF2 controlled by a program. CF2 /XT2 • Input pin • Oscillation not started • CF feedback resistor and XT feedback resistor off P00-P07 • Input mode • Pull-up resistor off P10-P17 • Input mode • Pull-up resistor off P20-P21 • Input mode • Pull-up resistor off P30-P35 • Input mode • Pull-up resistor off P70-P73 • Input mode • Pull-up resistor off • CF oscillation inverter intput/general-purpose input selected by bit 3 of register XT2PC (FE43H). • Oscillation enabled or disabled by register OCR (FE0EH). • Feedback resistor between CF1 and CF2 controlled by a program. • Input/output/pull-up resistor controlled by a program • Input/output/pull-up resistor controlled by a program • Input/output/pull-up resistor controlled by a program • Input/output/pull-up resistor controlled by a program • Input/output/pull-up resistor controlled by a program ← HOLD Mode • CF oscillation inverter input/general-purpose input is in the state established on entry into HOLD mode. • Feedback resistor between CF1 and CF2 is in the state established on entry into HOLD mode • CF oscillation inverter input/general-purpose input is in the state established on entry into HOLD mode. • Feedback resistor between CF1 and CF2 is in the state established on entry into HOLD mode On Exit from HOLD • State established on entry into HOLD mode • State established on entry into HOLD mode ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← 4-18 LC870800 Chapter 4 All modes Reset state entry conditions • Low level applied to the RES pin. • Reset signal generated by Reset • Main clock stopped • Subclock stopped • Medium-speed RC oscillator started • High-speed RC oscillator stopped. • All registers initialized watchdog timer HOLD mode entry conditions • PCON register (FE07H), bit 2 set to 0 and bit 1 to 1 Normal operating mode • Start/stop of oscillators programmable • CPU and peripheral modules run normally. HOLD mode • All oscillators stopped • Since OCR register, bits 1, 4, and 5 are cleared, medium-speed RC oscillator starts oscillation as the system clock when CPU exits HOLD mode. • CPU and peripheral modules are stopped. HALT mode • All oscillators retain the state established when HALT mode is entered. • CPU stopped. Peripheral modules keep running. HOLD mode release conditions • INT0 or INT1 level interrupt request generated • Request for INT2, INT4, or port 0 interrupt generated • Reset conditions established (Note 1) HALT mode entry condition • PCON register (FE07H), bit 1 set to 0 and bit 0 to 1 HALT mode release conditions • Interrupt request accepted (Note 2) • Reset conditions established (Note 1) Reset state cancellation condition • Lapse of predetermined time after reset conditions are cancelled. X’tal HOLD mode entry condition • PCON register (FE07H), bit 2 set to 1 and bit 1 to 1 X’tal HOLD mode • Main clock, medium-speed RC, and high-speed RC oscillators stopped. Subclock retains the state established when X'tal HOLD mode is entered. • Contents of OCR and OCR2 registers remain unchanged. • CPU enters this mode after selecting subclock, medium-speed RC oscillator, or high-speed RC oscillator as the system clock. • CPU and all peripheral modules except base timer and remote control receiver circuit stop operation. Base timer and remote control receiver circuit retain the state established when X'tal HOLD mode is entered. • When X'tal HOLD mode is exited, the oscillators return to the state established when the mode is entered X'tal HOLD mode release conditions • Base timer or remote control receiver circuit interrupt request generated • INT0 or INT1 level interrupt request generated • Request for INT2, INT4,or port 0 interrupt generated • Reset conditions established (Note 1) Note 1: The CPU enters the reset state when the reset conditions are established. Note 2: The CPU cannot return from HALT mode since no interrupt request can be accepted unless its interrupt level is higher than the interrupt level that placed the CPU into HALT, HOLD, or X'tal HOLD mode. Interrupt level at which the CPU entered HALT, HOLD, or X'tal HOLD mode Interrupt request level that can release HALT mode No interrupt request present X, H and L levels L level X and H levels H level X level X level None (unable to release with interrupt) Fig. 4.4.1 Standby Mode State Transition Diagram 4-19 Reset 4.5 Reset Function 4.5.1 Overview The reset function initializes the microcontroller when it is powered on or while it is running. 4.5.2 Functions This series of microcontrollers provides the following three types of reset functions: 1) External reset via the RES pin The microcontroller is reset without fail by applying and holding a low level to the RES pin for 200 μs or longer. Note, however, that a low level of a small duration (less than 200 μs) is likely to trigger a reset. The RES pin can serve as a power-on reset pin when it is provided with an external time constant element. 2) Internal reset The internal reset function is available in two types: the power-on reset (POR) that triggers a reset when power is turned on and the low-voltage detection reset (LVD) that triggers a reset when the power voltage falls below a certain level. Options are available to set the power-on reset release level, to enable (use) and disable (non-use) the low-voltage detection reset function, and to set its threshold level. 3) Reset function using a watchdog timer The watchdog timer of this series of microcontroller can be used to generate a reset by the internal low-speed RC oscillator at a predetermined time intervals. An example of a reset circuit is shown in Figure 4.5.1. The external circuit connected to the reset pin shows an example that the internal reset function is disabled and an external power-on reset circuit is configured. Exterior of microcontroller Interior of microcontroller Watchdog timer (WDT) RES Internal low-speed RC oscillator Sync. circuit Internal reset circuit (POR/LVD) Figure 4.5.1 Sample Reset Circuit Block Diagram 4-20 Int. reset signal LC870800 Chapter 4 4.5.3 Reset State When a reset is generated by the RES pin, internal reset circuit, or watchdog timer, the hardware functional blocks of the microcontroller are initialized by a reset signal that is in synchronization with the system clock. Since the system clock is switched to the internal medium-speed RC oscillator when a reset occurs, hardware initialization is also carried out immediately even when the power is turned on. The system clock must be switched to the main clock when the main clock is stabilized. The program counter is initialized to 0000H on a reset. See Appendix (A-I), Special Functions Register (SFR) Map, for the initial values of the special function registers (SFR). <Notes and precautions> • The stack pointer is initialized to 0000H. • Data RAM is not initialized by a reset. Consequently, the contents of RAM are undefined when power is turned on. • When using the internal reset function, it is necessary to implement and connect an external circuit to the reset pin according to the user's operating environment. Be sure to review and observe the operating specifications, circuit configuration, precautions, and considerations discussed in Section 4.7, "Internal Reset Function." 4-21 WDT 4.6 Watchdog Timer (WDT) 4.6.1 Overview This series of microcontrollers is provided with a watchdog timer (WDT) that has the following features: 1) Capable of generating an internal reset on an overflow of a timer that runs on a WDT-dedicated low-speed RC oscillator clock. 2) The continuation, termination, or holding (count value) of the WDT operation on entry into standby mode is programmable. 4.6.2 Functions 1) Watchdog timer function • The 16-bit up-counter (WDTCT) runs on a low-speed RC oscillator clock. A WDT reset (internal reset) signal is generated when the overflow time (selected from 8 time values) that is selected by the watchdog timer control register (WDTCNT) is reached. At this time, the reset detection flag (RSTFLG) is set. • Since the WDTCT can be cleared by a program, it is necessary to code the program so that the WDTCT can be cleared at regular intervals. • Since the WDT used in this series of microcontrollers uses a dedicated low-speed RC oscillator, the system continues operation even when the system clock is stopped due to a program runaway, making it possible to detect any system runaway conditions. • The WDT operation mode on entry into standby mode can be selected from three modes, i.e., "continuation of operation," "termination of operation," and "holding of WDTCT count value and resuming WDT operation at the holding count value when standby mode is exited." In "continuation of operation" mode, the low-speed RC oscillator circuit continues oscillation even in standby mode, allowing an operating current of several μA to flow at all times. (For details, refer to the latest "SANYO Semiconductor Data Sheet.") 2) It is necessary to manipulate the following special function register to control the watchdog timer (WDT). • WDTCNT Address Initial value R/W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE79 0000 0000 R/W WDTCNT RSTFLG FIX0 WDTRUN IDLOP1 IDLOP0 WDTSL2 WDTSL1 WDTSL0 4.6.3 Circuit Configuration 4.6.3.1 1) WDT control register (WDTCNT) (8-bit register) This register is used to manipulate the reset detection flag, to select operations in standby mode, to select the overflow time, and to control the operation of the WDT. Note: The WDTCNT is initialized to 00H when a low-level signal is applied to the external RES pin or a reset is triggered by the internal reset (POR/LVD) function. Bits 4 to 0 of the WDTCNT are not initialized, however, when a WDT-triggered reset occurs. Note: The WDTCNT is disabled for writes once the WDT is started (WDTRUN set to 1). If the instruction MOV #55H, WDTCNT is executed in this case, the WDTCT is cleared and counting is restarted at a count value of 0. The WDTCT is not cleared when it is loaded with 55H with any other instruction. 4-22 LC870800 Chapter 4 Note: The low-speed RC oscillator circuit is started and stopped by setting WDTRUN bit (WDTCNT, bit 5) to 1 and 0, respectively. Once the oscillator starts oscillation, an operating current of several μA flows at all times (For details, refer to the latest "SANYO Semiconductor Data Sheet"). 4.6.3.2 1) 2) 3) 4) * WDT counter (WDTCT) (16-bit counter) Operation start/stop: Start/stop is controlled by the 1/0 value of WDTRUN. When WDTRUN is set to 1 and IDLOP1 and IDLOP0 (WDTCNT, bits 4 and 3) are set to 1, the microcontroller enters standby mode. Count clock: The low-speed RC oscillator clock Overflow: Generated when the WDTCT count value matches the count value designated by WDTSL2 to WDTSL0 (WDTCNT, bits 2 to 0). *Generates the RSTFLG (WDTCNT, bit 7) set signal. *Generates the WDT reset signal and the WDTRUN clear signal. Reset: Places the microcontroller into standby mode when WDTRUN is set to 0, overflow occurs, WDTRUN is set to 1 and instruction MOV #55H, WDTCNT is executed, or WDTRUN is set to 1 and IDLOP1 and IDLOP0 are set to 1. See Figure 4.6.2 for details on WDT operation. BUS Write WDTCNT MOV #55H, WDTCNT Write instruction detector circuit Oscillation Low-speed RC control Clock oscillator circuit WDT counter Reset (WDTCT) Stop oscillation Selector WDTRUN WDTRUN Set WDT reset WDTRST=1 generator circuit WDTRUN clear signal WDT reset signal RSTFLG set signal 3 WDTSL2-0 IDLOP1-0=2 Standby mode WDTRST=0 IDLOP1-0=1 Enter standby mode Figure 4.6.1 Watchdog Timer Operation Block Diagram 4-23 WDTRUN clear signal WDT Overflow *Operation performed when IDLOP1-0 are set to 0 or 3 (continue count operation) WDTSL2-0 set count value WDTCT Count value 0 Time set in WDTSL2-0 "MOV #55H,WDTCNT" instruction executed (WDTCT cleared to 0) WDT operation started (WDTRUN=1) Low-speed RC oscillator started WDT reset signal generated WDTRUN cleared to 0 RSTFLG set to 1 Low-speed RC oscillator stopped *Operation performed when IDLOP1-0 are set to 1 (suspend operation) Standby mode entered WDTSL2-0 set count value WDTCT Count value 0 WDT operation started (WDTRUN=1) Low-speed RC oscillator started WDTRUN cleared to 0 Low-speed RC oscillator stopped *Operation performed when IDLOP1-0 are set to 2 (operation with the count value retained) Standby mode entered Low-speed RC oscillator stopped Standby mode exited Low-speed RC oscillator started Overflow WDTSL2-0 set count value WDTCT Count value 0 Time set in WDTSL2-0 + Standby mode time WDT operation started (WDTRUN=1) Low-speed RC oscillator started Figure 4.6.2 WDT reset signal generated WDTRUN cleared to 0 RSTFLG set to 1 Low-speed RC oscillator stopped Sample Watchdog Timer Operation Waveforms 4.6.4 Related Registers 4.6.4.1 1) WDT control register (WDTCNT) This register is used to manipulate the reset detection flag, to select the standby mode operation, to select the overflow time, and to control the operation of the WDT. Address Initial value R/W Name BIT7 FE79 0000 0000 R/W WDTCNT RSTFLG BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FIX0 WDTRUN IDLOP1 IDLOP0 WDTSL2 WDTSL1 WDTSL0 RSTFLG (bit 7): WDT reset detection flag This bit is cleared when a reset is triggered by applying a low level signal to the external RES pin or by using the internal reset (POR/LVD) function. This bit is set when a WDT-triggered reset occurs. This flag can be rewritten with an instruction. FIX0 (bit 6): Test bit This bit is available for testing purposes and must always be set to 0. WDTRUN (bit 5): WDT operation control Setting this bit to 0 stops the WDT operation. Setting this bit to 1 starts the WDT operation. 4-24 LC870800 Chapter 4 IDLOP1 (bit 4): IDLOP0 (bit 3): WDT standby mode operation select IDLOP1 IDLOP0 WDT Standby Mode Operation 0 0 Continue count operation 0 1 Suspend operation 1 0 Operation with the count value retained 1 1 Continue count operation * See Figure 4.6.2 for details of WDT operating modes. * There are notes to be taken when running WDT by specifying “Operation with the count value retained.” See Subsection 4.6.5, “Notes on the Use of the Watchdog Timer.” WDTSL2 (bit 2): WDTSL1 (bit 1): WDT counter (WDTCT) control WDTSL0 (bit 0): WDTSL2 WDTSL1 WDTSL0 WDT Counter Count Value 0 0 0 512 (17.06 ms) 0 0 1 1024 (34.13 ms) 0 1 0 2048 (68.26 ms) 0 1 1 4096 (136.53 ms) 1 0 0 8192 (273.06 ms) 1 0 1 16384 (546.13 ms) 1 1 0 32768 (1092.26 ms) 1 1 1 65536 (2184.53 ms) * Time values enclosed in parentheses refer to the time for a WDTCT overflow to occur when the low-speed RC oscillation frequency is 30 kHz (typical). The low-speed RC oscillation frequency varies from IC to IC. For details, refer to the latest "SANYO Semiconductor Data Sheet." Note: The WDTCNT is initialized to 00H when a low-level signal is applied to the external RES pin or a reset is triggered by the internal reset (POR/LVD) function. Bits 4 to 0 of the WDTCNT are not initialized, however, when a WDT-triggered reset occurs. Note: The WDTCNT is disabled for writes once the WDT starts operation (WDTRUN set to 1). If the instruction MOV #55H, WDTCNT is executed in this case, the WDTCT is cleared and counting is restarted at a count value of 0 (the WDTCT is not cleared when it is loaded with 55H with any other instruction). Note: The low-speed RC oscillator circuit is started and stopped by setting WDTRUN bit to 1 and 0, respectively. Once the oscillator starts oscillation, an operating current of several μA flows at all times (For details, refer to the latest "SANYO Semiconductor Data Sheet"). 4-25 WDT 4.6.5 1) Notes on the Use of the Watchdog Timer When “Operation with the count value retained” is selected in the standby mode operation (IDLOP1 to IDLOP0 = 2) • When the microcontroller is placed in standby mode (HALT/HOLD) after the watchdog timer is started with “Operation with the count value retained” selected, the low-speed RC oscillator circuit stops oscillation and the watchdog timer stops counting and retains the count value. When the microcontroller subsequently exits standby mode, the low-speed RC oscillator circuit resumes oscillation and the watchdog timer starts counting. If the period between the release of standby mode to the next entry into standby mode is less than “low-speed RC oscillator clock 4,” however, the low-speed RC oscillator circuit may not stop oscillation when the CPU enters standby mode. In such a case (a standby mode is on), several μA of operating current flows because the low-speed RC oscillator circuit is active though the watchdog timer count operation is suspended. To minimize the standby power requirement of the set, code the program so that an interval of “low-speed RC oscillator clock 4” or longer be provided between release from standby mode and entry into the next standby mode. (Note that the oscillation frequency of the low-speed RC oscillator may fluctuate. See the latest “SANYO Semiconductor Data Sheet” for details.) 4-26 LC870800 Chapter 4 4.7 Internal Reset Function 4.7.1 Overview This series of microcontroller incorporates internal reset functions called the power-on reset (POR) and low-voltage detection reset (LVD). The use of these functions contributes to a reduction in the number of externally required reset circuit components (reset IC, etc.). 4.7.2 Functions 1) Power-on reset (POR) function POR is a hardware feature that generates a reset to the microcontroller at power-on time. This function allows the user to select the POR release level by option only when “Disable” of the low-voltage detection reset function is selected. It is necessary to use the below-mentioned low-voltage detection reset function together with this function, or configure an external reset circuit if there are possibilities that chatter occurs or a momentary power loss occurs at power-on time. 2) Low-voltage detection reset (LVD) function This function, when used together with the POR function, can generate a reset when power is turned on and when the power level lowers. As a user option “Enable (use)” or “Disable (non-use)” and the detection level of this function can be specified. 4.7.3 Circuit Configuration The internal reset circuit consists of the POR, LVD, pulse stretcher circuit, capacitor CRES discharging transistor, external capacitor CRES + pull-up resistor RRES or pull-up resistor RRES alone. The circuit diagram is provided in Figure 4.7.1. • Pulse stretcher circuit The pulse stretcher circuit stretches the POR and LVD reset signals. It is used to stretch the internal reset period and discharge the external capacitor CRES connected to the reset pin. The stretching time lasts from 30μs to 100μs. • Capacitor CRES discharging transistor This is an N-channel transistor used to discharge the external capacitor CRES connected to the reset pin. If the capacitor CRES is not to be connected to the reset pin, it is possible to monitor the internal reset signal by connecting only the external pull-up resistor RRES. • Option selector circuit The option selector circuit is used to configure the LVD options. This circuit selects whether to Enable (use) or Disable (non-use) the LVD and selects its detection levels. See Subsection 4.7.4. • External capacitor CRES +Pull-up resistor RRES After the reset signal from the internal reset circuit is released, the reset period is further stretched according to the external CR time constant. This enables the microcontroller to avoid repetitive entries and releases of the reset state from occurring when power-on chatter occurs. The circuit configuration shown in Figure 4.7.1, in which the capacitor CRES and pull-up resistor RRES are externally connected, is recommended when both POR and LVD functions are to be used. The recommended constant values are: CRES =0.022μF and RRES =510 kΩ. The external pull-up resistor RRES must always be installed even when the set's specifications inhibit the installation of the external capacitor CRES. 4-27 Internal Reset Interior of microcontroller RRES =510kΩ RES Reset CRES =0.022μF Power-on reset （POR） Pulse stretcher Options Low-voltage detection reset (LVD) Figure 4.7.1 4.7.4 Internal Reset Circuit Configuration Options The POR and LVD options are available for the reset circuit. 1) LVD Reset Function Options "Enable": Use "Disable": Non-use 2) LVD Reset Level Option 3) POR Release Level Option Typical value of Min. operating Typical value of Min. operating selected option VDD value (*) selected option VDD value (*) － － "1.67V" 1.8V to "1.91V" 2.1V to "1.97V" 2.1V to "2.01V" 2.2V to "2.07V" 2.2V to "2.31V" 2.5V to "2.37V" 2.5V to "2.51V" 2.7V to "2.57V" 2.7V to "2.81V" 3.0V to "2.87V" 3.0V to "3.79V" 4.0V to "3.86V" 4.0V to "4.28V" 4.5V to "4.35V" 4.5V to * The minimum operating VDD value specifies the approximate lower limit value of the VDD value beyond which the selected POR release level or LVD reset level cannot be effected without generating a reset. 1) LVD reset function option When “Enable” is selected, a reset is generated at the voltage that is selected by the LVD reset level option. Note 1: In this configuration, an operating current of severalμA always flows in all modes. When "Disable" is selected, no LVD reset is generated. Note 2: In this configuration, no operating current will flow in all modes. * See the sample operating waveforms of the reset circuit shown in Subsection 4.7.5 for details. 2) LVD reset level option The LVD reset level can be selected from 7 level values only when “Enable” is selected in the LVD reset function options. Select the appropriate detection level according to the user's operating conditions. 3) POR release level option The POR release level can be selected from 8 level values only when “Disable” is selected in the LVD reset function options. When not using the internal reset circuit, set the POR release level to the lowest level (1.67V) that will not affect the minimum guaranteed operating voltage. Note 3: No operating current flows when the POR reset state is released. Note 4: See the notes in paragraph 2) of Subsection 4.7.6 when selecting a POR release level that is lower than the minimum guaranteed operating voltage (1.67V). 4-28 LC870800 Chapter 4 Selection example 1 Selecting the optimum LVD reset level to keep the microcontroller running without resetting it until VDD falls below 2.7V according to the set’s requirements Set the LVD reset function option to "Enable" and select "2.51V" as the LVD reset level option. Set operating range VDD=2.7V LVD release voltage (LVDET+LVHYS) LVD reset voltage (LVDET=Typ. 2.51V) Selection example 2 Selecting the optimum LVD reset level that meets the guaranteed operating conditions to VDD = 2.7V/Tcyc = 250 ns Set the LVD reset function option to "Enable" and select "2.81V" as the LVD reset level option. Microcontroller guaranteed operating range (VDD=2.7V to 5.5V/Tcyc=250ns) LVD release voltage (LVDET+LVHYS) LVD reset voltage (LVDET=Typ. 2.81V) Lower limit operation guarantee voltage (VDD=2.7V /Tcyc=250ns) Selection example 3 Disabling the internal reset circuit and using an external reset IC that can detect and react at 3.0V (see also paragraph 1) of Subsection 4.7.7) Set the LVD reset function option to "Disable" and select "1.67V" as the POR release level option. Set operating range VDD=3.1V External 3.0V detection circuit POR release voltage (PORRL=Typ. 1.67V) Note 5: The operation guarantee values (voltage/operating frequency) shown in the examples vary with the microcontroller type. Be sure to see the latest “SANYO Semiconductor Data Sheet” for details. 4-29 Internal Reset 4.7.5 1) Sample Operating Waveforms of the Internal Reset Circuit Waveform observed when only POR is used (LVD not used) (Reset pin: Pull-up resistor RRES only) (a) POR release voltage (b) (PORRL) VDD Reset period 100μs or longer Reset period Undefined state (POUKS) RES# • There exists an undefined state (POUKS), before the POR transistor starts functioning normally. • The POR function generates a reset only at power-on time starting at the VSS level. The reset release voltage in this case may have some range. Refer to the latest “SANYO Semiconductor Data Sheet” for details. • No stable reset will be generated if power is turned on again if the power level does not go down to the VSS level as shown in (a). If such a case is anticipated, use the LVD function together as explained in 2) or implement an external reset circuit. • As shown in (b), reset is generated when the power level goes down to the VSS level and only when power is turned on again after this condition continues for 100µs or longer. 2) Waveform observed when both POR and LVD functions are used (Reset pin: Pull-up resistor RRES only) LVD hysteresis width LVD release voltage (LVHYS) (LVDET+LVHYS) VDD LVD reset voltage (LVDET) Reset period Reset period Reset period Undefined state (LVUKS) RES# • There also exists an undefined state (LVUKS), before the POR transistor starts functioning normally when both POR and LVD functions are used. • Resets are generated both when power is turned on and when the power level lowers. The reset release voltage and entry voltage in this case may have some range. Refer to the latest “SANYO Semiconductor Data Sheet” for details. • A hysteresis width (LVHYS) is provided to prevent repetitions of reset release and entry cycles near the detection level. 4-30 LC870800 Chapter 4 4.7.6 Notes on the Use of the Internal Reset Circuit 1) When generating resets only with the internal POR function When generating resets using only the internal POR function, do not short the reset pin directly to VDD as when using it with the LVD function. Be sure to use an external capacitor CRES of an appropriate capacitance and a pull-up resistor RRES or the pull-up resistor RRES alone. Test the circuit extensively under the anticipated power supply conditions to verify that resets are reliably generated. Microcontroller RRES RES Reset CRES From POR Figure 4.7.2 Reset Circuit Configuration Using Only the Internal POR Function 2) When selecting a release voltage level of 1.67V only with the internal POR function When selecting an internal POR release level of 1.67V, connect the external capacitor CRES and pull-up resistor RRES of the values that match the power supply's rise time to the reset pin and make necessary adjustments so that the reset state is released after the release voltage exceeds the minimum guaranteed operating voltage. Alternatively, set and hold the voltage level of the reset pin at the low level until the release voltage exceeds the minimum guaranteed operating voltage. When POR release level is 1.67V Min. guaranteed operating voltage VDD Reset VIH level Undefined state Reset period (LVUKS) RES Figure 4.7.3 Sample Release Level Waveform in Internal POR Only Configuration 4-31 Internal Reset 3) When momentary power loss or voltage fluctuations shorter than several hundred s are anticipated The response time measured from the time the internal LVD detects a power voltage drop at the option-selected level until it generates a reset signal is defined as the minimum low-voltage detection width TLVDW as shown in Figure 4.7.4 (Refer to the latest “SANYO Semiconductor Data Sheet” for details.). If momentary power loss or power voltage fluctuations shorter than this minimum low-voltage detection width are anticipated, be sure to take the preventive measures shown in Figure 4.7.5 or other necessary measures. VDD LVD release voltage LVD reset voltage LVDET-0.5V (LVDET) TLVDW VSS Figure 4.7.4 Example of Momentary Power Loss or Voltage Fluctuation Waveform Microcontroller VDD1 Power supply VSS1 RES Figure 4.7.5 Example of Momentary Power Loss or Voltage Fluctuation Countermeasures 4-32 LC870800 Chapter 4 4.7.7 1) Notes to be Taken When Not Using the Internal Reset Circuit When configuring an external reset IC without using the internal reset circuit The internal POR function is activated and the capacitor CRES discharging N-channel transistor connected to the reset pin turns on when power is turned on even if the internal reset circuit is not used. For this reason, when connecting an external reset IC, adopt a reset IC of a type whose detection level is not lower than the minimum guaranteed operating voltage level and select the lowest POR release level (1.67V) that does not affect the minimum guaranteed operating voltage. The figures provided below show sample reset circuit configurations that use reset ICs of N-channel open drain and CMOS types, respectively. Reset IC N-channel open drain type Microcontroller Several hundred kΩ RES Reset From POR Figure 4.7.6 Sample Reset Circuit Configuration Using an N-channel Open Drain Type Reset IC Reset IC Insert a protective resistor of several to dozens of kΩ to prevent through current. Microcontroller CMOS type RES Reset From POR Figure 4.7.7 Sample Reset Circuit Configuration Using a CMOS Type Reset IC 4-33 Internal Reset 2) When configuring the external POR circuit without using the internal reset circuit The internal POR is activated when the power is turned on even if the internal reset circuit is not used as in case 1) in Subsection 4.7.7. When configuring an external POR circuit with a CRES value of 0.1µF or larger to obtain a longer reset period than with the internal POR, however, be sure to connect an external diode DRES as shown in Figure 4.7.8. Microcontroller DRES RRES RES Reset CRES From POR Connect an external diode. Figure 4.7.8 Sample External POR Circuit Configuration 4-34 Appendixes Table of Contents Appendix I • Special Functions Register (SFR) Map Appendix-II • • • • • Port 0 Block Diagram Port 1 Block Diagram Port 2 Block Diagram Port 3 Block Diagram Port 7 Block Diagram LC870800 APPENDIX-Ｉ Address Initial value R/W LC870800 Remarks BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 0-00FF XXXX XXXX R/W RAM256B FE00 0000 0000 R/W AREG 9 bits long - AREG7 AREG6 AREG5 AREG4 AREG3 AREG2 AREG1 AREG0 FE01 0000 0000 R/W BREG - BREG7 BREG6 BREG5 BREG4 BREG3 BREG2 BREG1 BREG0 FE02 0000 0000 R/W CREG - CREG7 CREG6 CREG5 CREG4 CREG3 CREG2 CREG1 CREG0 FE06 0000 0000 R/W PSW - CY AC PSWB5 PSWB4 LDCBNK OV P1 PARITY FE07 HHHH H000 R/W PCON - - - - - - XTIDLE PDN IDLE FE08 0000 HH00 R/W IE - IE7 XFLG HFLG LFLG - - XCNT1 XCNT0 FE09 0000 0000 R/W IP - IP4B IP43 IP3B IP33 IP2B IP23 IP1B IP13 FE0A 0000 0000 R/W SPL - SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 FE0B 0000 0000 R/W SPH - SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP FE0C HHHH H000 R/W CLKDIV - - - - - - CLKDV2 CLKDV1 CLKDV0 FE0E 0000 XX00 R/W OCR - CLKSGL EXTOSC CLKCB5 CLKCB4 XT2IN XT1IN RCSTOP CFSTOP FE0F 0H00 H000 R/W WDT - WDTFLG - WDTB5 WDTHLT - WDTCLR WDTRST WDTRUN FE10 0000 0000 R/W T0CNT - T0HRUN T0LRUN T0LONG T0LEXT T0HCMP T0HIE T0LCMP T0LIE FE11 0000 0000 R/W T0PRR - T0PRR7 T0PRR6 T0PRR5 T0PRR4 T0PRR3 T0PRR2 T0PRR1 T0PRR0 FE12 0000 0000 R T0L - T0L7 T0L6 T0L5 T0L4 T0L3 T0L2 T0L1 T0L0 FE13 0000 0000 R T0H - T0H7 T0H6 T0H5 T0H4 T0H3 T0H2 T0H1 T0H0 FE14 0000 0000 R/W T0LR - T0LR7 T0LR6 T0LR5 T0LR4 T0LR3 T0LR2 T0LR1 T0LR0 FE15 0000 0000 R/W T0HR - T0HR7 T0HR6 T0HR5 T0HR4 T0HR3 T0HR2 T0HR1 T0HR0 FE16 XXXX XXXX R T0CAL Timer 0 capture register L - T0CAL7 T0CAL6 T0CAL5 T0CAL4 T0CAL3 T0CAL2 T0CAL1 T0CAL0 FE17 XXXX XXXX R T0CAH Timer 0 capture register H - T0CAH7 T0CAH6 T0CAH5 T0CAH4 T0CAH3 T0CAH2 T0CAH1 T0CAH0 FE18 0000 0000 R/W T1CNT - T1HRUN T1LRUN T1LONG T1PWM T1HCMP T1HIE T1LCMP T1LIE FE19 0000 0000 R/W T1PRR - T1HPRE T1HPRC2 T1HPRC1 T1HPRC0 T1LPRE T1LPRC2 T1LPRC1 T1LPRC0 FE1A 0000 0000 R T1L - T1L7 T1L6 T1L5 T1L4 T1L3 T1L2 T1L1 T1L0 FE1B 0000 0000 R T1H - T1H7 T1H6 T1H5 T1H4 T1H3 T1H2 T1H1 T1H0 FE1C 0000 0000 R/W T1LR - T1LR7 T1LR6 T1LR5 T1LR4 T1LR3 T1LR2 T1LR1 T1LR0 FE1D 0000 0000 R/W T1HR - T1HR7 T1HR6 T1HR5 T1HR4 T1HR3 T1HR2 T1HR1 T1HR0 FE03 FE04 FE05 FE0D XT1 and XT2 read at bits 2 and 3 Prescaler is 8 bits long. (max. 256 Tcyc). AI-1 Address Initial value R/W LC870800 FE1E FE1F FE20 FE21 FE22 FE23 FE24 FE25 FE26 FE27 FE28 FE29 FE2A FE2B FE2C FE2D FE2E FE2F FE30 0000 0000 R/W FE31 0000 0000 FE32 0000 0000 FE33 FE34 Remarks BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 SCON0 - FIX0 FIX0 SI0RUN FIX0 SI0DIR SI0OVR SI0END SI0IE R/W SBUF0 - SBUF07 SBUF06 SBUF05 SBUF04 SBUF03 SBUF02 SBUF01 SBUF00 R/W SBR0 - SBRG07 SBRG06 SBRG05 SBRG04 SBRG03 SBRG02 SBRG01 SBRG00 0000 0000 R/W SCTR0 - FIX0 FIX0 FIX0 FIX0 FIX0 FIX0 FIX0 FIX0 0000 0000 R/W SCON1 - SI1M1 SI1M0 SI1RUN SI1REC SI1DIR SI1OVR SI1END SI1IE FE35 00000 0000 R/W SBUF1 SBUF18 SBUF17 SBUF16 SBUF15 SBUF14 SBUF13 SBUF12 SBUF11 SBUF10 FE36 0000 0000 R/W SBR1 - SBRG17 SBRG16 SBRG15 SBRG14 SBRG13 SBRG12 SBRG11 SBRG10 FE37 0000 0000 R/W SWCON0 - FIX0 FIX0 FIX0 FIX0 FIX0 FIX0 FIX0 FIX0 9-bit REG Controls suspension of continuous SIO0 transmission. FE38 FE39 FE3A FE3B FE3C FE3D AI-2 LC870800 APPENDIX-Ｉ Address Initial value R/W LC870800 FE40 0000 0000 R/W FE41 0000 0000 FE42 00HH 0000 FE43 FE44 Remarks BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 P0 - P07 P06 P05 P04 P03 P02 P01 P00 R/W P0DDR - P0HPUS P0LPUS P0FLG P0IE P0HPU P0LPU P0HDDR P0LDDR R/W P0FCR - T7OE T6OE - - CLKOEN CKODV2 CKODV1 CKODV0 HHHH 0H00 R/W XT2PC - - - - - XTCFSEL - XT2PCB1 XT2PCB0 0000 0000 R/W P1 - P17 P16 P15 P14 P13 P12 P11 P10 FE45 0000 0000 R/W P1DDR - P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR FE46 0000 0000 R/W P1FCR - P17FCR P16FCR P15FCR P14FCR P13FCR P12FCR P11FCR P10FCR FE47 000H HHH0 R/W P1TST - FIXO FIX0 MRCSHIFT - - - - FIXO FE48 HHHH HH00 R/W P2 - - - - - - - P21 P20 FE49 HHHH HH00 R/W P2DDR - - - - - - - P21DDR P20DDR FE4A HHHH 0000 R/W I45CR - - - - - INT4HEG INT4LEG INT4IF INT4IE FE4B HHHH 0000 R/W I45SL - - - - - I4SL3 I4SL2 I4SL1 I4SL0 FE4C HH00 0000 R/W P3 - - - P35 P34 P33 P32 P31 P30 FE4D HH00 0000 R/W P3DDR - - - P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR FE57 HHH0 HH00 R/W CFLVM FE58 0000 0000 R/W ADCRC 12-bit AD control FE59 0000 0000 R/W ADMRC 12-bit AD mode - ADMD4 ADMD3 ADMD2 ADMD1 ADMD0 ADMR2 ADTM1 ADTM0 FE5A 0000 0000 R/W ADRLC 12-bit AD conversion result L - DATAL3 DATAL2 DATAL1 DATAL0 ADRL3 ADRL2 ADRL1 ADTM2 FE5B 0000 0000 R/W ADRHC FE5C 0000 0000 R/W P7 FE5D 0000 0000 R/W I01CR FE3E FE3F FE4E FE4F FE50 FE51 FE52 FE53 FE54 FE55 FE56 - - - - CFMON - - FIX0 FIX0 - ADCHSEL3 ADCHSEL2 ADCHSEL1 ADCHSEL0 ADCR3 ADSTART ADENDF ADIE 12-bit AD conversion result H - DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 4bit-IO (7-4:DDR - P73DDR P72DDR P71DDR P70DDR P73DT P72DT P71DT P70DT - INT1LH INT1LV INT1IF INT1IE INT0LH INT0LV INT0IF INT0IE 3:0:DATA) AI-3 Address Initial value R/W LC870800 FE5E 0000 0000 R/W FE5F 00000 0000 R/W 0000 0000 FE7A Remarks BIT8 BIT7 BIT6 I23CR - INT3HEG INT3LEG ISL BUZDIV ST0HCP ST0LCP R/W T67CNT - T7C1 T7C0 0000 0000 R/W T6R - T6R7 FE7B 0000 0000 R/W T7R - FE7C 00HH HHHH R/W OCR2 - BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 INT3IF INT3IE INT2HEG INT2LEG INT2IF INT2IE BTIMC1 BTIMC0 BUZON NFSEL NFON ST0IN T6C1 T6C0 T7OV T7IE T6OV T6IE T6R6 T6R5 T6R4 T6R3 T6R2 T6R1 T6R0 T7R7 T7R6 T7R5 T7R4 T7R3 T7R2 T7R1 T7R0 FRCSEL FRCSTART - - - - - - FE60 FE61 FE62 FE63 FE64 FE65 FE66 FE67 FE68 FE69 FE6A FE6B FE6C FE6D FE6E FE6F FE70 FE71 FE72 FE73 FE74 FE75 FE76 FE77 FE78 FE79 AI-4 LC870800 APPENDIX-Ｉ Address Initial value R/W LC870800 Remarks BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FE7E 0000 0000 R/W FSR0 FLASH control (bit 4 is R/O.) - FSR0B7 Fix to 0 FSR0B6 Fix to 0 FSAERR FSWOK INTHIGH FSLDAT FSPGL FSWREQ FE7F 0000 0000 R/W BTCR Base timer control - BTFST BTON BTC11 BTC10 BTIF1 BTIE1 BTIF0 BTIE0 FE90 0000 0000 R/W PWMCR - PWMEN PWMMD OPOL OPOLB ATRGEN PCKDV2 PCKDV1 PCKDV0 FE91 0000 0000 R/W PINTCR - CRTSEL CRTEN ERTSEL ERTEN HPRDRQ HPRDEN PRDRQ PRDEN FE92 H000 H000 R/W POMD0 - - P1OMD2 P1OMD1 P1OMD0 - P0OMD2 P0OMD1 P0OMD0 FE93 HHHH H000 R/W POMD1 - - - - - - P2OMD2 P2OMD1 P2OMD0 FE94 0000 0000 R/W PPRDL - PPRD7 PPRD6 PPRD5 PPRD4 PPRD3 PPRD2 PPRD1 PPRD0 FE95 HHHH 0000 R/W PPRDH - - - - - PPRDB PPRDA PPRD9 PPRD8 FE96 0000 0000 R/W P0MTL - P0MT7 P0MT6 P0MT5 P0MT4 P0MT3 P0MT2 P0MT1 P0MT0 FE97 HHHH 0000 R/W P0MTH - - - - - P0MTB P0MTBA P0MTB9 P0MTB9 FE98 0000 0000 R/W P1MTL - P1MT7 P1MT6 P1MT5 P1MT4 P1MT3 P1MT2 P1MT1 P1MT0 FE99 HHHH 0000 R/W P1MTH - - - - - P1MTB P1MTBA P1MTB9 P1MT8 FE9A 0000 0000 R/W P2MTL - P2MT7 P2MT6 P2MT5 P2MT4 P2MT3 P2MT2 P2MT1 P2MT0 FE9B HHHH 0000 R/W P2MTH - - - - - P2MTB P2MTBA P2MTB9 P2MT8 FE7D FE80 FE81 FE82 FE83 FE84 FE85 FE86 FE87 FE88 FE89 FE8A FE8B FE8C FE8D FE8E FE8F AI-5 Address Initial value R/W FE9C 0000 0000 R/W FE9D HH00 0000 R/W FEA0 000H X000 R/W FEA1 000H X000 R/W LC870800 Remarks BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 DTIM - DTIM7 DTIM6 DTIM5 DTIM4 DTIM3 DTIM2 DTIM1 DTIM0 PIOCR - - - POEN2B POEN2 POEN1B POEN1 POEN0B POEN0 CPAPCR1 - CPAP1EN CPAP1SL CP1OUTEN - CMP1OUT CMP1EG CMP1IF CMP1IE CPAPCR2 - CPAP2EN CPAP2SL CP2OUTEN - CMP2OUT CMP2EG CMP2IF CMP2IE FE9E FE9F FEA2 FEA3 FEA4 FEA5 FEA6 FEA7 FEA8 FEA9 FEAA FEAB FEAC FEAD FEAE FEAF FEB0 FEB1 FEB2 FEB3 FEB4 FEB5 FEB6 FEB7 FEB8 FEB9 FEBA FEBB AI-6 LC870800 APPENDIX-Ｉ Address Initial value R/W LC870800 FED0 0000 0000 R/W FED1 0000 0000 R/W FED2 0000 0000 FED3 FED4 Remarks BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 UCON0 - UBRSEL STRDET RECRUN UCON1 - TRUN 8/9BIT TDDR R/W UBR - UBRG7 UBRG6 0000 0000 R/W TBUF - T1BUF7 0000 0000 R/W RBUF - R1BUF7 BIT0 STPERR U0B3 RBIT8 RECEND RECIE TCMOS 8/7BIT TBIT8 TEPTY TRNSIE UBRG5 UBRG4 UBRG3 UBRG2 UBRG1 UBRG0 T1BUF6 T1BUF5 T1BUF4 T1BUF3 T1BUF2 T1BUF1 T1BUF0 R1BUF6 R1BUF5 R1BUF4 R1BUF3 R1BUF2 R1BUF1 R1BUF0 FEBC FEBD FEBE FEBF FEC0 FEC1 FEC2 FEC3 FEC4 FEC5 FEC6 FEC7 FEC8 FEC9 FECA FECB FECC FECD FECE FECF FED5 FED6 FED7 FED8 FED9 FEDA FEDB AI-7 AI-8 LC870800 APPENDIX-II Hi-PU Bus Low-PU T7OUT(P07), T6OUT(P06) CLKOUT(P05) P0 (FE40) bits 7-5 SW S E L SW D CMOS or Nch-OD Q W-P0 C Pin P07-P05 S E L AD input (AN6-AN5) R-P0 Low-PU Hi-PU SW SW P0 (FE40) bit 4 D CMOS or Nch-OD Q C Pin P04 S E L AD input (AN4) Low-PU Hi-PU SW SW P0 (FE40) bits 3-0 D CMOS or Nch-OD Q C Pin P03-P00 S E L AD input (AN3-AN0) 7 6 5 4 3 2 1 0 P0DDR (FE41) Pull-up resistor is: Not attached if N-channel-OD option is selected. Programmable if CMOS option is selected. Port Multiplexed port pin function P07 Timer 7 toggle output P06 Timer 6 toggle output P05 Clock output (system/subclock selectable) Port 0 Block Diagram Option: Output type (CMOS or N-channel OD) selectable in 1-bit units. AII-1 Port Block Diagrams P0DDR(FE41) - - 5 4 3 2 1 0 Int. request to address 0004B P0(FE40) bit 7 P07 pin input data P0 interrupt detect P0(FE40) bit 6 P06 pin input data P0(FE40) bit 5 P05 pin input data P0(FE40) bit 4 P04 pin input data P0 interrupt detect P0DDR(FE41) bit 1 P0(FE40) bit 3 P03 pin input data P0(FE40) bit 2 P02 pin input data P0(FE40) bit 1 P01 pin input data P0(FE40) bit 0 P00 pin input data P0DDR(FE41) bit 0 Port 0 (Interrupt) Block Diagram ＡII-2 LC870800 APPENDIX-II Function 2 output Function output P1FCR (FE46) bit 7 D W-P1FCR Q Bus C Low-PU R-P1FCR SW P1 (FE44) bit 7 CMOS or Nch-OD D W-P1 C Q Pin XOR P17 S E L R-P1 Special input P17 AD input (AN9) AMP2 output AMP2 output control P1DDR (FE45) bit 7 D W-P1DDR Q C R-P1DDR Function 2 output Function output P1FCR (FE46) bit 6 D W-P1FCR Q C Bus Low-PU R-P1FCR SW P1 (FE44) bit 6 CMOS or Nch-OD D W-P1 R-P1 C Q Pin P16 XOR S E L Special input P16 Function 2 control P1DDR (FE45) bit 6 D W-P1DDR Q C Table of Port 1 Multiplexed Pin R-P1DDR Port P17 P16 P15 P14 P13 P12 P11 P10 Special Input UART1 data input AMP2(-)/CMP2(-) input SIO1 clock input/AMP2(+)/CMP2(+) input SIO1 data input AMP1(-)/CMP1(-) input SIO0 clock input/AMP1(+)/CMP1(+) input SIO0 data input None AII-3 Function Output Timer1HPWM/ＡＭＰ2，ＣＭＰ2 output Timer1LPWM output/UART1 data output SIO1 clock output SIO1 data output/ＡＭＰ1，ＣＭＰ1 output SIO1 data output SIO0 clock output SIO0 data output SIO0 data output Port Block Diagrams Function 2 output Function output P1FCR (FE46) bit 4 D W-P1FCR Q C Bus Low-PU R-P1FCR SW P1 (FE44) bit 4 CMOS or Nch-OD D W-P1 C Q Pin OR P14 S E L R-P1 Special input P14 AD input (AN8) AMP1output AMP1output control P1DDR (FE45) bit 4 D W-P1DDR Q C R-P1DDR Function output 5, 3-0 P1FCR (FE46) bits 5, 3-0 D W-P1FCR Q C Bus Low-PU R-P1FCR SW P1 (FE44) bits 5, 3-0 CMOS or Nch-OD D W-P1 R-P1 C Q OR S E L Pin P15, P13-P10 Special input P15, P13-P10 P1DDR (FE45) bits 5, 3-0 D W-P1DDR Q C R-P1DDR Port 1 Block Diagram Option: Output type (CMOS or N-channel OD) selectable in 1-bit units. ＡII-4 Bus LC870800 APPENDIX-II Low-PU Function output SW P2 (FE48) bit 1 D W-P2 Q CMOS or Nch-OD C Pin P21 S E L Special input P21 R-P2 P2DDR (FE49) bit 1 D W-P2DDR Q C Bus R-P2DDR Low-PU SW P2 (FE48) bit 0 D W-P2 CMOS or Nch-OD Q C Pin P20 S E L Special input P20 R-P2 P2DDR (FE49) bit 0 D W-P2DDR Q C R-P2DDR Port P21 P20 Special Input INT4/T1IN/T0LCP/T0HCP input Function Output BUZ output INT4/T1IN/T0LCP/T0HCP input None Table of Port 2 Multiplexed Pin Port 2 Block Diagram Option: Output type (CMOS or N-channel OD) selectable in 1-bit units. AII-5 Port Block Diagrams Int. request to address 00013 7 6 5 4 3 2 1 0 7 I45SL (FE4B) 6 5 4 3 2 1 0 I45CR (FE4A) P21 Timer 1 count clock S E L P20 S E L Timer 0L capture signal Timer 0H capture signal Bus Port 2 (Interrupt) Block Diagram Low-PU Function output 5-0 SW P3 (FE4C) bits 5-0 D CMOS or Nch-OD Q W-P3 C Pin P35-P30 S E L R-P3 P3DDR (FE4D) bits 5-0 D W-P3DDR Q C R-P3DDR Port Special Input Function Output P35 None MCPWM2# output P34 P33 None None MCPWM2 output MCPWM1# output P32 P31 P30 None MCPWM1 output MCPWM0# output MCPWM0 output None None Table of Port 3 Multiplexed Pin Port 3 Block Diagram Option: Output type (CMOS or N-channel OD) selectable in 1-bit units. ＡII-6 Bus LC870800 APPENDIX-II Low-PU SW P7 (FE5C) bits 3-0 D CMOS Q W-P7 Pin C P73-P70 S E L R-P7 INT3-INT0 P7 (FE5C) bits 7-4 D Q C Port 7 Block Diagram Option: None AII-7 Port Block Diagrams ISL(FE5F) 7 INT3 6 5 4 3 Noise filter Int. request to address 00013 7 6 5 4 3 2 1 2 1 0 S E L Timer 0 clock input S E L Timer 0H capture signal S E L Timer 0L capture signal 0 I23CR(FE5E) Int. request to address 0001B INT2 INT1 H level L level Int. request to address 00003 7 6 5 4 3 2 1 0 I01CR(FE5D) Int. request to address 0000B INT0 H level L level Port 7 (Interrupt) Block Diagram ＡII-8 Important Note This document is designed to provide the reader with accurate information in easily understandable form regarding the device features and the correct device implementation procedures. The sample configurations included in the various descriptions are intended for reference only and should not be directly incorporated in user product configurations. ON Semiconductor shall bear no responsibility for obligations concerning patent infringements, safety or other legal disputes arising from prototypes or actual products created using the information contained herein. LC870800 SERIES USER’S MANUAL Rev : 1.01 June 29, 2011 ON Semiconductor Digital Solution Division Microcontroller & Flash Business Unit