Si86xx 1 Mbps, 2.5 kVrms Digital Isolators

Si86xx
1 M B PS , 2.5 K V RMS D IGITAL I SOLATORS
Features







High-speed operation
DC to 1 Mbps
No start-up initialization required
Wide Operating Supply Voltage
2.5–5.5 V
Up to 2500 VRMS isolation
60-year life at rated working voltage
High electromagnetic immunity
Ultra low power (typical)
5 V Operation
1.6 mA per channel at 1 Mbps
2.5 V Operation
1.5 mA per channel at 1 Mbps
Tri-state outputs with ENABLE
Schmitt trigger inputs
Transient Immunity 50 kV/µs
AEC-Q100 qualification
Wide temperature range
–40 to 125 °C
 RoHS-compliant packages
SOIC-16 wide body
SOIC-16 narrow body
SOIC-8 narrow body





Applications




Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated switch mode supplies




Isolated ADC, DAC
Motor control
Power inverters
Communication systems
Safety Regulatory Approvals
UL 1577 recognized
Up to 2500 VRMS for 1 minute
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
 CSA component notice 5A approval

CQC
certification approval
IEC 60950-1, 61010-1
GB4943.1


Ordering Information:
See page 38.
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices
offering substantial data rate, propagation delay, power, size, reliability, and
external BOM advantages over legacy isolation technologies. The operating
parameters of these products remain stable across wide temperature ranges
and throughout device service life for ease of design and highly uniform
performance. All device versions have Schmitt trigger inputs for high noise
immunity and only require VDD bypass capacitors.
All products support Data rates up to 1 Mbps and Enable inputs which provide
a single point control for enabling and disabling output drive. All products are
safety certified by UL, CSA, VDE, and CQC and support withstand ratings up
to 2.5 kVRMS.
Rev. 1.0 6/15
Copyright © 2015 by Silicon Laboratories
Si86xx
Si86xx
2
Rev. 1.0
Si86xx
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.2. Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4. Pin Descriptions (Si861x/2x Narrow Body SOIC-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5. Pin Descriptions (Si863x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
6. Pin Descriptions (Si864x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
7. Pin Descriptions (Si8650/51/52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8. Pin Descriptions (Si866x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
11. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
14. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
15. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
16. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
16.1. Top Marking (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
16.2. Top Marking Explanation (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . 48
16.3. Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
16.4. Top Marking Explanation (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . 49
16.5. Top Marking (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
16.6. Top Marking Explanation (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . 50
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Rev. 1.0
3
Si86xx
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating Temperature*
Supply Voltage
Symbol
Min
Typ
Max
Unit
TA
–40
25
125
ºC
VDD1
2.5
—
5.5
V
VDD2
2.5
—
5.5
V
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Electrical Characteristics
(VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 °C)
Parameter
Symbol
VDD Undervoltage
VDDUV+
Threshold
VDD Undervoltage
VDDUV–
Threshold
VDD Undervoltage
VDDHYS
Hysteresis
Positive-Going Input
VT+
Threshold
Negative-Going
VT–
Input Threshold
Input Hysteresis
VHYS
High Level Input Voltage
VIH
Low Level input voltage
VIL
High Level Output Voltage
VOH
Low Level Output Voltage
Input Leakage Current
Output Impedance1
Enable Input High Current
Enable Input Low Current
VOL
IL
ZO
IENH
IENL
Test Condition
VDD1, VDD2 rising
Min
1.95
Typ
2.24
Max
2.375
Unit
V
VDD1, VDD2 falling
1.88
2.16
2.325
V
50
70
95
mV
All inputs rising
1.4
1.67
1.9
V
All inputs falling
1.0
1.23
1.4
V
0.38
2.0
—
VDD1,VDD2 –
0.4
—
—
—
—
—
0.44
—
—
4.8
0.50
—
0.8
—
V
V
V
V
0.2
—
50
2.0
2.0
0.4
±10
—
—
—
V
µA

µA
µA
loh = –4 mA
lol = 4 mA
VENx = VIH
VENx = VIL
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
4
Rev. 1.0
Si86xx
Table 2. Electrical Characteristics (Continued)
(VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
DC Supply Current (All inputs 0 V or at Supply)
Typ
Max
Unit
Si8610Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
0.6
0.8
1.8
0.8
1.2
1.5
2.9
1.5
Si8620Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
0.8
1.4
3.3
1.4
1.4
2.2
5.3
2.2
Si8621Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.2
1.2
2.4
2.4
1.9
1.9
3.8
3.8
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
0.9
1.9
4.6
1.9
1.6
3.0
7.4
3.0
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.3
1.7
3.9
3.0
2.1
2.7
5.9
4.5
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.0
2.4
6.1
2.5
1.6
3.8
9.2
4.0
mA
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.4
2.3
5.2
3.6
2.2
3.7
7.8
5.4
mA
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.8
1.8
4.4
4.4
2.9
2.9
6.6
6.6
mA
Si8630Ax
VDD1
VDD2
VDD1
VDD2
Si8631Ax
VDD1
VDD2
VDD1
VDD2
Si8640Ax
VDD1
VDD2
VDD1
VDD2
Si8641Ax
VDD1
VDD2
VDD1
VDD2
Si8642Ax
VDD1
VDD2
VDD1
VDD2
mA
mA
mA
mA
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.0
5
Si86xx
Table 2. Electrical Characteristics (Continued)
(VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 °C)
Parameter
Si8650Ax
VDD1
VDD2
VDD1
VDD2
Si8651Ax
VDD1
VDD2
VDD1
VDD2
Si8652Ax
VDD1
VDD2
VDD1
VDD2
Si8660Ax
VDD1
VDD2
VDD1
VDD2
Si8661Ax
VDD1
VDD2
VDD1
VDD2
Si8662Ax
VDD1
VDD2
VDD1
VDD2
Si8663Ax
VDD1
VDD2
VDD1
VDD2
Symbol
Test Condition
Min
Typ
Max
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.1
3.1
7.0
3.3
1.8
4.7
9.8
5.0
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.5
2.7
6.6
4.0
2.4
4.1
9.2
6.0
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
2.0
2.4
5.6
5.0
3.0
3.6
7.8
7.5
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.2
3.5
8.8
3.7
1.9
5.3
12.3
5.6
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.7
3.4
7.9
4.8
2.7
5.1
11.1
7.2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
2.2
3.0
7.5
5.6
3.3
4.5
10.5
8.4
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
2.6
2.6
6.5
6.5
3.9
3.9
9.1
9.1
Unit
mA
mA
mA
mA
mA
mA
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
6
Rev. 1.0
Si86xx
Table 2. Electrical Characteristics (Continued)
(VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all Outputs)
Si8610Ax
VDD1
—
1.2
2.0
—
0.9
1.5
VDD2
Si8620Ax
—
2.1
3.1
VDD1
—
1.6
2.4
VDD2
Si8621Ax
VDD1
—
1.9
2.9
—
1.9
2.9
VDD2
Si8630Ax
VDD1
—
2.8
3.9
—
2.2
3.1
VDD2
Si8631Ax
VDD1
—
2.7
3.8
—
2.6
3.6
VDD2
Si8640Ax
VDD1
—
3.6
5.0
—
2.9
4.0
VDD2
Si8641Ax
VDD1
—
3.4
4.8
—
3.3
4.6
VDD2
Si8642Ax
—
3.3
4.6
VDD1
—
3.3
4.6
VDD2
Si8650Ax
VDD1
—
4.1
5.7
—
3.7
5.2
VDD2
Si8651Ax
VDD1
—
4.2
5.8
—
3.8
5.3
VDD2
Si8652Ax
—
4.0
5.6
VDD1
—
4.0
5.6
VDD2
Si8660Ax
VDD1
—
5.0
7.0
—
4.2
5.9
VDD2
Si8661Ax
VDD1
—
4.9
6.9
—
4.6
6.4
VDD2
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.0
7
Si86xx
Table 2. Electrical Characteristics (Continued)
(VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 °C)
Parameter
Si8662Ax
VDD1
VDD2
Si8663Ax
VDD1
VDD2
Symbol
Test Condition
Min
Typ
Max
Unit
—
—
5.1
4.7
7.1
6.6
mA
—
—
4.9
4.9
6.8
6.8
mA
0
—
—
—
—
—
—
—
1
250
35
25
Mbps
ns
ns
ns
—
—
—
—
—
40
35
2.5
4.0
ns
ns
ns
2.5
4.0
—
35
350
50
—
—
ps
kV/µs
—
—
—
6.0
8.0
15
11
12
40
ns
ns
µs
Timing Characteristics
All Models
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
|tPLH – tPHL|
Propagation Delay Skew2
Channel-Channel Skew
Output Rise Time
Output Fall Time
tPHL, tPLH
PWD
tPSK(P-P)
tPSK
tr
tf
Peak eye diagram jitter
Common Mode
Transient Immunity
tJIT(PK)
CMTI
Enable to Data Valid
Enable to Data Tri-State
Start-up Time3
ten1
ten2
tSU
See Figure 2
See Figure 2
CL = 15 pF
See Figure 2
CL = 15 pF
See Figure 2
See Figure 8
VI = VDD or 0 V
VCM = 1500 V (see
Figure 3)
See Figure 1
See Figure 1
—
ns
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
8
Rev. 1.0
Si86xx
ENABLE
OUTPUTS
ten1
ten2
Figure 1. ENABLE Timing Diagram
1.4 V
Typical
Input
tPLH
tPHL
90%
90%
10%
10%
1.4 V
Typical
Output
tr
tf
Figure 2. Propagation Delay Timing
Rev. 1.0
9
Si86xx
3 to 5 V
Supply
Si86xx
Input Signal
Switch
3 to 5 V
Isolated Supply
VDD1
VDD2
INPUT
OUTPUT
Oscilloscope
GND1
GND2
Isolated Ground
Input
High Voltage
Differential
Probe
Output
Vcm Surge
Output
High Voltage
Surge Generator
Figure 3. Common-Mode Transient Immunity Test Circuit
10
Rev. 1.0
Si86xx
Table 3. Electrical Characteristics
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 °C)
Parameter
Test Condition
Min
Typ
Max
Unit
VDD Undervoltage Threshold VDDUV+
VDD1, VDD2 rising
1.95
2.24
2.375
V
VDD Undervoltage Threshold VDDUV–
VDD1, VDD2 falling
1.88
2.16
2.325
V
50
70
95
mV
VDD Undervoltage
Hysteresis
Symbol
VDDHYS
Positive-Going Input
Threshold
VT+
All inputs rising
1.4
1.67
1.9
V
Negative-Going Input
Threshold
VT–
All inputs falling
1.0
1.23
1.4
V
Input Hysteresis
VHYS
0.38
0.44
0.50
V
High Level Input Voltage
VIH
2.0
—
—
V
Low Level Input Voltage
VIL
—
—
0.8
V
High Level Output Voltage
VOH
loh = –4 mA
VDD1, VDD2 – 0.4
3.1
—
V
Low Level Output Voltage
VOL
lol = 4 mA
—
0.2
0.4
V
IL
—
—
±10
µA
ZO
—
50
—

Input Leakage Current
1
Output Impedance
Enable Input High Current
IENH
VENx = VIH
—
2.0
—
µA
Enable Input Low Current
IENL
VENx = VIL
—
2.0
—
µA
mA
DC Supply Current (All inputs 0 V or at supply)
Si8610Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
0.6
0.8
1.8
0.8
1.2
1.5
2.9
1.5
Si8620Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
0.8
1.4
3.3
1.4
1.4
2.2
5.3
2.2
Si8621Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.2
1.2
2.4
2.4
1.9
1.9
3.8
3.8
Si8630Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
0.9
1.9
4.6
1.9
1.6
3.0
7.4
3.0
mA
mA
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.0
11
Si86xx
Table 3. Electrical Characteristics (Continued)
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si8631Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.3
1.7
3.9
3.0
2.1
2.7
5.9
4.5
mA
Si8640Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.0
2.4
6.1
2.5
1.6
3.8
9.2
4.0
mA
Si8641Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.4
2.3
5.2
3.6
2.2
3.7
7.8
5.4
mA
Si8642Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.8
1.8
4.4
4.4
2.9
2.9
6.6
6.6
mA
Si8650Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.1
3.1
7.0
3.3
1.8
4.7
9.8
5.0
Si8651Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.5
2.7
6.6
4.0
2.4
4.1
9.2
6.0
Si8652Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
2.0
2.4
5.6
5.0
3.0
3.6
7.8
7.5
mA
mA
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
12
Rev. 1.0
Si86xx
Table 3. Electrical Characteristics (Continued)
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Si8660Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.2
3.5
8.8
3.7
1.9
5.3
12.3
5.6
Si8661Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.7
3.4
7.9
4.8
2.7
5.1
11.1
7.2
Si8662Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
2.2
3.0
7.5
5.6
3.3
4.5
10.5
8.4
Si8663Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
2.6
2.6
6.5
6.5
3.9
3.9
9.1
9.1
Unit
mA
mA
mA
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.0
13
Si86xx
Table 3. Electrical Characteristics (Continued)
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8610Ax
VDD1
VDD2
—
—
1.2
0.9
2.0
1.5
mA
Si8620Ax
VDD1
VDD2
—
—
2.1
1.6
3.1
2.4
mA
Si8621Ax
VDD1
VDD2
—
—
1.9
1.9
2.9
2.9
mA
Si8630Ax
VDD1
VDD2
—
—
2.8
2.2
3.9
3.1
mA
Si8631Ax
VDD1
VDD2
—
—
2.7
2.6
3.8
3.6
mA
Si8640Ax
VDD1
VDD2
—
—
3.6
2.9
5.0
4.0
mA
Si8641Ax
VDD1
VDD2
—
—
3.4
3.3
4.8
4.6
mA
Si8642Ax
VDD1
VDD2
—
—
3.3
3.3
4.6
4.6
mA
Si8650Ax
VDD1
VDD2
—
—
4.1
3.7
5.7
5.2
mA
Si8651Ax
VDD1
VDD2
—
—
4.2
3.8
5.8
5.3
mA
Si8652Ax
VDD1
VDD2
—
—
4.0
4.0
5.6
5.6
mA
Si8660Ax
VDD1
VDD2
—
—
5.0
4.2
7.0
5.9
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
14
Rev. 1.0
Si86xx
Table 3. Electrical Characteristics (Continued)
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si8661Ax
VDD1
VDD2
—
—
4.9
4.6
6.9
6.4
mA
Si8662Ax
VDD1
VDD2
—
—
5.1
4.7
7.1
6.6
mA
Si8663Ax
VDD1
VDD2
—
—
4.9
4.9
6.8
6.8
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.0
15
Si86xx
Table 3. Electrical Characteristics (Continued)
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Maximum Data Rate
0
—
1
Mbps
Minimum Pulse Width
—
—
250
ns
Timing Characteristics
All Models
Propagation Delay
Pulse Width Distortion
|tPLH – tPHL|
Propagation Delay Skew2
Channel-Channel Skew
tPHL, tPLH
See Figure 2
—
—
35
ns
PWD
See Figure 2
—
—
25
ns
tPSK(P-P)
—
—
40
ns
tPSK
—
—
35
ns
2.5
4.0
2.5
4.0
Output Rise Time
tr
CL = 15 pF
See Figure 2
—
Output Fall Time
tf
CL = 15 pF
See Figure 2
—
Peak eye diagram jitter
tJIT(PK)
See Figure 8
—
350
—
ps
Common Mode
Transient Immunity
CMTI
VI = VDD or 0 V
VCM = 1500 V (see
Figure 3)
35
50
—
kV/µs
Enable to Data Valid
ten1
See Figure 1
—
6.0
11
ns
Enable to Data Tri-State
ten2
See Figure 1
—
8.0
12
ns
—
15
40
µs
Start-Up Time
3
tSU
ns
ns
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
16
Rev. 1.0
Si86xx
Table 4. Electrical Characteristics
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD Undervoltage Threshold
VDDUV+
VDD1, VDD2 rising
1.95
2.24
2.375
V
VDD Undervoltage Threshold
VDDUV–
VDD1, VDD2 falling
1.88
2.16
2.325
V
VDD Undervoltage Hysteresis
VDDHYS
50
70
95
mV
Positive-Going Input Threshold
VT+
All inputs rising
1.4
1.67
1.9
V
Negative-Going Input Threshold
VT–
All inputs falling
1.0
1.23
1.4
V
Input Hysteresis
VHYS
0.38
0.44
0.50
V
High Level Input Voltage
VIH
2.0
—
—
V
Low Level Input Voltage
VIL
—
—
0.8
V
High Level Output Voltage
VOH
loh = –4 mA
VDD1,VD
D2 – 0.4
2.3
—
V
Low Level Output Voltage
VOL
lol = 4 mA
—
0.2
0.4
V
IL
—
—
±10
µA
ZO
—
50
—

Input Leakage Current
Output Impedance
1
Enable Input High Current
IENH
VENx = VIH
—
2.0
—
µA
Enable Input Low Current
IENL
VENx = VIL
—
2.0
—
µA
mA
DC Supply Current (All inputs 0 V or at supply)
Si8610Ax
VDD1
VDD2
VDD1
VDD2
Si8620Ax
VDD1
VDD2
VDD1
VDD2
Si8621Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax))
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
0.6
0.8
1.8
0.8
1.2
1.5
2.9
1.5
VI = 0(Ax))
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
0.8
1.4
3.3
1.4
1.4
2.2
5.3
2.2
VI = 0(Ax))
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.2
1.2
2.4
2.4
1.9
1.9
3.8
3.8
mA
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.0
17
Si86xx
Table 4. Electrical Characteristics (Continued)
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si8630Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
0.9
1.9
4.6
1.9
1.6
3.0
7.4
3.0
mA
Si8631Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.3
1.7
3.9
3.0
2.1
2.7
5.9
4.5
mA
Si8640Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.0
2.4
6.1
2.5
1.6
3.8
9.2
4.0
mA
Si8641Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.4
2.3
5.2
3.6
2.2
3.7
7.8
5.4
mA
Si8642Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.8
1.8
4.4
4.4
2.9
2.9
6.6
6.6
mA
Si8650Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.1
3.1
7.0
3.3
1.8
4.7
9.8
5.0
Si8651Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.5
2.7
6.6
4.0
2.4
4.1
9.2
6.0
mA
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
18
Rev. 1.0
Si86xx
Table 4. Electrical Characteristics (Continued)
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Si8652Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
2.0
2.4
5.6
5.0
3.0
3.6
7.8
7.5
Si8660Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.2
3.5
8.8
3.7
1.9
5.3
12.3
5.6
Si8661Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.7
3.4
7.9
4.8
2.7
5.1
11.1
7.2
Si8662Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
2.2
3.0
7.5
5.6
3.3
4.5
10.5
8.4
Si8663Ax
VDD1
VDD2
VDD1
VDD2
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
2.6
2.6
6.5
6.5
3.9
3.9
9.1
9.1
Unit
mA
mA
mA
mA
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.0
19
Si86xx
Table 4. Electrical Characteristics (Continued)
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8610Ax
VDD1
VDD2
—
—
1.2
0.9
2.0
1.5
mA
Si8620Ax
VDD1
VDD2
—
—
2.1
1.6
3.1
2.4
mA
Si8621Ax
VDD1
VDD2
—
—
1.9
1.9
2.9
2.9
mA
Si8630Ax
VDD1
VDD2
—
—
2.8
2.2
3.9
3.1
mA
Si8631Ax
VDD1
VDD2
—
—
2.7
2.6
3.8
3.6
mA
Si8640Ax
VDD1
VDD2
—
—
3.6
2.9
5.0
4.0
mA
Si8641Ax
VDD1
VDD2
—
—
3.4
3.3
4.8
4.6
mA
Si8642Ax
VDD1
VDD2
—
—
3.3
3.3
4.6
4.6
mA
Si8650Ax
VDD1
VDD2
—
—
4.1
3.7
5.7
5.2
mA
Si8651Ax
VDD1
VDD2
—
—
4.2
3.8
5.8
5.3
mA
Si8652Ax
VDD1
VDD2
—
—
4.0
4.0
5.6
5.6
mA
Si8660Ax
VDD1
VDD2
—
—
5.0
4.2
7.0
5.9
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
20
Rev. 1.0
Si86xx
Table 4. Electrical Characteristics (Continued)
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si8661Ax
VDD1
VDD2
—
—
4.9
4.6
6.9
6.4
mA
Si8662Ax
VDD1
VDD2
—
—
5.1
4.7
7.1
6.6
mA
Si8663Ax
VDD1
VDD2
—
—
4.9
4.9
6.8
6.8
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.0
21
Si86xx
Table 4. Electrical Characteristics (Continued)
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Maximum Data Rate
0
—
1
Mbps
Minimum Pulse Width
—
—
250
ns
Timing Characteristics
All Models
Propagation Delay
Pulse Width Distortion
|tPLH - tPHL|
Propagation Delay Skew2
Channel-Channel Skew
tPHL, tPLH
See Figure 2
—
—
35
ns
PWD
See Figure 2
—
—
25
ns
tPSK(P-P)
—
—
40
ns
tPSK
—
—
35
ns
2.5
4.0
2.5
4.0
Output Rise Time
tr
CL = 15 pF
See Figure 2
—
Output Fall Time
tf
CL = 15 pF
See Figure 2
—
Peak Eye Diagram Jitter
tJIT(PK)
See Figure 8
—
350
—
ps
Common Mode
Transient Immunity
CMTI
VI = VDD or 0 V
VCM = 1500 V (see Figure 3)
35
50
—
kV/µs
Enable to Data Valid
ten1
See Figure 1
—
6.0
11
ns
Enable to Data Tri-State
ten2
See Figure 1
—
8.0
12
ns
—
15
40
µs
Startup Time
3
tSU
ns
ns
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
22
Rev. 1.0
Si86xx
Table 5. Regulatory Information*
CSA
The Si86xx is certified under CSA Component Acceptance Notice 5A, IEC61010-1 and IEC60950-1. For more
details, see File 232873.
VDE
The Si86xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
UL
The Si86xx is certified under UL1577 component recognition program. For more details, see File E257455.
CQC
The Si86xx is certified under GB4943.1-2011. For more details, see certificates CQC13001096110 and
CQC13001096239.
*Note: Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
For more information, see "8. Pin Descriptions (Si866x)" on page 38.
Rev. 1.0
23
Si86xx
Table 6. Insulation and Safety-Related Specifications
Value
Parameter
Symbol
Test Condition
WB
SOIC-16
NB
SOIC-16
NB
SOIC-8
Unit
Nominal Air Gap (Clearance)1
L(IO1)
8.0
4.9
4.9
mm
Nominal External Tracking
(Creepage)1
L(IO2)
8.0
4.01
4.01
mm
0.014
0.014
0.014
600
600
600
VRMS
0.019
0.019
0.040
mm
1012

Minimum Internal Gap
(Internal Clearance)
Tracking Resistance
(Proof Tracking Index)
PTI
Erosion Depth
ED
Resistance (Input-Output)
2
Capacitance (Input-Output)2
Input Capacitance
IEC60112
3
RIO
10
CIO
f = 1 MHz
CI
12
10
12
mm
2.0
2.0
2.0
pF
4.0
4.0
4.0
pF
Notes:
1. The values in this table correspond to the nominal creepage and clearance values. VDE certifies the clearance and
creepage limits as 4.7 mm minimum for the NB SOIC-16 and SOIC-8 packages and 8.5 mm minimum for the WB
SOIC-16 package. UL does not impose a clearance and creepage minimum for component-level certifications. CSA
certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC-16 and SOIC-8 and 7.6 mm minimum
for the WB SOIC-16 package.
2. To determine resistance and capacitance, the Si86xx is converted into a 2-terminal device. Pins 1–8 (Pins 1-4 for the
NB SOIC-8) are shorted together to form the first terminal and pins 9–16 (Pins 5-8 for the NB SOIC-8) are shorted
together to form the second terminal. The parameters are then measured between these two terminals.
3. Measured from input pin to ground.
Table 7. IEC 60664-1 (VDE 0844 Part 2) Ratings
Specification
Parameter
Basic Isolation Group
Installation Classification
24
Test Conditions
NB SOIC-16
NB SOIC-8
WB SOIC-16
I
I
Rated Mains Voltages < 150 VRMS
I-IV
I-IV
Rated Mains Voltages < 300 VRMS
I-III
I-IV
Rated Mains Voltages < 400 VRMS
I-II
I-III
Rated Mains Voltages < 600 VRMS
I-II
I-III
Material Group
Rev. 1.0
Si86xx
Table 8. IEC 60747-5-2 Insulation Characteristics for Si86xxxx*
Characteristic
Parameter
WB
SOIC-16
NB
SOIC-16
SOIC-8
Unit
1200
630
Vpeak
VPR
Method b1
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
2250
1182
VIOTM
t = 60 sec
6000
6000
2
2
>109
>109
Symbol
Maximum Working Insulation
Voltage
Input to Output Test Voltage
Transient Overvoltage
Test Condition
VIORM
Pollution Degree
(DIN VDE 0110, Table 1)
Insulation Resistance at TS,
VIO = 500 V
RS
Vpeak

*Note: Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of
40/125/21.
Table 9. IEC Safety Limiting Values1
Max
Parameter
Symbol
Case Temperature
TS
Safety Input, Output,
or Supply Current
IS
Device Power
Dissipation2
PD
Test Condition
JA = 100 °C/W (WB SOIC-16),
105 °C/W (NB SOIC-16),
140 °C/W (NB SOIC-8),
VI = 5.5 V, TJ = 150 °C,
TA = 25 °C
WB
SOIC-16
NB
SOIC-16
NB
SOIC-8
Unit
150
150
150
°C
220
215
160
mA
415
415
150
mW
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 4, 5 and 6.
2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square
wave.
Rev. 1.0
25
Si86xx
Table 10. Thermal Characteristics
Parameter
Symbol
WB SOIC-16
NB SOIC-16
NB SOIC-8
Unit
JA
100
105
140
ºC/W
IC Junction-to-Air Thermal
Resistance
Safety-Limiting Current (mA)
500
450
VDD1, VDD2 = 2.70 V
400
370
VDD1, VDD2 = 3.6 V
300
220
200
VDD1, VDD2 = 5.5 V
100
0
0
50
100
Temperature (ºC)
150
200
Figure 4. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Safety-Limiting Current (mA)
500
430
VDD1, VDD2 = 2.70 V
400
360
VDD1, VDD2 = 3.6 V
300
215
200
VDD1, VDD2 = 5.5 V
100
0
0
50
100
Temperature (ºC)
150
200
Figure 5. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
26
Rev. 1.0
Safety-Limiting Values (mA)
Si86xx
400
320
VDD1, VDD2 = 2.5 V
300 270
200
VDD1, VDD2 = 3.3 V
160
VDD1, VDD2 = 5.5 V
100
0
0
50
100
150
Case Temperature (ºC)
200
Figure 6. (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Rev. 1.0
27
Si86xx
Table 11. Absolute Maximum Ratings1
Parameter
Symbol
Min
Max
Unit
TSTG
–65
150
ºC
Ambient Temperature Under Bias
TA
–40
125
ºC
Junction Temperature
TJ
—
150
°C
VDD1, VDD2
–0.5
7.0
V
Input Voltage
VI
–0.5
VDD + 0.5
V
Output Voltage
VO
–0.5
VDD + 0.5
V
Output Current Drive Channel
(All devices unless otherwise stated)
IO
—
10
mA
Output Current Drive Channel
(All Si86xxxA-x-xx devices)
IO
—
22
mA
Latchup Immunity3
—
100
V/ns
Lead Solder Temperature (10 s)
—
260
ºC
Maximum Isolation (Input to Output) (1 sec)
NB SOIC-16, SOIC-8
—
4500
VRMS
Maximum Isolation (Input to Output) (1 sec)
WB SOIC-16
—
6500
VRMS
Storage Temperature2
Supply Voltage
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
3. Latchup immunity specification is for slew rate applied across GND1 and GND2.
28
Rev. 1.0
Si86xx
2. Functional Description
2.1. Theory of Operation
The operation of an Si86xx channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si86xx channel is shown in
Figure 7.
Transmitter
Receiver
RF
OSCILLATOR
A
MODULATOR
SemiconductorBased Isolation
Barrier
DEMODULATOR
B
Figure 7. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 8 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 8. Modulation Scheme
Rev. 1.0
29
Si86xx
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 9, where UVLO+ and UVLOare the positive-going and negative-going thresholds respectively. Refer to Table 12 to determine outputs when
power supply (VDD) is not present. Additionally, refer to Table 13 for logic conditions when enable pins are used.
Table 12. Si86xx Logic Operation
VI
Input1,2
EN
Input1,2,3,4
VDDI
State1,5,6
VDDO
State1,5,6
VO Output1,2
H
H or NC
P
P
H
L
H or NC
P
P
L
X7
L
P
P
Hi-Z8
H or NC
UP
P
X7
L
UP
P
X7
X7
P
UP
X
7
L
Hi-Z8
Comments
Enabled, normal operation.
Disabled.
Upon transition of VDDI from unpowered to powered, VO returns to the same state as VI in less
than 1 µs.
Disabled.
Undetermined Upon transition of VDDO from unpowered to powered, VO returns to the same state as VI within
1 µs, if EN is in either the H or NC state. Upon transition of VDDO from unpowered to powered, VO
returns to Hi-Z within 1 µs if EN is L.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN
is the enable control input located on the same output side.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si86xx is
operating in noisy environments.
4. No Connect (NC) replaces EN1 on some devices. No Connects are not internally connected and can be left floating,
tied to VDD, or tied to GND.
5. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V.
6. “Unpowered” state (UP) is defined as VDD = 0 V.
7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
8. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is
disabled (EN = 0).
30
Rev. 1.0
Si86xx
Table 13. Enable Input Truth1
P/N
Operation
EN11,2 EN21,2
Si861x/2x
—
—
Outputs are enabled and follow input state.
Si8630
—
H
Outputs B1, B2, B3 are enabled and follow input state.
—
L
Outputs B1, B2, B3 are disabled and in high impedance state.3
H
X
Output A3 enabled and follows input state.
L
X
Output A3 disabled and in high impedance state.3
X
H
Outputs B1, B2 are enabled and follow input state.
X
L
Outputs B1, B2 are disabled and in high impedance state.3
—
H
Outputs B1, B2, B3, B4 are enabled and follow the input state.
—
L
Outputs B1, B2, B3, B4 are disabled and in high impedance state.3
H
X
Output A4 enabled and follows the input state.
L
X
Output A4 disabled and in high impedance state.3
X
H
Outputs B1, B2, B3 are enabled and follow the input state.
X
L
Outputs B1, B2, B3 are disabled and in high impedance state.3
H
X
Outputs A3 and A4 are enabled and follow the input state.
L
X
Outputs A3 and A4 are disabled and in high impedance state.3
X
H
Outputs B1 and B2 are enabled and follow the input state.
X
L
Outputs B1 and B2 are disabled and in high impedance state.3
—
H
Outputs B1, B2, B3, B4, B5 are enabled and follow input state.
—
L
Outputs B1, B2, B3, B4, B5 are disabled and Logic Low or in high impedance
state.3
H
X
Output A5 enabled and follow input state.
L
X
Output A5 disabled and in high impedance state.3
X
H
Outputs B1, B2, B3, B4 are enabled and follow input state.
X
L
Outputs B1, B2, B3, B4 are disabled and in high impedance state.3
H
X
Outputs A4 and A5 are enabled and follow input state.
L
X
Outputs A4 and A5 are disabled and in high impedance state.3
X
H
Outputs B1, B2, B3 are enabled and follow input state.
X
L
Outputs B1, B2, B3 are disabled and in high impedance state.3
—
—
Outputs are enabled and follow input state.
Si8631
Si8640
Si8641
Si8642
Si8650
Si8651
Si8652
Si866x
Notes:
1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. These inputs are
internally pulled-up to local VDD by a 2 µA current source allowing them to be connected to an external logic level (high
or low) or left floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If
EN1, EN2 are unused, it is recommended they be connected to an external logic level, especially if the Si86xx is
operating in a noisy environment.
2. X = not applicable; H = Logic High; L = Logic Low.
3. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is
disabled (EN = 0).
Rev. 1.0
31
Si86xx
3.1. Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following
this, the outputs follow the states of inputs.
3.2. Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDD is below its specified operating circuits range. Both Side A and Side B each have their own
undervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A
unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when VDD1 rises above
VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply.
UVLO+
UVLO-
VDD1
UVLO+
UVLO-
VDD2
INPUT
tSTART
tSD
tSTART
tSTART
tPHL
OUTPUT
Figure 9. Device Behavior during Normal Operation
32
Rev. 1.0
tPLH
Si86xx
3.3. Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically
separated from the safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance
(creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those
creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating
(commonly referred to as working voltage protection). Table 5 on page 23 and Table 6 on page 24 detail the
working voltage and creepage/clearance capabilities of the Si86xx. These tables also detail the component
standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for
end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, 60601-1, etc.)
requirements before starting any design that uses a digital isolator.
3.3.1. Supply Bypass
The Si86xx family requires a 0.1 µF bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The
capacitor should be placed as close as possible to the package. To enhance the robustness of a design, the user
may also include resistors (50–300  ) in series with the inputs and outputs if the system is excessively noisy.
3.3.2. Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination
of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving
loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
Rev. 1.0
33
Si86xx
4. Pin Descriptions (Si861x/2x Narrow Body SOIC-8)
VDD1
RF
XMITR
A1
VDD1/NC
GND1
I
s
o
l
a
t
i
o
n
VDD2
RF
RCVR
GND2/NC
A1
RF
XMITR
B1
A2
RF
XMITR
GND2
Si8610 NB SOIC-8
VDD1
GND1
I
s
o
l
a
t
i
o
n
VDD2
VDD1
RF
RCVR
B1
A1
RF
XMITR
RF
RCVR
B2
A2
RF
RCVR
Si8620 NB SOIC-8
GND2
GND1
I
s
o
l
a
t
i
o
n
VDD2
RF
RCVR
B1
RF
XMITR
B2
Si8621 NB SOIC-8
Name
SOIC-8 Pin#
Si861x
SOIC-8 Pin#
Si862x
Type
Description
VDD1/NC*
1,3
1
Supply
Side 1 power supply.
GND1
4
4
Ground
Side 1 ground.
A1
2
2
Digital I/O
Side 1 digital input or output.
A2
NA
3
Digital I/O
Side 1 digital input or output.
B1
6
7
Digital I/O
Side 2 digital input or output.
B2
NA
6
Digital I/O
Side 2 digital input or output.
VDD2
8
8
Supply
Side 2 power supply.
GND2/NC*
5.7
5
Ground
Side 2 ground.
*Note: No connect. These pins are not internally connected. They can be left floating, tied to VDD, or tied to GND.
34
Rev. 1.0
GND2
Si86xx
5. Pin Descriptions (Si863x)
VDD1
VDD1
VDD2
GND2
GND1
A1
RF
XMITR
A2
RF
XMITR
A3
RF
XMITR
NC
I
s
o
l
a
t
i
o
n
GND2
GND1
RF
RCVR
B1
A1
RF
XMITR
RF
RCVR
B2
A2
RF
XMITR
RF
RCVR
B3
A3
RF
RCVR
NC
NC
EN2
EN1
NC
GND1
VDD2
GND2
Si8630
GND1
I
s
o
l
a
t
i
o
n
RF
RCVR
B1
RF
RCVR
B2
RF
XMITR
B3
NC
EN2
Si8631
Name
SOIC-16 Pin#
Type
VDD1
1
Supply
Side 1 power supply.
1
Side 1 ground.
GND2
Description
GND1
2
Ground
A1
3
Digital Input
Side 1 digital input.
A2
4
Digital Input
Side 1 digital input.
A3
5
Digital I/O
NC
6
NA
EN1/NC2
7
Digital Input
GND1
81
Ground
Side 1 ground.
GND2
91
Ground
Side 2 ground.
EN2
10
Digital Input
NC
11
NA
B3
12
Digital I/O
B2
13
Digital Output
Side 2 digital output.
B1
14
Digital Output
Side 2 digital output.
GND2
151
Ground
Side 2 ground.
VDD2
16
Supply
Side 2 power supply.
Side 1 digital input or output.
No Connect.
Side 1 active high enable. NC on Si8630
Side 2 active high enable.
No Connect.
Side 2 digital input or output.
Notes:
1. For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pin 15
must also be connected to external ground.
2. No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
Rev. 1.0
35
Si86xx
6. Pin Descriptions (Si864x)
VDD1
VDD2
GND2
GND1
A1
RF
XMITR
A2
RF
XMITR
A3
RF
XMITR
A4
RF
XMITR
I
s
o
l
a
t
i
o
n
RF
RCVR
B1
RF
RCVR
B2
RF
RCVR
B3
RF
RCVR
B4
EN2
NC
GND1
GND2
Si8640
VDD1
VDD2
GND2
GND1
A1
RF
XMITR
A2
RF
XMITR
A3
RF
XMITR
A4
RF
RCVR
I
s
o
l
a
t
i
o
n
RF
RCVR
RF
RCVR
RF
RCVR
RF
XMITR
GND1
Si8641
B2
B3
B4
GND2
VDD2
GND2
GND1
B1
EN2
EN1
VDD1
A1
RF
XMITR
A2
RF
XMITR
A3
RF
RCVR
A4
RF
RCVR
I
s
o
l
a
t
i
o
n
RF
RCVR
B1
RF
RCVR
B2
RF
RF
XMITR
RCVR
B3
RF
XMITR
B4
EN2
EN1
GND1
Name
SOIC-16 Pin#
Type
VDD1
1
Supply
Side 1 power supply.
1
Side 1 ground.
Si8642
GND2
Description
GND1
2
Ground
A1
3
Digital Input
Side 1 digital input.
A2
4
Digital Input
Side 1 digital input.
A3
5
Digital I/O
Side 1 digital input or output.
A4
6
Digital I/O
Side 1 digital input or output.
EN1/NC2
7
Digital Input
GND1
81
Ground
Side 1 ground.
GND2
91
Ground
Side 2 ground.
EN2
10
Digital Input
B4
11
Digital I/O
Side 2 digital input or output.
B3
12
Digital I/O
Side 2 digital input or output.
B2
13
Digital Output
Side 2 digital output.
B1
14
Digital Output
Side 2 digital output.
GND2
151
Ground
Side 2 ground.
VDD2
16
Supply
Side 2 power supply.
Side 1 active high enable. NC on Si8640.
Side 2 active high enable.
Notes:
1. For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pin 15
must also be connected to external ground.
2. No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
36
Rev. 1.0
Si86xx
7. Pin Descriptions (Si8650/51/52)
VDD1
VDD2
A1
RF
XMITR
A2
RF
XMITR
A3
RF
XMITR
A4
RF
XMITR
A5
RF
XMITR
I
s
o
l
a
t
i
o
n
B1
B2
A2
RF
XMITR
RF
RCVR
B3
A3
RF
XMITR
RF
RCVR
B4
A4
RF
XMITR
A5
RF
RCVR
RF
RCVR
B5
EN2
GND2
Si8650
VDD1
VDD2
RF
RCVR
NC
GND1
VDD1
RF
RCVR
RF
XMITR
A1
I
s
o
l
a
t
i
o
n
B1
RF
RCVR
B2
A2
RF
XMITR
RF
RCVR
B3
A3
RF
XMITR
RF
RCVR
B4
A4
RF
RCVR
A5
RF
RCVR
RF
XMITR
A1
B5
EN2
EN1
GND1
VDD2
RF
RCVR
Si8651
GND2
RF
XMITR
I
s
o
l
a
t
i
o
n
RF
RCVR
B1
RF
RCVR
B2
RF
RCVR
B3
RF
RF
XMITR
RCVR
B4
RF
XMITR
B5
EN2
EN1
GND1
Name
SOIC-16 Pin#
Type
VDD1
1
Supply
A1
2
Digital Input
Side 1 digital input.
A2
3
Digital Input
Side 1 digital input.
A3
4
Digital Input
Side 1 digital input.
A4
5
Digital I/O
Side 1 digital input or output.
A5
6
Digital I/O
Side 1 digital input or output.
EN1/NC*
7
Digital Input
GND1
8
Ground
Side 1 ground.
GND2
9
Ground
Side 2 ground.
EN2
10
Digital Input
B5
11
Digital I/O
Side 2 digital input or output.
B4
12
Digital I/O
Side 2 digital input or output.
B3
13
Digital Output
Side 2 digital output.
B2
14
Digital Output
Side 2 digital output.
B1
15
Digital Output
Side 2 digital output.
VDD2
16
Supply
Side 2 power supply.
Si8652
GND2
Description
Side 1 power supply.
Side 1 active high enable. NC on Si8650.
Side 2 active high enable.
*Note: No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
Rev. 1.0
37
Si86xx
8. Pin Descriptions (Si866x)
VDD1
RF
XMITR
A2
RF
XMITR
A3
RF
XMITR
A4
RF
XMITR
A5
RF
XMITR
A6
RF
XMITR
GND1
38
VDD1
VDD2
A1
I
s
o
l
a
t
i
o
n
VDD2
RF
RCVR
B1
A1
RF
XMITR
RF
RCVR
B2
A2
RF
XMITR
RF
RCVR
B3
A3
RF
XMITR
RF
RCVR
B4
A4
RF
XMITR
RF
RCVR
B5
A5
RF
XMITR
RF
RCVR
B6
A6
RF
RCVR
Si8660
GND2
GND1
I
s
o
l
a
t
i
o
n
VDD1
B1
A1
RF
XMITR
RF
RCVR
B2
A2
RF
XMITR
RF
RCVR
B3
A3
RF
XMITR
RF
RCVR
B4
A4
RF
XMITR
RF
RCVR
B5
A5
RF
RCVR
RF
XMITR
B6
A6
RF
RCVR
GND2
Si8661
GND1
VDD1
VDD2
RF
RCVR
I
s
o
l
a
t
i
o
n
B1
A1
RF
XMITR
RF
RCVR
B2
A2
RF
XMITR
RF
RCVR
B3
A3
RF
XMITR
RF
RCVR
B4
A4
RF
RCVR
RF
XMITR
B5
A5
RF
RCVR
RF
RF
XMITR
RCVR
B6
A6
RF
RCVR
Si8662
GND2
GND1
Name
SOIC-16 Pin#
Type
Description
VDD1
1
Supply
A1
2
Digital Input
Side 1 digital input.
A2
3
Digital Input
Side 1 digital input.
A3
4
Digital Input
Side 1 digital input.
A4
5
Digital I/O
Side 1 digital input or output.
A5
6
Digital I/O
Side 1 digital input or output.
A6
7
Digital I/O
Side 1 digital input or output.
GND1
8
Ground
Side 1 ground.
GND2
9
Ground
Side 2 ground.
B6
10
Digital I/O
Side 2 digital input or output.
B5
11
Digital I/O
Side 2 digital input or output.
B4
12
Digital I/O
Side 2 digital input or output.
B3
13
Digital Output
Side 2 digital output.
B2
14
Digital Output
Side 2 digital output.
B1
15
Digital Output
Side 2 digital output.
VDD2
16
Supply
Side 2 power supply.
Side 1 power supply.
Rev. 1.0
VDD2
RF
RCVR
I
s
o
l
a
t
i
o
n
RF
RCVR
B1
RF
RCVR
B2
RF
RCVR
B3
RF
XMITR
B4
RF
XMITR
B5
RF
RF
XMITR
RCVR
B6
Si8663
GND2
Si86xx
9. Ordering Guide
Table 14. Ordering Guide for Valid OPNs1,2
Ordering Part
Number (OPN)
Number of Number of Max Data
Rate
Inputs
Inputs
VDD1 Side VDD2 Side (Mbps)
Default
Output
State
Isolation
Rating
(kV)
Temp (°C)
Package
Si8610AB-B-IS
1
0
1
Low
2.5
–40 to 125 °C
SOIC-8
Si8620AB-B-IS
2
0
1
Low
2.5
–40 to 125 °C
SOIC-8
Si8621AB-B-IS
1
1
1
Low
2.5
–40 to 125 °C
SOIC-8
Si8630AB-B-IS
3
0
1
Low
2.5
–40 to 125 °C
WB SOIC-16
Si8630AB-B-IS1
3
0
1
Low
2.5
–40 to 125 °C
NB SOIC-16
Si8631AB-B-IS
2
1
1
Low
2.5
–40 to 125 °C
WB SOIC-16
Si8631AB-B-IS1
2
1
1
Low
2.5
–40 to 125 °C
NB SOIC-16
Si8640AB-B-IS1
4
0
1
Low
2.5
–40 to 125 °C
NB SOIC-16
Si8640AB-B-IS
4
0
1
Low
2.5
–40 to 125 °C
WB SOIC-16
Si8641AB-B-IS1
3
1
1
Low
2.5
–40 to 125 °C
NB SOIC-16
Si8641AB-B-IS
3
1
1
Low
2.5
–40 to 125 °C
WB SOIC-16
Si8642AB-B-IS1
2
2
1
Low
2.5
–40 to 125 °C
NB SOIC-16
Si8642AB-B-IS
2
2
1
Low
2.5
–40 to 125 °C
WB SOIC-16
Si8650AB-B-IS1
5
0
1
Low
2.5
–40 to 125 °C
NB SOIC-16
Si8651AB-B-IS1
4
1
1
Low
2.5
–40 to 125 °C
NB SOIC-16
Si8652AB-B-IS1
3
2
1
Low
2.5
–40 to 125 °C
NB SOIC-16
Si8660AB-B-IS1
6
0
1
Low
2.5
–40 to 125 °C
NB SOIC-16
Si8661AB-B-IS1
5
1
1
Low
2.5
–40 to 125 °C
NB SOIC-16
Si8662AB-B-IS1
4
2
1
Low
2.5
–40 to 125 °C
NB SOIC-16
Si8663AB-B-IS1
3
3
1
Low
2.5
–40 to 125 °C
NB SOIC-16
Notes:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard
classifications and peak solder temperatures.
2. “Si” and “SI” are used interchangeably.
Rev. 1.0
39
Si86xx
10. Package Outline: 16-Pin Wide Body SOIC
Figure 10 illustrates the package details for the Si86xx Digital Isolator. Table 15 lists the values for the dimensions
shown in the illustration.
Figure 10. 16-Pin Wide Body SOIC
40
Rev. 1.0
Si86xx
Table 15. Package Diagram Dimensions
Dimension
Min
Max
A
—
2.65
A1
0.10
0.30
A2
2.05
—
b
0.31
0.51
c
0.20
0.33
D
10.30 BSC
E
10.30 BSC
E1
7.50 BSC
e
1.27 BSC
L
0.40
1.27
h
0.25
0.75

0°
8°
aaa
—
0.10
bbb
—
0.33
ccc
—
0.10
ddd
—
0.25
eee
—
0.10
fff
—
0.20
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020C specification for
small body, lead-free components.
Rev. 1.0
41
Si86xx
11. Land Pattern: 16-Pin Wide-Body SOIC
Figure 11 illustrates the recommended land pattern details for the Si86xx in a 16-pin wide-body SOIC. Table 16
lists the values for the dimensions shown in the illustration.
Figure 11. 16-Pin SOIC Land Pattern
Table 16. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
9.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.90
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
42
Rev. 1.0
Si86xx
12. Package Outline: 16-Pin Narrow Body SOIC
Figure 12 illustrates the package details for the Si86xx in a 16-pin narrow-body SOIC (SO-16). Table 17 lists the
values for the dimensions shown in the illustration.
Figure 12. 16-pin Small Outline Integrated Circuit (SOIC) Package
Rev. 1.0
43
Si86xx
Table 17. Package Diagram Dimensions
Dimension
Min
Max
A
—
1.75
A1
0.10
0.25
A2
1.25
—
b
0.31
0.51
c
0.17
0.25
D
9.90 BSC
E
6.00 BSC
E1
3.90 BSC
e
1.27 BSC
L
0.40
L2
1.27
0.25 BSC
h
0.25
0.50
θ
0°
8°
aaa
0.10
bbb
0.20
ccc
0.10
ddd
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012,
Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
44
Rev. 1.0
Si86xx
13. Land Pattern: 16-Pin Narrow Body SOIC
Figure 13 illustrates the recommended land pattern details for the Si86xx in a 16-pin narrow-body SOIC. Table 18
lists the values for the dimensions shown in the illustration.
Figure 13. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 18. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.0
45
Si86xx
14. Package Outline: 8-Pin Narrow Body SOIC
Figure 14 illustrates the package details for the Si86xx. Table 19 lists the values for the dimensions shown in the
illustration.

Figure 14. 8-pin Small Outline Integrated Circuit (SOIC) Package
Table 19. Package Diagram Dimensions
Symbol
Millimeters
Min
Max
A
1.35
1.75
A1
0.10
0.25
A2
1.40 REF
1.55 REF
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
4.00
e
46
1.27 BSC
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27

0
8
Rev. 1.0
Si86xx
15. Land Pattern: 8-Pin Narrow Body SOIC
Figure 15 illustrates the recommended land pattern details for the Si86xx in an 8-pin narrow-body SOIC. Table 20
lists the values for the dimensions shown in the illustration.
Figure 15. PCB Land Pattern: 8-Pin Narrow Body SOIC
Table 20. PCM Land Pattern Dimensions (8-Pin Narrow Body SOIC)
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.0
47
Si86xx
16. Top Markings
16.1. Top Marking (16-Pin Wide Body SOIC)
Si86XYSV
YYWWRTTTTT
e4
TW
16.2. Top Marking Explanation (16-Pin Wide Body SOIC)
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (5, 4, 3, 2, 1)
Y = # of reverse channels (2, 1, 0)
(See Ordering Guide for more
information).
S = Speed Grade (max data rate) and operating mode:
A = 1 Mbps (default output = low)
B = 150 Mbps (default output = low)
D = 1 Mbps (default output = high)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5.0 kV
Line 1 Marking:
Base Part Number
Ordering Options
Line 2 Marking:
YY = Year
WW = Workweek
Assigned by assembly subcontractor. Corresponds to the
year and work week of the mold date.
RTTTTT = Mfg Code
Manufacturing code from assembly house
“R” indicates revision
Circle = 1.7 mm Diameter
(Center-Justified)
“e4” Pb-free symbol
Country of Origin ISO Code
Abbreviation
TW = Taiwan
Line 3 Marking:
48
Rev. 1.0
Si86xx
16.3. Top Marking (16-Pin Narrow Body SOIC)
e3
Si86XYSV
YYWWRTTTTT
16.4. Top Marking Explanation (16-Pin Narrow Body SOIC)
Base Part Number
Ordering Options
Line 1 Marking:
(See Ordering Guide for more
information).
Line 2 Marking:
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (5, 4, 3, 2, 1)
Y = # of reverse channels (2, 1, 0)
S = Speed Grade (max data rate) and operating mode:
A = 1 Mbps (default output = low)
B = 150 Mbps (default output = low)
D = 1 Mbps (default output = high)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV
Circle = 1.2 mm Diameter
“e3” Pb-Free Symbol
YY = Year
WW = Work Week
Assigned by the assembly subcontractor. Corresponds
to the year and work week of the mold date.
RTTTTT = Mfg Code
Manufacturing code from assembly house
“R” indicates revision
Rev. 1.0
49
Si86xx
16.5. Top Marking (8-Pin Narrow Body SOIC)
Si86XYSV
YYWWRF
e3 AIXX
16.6. Top Marking Explanation (8-Pin Narrow Body SOIC)
Line 1 Marking:
Base Part Number
Ordering Options
(See Ordering Guide for more
information).
Line 2 Marking:
YY = Year
WW = Workweek
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (2, 1)
Y = # of reverse channels (1, 0)
S = Speed Grade (max data rate) and operating mode:
A = 1 Mbps (default output = low)
B = 150 Mbps (default output = low)
D = 1 Mbps (default output = high)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV
Assigned by assembly subcontractor. Corresponds to
the year and workweek of the mold date.
R = Product (OPN) Revision
F = Wafer Fab
Line 3 Marking:
50
Circle = 1.1 mm Diameter
Left-Justified
“e3” Pb-Free Symbol.
First two characters of the manufacturing code.
A = Assembly Site
I = Internal Code
XX = Serial Lot Number
Last four characters of the manufacturing code.
Rev. 1.0
Si86xx
DOCUMENT CHANGE LIST
Revision 0.9 to Revision 1.0

Updated Table 5 on page 23.
Added

CQC certificate numbers.
Updated "9. Ordering Guide" on page 39.
Removed
Removed
references to moisture sensitivity levels.
note 2.
Rev. 1.0
51
Si86xx
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
Patent Notice
Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
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the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty,
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52
Rev. 1.0