Si 5 3 1 5 - EVB S I 5315-EVB U SER ’ S G UIDE Description The Si5315 Evaluation Board User’s Guide provides for a complete and simple evaluation of the functions, features, and performance of the Si5315-EVB. The Si5315 Synchronous Ethernet/Telecom jitter attenuating clock multiplier has a comprehensive feature set, including any-rate frequency synthesis, multiple clock inputs, multiple clock outputs, alarm and status outputs, hitless switching between input clocks, and programmable output clock signal format (LVPECL, LVDS, CML, CMOS). For more details, consult the Silicon Labs timing products website at: www.silabs.com/timing. TheSi5315-EVB has two differential clock input and output ports that are AC terminated to 50 ohms and then AC coupled to the Si5315. The XA-XB reference is usually a 40 MHz crystal; however, there are provisions for an external XA-XB reference clock (either differential or single ended). The evaluation board (EVB) can be powered using two different approaches: external power supplies or by USB. Jumper plugs are provided to select between these two options. Jumper plugs are used to strap the device pins for the various pin value options. Status outputs are available on a ribbon connector header. SMA connectors are used for the clock input, output, and XA-XB reference signals. Features The Si5315-EVB includes the following: Evaluation board CD with the Si5315 documentation and the Si5315EVB User’s Guide Function Block Diagram Ext RefClk Input SMAs CKOUT1 Terminate Output Si5315 SMAs CKOUT2 USB +3.3V Vreg +3.3V DUT PWR 1.8V to 3.3V LEDs LED power To DUT Jumper status signals Headers Control signals Rev. 0.2 6/09 Copyright © 2009 by Silicon Laboratories Si5315-EVB Si5315-EVB 1. Introduction The Si5315 is a jitter-attenuating clock multiplier for Gb and 10G Synchronous Ethernet, SONET/SDH, and PDH (T1/E1) applications. The Si5315 accepts dual clock inputs ranging from 8 kHz to 644.53 MHz and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to 644.53 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SyncE and T1/E1 rates. The Si5315 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is user programmable, providing jitter performance optimization at the application level. Refer to the Si5315 data sheet for technical details of the device. Front Back Figure 1. Si5315 EVB 2 Rev. 0.2 Si5315-EVB 2. Si53315-EVB Input and Output Clocks Refer to the schematics, diagrams, and tables while reading this section. 2.1. Input Clocks The Si5315 has two differential clock inputs that are AC terminated and AC coupled before being presented to the Si5315. If the input clock frequencies are low (below 1 MHz), there are extra considerations that should be taken into account. The Si5315 has a maximum clock input rise time specification of 11 ns that must be met (see CKNtrf in the Si5315 data sheet). Also, if the input clock is LVCMOS, it might be advantageous to replace the input coupling capacitors (C7, C12, C16, and C18) with zero ohm resistors. Regardless of the input format, if the clock inputs are not roughly 50% duty cycle, it is highly recommended to avoid AC coupling. For input clocks that are far off of 50% duty cycle, the average value of the signal that passes through the coupling capacitor will be significantly off of the midpoint between the maximum and minimum value of the clock signal, resulting in a mismatch with the common mode input threshold voltage (see VICM in Table 2 of the Si5315 data sheet). 2.2. XA-XB Reference To achieve very low jitter generation and for stability during holdover, the Si5315 requires a stable, low jitter reference at its XA-XB pins. To that end, the EVB is configured with a 40 MHz fundamental mode crystal connected between pins 6 and 7 of the Si5315. However, the Si5315-EVB is capable of using an external XA-XB reference oscillator, either differential or single ended. J1 and J2 are the SMA connectors with AC termination. AC coupling is also provided that needs to be installed at C6 and C8. Table 1 explains the changes of components that are needed to implement an external XA-XB reference oscillator. Table 1. XA-XB Reference Mode of Operation Mode Xtal Ext Ref Ext Ref In+ NC J1 Ext Ref In- NC J2 NOPOP install install NOPOP L M C6, C8 R8 XTAL/CLOCK (J12 jumper, see Table 3.) Notes: 1. Xtal is 40 MHz. 2. NC – no connect. 3. NOPOP – do not install. 2.3. Output Clocks The clock outputs are AC coupled and are available on SMA's J5, J7, J9, and J11. For LVCMOS outputs, it might be desirable to replace the AC coupling capacitors (C9, C14, C17, and C 20) with zero ohm resistors. Also, if greater drive strength is desired for LVCMOS outputs, R6 and R10 can be installed. Rev. 0.2 3 Si5315-EVB 2.4. Pin Configuration J12 is the large jumper header in the center left of the board that implements the jumper plugs that configure the pins of the Si5315. Each pin can be strapped to be either H, M or L. H is achieved by installing a jumper plug between the appropriate middle row pin and its VDD row pin. L is achieved by installing a jumper plug between the appropriate middle row pin and its GND row pin. M is achieved by not installing a jumper plug. 2.5. Evaluation Board Power Options The EVB can be powered from two possible sources: USB or external supplies. A 3.3 V supply is required to run the LEDs because of their large forward drop. The Si5315 power supply can be separated from the 3.3 V supply so that the Si5315 can be evaluated at voltages other than 3.3 V. It is important to note that when the USB supply is being used, the EVB uses the USB port only for power and that the resulting power supply is strictly 3.3 V. Here are the instructions for the various possibilities: 2.5.1. Two External Power Supplies 1. Install a jumper between J16.1 and J16.2 (labeled EXT). 2. No USB connection. 3. If the Si5315 is not being operated at 3.3 V, two different supplies should be connected to J14. Connect the 3.3 V supply to J14.1 and J14.2 (labeled 3.3 V and GND). Connect the SI5315 power supply between J14.2 and J14.3 (labeled GND and DUT). 4. If the Si5315 is to be operated at 3.3 V, J15 (labeled ONE PWR) can be installed, requiring only one external supply. Connect 3.3 V power between J14.2 and J14.3 (labeled GND and DUT). 2.5.2. USB Power 1. With a USB cable, plug the EVB into a powered USB port. 2. Install a jumper between J16.2 and J16.3 (labeled USB). 3. Install a jumper at J15 (labeled ONE PWR). 2.5.3. USB 3.3 V Power, External Si5315 Power 1. Install a jumper between J16.2 and J16.3 (labeled USB). 2. No jumper at J15 (labeled ONE PWR). 3. Connect the Si5315 power supply between J14.2 and J14.3 (labeled GND and DUT). 4 Rev. 0.2 Si5315-EVB 3. Connectors and LEDs 3.1. LEDs Table 2. LED Descriptions LED Color Label Significance D1 Yellow CS_CA ON = clock input 2 selected, else clock 1 D2 Red LOS2 ON = no valid clock input 2 D3 Red LOS1 ON = no valid clock input 1 D4 Red LOL ON = Si5315 is not locked D5 Green DUT_PWR ON = Si5315 power is present D6 Green 3.3V ON = 3.3V power is present 3.2. Connectors, Headers, and Jumpers Refer to Figure 2 to locate the items described in this section. C7, C12, C16, C18 J12 R8 U1, Si5315 J16 J15 J13 Figure 2. Connectors, Headers, and Jumper Locations Rev. 0.2 5 Si5315-EVB Table 3. Configuration Header, J12 J12 Pin J12.1 Not used* J12.2 SFOUT0 J12.3 SFOUT1 J12.4 FRQTBL J12.5 FRQSEL0 J12.6 FRQSEL1 J12.7 FRQSEL2 J12.8 FRQSEL3 J12.9 BWSEL0 J12.10 BSWEL1 J12.11 DBL2_BY J12.12 AUTOSEL J12.13 XTAL/CLOCK J12.14 Not used* *Note: Unused header pin locations should be left open. Table 4. Status Indication Header, J13 6 J13 Signal J13.1 LOS1 J13.3 LOS2 J13.5 CS_CA J13.7 LOL J13.9 RST_B Rev. 0.2 Jumper Plugs CKIN2- NOPOP for Si5317-EVB CKIN2+ CKIN1- J4 SMA_EDGE 1 J6 SMA_EDGE 1 2 CKIN1+ 2 2 J2 SMA_EDGE 1 3 3 Ext Ref In - 3 J1 SMA_EDGE 1 J8 SMA_EDGE 1 J12 14A 14B 13A 13B 12A 12B 11A 11B 10A 10B 9A 9B 8A 8B 7A 7B 6A 6B 5A 5B 4A 4B 3A 3B 2A 2B 1A 1B TP2 1 2 14x3_M_HDR_THRU 1C 2C 3C 4C 5C 6C 7C 8C 9C 10C 11C 12C 13C 14C J10 SMA_EDGE 1 R7 SFOUT0 SFOUT1 FRQTBL 10 FRQSEL0 FRQSEL1 FRQSEL2 FRQSEL3 BWSEL0 BWSEL1 DBL2_BY AUTOSEL RATE0 DUT_PWR 0 ohm 49.9 R11 100N C18 100N C16 49.9 R9 49.9 RATE1 R14 R5 100N C12 100N C7 49.9 R3 C1 10NF R13 C19 10NF 10NF C15 C13 10NF C3 10NF 49.9 X1 4 3 R8 0 ohm C2 10NF TP1 1 2 R12 0 ohm NOPOP 1 36 2 27 26 25 24 23 22 14 9 12 13 16 17 6 7 RST NC FRQTBL FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 BWSEL1 BWSEL0 DBL2_BY AUTOSEL U1 1 2 J3 NOPOP Ferrite L1 2 LOL CS_CA LOS1 LOS2 SFOUT0 SFOUT1 CKOUT2+ CKOUT2- 18 21 3 4 33 30 35 34 28 29 C10 100N C4 100N C5 1UF DUT_PWR C11 100N FILT_DUT_PWR 1 CKOUT1+ CKOUT1- Si5315/17 CKIN_2+ CKIN_2- CKIN1+ CKIN1- XA XB 40 MHz for Si5315-EVB C8 10NF NOPOP 49.9 R4 R2 0 ohm Figure 3. Si5315/17-EVB R15 10k DUT_PWR NOPOP for Si5315-EVB NOPOP for Si5317-EVB 114.285 MHz 2 GND 1 C6 10NF NOPOP NOPOP 100 R1 15 Rate1 2 2 2 11 Rate0 3 3 3 5 10 32 C14 100N R10 0 ohm C20 100N LOS1 LOS2 CS_CA LOL RST_B NOPOP 100N C17 install for CMOS outputs R6 0 ohm NOPOP 100N C9 J5 SMA_EDGE 1 J7 SMA_EDGE 1 J9 SMA_EDGE 1 J11 SMA_EDGE 1 1 3 5 7 9 J13 2 4 6 8 10 10_M_Header LOS1 LOS2 NOPOP for Si5317-EVB LOL CS_CA Status CKOUT2- CKOUT2+ CKOUT1- CKOUT1+ to power plane to measure DUT supply 3 3 3 3 VDD1 VDD2 VDD3 GND1 GND2 GND3 GND4 GND5 Rev. 0.2 8 31 20 19 37 2 2 2 2 Ext Ref In + Si5315-EVB 4. Schematics 7 * * * J14 1 2 3 Phoenix_3_screw 3.3V GND DUT_PWR EVB main power 1 2 LOL LOS1 LOS2 CS_CA C25 1UF PHOENIX_3P3V RAW_3P3V J15 Single 3.3V supply 1 + C21 220UF C22 1UF 1 2 BSS138 Q2 Ferrite 1 R20 10k 1 150 150 V3P3 J16 1 2 3 4 8 7 6 5 R150x4 R19 R18 R17 C A 1 1 2 2 2 D6 D5 A A D4 A D3 A D2 D1 1 1 1 #4 H3 #4 H4 3.3V DUT_PWR LOL LOS1 LOS2 CS_CA 3 2 D+ D- J17 Gnd V USB 4 1 USB power mounting holes #4 H2 1 Figure 4. Power and LED Grn 2 C Grn 2 Red 1 C Red 1 C Red 1 C A #4 H1 USB_3P3V 1 LED_PWR Yel 2 C 0 ohm R16 Power Source Selection BSS138 Q5 BSS138 Q4 BSS138 Q3 1 L2 1 DUT_PWR BSS138 Q1 C24 220UF + 3 1 2 3 DUT_PWR 3 2 S2 6 DUT_PWR 3 2 3 2 3 2 Rev. 0.2 2 S1 5 VBUS + C23 33UF + VIN VOUT NC1 U2 FAN1540B C26 33UF 3 2 1 PAD 8 7 DUT Power NC2 NC3 GND 4 5 6 ground pins 1 J26 J25 J24 1 J23 1 J22 J21 J20 J19 J18 1 1 1 1 1 1 Si5315-EVB Si5315-EVB 5. Bill of Materials Table 5. Si5315-EVB Bill of Materials Item Qty Reference Part Mfr Manufacturer Part No. 1 6 C1,C2,C3,C13,C15,C19 10NF Venkel C0603X7R160-103KNE 2 11 C4,C7,C9,C10,C11,C12,C14, C16,C17,C18,C20 100N Venkel C0603X7R160-104KNE 3 3 C5,C22,C25 1UF Venkel C0603X7R6R3-105KNE 5 2 C21,C24 220UF Kemet T494B227M004AT 6 2 C23,C26 33UF Venkel TA006TCM336MBR 7 1 D1 Yel Panasonic LN1471YTR 8 3 D2,D3,D4 Red Lumex LN1271RAL 9 2 D5,D6 Grn Panasonic LN1371G 11 10 J1,J2,J4,J5,J6,J7, J8,J9,J10,J11 SMA_EDGE Johnson 142-0701-801 13 1 J12 14x3_M_HDR_THRU — 14 1 J13 10_M_Header 3M N2510-6002RB 15 1 J14 Phoenix_3_screw Phoenix MKDSN 1.5/3-5.08 16 1 J15 Jmpr_2pin 17 1 J16 Jmpr_3pin 18 1 J17 USB FCI 61729-0010BLF 19 9 J18,J19,J20,J21, J22,J23,J24,J25,J26 Jmpr_1pin 20 2 L1,L2 Ferrite Venkel FBC1206-471H 21 5 Q1,Q2,Q3,Q4,Q5 BSS138 On Semi BSS138LT1G 23 4 R2,R8,R12,R16 0 ohm Venkel CR0603-16W-000T 24 6 R3,R4,R5,R7,R9,R11 49.9 Venkel CR0603-16W-49R9FT 26 1 R14 10 Venkel CR0603-16W-10R0FT 27 2 R15,R20 10k Venkel CR603-16W-1002FT 28 2 R17,R18 150 Venkel CR0603-16W-1500FT 29 1 R19 R150x4 Panasonic EXB-38V151JV 31 1 U1 Si5315 Silicon Labs Si5315A-C-GM Rev. 0.2 9 Si5315-EVB Table 5. Si5315-EVB Bill of Materials Item Qty Reference Part Mfr Manufacturer Part No. 32 1 U2 FAN1540B Fairchild FAN1540BPMX 33 1 X1 40 MHz Abracon ABM8-40.000 MHz-BZT Venkel C0603X7R160-103KNE Not Populated 4 2 C6,C8 10NF 12 1 J3 Jmpr_2pin 22 1 R1 100 Venkel CR0603-16W-1000FT 25 3 R6,R10,R13 0 ohm Venkel CR0603-16W-000T 10 Rev. 0.2 Si5315-EVB 6. Layout Figure 5. Silkscreen Top Rev. 0.2 11 Si5315-EVB Figure 6. Layer 1 12 Rev. 0.2 Si5315-EVB Figure 7. Layer 2—Ground Plane Rev. 0.2 13 Si5315-EVB Figure 8. Layer 3 14 Rev. 0.2 Si5315-EVB Figure 9. Layer 4 Rev. 0.2 15 Si5315-EVB Figure 10. Layer 5, FILT_DUT_PWR 16 Rev. 0.2 Si5315-EVB Figure 11. Layer 6, Bottom Rev. 0.2 17 Si5315-EVB Figure 12. Bottom Silkscreen 18 Rev. 0.2 Si5315-EVB 7. Factory Default Configuration Table 6. Factory Default Jumper Settings J12 Pin Jumper J12.1 Not used — J12.2 SFOUT0 H J12.3 SFOUT1 M J12.4 FRQTBL H J12.5 FRQSEL0 L J12.6 FRQSEL1 H J12.7 FRQSEL2 M J12.8 FRQSEL3 L J12.9 BWSEL0 H J12.10 BSWEL1 H J12.11 DBL2_BY L J12.12 AUTOSEL H J12.13 XTAL/CLOCK L J12.14 Not used — The jumper settings in Table 6 result in the following: SFOUT = LVPECL outputs 19.44 MHz input clocks 155.52 MHz output clocks BW = 112 Hz DBL2_BY = CKOUT2 enabled AUTOSEL = automatic revertive clock selection XTAL/CLOCK = 40 MHz crystal Refer to Table 7 in the Si5315 Data Sheet for other frequency plans. The factory configuration for the board is to use only USB power by using the following jumper configuration: Jumper between J16.2 and J16.3 (labeled PWR, USB) Jumper installed on J15 (labeled ONE POWER) Rev. 0.2 19 Si5315-EVB NOTES: 20 Rev. 0.2 Si5315-EVB DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.2 Removed Si5315-EVB from Appendix of Si5315EVB, Si5316-EVB, Si5319-EVB, Si532/23-EVB, Si5325/26-EVB with Si5315-EVB Appendix B User’s Guide Revised Revision 0.2 as a stand-alone Si5315-EVB User’s Guide Rev. 0.2 21 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. 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