S i53119-E V B S i5311 9 E V A L U A T I O N B O A R D U S E R ’ S G U I D E Description Features The Si53119-EVB can be used to evaluate the Si53119A01AGM, 19-output PCIe buffer in zero delay and nonzero delay modes. The signal traces of the input and outputs have a singleended impedance of 50 , and differential impedance of 100 . The series resistance on the outputs are set to match to this impedance design. DC pin controls per data sheet specification. Ability to measure input to output propagation delay. Ability to program features of Si53119 via I2C lines. Rev. 0.1 11/14 10-inch traces to evaluate signal integrity at the longest trace lengths Copyright © 2014 by Silicon Laboratories Si53119-EVB CLK_IN#_RET CLK_IN_RET CLK_IN# CLK_IN 0 0 R6 SCL SDA SA_1 SA_0 R3 10K R4 10K 10K R2 R1 10K R16 10K R17 10K R9 10K 100M_133M# PWRGD/# BYPASS/BWSEL 14 15 12 11 13 10 3 9 8 5 4 VDDR FBOUT_NC# FBOUT_NC SCL SDA SA_1 SA_0 100M_133M# CLK_IN# CLK_IN PW RGD_PW RDN# HBW _BYPASS_LBW # DIF_0 DIF_0# VDD VDD_IO 69 64 Si53119 DIFF_1 DIFF_2 DIFF_3 DIFF_4 DIFF_5 DIFF_6 DIFF_7 DIFF_8 DIFF_9 DIFF_0 DIFF_0# DIFF_1# DIFF_2# DIFF_3# DIFF_4# DIFF_5# DIFF_6# DIFF_7# DIFF_8# DIFF_9# 17 18 R5 U1 1 VDDA 7 VDDR 28 VDD DIF1 DIF1_# 19 20 VDD 45 VDD DIF_2 DIF_2# 23 24 57 VDD_IO 33 VDD_IO 52 VDD_IO DIF_3 DIF_3# 25 26 DIF_5 DIF_5# 31 32 DIF_6 DIF_6# 35 36 DIF_4 DIF_4# 29 30 VDD_IO 40 VDD_IO 21 VDD_IO 39 GND 58 GND 63 GND DIF_8 DIF_8# 70 GND 73 GND DIF_9 DIF_9# 51 GND DIF_7 DIF_7# 37 38 Rev. 0.1 41 42 Figure 1. Schematic 1 43 44 46 GND 34 GND 27 GND 22 GND 16 GND 6 GND 2 2 DIF_18 DIF_18# DIF_17 DIF_17# DIF_16 DIF_16# DIF_15 DIF_15# DIF_14 DIF_14# DIF_13 DIF_13# DIF_12 DIF_12# DIF_11 DIF_11# DIF_10 DIF_10# GNDA VDDA 71 72 67 68 65 66 61 62 59 60 55 56 53 54 49 50 47 48 DIFF_18 DIFF_18# DIFF_17 DIFF_17# DIFF_16 DIFF_16# DIFF_15 DIFF_15# DIFF_14 DIFF_14# DIFF_13 DIFF_13# DIFF_12 DIFF_12# DIFF_11 DIFF_11# DIFF_10 DIFF_10# Si5 311 9- E V B 1. Schematics Si5 3 11 9 - E V B Figure 2. Schematic 2 Rev. 0.1 3 5 4 3 2 1 A B C D Si5 311 9- E V B Figure 3. Schematic 3 4 Rev. 0.1 Si5 3 11 9 - E V B 2. Jumpers Jumpers can be set per the diagram above. Please refer to the Si53119-A01AGM data sheet for a description on how the pin states affect the device. (M--Insert link here to data sheet when it’s released.) 1. P15 and P17 disable I2C control when shorted. 2. P14 can be used to set PWRGD# (VDD or Ground). 3. P16 can be used to set outputs clocks to either 100MHz or 133MHz (controls the 100_133@# pin). 4. Jumpers J11, J14, and J19 are tri-level jumpers that control BYPASS/BWSEL, SA_0, and SA_1 respectively. 5. P1 needs to be shorted to enable generation of VDD/2. Default jumper setting on the EVB: 1. P15, P17 are shorted, disabling I2C. 2. P14 is shorted to VDD (PWRGD# = High). 3. P16 is shorted to VDD (100_133# = High). 4. BYPASS/BWSEL, SA_0, SA_1 are all pulled low (J11, J14, J19 pulled to ground). 5. P1 is shorted to enable VDD/2 (needed for tristate input pin conditioning). 3. Input and Power Supply Sequencing The Si53119 should be powered up with supply at both the VDD and VDD_IO nodes (at the jumpers available on the EVB). A 100 MHz or 133 MHz HCSL input clock should be applied to pins 8 and 9, and should comply with HCSL formats. There is no internal or onboard resistive termination, therefore HCSL termination needs to be provided at the input if needed by the driver. The input clock should be applied only after the supplies are stable. 4. Quick Start Guide: 1. Enable supply on the VDD pin. 2. Enable supply on the VDDIO pin. 3. Apply input clock on SMA connectors J26, J29 and measure the return path clock on J32, J33 (as shown below). Figure 4. Clock Return Path a. The input clock measured at J32, J33 needs a 50-ohm termination on the scope. b. The attenuation will be 1:10 after the above termination. Appropriate scaling (10x) needs to be set at the scope to adjust for the scaling. 4. The output clocks are now set up and can be measured on an oscilloscope or frequency domain measurement instrument. Rev. 0.1 5 Si5 311 9- E V B 5. Usage of the EVB Once the EVB has been set up, the following can be evaluated: 1. Signal integrity of the device when driving 10-inch, 100-ohm differential traces. 2. Effect of capacitance load on output signal integrity. 3. Output-to-output skew over 10-inch traces. 4. Input-to-output prorogation delay in BYPASS, HBW, and LBW modes using the input clock return path. 5. Measuring the power consumption of the device. 6. Modification of the device settings via the I2C interface. 6 Rev. 0.1 Si5 3 11 9 - E V B 6. Bill of Materials Rev. 0.1 7 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW Quality Support and Community www.silabs.com/CBPro www.silabs.com/quality community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. 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