Si52143 PCI-E XPRESS 1 代 、 2 代 和 3 代 四 输 出 时 钟 发 生 器 及 25 MH Z 参 考 时 钟 特点 订购信息： 参阅第 18 页 应用 网络附加存储 多功能打印机 无线接入点 路由器 引脚分配 描述 功能模块示意图 24 23 22 21 20 19 VDD_REF 1 1 18 OE[3:2] 17 VDD_DIFF REF 2 SSON2 3 VSS_REF 4 OE_REF1 5 VDD_DIFF 6 16 DIFF3 25 GND 15 DIFF3 14 DIFF2 13 DIFF2 7 8 9 10 11 12 VDD_DIFF Si52143 是扩频时钟使能 PCIe 时钟发生器，可作为四个 PCIe 时钟和一个 25 MHz 参考时钟的时钟源。设备有三个用于启用输出 （打开电源时即动态生成）的硬件输 出使能引脚，和一个控制 PCIe 时钟输出上的扩频的硬件引脚。除硬件控制引脚外， I2C 编程功能还可用于动态控制 PCIe 时钟输出上的真、补偿或两种差分信号上的 偏移、边缘频率和振幅。这种控制功能可在 PCIe 时钟输出上实现最佳信号完整性 和最佳 EMI 签名。关于信号完整性调整和可配置性的信息请参考 AN636。 DIFF1 SCLK VDD_CORE SDATA XOUT DIFF1 支持 I2C，带回读功能 使用三角扩频改善图最大程度地减少 电磁干扰 (EMI) 扩展温度范围 –40 至 85 oC 3.3 V 电源 24 引脚 QFN 封装 XIN/CLKIN DIFF0 VSS_CORE 25 MHz 参考时钟 25 MHz 晶体输入或时钟输入 信号完整性调整 DIFF0 PCI-Express 1 代、 2 代和 3 代兼容 100 MHz 下支持串行 ATA (SATA) 低功耗，差分输出 无需终端电阻 各时钟专用输出使能硬件引脚 差分时钟上有扩频使能引脚 四个 PCI-Express 时钟 OE[1:0]1 Notes: 1. Internal 100 kohm pull-up. 2. Internal 100 kohm pull-down. REF XIN/CLKIN XOUT 专利申请中 DIFF0 DIFF1 PLL (SSC) Divider DIFF2 DIFF3 SCLK SDATA Control & Memory OE_REF OE [1:0] Control RAM OE [3:2] SSON 修订版 1.2 2/14 版权所有 © 2014 Silicon Laboratories Si52143 Si52143 2 ??? 1.2 Si52143 目录 章节 页码 1. 电气规格 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. 功能描述 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1. 晶体建议 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2. OE 引脚定义 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.3. OE 断言 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.4. OE 无效置位 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.5. SSON 引脚定义 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. 测试和测量设置 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. 控制寄存器 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1. I2C 接口 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2. 数据协议 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5. 引脚描述：24- 引脚 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6. 订购指南 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7. 封装外形 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 文档修改列表 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 联系信息 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ??? 1.2 3 Si52143 1. 电气规格 Table 1. DC Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit 3.3 V Operating Voltage VDD core 3.3 ± 5% 3.135 3.3 3.465 V 3.3 V Input High Voltage VIH Control input pins 2.0 — VDD + 0.3 V 3.3 V Input Low Voltage VIL Control input pins VSS – 0.3 — 0.8 V Input High Voltage VIHI2C SDATA, SCLK 2.2 — — V Input Low Voltage VILI2C SDATA, SCLK — — 1.0 V Input High Leakage Current IIH Except internal pull-down resistors, 0 < VIN < VDD — — 5 A Input Low Leakage Current IIL Except internal pull-up resistors, 0 < VIN < VDD –5 — — A 3.3 V Output High Voltage (Single-Ended Outputs) VOH IOH = –1 mA 2.4 — — V 3.3 V Output High Voltage (Single-Ended Outputs) VOL IOL = 1 mA – — 0.4 V High-impedance Output Current IOZ –10 — 10 µA Input Pin Capacitance CIN 1.5 — 5 pF COUT — — 6 pF LIN — — 7 nH — — 55 mA Output Pin Capacitance Pin Inductance Dynamic Supply Current 4 IDD_3.3V All outputs enabled. Differential clocks with 5” traces and 2 pF load. ??? 1.2 Si52143 Table 2. AC Electrical Specification Parameter Symbol Test Condition Min Typ Max Unit LACC Measured at VDD/2 differential — — 250 ppm TDC Measured at VDD/2 45 — 55 % CLKIN Rising and Falling Slew Rate TR/TF Measured between 0.2 VDD and 0.8 VDD 0.5 — 4.0 V/ns Cycle to Cycle Jitter TCCJ Measured at VDD/2 — — 250 ps Long Term Jitter TLTJ Measured at VDD/2 — — 350 ps Input High Voltage VIH XIN/CLKIN pin 2 — VDD+0.3 V Input Low Voltage VIL XIN/CLKIN pin — — 0.8 V Input High Current IIH XIN/CLKIN pin, VIN = VDD — — 35 µA Input Low Current IIL XIN/CLKIN pin, 0 < VIN <0.8 –35 — — µA TDC Measured at 0 V differential 45 — 55 % TSKEW Measured at 0 V differential — — 50 ps Cycle to Cycle Jitter TCCJ Measured at 0 V differential — 35 50 ps PCIe Gen 1 Pk-Pk Jitter Pk-Pk PCIe Gen 1 0 40 50 ps PCIe Gen 2 Phase Jitter RMSGEN2 10 kHz < F < 1.5 MHz 0 2 2.6 ps 1.5 MHz< F < Nyquist Rate 0 2 2.6 ps RMSGEN3 Includes PLL BW 2–4 MHz (CDR = 10 MHz) 0 0.5 0.9 ps LACC Measured at 0 V differential — — 100 ppm Rising/Falling Slew Rate TR / TF Measured differentially from ±150 mV 1 — 8 V/ns Voltage High VHIGH — — 1.15 V Voltage Low VLOW –0.3 — — V VOX 300 — 550 mV — –0.5 — % 30 31.5 33 kHz Crystal Long-term Accuracy Clock Input Duty Cycle DIFF at 0.7 V Duty Cycle Output-to-Output Skew PCIe Gen 3 Phase Jitter Long Term Accuracy Crossing Point Voltage at 0.7 V Swing Spread Range SPR-2 Modulation Frequency FMOD Down spread Note: Visit www.pcisig.com for complete PCIe specifications. ??? 1.2 5 Si52143 Table 2. AC Electrical Specification (Continued) Parameter Symbol Test Condition Min Typ Max Unit TDC Measurement at 1.5 V 45 — 55 % TR / TF Measured between 0.8 and 2.0 V 1.0 — 4.0 V/ns Cycle to Cycle Jitter TCCJ Measurement at 1.5 V — — 300 ps Long Term Accuracy LACC Measured at 1.5 V — — 100 ppm REF(25 MHz) at 3.3 V Duty Cycle Rising and Falling Edge Rate Enable/Disable and Set-Up Clock Stabilization from Power-up TSTABLE — — 1.8 ms Stopclock Set-up Time TSS 10.0 — — ns Note: Visit www.pcisig.com for complete PCIe specifications. Table 3. Absolute Maximum Conditions Parameter Symbol Test Condition Min Typ Max Unit VDD_3.3V Functional — — 4.6 V Input Voltage VIN Relative to VSS –0.5 — 4.6 VDC Temperature, Storage TS Non-functional –65 — 150 °C Temperature, Operating Ambient TA Functional –40 — 85 °C Temperature, Junction TJ Functional — — 150 °C Dissipation, Junction to Case ØJC JEDEC (JESD 51) — — 35 °C/W Dissipation, Junction to Ambient ØJA JEDEC (JESD 51) — — 37 °C/W ESDHBM JEDEC (JESD 22-A114) 2000 — — V UL-94 UL (Class) Main Supply Voltage ESD Protection (Human Body Model) Flammability Rating V–0 Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required. 6 ??? 1.2 Si52143 2. 功能描述 2.1. 晶体建议 如果使用晶体输入，则该设备需要并联谐振 25 MHz 晶体。 Table 4. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap 25 MHz AT Parallel 12–15 pF Shunt Cap (max) Motional (max) Tolerance (max) Stability (max) Aging (max) 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm 2.1.1. 晶体负载 晶体负载是 ppm 准确性的关键。为实现低 / 零 ppm 错误，请使用下面第 2.1.2 节中的计算估计合适的电容性负载 (CL)。图 1 显 示的是使用两个微调电容的典型晶体结构。请注意微调电容与晶体是串联的。 Figure 1. Crystal Capacitive Clarification 2.1.2. 计算负载电容 除标准外部微调电容外，还可考虑使用走线电容和引脚电容正确地计算晶体负载。每一侧的电容都是与晶体串联的。两侧总电容 是晶体负载电容 (CL) 上标示的两倍。 计算微调电容以便在两侧提供相等的电容负载。 Figure 2. Crystal Loading Example 使用以下公式为 Ce1 和 Ce2 计算微调电容值。 ??? 1.2 7 Si52143 Load Capacitance (each side) Ce = 2 x CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = CL: 1 1 ( Ce1 + Cs1 + Ci1 + ) 晶体负载电容 CLe: 从晶体来看使用标准值微调电容时的实际负载 Ce: 外部微调电容 Cs: 杂散电容 （阶梯） Ci 1 Ce2 + Cs2 + Ci2 : 内部电容 （引线框架、接合线等） 2.2. OE 引脚定义 OE 是用于启用和禁用输出时钟的有效高输入。要启用输出时钟，OE 引脚应为逻辑高且 I2C 输出位使能应为逻辑高。 有两种禁用输出时钟的方法：将 OE 拉到逻辑低，或将 I2C 使能位设置为逻辑低。 OE 引脚虽然有一个内置 100 k 电阻，但仍需要随时处于驱动状态。 2.3. OE 断言 OE 信号是用于分别同步停止和启动输出时钟且其他时钟发生器继续发挥作用的有效高输入。将 OE 信号设置为逻辑 高的断言会使停止的各输出时钟恢复正常运行。时钟恢复时不会产生短时或延长的时钟脉冲。从断言到有效输出的 最大延迟不超过二到六个输出时钟周期。 2.4. OE 无效置位 将 OE 引脚设为逻辑低而使其为无效置位时，相应的输出时钟将完全停止，最终输出状态被拉低。 2.5. SSON 引脚定义 SSON 是用于在所有 DIFF 输出上启用 –0.5% 扩频的有效输入。采样高时，所有 DIFF 输出上均启用 –0.5% 扩频。采样低时， DIFF 输出频率不扩频。 8 ??? 1.2 Si52143 3. 测试和测量设置 图 3 显示 HCSL 时钟输出的测试负载配置。 M e a s u re m e n t P o in t L1 O U T+ 5 0 2 pF L1 = 5" M e a s u re m e n t P o in t L1 O U T- 5 0 2 pF Figure 3. 0.7 V Differential Load Configuration 关于如何终止 LVDS、 LVPECL 或 CML 信号水平的差分输出的建议，请见应用注释 AN781。 Figure 4. Differential Output Measurement for Differential Signals (for AC Parameters Measurement) ??? 1.2 9 Si52143 VMIN = –0.30V VMIN = –0.30V Figure 5. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement L1 = 0.5", L2 = 5" Measurement 50 SE Clocks Point L1 33 L2 4 pF Figure 6. Single-Ended Clocks with Single Load Configuration Figure 7. Single Ended Output Signal (for AC Parameter Measurement) 10 ??? 1.2 Si52143 4. 控制寄存器 4.1. I2C 接口 为提高时钟合成器的灵活性和功能，可使用 I2C 接口。通过 I2C 接口可使用各种设备功能，如启用单个时钟。与 I2C 接口相关的 寄存器在上电时初始化为默认设置。此接口的使用是可选的。若需要更改时钟寄存器，则这种更改通常是在系统初始化时进行的。 电源管理功能只能在程序模式下编程，不能在普通运行模式下进行。 4.2. 数据协议 时钟驱动器 I2C 协议可接受控制器的写字节、读字节、写块和读块操作。对于写 / 读块操作，从低到高依次存取字节 （从最高有 效位开始），并有在传输完任何完整字节后停止的能力。对于写字节和读字节操作，系统控制器可存取独立索引的字节。 写块和读块协议请见 表 5，写字节和读字节协议请见 表 6。从接收器地址为 11010110 (D6h)。 Table 5. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Block Read Protocol Description Bit 1 Start 8:2 Slave address—7 bits Description Start Slave address—7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code—8 bits 18:11 Command Code—8 bits 19 Acknowledge from slave 19 Acknowledge from slave Byte Count—8 bits 20 Repeat start 27:20 28 36:29 37 45:38 Acknowledge from slave 27:21 Slave address—7 bits Data byte 1—8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave 37:30 Data byte 2—8 bits 46 Acknowledge from slave .... Data Byte /Slave Acknowledges .... Data Byte N—8 bits .... Acknowledge from slave .... Stop 38 46:39 47 55:48 Byte Count from slave—8 bits Acknowledge Data byte 1 from slave—8 bits Acknowledge Data byte 2 from slave—8 bits 56 Acknowledge .... Data bytes from slave/Acknowledge .... Data Byte N from slave–8 bits .... NOT Acknowledge .... Stop Table 6. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Byte Read Protocol Description Bit Start 1 Slave address–7 bits 8:2 ??? 1.2 Description Start Slave address–7 bits 11 Si52143 Table 6. Byte Read and Byte Write Protocol 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 19 27:20 Command Code–8 bits 18:11 Acknowledge from slave 19 Acknowledge from slave Data byte–8 bits 20 Repeated start 28 Acknowledge from slave 29 Stop 27:21 ??? 1.2 Slave address–7 bits 28 Read 29 Acknowledge from slave 37:30 12 Command Code–8 bits Data from slave–8 bits 38 NOT Acknowledge 39 Stop Si52143 Control Register 0. Byte 0 Bit D7 D6 D5 D4 D3 D1 D0 R/W R/W R/W D2 D1 D0 REF_OE Name Type D2 R/W R/W R/W R/W R/W 重置设置 = 00000100 Bit Name Function 7:3 Reserved 2 REF_OE Output Enable for REF. 0: Output disabled. 1: Output enabled. 1:0 Reserved Control Register 1. Byte 1 Bit D7 D6 D5 D4 D3 Name Type DIFF0_OE R/W R/W R/W R/W R/W R/W DIFF1_OE R/W R/W 重置设置 = 00000101 Bit Name 7:3 Reserved 2 DIFF0_OE Function Output Enable for DIFF0. 0: Output disabled. 1: Output enabled. 1 Reserved 0 DIFF1_OE Output Enable for DIFF1. 0: Output disabled. 1: Output enabled. ??? 1.2 13 Si52143 Control Register 2. Byte 2 Bit D7 D6 Name DIFF2_OE DIFF3_OE Type R/W R/W D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W D2 D1 D0 重置设置 = 11000000 Bit Name Function 7 DIFF2_OE Output Enable for DIFF2. 0: Output disabled. 1: Output enabled. 6 DIFF3_OE Output Enable for DIFF3. 0: Output disabled. 1: Output enabled. 5:0 Reserved Control Register 3. Byte 3 Bit D7 D6 Name Type D5 D4 D3 Rev Code[3:0] R/W R/W R/W Vendor ID[3:0] R/W R/W R/W R/W R/W D3 D2 D1 D0 R/W R/W R/W R/W 重置设置 = 00001000 Bit Name Function 7:4 Rev Code[3:0] Program Revision Code. 3:0 Vendor ID[3:0] Vendor Identification Code. Control Register 4. Byte 4 Bit D7 D6 D5 D4 Name Type BC[7:0] R/W R/W R/W R/W 重置设置 = 00000110 14 ??? 1.2 Si52143 Bit Name 7:0 BC[7:0] Function Byte Count Register. Control Register 5. Byte 5 Bit D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W Name DIFF_Amp_Sel DIFF_Amp_Cntl[2] DIFF_Amp_Cntl[1] DIFF_Amp_Cntl[0] Type R/W R/W R/W R/W 重置设置 = 11011000 Bit Name 7 DIFF_Amp_Sel Function Amplitude Control for DIFF Differential Outputs. 0: Differential outputs with Default amplitude. 1: Differential outputs amplitude is set by Byte 5[6:4]. 6 DIFF_Amp_Cntl[2] 5 DIFF_Amp_Cntl[1] 4 DIFF_Amp_Cntl[0] 3:0 Reserved DIFF Differential Outputs Amplitude Adjustment. 000: 300 mV 001: 400 mV 010: 500 mV 100: 700 mV 101: 800 mV 110: 900 mV ??? 1.2 011: 600 mV 111: 1000 mV 15 Si52143 VSS_CORE XIN/CLKIN XOUT VDD_CORE SDATA SCLK 5. 引脚描述：24- 引脚 QFN 24 23 22 21 20 19 VDD_REF 1 1 18 OE[3:2] REF 2 17 VDD_DIFF SSON2 3 VSS_REF 4 OE_REF1 5 VDD_DIFF 6 16 DIFF3 25 GND 15 DIFF3 14 DIFF2 7 8 9 10 11 12 OE[1:0]1 DIFF0 DIFF0 DIFF1 DIFF1 VDD_DIFF 13 DIFF2 Notes: 1. Internal 100 kohm pull-up. 2. Internal 100 kohm pull-down. Table 7. Si52143 24-Pin QFN Descriptions Pin # Name 1 VDD_REF 2 REF 3 SSON I,PD Active high input pin enables –0.5% spread on DIFF outputs (internal 100 k pull-down). 4 VSS_REF GND Ground 5 OE_REF I,PU Active high input to enable or disable REF clock. 6 VDD_DIFF 7 OE[1:0] 8 DIFF0 O, DIF 0.7 V, 100 MHz differential clock output. 9 DIFF0 O, DIF 0.7 V, 100 MHz differential clock output. 10 DIFF1 O, DIF 0.7 V, 100 MHz differential clock output. 16 Type Description PWR 3.3 V power supply. O, SE 3.3 V, 25 MHz crystal reference clock output. PWR 3.3 V power supply. I,PU Active high input to enable or disable DIFF0 and DIFF1 clocks. ??? 1.2 Si52143 Table 7. Si52143 24-Pin QFN Descriptions (Continued) Pin # Name Type Description 11 DIFF1 12 VDD_DIFF 13 DIFF2 O, DIF 0.7 V, 100 MHz differential clock output. 14 DIFF2 O, DIF 0.7 V, 100 MHz differential clock output. 15 DIFF3 O, DIF 0.7 V, 100 MHz differential clock output. 16 DIFF3 O, DIF 0.7 V, 100 MHz differential clock output. 17 VDD_DIFF 18 OE[3:2] I,PU 19 SCLK I 20 SDATA I/O 21 VDD_CORE 22 XOUT O 25.00 MHz crystal output, Float XOUT if using only CLKIN (Clock input). 23 XIN/CLKIN I 25.00 MHz crystal input or 3.3 V, 25 MHz Clock Input. 24 VSS_CORE GND Ground. 25 GND GND Ground for bottom pad of the IC. O, DIF 0.7 V, 100 MHz differential clock output. PWR 3.3 V power supply. PWR 3.3 V power supply. Active high input to enable or disable DIFF2 and DIFF3 clocks. I2C SCLOCK. I2C SDATA. PWR 3.3 V power supply. ??? 1.2 17 Si52143 6. 订购指南 Part Number Package Type Temperature Si52143-A01AGM 24-pin QFN Industrial, –40 to 85 C Si52143-A01AGMR 24-pin QFN—Tape and Reel Industrial, –40 to 85 C Lead-free 18 ??? 1.2 Si52143 7. 封装外形 图 8 说明 Si52142 的封装详细信息。表 8 列出插图中尺寸值。 Figure 8. 24-Pin Quad Flat No Lead (QFN) Package Table 8. Package Diagram Dimensions Symbol Millimeters Min Nom Max 0.70 0.75 0.80 A1 0.00 0.025 0.05 b 0.20 0.25 0.30 A D D2 4.00 BSC 2.60 2.70 e 0.50 BSC E 4.00 BSC 2.80 E2 2.60 2.70 2.80 L 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.07 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VGGD-8. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. ??? 1.2 19 Si52143 文档修改列表 修订版 0.1 至修订版 1.0 已更新第 1 页上的功能。 已更新第 1 页上的说明。 已更新第 4 页上的表 1。 已更新第 5 页上的表 2。 已更新第 7 页上的第 2 节。 已更新第 7 页上的第 2.1.1 节。 已更新第 11 页上的第 4.1 节。 已更新第 11 页上的第 4.2 节。 已更新第 16 页上的引脚说明。 修订版 1.0 至修订版 1.1 从表 3 删除了湿敏度规格。 修订版 1.1 至修订版 1.2 20 更新了表 2。 更新了第 3 节。 ??? 1.2 Si52143 注意： ??? 1.2 21 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW Quality Support and Community www.silabs.com/CBPro www.silabs.com/quality community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories. 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