Data Sheet

Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS transistor
FEATURES
BSP100
SYMBOL
• ’Trench’ technology
• Low on-state resistance
• Fast switching
• High thermal cycling performance
• Low thermal resistance
QUICK REFERENCE DATA
VDSS = 30 V
d
ID = 6 A
RDS(ON) ≤ 100 mΩ (VGS = 10 V)
g
RDS(ON) ≤ 200 mΩ (VGS = 4.5 V)
s
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect transistor in a plastic
envelope
using
’trench’
technology.
Applications:• Motor and relay drivers
• d.c. to d.c. converters
• Logic level translator
PINNING
SOT223
PIN
DESCRIPTION
1
gate
2
drain
3
source
4
drain (tab)
4
2
1
3
The BSP100 is supplied in the
SOT223
surface
mounting
package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
VDSS
VDGR
VGS
ID
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
IDM
PD
Tj, Tstg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
MIN.
MAX.
UNIT
Tj = 25 ˚C to 150˚C
Tj = 25 ˚C to 150˚C; RGS = 20 kΩ
- 65
30
30
± 20
61
4.4
3.2
24
8.3
150
V
V
V
A
A
A
A
W
˚C
Tsp = 25 ˚C
Tsp = 100 ˚C
Tamb = 25 ˚C
Tsp = 25 ˚C
Tsp = 25 ˚C
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
Rth j-sp
Thermal resistance junction to
solder point
Thermal resistance junction to
ambient
surface mounted, FR4
board
surface mounted, FR4
board
Rth j-amb
TYP.
MAX.
UNIT
12
15
K/W
70
-
K/W
1 Continuous current rating limited by package
February 1999
1
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS transistor
BSP100
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
EAS
Non-repetitive avalanche
energy
IAS
Non-repetitive avalanche
current
CONDITIONS
MIN.
MAX.
UNIT
-
23
mJ
-
6
A
Unclamped inductive load, IAS = 6 A;
tp = 0.2 ms; Tj prior to avalanche = 25˚C;
VDD ≤ 15 V; RGS = 50 Ω; VGS = 10 V
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
V(BR)DSS
VGS = 0 V; ID = 10 µA;
VGS(TO)
Drain-source breakdown
voltage
Gate threshold voltage
MIN.
Tj = -55˚C
VDS = VGS; ID = 1 mA
Tj = 150˚C
Tj = -55˚C
RDS(ON)
2
80
120
4.5
10
0.6
10
2.8
3.2
100
200
170
100
10
100
V
V
V
V
V
mΩ
mΩ
mΩ
S
A
A
nA
µA
nA
IGSS
VGS = 10 V; ID = 2.2 A
VGS = 4.5 V; ID = 1 A
VGS = 10 V; ID = 2.2 A; Tj = 150˚C
Forward transconductance
VDS = 20 V; ID = 2.2 A
On-state drain current
VGS = 10 V; VDS = 1 V;
VGS = 4.5 V; VDS = 5 V
Zero gate voltage drain
VDS = 24 V; VGS = 0 V;
current
VDS = 24 V; VGS = 0 V; Tj = 150˚C
Gate source leakage current VGS = ±20 V; VDS = 0 V
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 2.3 A; VDD = 15 V; VGS = 10 V
-
6
0.7
0.7
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 20 V; RD = 18 Ω;
VGS = 10 V; RG = 6 Ω
Resistive load
-
6
8
21
15
-
ns
ns
ns
ns
Ld
Ls
Internal drain inductance
Internal source inductance
Measured tab to centre of die
Measured from source lead to source
bond pad
-
2.5
5
-
nH
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 20 V; f = 1 MHz
-
250
88
54
-
pF
pF
pF
gfs
ID(ON)
IDSS
Drain-source on-state
resistance
30
27
1
0.4
2
3.5
2
-
TYP. MAX. UNIT
February 1999
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS transistor
BSP100
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
Tsp = 25 ˚C
VSD
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
trr
Qrr
Reverse recovery time
Reverse recovery charge
IS
ISM
TYP. MAX. UNIT
-
-
6
A
-
-
24
A
IF = 1.25 A; VGS = 0 V
-
0.82
1.2
V
IF = 1.25 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 25 V
-
69
55
-
ns
nC
Normalised Power Derating
PD%
120
110
100
90
80
70
60
50
40
30
20
10
0
MIN.
100
BSP100
Peak Pulsed Drain Current, IDM (A)
RDS(on) = VDS/ ID
tp = 10 us
10
100 us
1 ms
d.c.
1
10 ms
100 ms
0.1
0
20
40
60
80
Tsp / C
100
120
140
1
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tsp)
120
110
100
90
80
70
60
50
40
30
20
10
0
10
Drain-Source Voltage, VDS (V)
100
Fig.3. Safe operating area. Tsp = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Normalised Current Derating
ID%
100
10
BSP100
Peak Pulsed Drain Current, IDM (A)
D = 0.5
0.2
0.1
1
P
D
0.05
0.1
tp
0.02
single pulse
0.01
1E-06
0
20
40
60
80
100
Tsp / C
120
140
1E-05
1E-04
T
1E-03
1E-02
1E-01
1E+00
1E+01
Pulse width, tp (s)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tsp); conditions: VGS ≥ 10 V
February 1999
D = tp/T
Fig.4. Transient thermal impedance.
Zth j-sp = f(t); parameter D = tp/T
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS transistor
BSP100
Transconductance, gfs (S)
6
Drain Current, ID (A)
10
VGS = 20 V
9
8
10 V
5
5V
Tj = 25 C
4
Tj = 25 C
7
150 C
6
4.2 V
5
4V
4
3
2
3.8 V
3.6 V
3.4 V
3.2 V
3
2
1
1
0
0
0
0.2
0.4 0.6 0.8
1
1.2 1.4 1.6
Drain-Source Voltage, VDS (V)
1.8
0
2
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
0.5
3.6 V 3.8V
4V
2
4.2 V
2
3
4
5
6
7
Drain current, ID (A)
8
9
10
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID) ; parameter Tj
Drain-Source On Resistance, RDS(on) (Ohms)
3.2 V
1
a
SOT223 30V Trench
Normalised RDS(ON) = f(Tj)
Tj = 25 C
3.4 V
0.4
1.5
0.3
1
0.2
VGS =5 V
10V
0.1
0.5
20V
0
0
1
2
3
4
5
6
Drain Current, ID (A)
7
8
9
0
-50
10
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
0
50
Tj / C
100
150
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj)
VGS(TO) / V
Drain current, ID (A)
10
4
VDS > ID X RDS(ON)
9
8
7
3
Tj = 25 C
6
max.
150 C
5
typ.
2
4
3
2
min.
1
1
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
-60 -40 -20
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
ID = f(VGS); parameter Tj
February 1999
0
20
40 60
Tj / C
80 100 120 140
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
4
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS transistor
BSP100
Sub-Threshold Conduction
1E-01
Source-Drain Diode Current, IF (A)
10
9
1E-02
VGS = 0 V
8
7
min
1E-03
typ
6
max
150 C
5
Tj = 25 C
4
1E-04
3
2
1
1E-05
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
1E-06
0
1
2
3
4
Drain-Source Voltage, VSDS (V)
5
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Non-repetitive Avalanche current, IAS (A)
BSP100
10
Capacitances, Ciss, Coss, Crss (pF)
1000
25 C
Tj prior to avalanche =125 C
Ciss
1
100
VDS
Coss
tp
Crss
ID
0.1
1E-06
10
0.1
1
10
Drain-Source Voltage, VDS (V)
100
1E-05
1E-04
1E-03
1E-02
Avalanche time, tp (s)
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.15. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tp);
unclamped inductive load
Gate-source voltage, VGS (V)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ID = 2.3A
Tj = 25 C
VDD = 15 V
0
1
2
3
4
5
6
7
Gate charge, QG (nC)
8
9
10
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
February 1999
5
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS transistor
BSP100
PRINTED CIRCUIT BOARD
Dimensions in mm.
36
18
60
4.5
4.6
9
10
7
15
50
Fig.16. PCB for thermal resistance and power rating for SOT223.
PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 µm thick).
February 1999
6
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS transistor
BSP100
MECHANICAL DATA
Plastic surface mounted package; collector pad for good heat transfer; 4 leads
D
SOT223
E
B
A
X
c
y
HE
v M A
b1
4
Q
A
A1
1
2
3
Lp
bp
e1
w M B
detail X
e
0
2
4 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
bp
b1
c
D
E
mm
1.8
1.5
0.10
0.01
0.80
0.60
3.1
2.9
0.32
0.22
6.7
6.3
3.7
3.3
OUTLINE
VERSION
e
4.6
e1
HE
Lp
Q
v
w
y
2.3
7.3
6.7
1.1
0.7
0.95
0.85
0.2
0.1
0.1
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
96-11-11
97-02-28
SOT223
Fig.17. SOT223 surface mounting package.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to Discrete Semiconductor Packages, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
February 1999
7
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS transistor
BSP100
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
February 1999
8
Rev 1.000
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