VISHAY SI4532CDY-T1-GE3

Si4532CDY
Vishay Siliconix
N- and P-Channel 30 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
RDS(on) ()
ID (A)a
0.047 at VGS = 10 V
6.0
0.065 at VGS = 4.5 V
5.2
VDS (V)
N-Channel
30
P-Channel
- 30
0.089 at VGS = - 10 V
- 4.3
0.140 at VGS = - 4.5 V
- 3.4
Qg (Typ.)
2.75
4.1
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• 100 % Rg Tested
• 100 % UIS Tested
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
S1
1
8
D1
G1
2
7
D1
S2
3
6
D2
G2
4
5
D2
D1
S2
• DC/DC Converter
• Load Switch
SO-8
G2
G1
Top View
Ordering Information: Si4532CDY-T1-GE3 (Lead (Pb)-free and Halogen-free)
S1
D2
N-Channel MOSFET
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Symbol
N-Channel
P-Channel
Drain-Source Voltage
VDS
30
- 30
Gate-Source Voltage
VGS
Continuous Drain Current (TJ = 150 °C)
TA = 25 °C
6.0
ID
TA = 70 °C
IDM
Pulsed Drain Current (10 µs Pulse Width)
Source-Drain Current Diode Current
TC = 25 °C
TA = 25 °C
IS
- 4.3
4.9
- 3.4
4.9b, c
- 3.4b, c
3.9b, c
- 2.7b, c
- 15
- 2.3
1.5b, c
- 1.5b, c
24
- 12
ISM
Single Pulse Avalanche Current
IAS
7
8
EAS
2.5
3.2
2.78
2.78
L = 0.1 mH
TC = 25 °C
TC = 70 °C
Maximum Power Dissipation
TA = 25 °C
PD
TA = 70 °C
mJ
1.78
1.78
1.78b, c
1.78b, c
1.14b, c
1.14b, c
TJ, Tstg
Operating Junction and Storage Temperature Range
A
24
2.3
Pulsed Source-Drain Current
Single Pulse Avalanche Energy
V
± 20
TC = 25 °C
TC = 70 °C
Unit
W
- 55 to 150
°C
THERMAL RESISTANCE RATINGS
N-Channel
Parameter
Maximum Junction-to-Ambient
b, d
Maximum Junction-to-Foot (Drain)
P-Channel
Symbol
Typ.
Max.
Typ.
Max.
t  10 s
RthJA
57
70
57
70
Steady State
RthJF
37
45
37
45
Unit
°C/W
Notes:
a. Based on TC = 25 °C.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. Maximum under steady state conditions is 120 °C/W (N-Channel) and 110 °C/W (P-Channel).
Document Number: 64805
S11-0652-Rev. B, 11-Apr-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si4532CDY
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
Parameter
Symbol
Test Conditions
Min.
Typ.a
Max.
Unit
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
VGS(th) Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward Transconductanceb
VDS
VDS/TJ
VGS(th)/TJ
VGS(th)
IGSS
IDSS
ID(on)
RDS(on)
gfs
VGS = 0 V, ID = 250 µA
N-Ch
30
VGS = 0 V, ID = - 250 µA
P-Ch
- 30
ID = 250 µA
N-Ch
V
33
ID = - 250 µA
P-Ch
- 33
ID = 250 µA
N-Ch
- 5.8
mV/°C
IID = - 250 µA
P-Ch
VDS = VGS, ID = 250 µA
N-Ch
1.0
3.0
VDS = VGS, ID = - 250 µA
P-Ch
- 1.0
- 3.0
VDS = 0 V, VGS = ± 20 V
4.5
N-Ch
100
P-Ch
- 100
VDS = 30 V, VGS = 0 V
N-Ch
1
VDS = - 30 V, VGS = 0 V
P-Ch
-1
VDS = 30 V, VGS = 0 V, TJ = 55 °C
N-Ch
5
VDS = - 30 V, VGS = 0 V, TJ = 55 °C
P-Ch
VDS =5 V, VGS = 10 V
N-Ch
20
VDS = -5 V, VGS = - 10 V
P-Ch
- 12
V
nA
µA
-5
A
VGS = 10 V, ID = 3.5 A
N-Ch
0.038
0.047
VGS = - 10 V, ID = - 3.5 A
P-Ch
0.073
0.089
VGS = 4.5 V, ID = 2.8 A
N-Ch
0.052
0.065
VGS = - 4.5 V, ID = - 2.5 A
P-Ch
0.113
0.140
VDS = 15 V, ID = 2.5 A
N-Ch
7
VDS = - 15 V, ID = - 3.5 A
P-Ch
7

S
Dynamica
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Crss
Qg
N-Channel
VDS = 15 V, VGS = 0 V, f = 1 MHz
P-Channel
VDS = - 15 V, VGS = 0 V, f = 1 MHz
305
P-Ch
340
N-Ch
65
P-Ch
67
N-Ch
29
P-Ch
51
pF
VDS = 15 V, VGS = 10 V, ID = 2.5 A
N-Ch
6
9
VDS = - 15 V, VGS = - 10 V, ID = - 2.5 A
P-Ch
7.8
12
N-Ch
2.75
4.5
N-Channel
VDS = 15 V, VGS = 4.5 V ID = 2.5 A
P-Ch
4.1
6.2
N-Ch
1.3
P-Ch
1.3
N-Ch
0.9
P-Ch
1.8
Qgs
Gate-Drain Charge
Qgd
P-Channel
VDS = - 15 V, VGS = - 4.5 V, ID = - 2.5 A
Gate Resistance
Rg
f = 1 MHz
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2
N-Ch
N-Ch
0.6
3.1
6.2
P-Ch
2.0
10
20
nC

Document Number: 64805
S11-0652-Rev. B, 11-Apr-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si4532CDY
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
Parameter
Dynamic
Symbol
Test Conditions
Min.
Typ.a
Max.
Unit
a
Turn-On Delay Time
td(on)
tr
Rise Time
Turn-Off Delay Time
td(off)
tf
Fall Time
Turn-On Delay Time
td(on)
tr
Rise Time
Turn-Off Delay Time
P-Channel
VDD = - 15 V, RL = 15 
ID  - 1 A, VGEN = - 10 V, Rg = 1 
N-Channel
VDD = 15 V, RL = 15 
ID  1 A, VGEN = 4.5 V, Rg = 1 
tf
P-Channel
VDD = - 15 V, RL = 15 
ID  - 1 A, VGEN = - 4.5 V, Rg = 1 
IS
TC = 25 °C
td(off)
Fall Time
N-Channel
VDD = 15 V, RL = 15 
ID  1 A, VGEN = 10 V, Rg = 1 
N-Ch
7
11
P-Ch
5.5
10
N-Ch
12
18
P-Ch
13
25
N-Ch
14
25
P-Ch
17
30
N-Ch
6
10
P-Ch
7.7
15
N-Ch
16
30
60
P-Ch
40
N-Ch
16
30
P-Ch
40
60
N-Ch
9
18
P-Ch
20
40
N-Ch
9
18
P-Ch
17
30
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode
Current
Pulse Diode Forward Currenta
Body Diode Voltage
ISM
N-Ch
2.3
P-Ch
- 2.3
N-Ch
24
P-Ch
VSD
A
- 12
IS = 1.25 A
N-Ch
0.8
1.2
IS = - 0.75 A
P-Ch
- 0.8
- 1.2
N-Ch
14
21
P-Ch
17
30
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
N-Channel
IF = 1.25 A, dI/dt = 100 A/µs, TJ = 25 °C
N-Ch
6
10
P-Ch
11
20
Reverse Recovery Fall Time
ta
P-Channel
IF = - 2.5 A, dI/dt = - 100 A/µs, TJ = 25 °C
N-Ch
9
P-Ch
12
Reverse Recovery Rise Time
tb
N-Ch
5
P-Ch
5
V
ns
nC
ns
Notes:
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width  300 µs, duty cycle  2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Document Number: 64805
S11-0652-Rev. B, 11-Apr-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si4532CDY
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
1.2
24
1.0
VGS = 10 V thru 6 V
I D - Drain Current (A)
I D - Drain Current (A)
18
VGS = 5 V
12
0.8
0.6
TC = 25 °C
0.4
6
TC = 125 °C
0.2
VGS = 4 V
TC = - 55 °C
0.0
0
0
2
4
6
8
0
10
1
2
3
4
5
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.10
400
Ciss
300
0.06
C - Capacitance (pF)
R DS(on) - On-Resistance ()
350
0.08
VGS = 4.5 V
VGS = 10 V
0.04
250
200
150
100
Coss
0.02
Crss
50
0.00
0
0
2
4
6
8
10
12
14
16
0
10
15
20
25
ID - Drain Current (A)
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current and Gate Voltage
Capacitance
30
1.7
10
ID = 2.5 A
ID = 6 A
VDS = 7.5 V
1.5
8
VDS = 15 V
6
VDS = 22.5 V
4
VGS = 10 V
(Normalized)
R DS(on) - On-Resistance
VGS - Gate-to-Source Voltage (V)
5
1.3
VGS = 4.5 V
1.1
0.9
2
0
0
2
4
Qg - Total Gate Charge (nC)
Gate Charge
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4
6
0.7
- 50
- 25
0
25
50
75
100
125
150
TJ - Junction Temperature (°C)
On-Resistance vs. Junction Temperature
Document Number: 64805
S11-0652-Rev. B, 11-Apr-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si4532CDY
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
0.25
TJ = 150 °C
R DS(on) - On-Resistance (Ω)
I S - Source Current (A)
10
TJ = 25 °C
1
0.20
0.15
0.10
TJ = 125 °C
0.05
TJ = 25 °C
0.1
0.0
0.00
0.2
0.4
0.6
0.8
1.0
0
1.2
1
VSD - Source-to-Drain Voltage (V)
2
3
4
5
6
7
8
9
10
VGS - Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
0.4
50
0.2
40
0.0
Power (W)
V GS(th) Variance (V)
ID = 250 µA
- 0.2
30
20
- 0.4
10
- 0.6
- 0.8
- 50
- 25
0
25
50
75
100
TJ - Temperature (°C)
125
0
0.001
150
0.01
0.1
1
10
Time (s)
Threshold Voltage
Single Pulse Power, Junction-to-Ambient
100
I D - Drain Current (A)
Limited by RDS(on)*
10 µs
100 µs
10
1 ms
1
10 ms
TA = 25 °C
Single Pulse
100 ms
0.1
BVDSS Limited
0.01
0.1
1
1s
10 s
100 s, DC
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
Document Number: 64805
S11-0652-Rev. B, 11-Apr-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si4532CDY
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
8
I D - Drain Current (A)
6
Package Limited
4
2
0
0
25
50
75
100
125
150
TC - Case Temperature (°C)
3.5
1.5
2.8
1.2
2.1
0.9
Power (W)
Power (W)
Current Derating*
1.4
0.6
0.3
0.7
0.0
0.0
0
25
50
75
100
125
TC - Case Temperature (°C)
Power Derating, Junction-to-Foot
150
0
25
50
75
100
125
150
TA - Ambient Temperature (°C)
Power Derating, Junction-to-Ambient
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
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Document Number: 64805
S11-0652-Rev. B, 11-Apr-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si4532CDY
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
Notes:
0.1
PDM
0.05
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = RthJA = 120 °C/W
0.02
3. TJM - T A = PDMZthJA(t)
Single Pulse
0.01
10 -4
10 -3
4. Surface Mounted
10 -2
10 -1
1
100
10
1000
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10 -4
10 -3
10 -2
10 -1
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Document Number: 64805
S11-0652-Rev. B, 11-Apr-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si4532CDY
Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
15
2.0
VGS = 5 V
VGS = 10 V thru 6 V
I D - Drain Current (A)
I D - Drain Current (A)
12
9
VGS = 4 V
6
1.5
1.0
TC = 25 °C
0.5
3
TC = 125 °C
VGS = 3 V
TC = - 55 °C
0
0.0
0.5
1.0
1.5
0.0
1.0
2.0
1.5
VDS - Drain-to-Source Voltage (V)
2.0
3.0
3.5
4.0
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.20
600
0.15
450
C - Capacitance (pF)
R DS(on) - On-Resistance (Ω)
2.5
VGS = 4.5 V
0.10
VGS = 10 V
Ciss
300
0.05
150
0.00
0
Coss
Crss
0
3
6
9
12
15
0
12
18
24
ID - Drain Current (A)
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current and Gate Voltage
Capacitance
10
30
1.8
ID = 2.5 A
ID = 3.2 A
VDS = 15 V
VGS = 10 V
1.6
8
VDS = 7.5 V
6
VDS = 22.5 V
4
2
1.4
(Normalized)
R DS(on) - On-Resistance
VGS - Gate-to-Source Voltage (V)
6
VGS = 4.5 V
1.2
1.0
0.8
0
0
2
4
6
Qg - Total Gate Charge (nC)
Gate Charge
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8
0.6
- 50
- 25
0
25
50
75
100
125
150
TJ - Junction Temperature (°C)
On-Resistance vs. Junction Temperature
Document Number: 64805
S11-0652-Rev. B, 11-Apr-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si4532CDY
Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
0.4
10
ID = 3.5 A
R DS(on) - On-Resistance (Ω)
I S - Source Current (A)
TJ = 25 °C
1
TJ = 150 °C
0.1
TJ = - 50 °C
0.01
0.3
0.2
TJ = 125 °C
0.1
TJ = 25 °C
0.0
0.001
0.0
0.3
0.6
0.9
1.2
0
1.5
2
VSD - Source-to-Drain Voltage (V)
6
8
10
VGS - Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
0.6
50
0.4
40
ID = 250 µA
ID = 1 mA
0.2
0.0
-0.2
-0.4
- 50
Power (W)
VGS(th) Variance (V)
4
30
20
10
- 25
0
25
50
75
100
125
150
0
0.001
0.01
TJ - Temperature (°C)
0.1
1
10
Time (s)
Single Pulse Power, Junction-to-Ambient
Threshold Voltage
100
I D - Drain Current (A)
Limited by RDS(on)*
10 µs
100 µs
10
1 ms
1
10 ms
TA = 25 °C
Single Pulse
100 ms
0.1
1s
10 s
100 s, DC
BVDSS Limited
0.01
0.1
1
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
Document Number: 64805
S11-0652-Rev. B, 11-Apr-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si4532CDY
Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
5
I D - Drain Current (A)
4
3
2
1
0
0
25
50
75
100
125
150
TC - Case Temperature (°C)
3.5
1.5
2.8
1.2
2.1
0.9
Power (W)
Power (W)
Current Derating*
1.4
0.6
0.3
0.7
0.0
0.0
0
25
50
75
100
125
150
0
25
50
75
100
125
TC - Case Temperature (°C)
TA - Ambient Temperature (°C)
Power Derating, Junction-to-Foot
Power Derating, Junction-to-Ambient
150
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
www.vishay.com
10
Document Number: 64805
S11-0652-Rev. B, 11-Apr-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si4532CDY
Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
Notes:
0.1
PDM
0.05
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = RthJA = 110 °C/W
0.02
3. TJM - T A = PDMZthJA(t)
Single Pulse
0.01
10 -4
10 -3
4. Surface Mounted
10 -2
10 -1
1
100
10
1000
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10 -4
10 -3
10 -2
10 -1
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
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reliability data, see www.vishay.com/ppg?64805.
Document Number: 64805
S11-0652-Rev. B, 11-Apr-11
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Package Information
Vishay Siliconix
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
8
6
7
5
E
1
3
2
H
4
S
h x 45
D
C
0.25 mm (Gage Plane)
A
e
B
All Leads
q
A1
L
0.004"
MILLIMETERS
INCHES
DIM
Min
Max
Min
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.20
0.004
0.008
B
0.35
0.51
0.014
0.020
C
0.19
0.25
0.0075
0.010
D
4.80
5.00
0.189
0.196
E
3.80
4.00
0.150
e
0.101 mm
1.27 BSC
0.157
0.050 BSC
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.50
0.93
0.020
0.037
q
0°
8°
0°
8°
S
0.44
0.64
0.018
0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
Document Number: 71192
11-Sep-06
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1
VISHAY SILICONIX
TrenchFET® Power MOSFETs
Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
0.288
7.3
0.050
1.27
0.196
5.0
0.027
0.69
0.078
1.98
0.2
5.07
Figure 1. Single MOSFET SO-8 Pad
Pattern With Copper Spreading
Document Number: 70740
Revision: 18-Jun-07
0.050
1.27
0.088
2.25
0.088
2.25
0.027
0.69
0.078
1.98
0.2
5.07
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
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APPLICATION NOTE
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a single MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
0.288
7.3
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-8
0.172
(4.369)
0.028
0.022
0.050
(0.559)
(1.270)
0.152
(3.861)
0.047
(1.194)
0.246
(6.248)
(0.711)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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22
Document Number: 72606
Revision: 21-Jan-08
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Document Number: 91000
Revision: 11-Mar-11
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