HD74LS194A 4-bit Bidirectional Universal Shift Register REJ03D0456–0300 Rev.3.00 Jul.15.2005 The bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and leftshift serial inputs. Operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely; • • • • Parallel (broadside) load Shift right (in the direction QA toward QD) Shift left (in the direction QD toward QA) Inhibit clock (do nothing) Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial input. Clocking of the flip-flop is inhibited when both mode control inputs are low. • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS194AP DILP-16 pin PRDP0016AE-B (DP-16FV) P — PRSP0016DH-B FP (FP-16DAV) Note: Please consult the sales office for the above package availability. HD74LS194AFPEL SOP-16 pin (JEITA) EL (2,000 pcs/reel) Pin Arrangement Clear 1 16 VCC CLR Shift Right Serial Input 2 R QA 15 QA A 3 A QB 14 QB B 4 B QC 13 QC C 5 C QD 12 QD D 6 D 11 Clock Shift Left Serial Input 7 L 10 S1 GND 8 9 S0 Parallel Inputs CK S0 S1 (Top view) Rev.3.00, Jul.15.2005, page 1 of 7 Parallel Outputs Mode Control HD74LS194A Function Table Mode Clear S1 X X H L L H H L L H H H H H H H S0 X X H H H L L L Clock X L ↑ ↑ ↑ ↑ ↑ X Inputs Serial Left Right X X X X X X X H X L H X L X X X Outputs Parallel B C X X X X b c X X X X X X X X X X A X X a X X X X X D X X d X X X X X QA QB QC QD L QA0 a H L QBn QBn QAo L QB0 b QAn QAn QCn QCn QBo L QC0 c QBn QBn QDn QDn QCo L QD0 d QCn QCn H L QDo Notes: 1. 2. 3. 4. H; high level, L; low level, X; irrelevant ↑; transition from low to high level a to d; the level of steady-state input at inputs A, B, C, or D, respectively QA0 to QD0; the level of QA, QB, QC, or QD, respectively before the indicated steady-state input conditions were established. 5. QAn to QDn; the level of QA, QB, QC, or QD, respectively before the most-recent ↑ transition of the clock. Block Diagram Parallel Inputs A Mode Control Inputs B C D S1 S0 Shift Right Serial Input Shift Left Serial Input S QA S QB S QC CK CK CK S QD CK R Clear R Clear R Clear R Clear Clock Clear QA QB QC Parallel Outputs Rev.3.00, Jul.15.2005, page 2 of 7 QD HD74LS194A Absolute Maximum Ratings Symbol Ratings Unit Supply voltage Item VCC 7 V Input voltage VIN 7 V Power dissipation PT 400 mW Tstg –65 to +150 °C Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Supply voltage Output current Operating temperature Symbol Min Typ Max Unit VCC 4.75 5.00 5.25 V IOH — — –400 µA IOL — — 8 mA Topr –20 25 75 °C Clock frequency ƒclock 0 — 25 MHz Clock pulse width tw (CK) 20 — — ns Clear pulse width tw (CLR) 20 — — ns 30 — — ns 20 — — ns 25 — — ns 0 — — ns Mode Control Setup time A, B, C, D, R, L tsu CLR (inactive state) th Hold time Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH VIL min. 2.0 — typ.* — — max. — 0.8 Unit V V VOH 2.7 — — V — — 0.4 II — — — — — — — — 0.5 20 –0.4 0.1 µA mA mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA IOL = 4 mA VCC = 4.75 V, VIH = 2 V, V IL = 0.8 V IOL = 8 mA VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V IOS –20 — –100 mA VCC = 5.25 V ICC VIK — — 15 — 23 –1.5 mA V VCC = 5.25 V VCC = 4.75 V, IIN = –18 mA Output voltage VOL Input current Short-circuit output current Supply current** Input clamp voltage IIH IIL V Condition Notes: * VCC = 5 V, Ta = 25°C ** With all outputs open, inputs A through D grounded, and 4.5 V applied to S0, S1, clear and the serial inputs, ICC is tested with a momentary GND, then 4.5 V, applied to clock. Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Maximum clock frequency Propagation delay time Symbol ƒmax tPHL tPLH tPHL Rev.3.00, Jul.15.2005, page 3 of 7 Inputs Clear Clock Clock Outputs Q min. 25 — — — typ. 36 19 14 17 max. — 30 22 26 Unit MHz ns ns ns Condition CL = 15 pF, RL = 2 kΩ HD74LS194A Count Sequences Clock S0 Mode Control Inputs S1 Clear Serial Inputs R L A Parallel Inputs B C D QA H L H L QB Outputs QC QD Shift Right Shift Left Inhibit Clear Load Clear Testing Method Test Circuit VCC 4.5V Output RL CK P.G. Zout = 50Ω Notes: See Testing Table Input QA CL S0 S1 Output R L QB Same as Load Circuit 1. Output A B C D CLR 1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H). Rev.3.00, Jul.15.2005, page 4 of 7 Load circuit 1 QC Same as Load Circuit 1. Output QD Same as Load Circuit 1. HD74LS194A Testing Table Item From input to output ƒmax right-shift left-shift Clear→Q tPLH tPHL Clock→Q Item From input to output ƒmax right-shift left-shift Clear→Q tPLH tPHL Inputs CLR 4.5V 4.5V IN 4.5V S1 4.5V GND 4.5V 4.5V S0 GND 4.5V 4.5V GND CK IN IN IN IN L 4.5V IN GND 4.5V R IN 4.5V GND IN A GND GND 4.5V GND B GND GND 4.5V GND C GND GND 4.5V GND D GND GND 4.5V GND 4.5V 4.5V GND IN IN 4.5V GND GND GND GND Outputs Clock→Q QA QB QC QD OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Waveforms 1 (ƒmax, CK→Q) tTLH CK 10% tTHL tn tn+1 90% 90% 1.3V 1.3V 10% tw (CK) tsu tn tn+1 3V 1.3V 1.3V th tsu 1.3V tPHL tTLH 90% 1.3V 10% tPLH 0V th tTHL L, R 1.3V 10% tPHL 3V 90% 1.3V 0V tPLH VOH Q 1.3V 1.3V 1.3V 1.3V VOL Notes: 1. Right-shift is measured with QA at tn + 1, QB at tn + 2, QC at tn + 3, and QD at tn + 4. Left-shift is measured with QA at tn + 4, QB at tn + 3, QC at tn + 2, and QD at tn + 1. Rev.3.00, Jul.15.2005, page 5 of 7 HD74LS194A Waveforms 2 (Clear→Q) tTLH tTHL 90% CK 3V 90% 1.3V 10% 1.3V 10% 0V tTHL 3V 90% 1.3V Clear 1.3V 10% tPLH 0V tw tPLH tPHL Q 1.3V 1.3V VOH 1.3V VOL Notes: Input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns Rev.3.00, Jul.15.2005, page 6 of 7 HD74LS194A Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B MASS[Typ.] 1.05g Previous Code DP-16FV D 9 E 16 1 8 b3 0.89 Z A1 A Reference Symbol L e Nom θ c e1 D 19.2 E 6.3 JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV 7.4 A1 0.51 b p 0.40 b 3 0.48 0.56 1.30 c 0.19 θ 0° e 2.29 0.25 0.31 2.54 2.79 15° 1.12 L 2.54 MASS[Typ.] 0.24g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 16 20.32 5.06 Z ( Ni/Pd/Au plating ) Max 7.62 1 A bp e Dimension in Millimeters Min 9 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 bp Nom D 10.06 E 5.50 Max 10.5 A2 8 e Dimension in Millimeters Min x A1 M 0.00 0.10 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 A L1 0.20 2.20 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 e 1.27 x 0.12 y 0.15 0.80 Z L L Rev.3.00, Jul.15.2005, page 7 of 7 8° 0.50 1 0.70 1.15 0.90 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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